wifi: add bcm43751 support [1/4]
authorWeiguang.ruan <Weiguang.ruan@amlogic.com>
Sun, 11 Feb 2018 14:16:52 +0000 (22:16 +0800)
committerWeiguang Ruan <Weiguang.ruan@amlogic.com>
Thu, 8 Mar 2018 07:31:46 +0000 (23:31 -0800)
PD#161120

1. add bcm43751 support

2. don't use enable_irq_wake/disable_irq_wake

Change-Id: I57d3a5b997d126ffa3ae6f0cd3df32c90afbc1f3

bcmdhd.1.579.77.41.1.cn/bcmsdh_linux.c
bcmdhd.1.579.77.41.1.cn/dhd_config.c
bcmdhd.1.579.77.41.1.cn/dhd_sdio.c
bcmdhd.1.579.77.41.1.cn/include/bcmdevs.h
bcmdhd.1.579.77.41.1.cn/include/sbchipc.h

index 53e233b2cef72a16973a2017309a1583df981f7f..6841c08c89d9cbf12aedeab9aedd7dcbdb636d89 100644 (file)
@@ -391,10 +391,12 @@ int bcmsdh_oob_intr_register(bcmsdh_info_t *bcmsdh, bcmsdh_cb_fn_t oob_irq_handl
        SDLX_MSG(("%s: disable_irq_wake\n", __FUNCTION__));
        bcmsdh_osinfo->oob_irq_wake_enabled = FALSE;
 #else
+/*
        err = enable_irq_wake(bcmsdh_osinfo->oob_irq_num);
        if (err)
                SDLX_MSG(("%s: enable_irq_wake failed with %d\n", __FUNCTION__, err));
        else
+*/
                bcmsdh_osinfo->oob_irq_wake_enabled = TRUE;
 #endif
        return 0;
@@ -402,7 +404,7 @@ int bcmsdh_oob_intr_register(bcmsdh_info_t *bcmsdh, bcmsdh_cb_fn_t oob_irq_handl
 
 void bcmsdh_oob_intr_unregister(bcmsdh_info_t *bcmsdh)
 {
-       int err = 0;
+       /*int err = 0;*/
        bcmsdh_os_info_t *bcmsdh_osinfo = bcmsdh->os_cxt;
 
        SDLX_MSG(("%s: Enter\n", __FUNCTION__));
@@ -410,11 +412,13 @@ void bcmsdh_oob_intr_unregister(bcmsdh_info_t *bcmsdh)
                SDLX_MSG(("%s: irq is not registered\n", __FUNCTION__));
                return;
        }
+/*
        if (bcmsdh_osinfo->oob_irq_wake_enabled) {
                err = disable_irq_wake(bcmsdh_osinfo->oob_irq_num);
                if (!err)
                        bcmsdh_osinfo->oob_irq_wake_enabled = FALSE;
        }
+*/
        if (bcmsdh_osinfo->oob_irq_enabled) {
                disable_irq(bcmsdh_osinfo->oob_irq_num);
                bcmsdh_osinfo->oob_irq_enabled = FALSE;
index e06201679136bebd9826b1c560c7f8197487b999..5f968bab7711c4335efee5b4d6d818bdc1305ef1 100644 (file)
@@ -92,6 +92,7 @@ uint config_msg_level = CONFIG_ERROR_LEVEL;
 #define FW_BCM4358A3 "fw_bcm4358a3_ag"\r
 #define FW_BCM4359B1 "fw_bcm4359b1_ag"\r
 #define FW_BCM4359C0 "fw_bcm4359c0_ag"\r
+#define FW_BCM43751 "fw_bcm43751_ag"\r
 \r
 #define CLM_BCM43013B0 "clm_bcm43013b0"\r
 #endif\r
@@ -540,6 +541,9 @@ dhd_conf_set_fw_name_by_chip(dhd_pub_t *dhd, char *fw_path)
                        else if (chiprev == BCM4359C0_CHIP_REV)\r
                                strcpy(&fw_path[i], FW_BCM4359C0);\r
                        break;\r
+               case BCM43751_CHIP_ID:\r
+                               strcpy(&fw_path[i], FW_BCM43751);\r
+                       break;\r
 #endif\r
 #ifdef BCMPCIE\r
                case BCM4354_CHIP_ID:\r
index fe2e874bffdbef61e37038969ebf83f948f2a56c..d69bcedc3e1b3f963a950c0aa72de8d62b9c63e8 100644 (file)
@@ -881,6 +881,7 @@ dhdsdio_sr_cap(dhd_bus_t *bus)
                (bus->sih->chip == BCM4371_CHIP_ID) ||
                (BCM4349_CHIP(bus->sih->chip))          ||
                (bus->sih->chip == BCM4350_CHIP_ID) ||
+               (bus->sih->chip == BCM43751_CHIP_ID) ||
                (bus->sih->chip == BCM43012_CHIP_ID)) {
                core_capext = TRUE;
        } else {
@@ -977,6 +978,7 @@ dhdsdio_sr_init(dhd_bus_t *bus)
        if (CHIPID(bus->sih->chip) == BCM43430_CHIP_ID ||
                CHIPID(bus->sih->chip) == BCM43018_CHIP_ID ||
                CHIPID(bus->sih->chip) == BCM4339_CHIP_ID ||
+               CHIPID(bus->sih->chip) == BCM43751_CHIP_ID ||
                CHIPID(bus->sih->chip) == BCM43012_CHIP_ID)
                dhdsdio_devcap_set(bus, SDIOD_CCCR_BRCM_CARDCAP_CMD_NODEC);
 
@@ -7642,6 +7644,9 @@ dhdsdio_chipmatch(uint16 chipid)
        if (chipid == BCM43012_CHIP_ID)
                return TRUE;
 
+       if (chipid == BCM43751_CHIP_ID)
+               return TRUE;
+
        return FALSE;
 }
 
@@ -8061,6 +8066,9 @@ dhdsdio_probe_attach(struct dhd_bus *bus, osl_t *osh, void *sdh, void *regsva,
                        case BCM4347_CHIP_GRPID:
                                bus->dongle_ram_base = CR4_4347_RAM_BASE;
                                break;
+                       case BCM43751_CHIP_ID:
+                               bus->dongle_ram_base = CR4_43751_RAM_BASE;
+                               break;
                        default:
                                bus->dongle_ram_base = 0;
                                DHD_ERROR(("%s: WARNING: Using default ram base at 0x%x\n",
index 70ef4678848339ff5fbff44151474cecf70e47bd..915f3720a7be53200ef79196f51afc4ff0ef2a0a 100644 (file)
 #define BCM43455_CHIP_ID       43455           /* 43455 chipcommon chipid */
 #define BCM43457_CHIP_ID       43457           /* 43457 chipcommon chipid */
 #define BCM43458_CHIP_ID       43458           /* 43458 chipcommon chipid */
+#define BCM43751_CHIP_ID       0x4362          /* 43751 chipcommon chipid */
 
 #define BCM4345_CHIP(chipid)   (CHIPID(chipid) == BCM4345_CHIP_ID || \
                                 CHIPID(chipid) == BCM43454_CHIP_ID || \
index ffec624c53dcca8eaa4f6f93b952a86dddf1975f..008276545efd072b404a8bdaa61dae7d48650efa 100644 (file)
@@ -3343,6 +3343,7 @@ typedef volatile struct {
 #define CA7_4365_RAM_BASE                    (0x200000)
 
 #define CR4_4347_RAM_BASE                    (0x170000)
+#define CR4_43751_RAM_BASE                   (0x170000)
 
 /* 4335 chip OTP present & OTP select bits. */
 #define SPROM4335_OTP_SELECT   0x00000010