bcmdhd.100.10.315.x/include/spid.h

   1 /*
   2  * SPI device spec header file
   3  *
   4  * Copyright (C) 1999-2019, Broadcom.
   5  *
   6  *      Unless you and Broadcom execute a separate written software license
   7  * agreement governing use of this software, this software is licensed to you
   8  * under the terms of the GNU General Public License version 2 (the "GPL"),
   9  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
  10  * following added to such license:
  11  *
  12  *      As a special exception, the copyright holders of this software give you
  13  * permission to link this software with independent modules, and to copy and
  14  * distribute the resulting executable under terms of your choice, provided that
  15  * you also meet, for each linked independent module, the terms and conditions of
  16  * the license of that module.  An independent module is a module which is not
  17  * derived from this software.  The special exception does not apply to any
  18  * modifications of the software.
  19  *
  20  *      Notwithstanding the above, under no circumstances may you combine this
  21  * software in any way with any other Broadcom software provided under a license
  22  * other than the GPL, without Broadcom's express prior written consent.
  23  *
  24  *
  25  * <<Broadcom-WL-IPTag/Open:>>
  26  *
  27  * $Id: spid.h 514727 2014-11-12 03:02:48Z $
  28  */
  29
  30 #ifndef _SPI_H
  31 #define _SPI_H
  32
  33 /*
  34  * Brcm SPI Device Register Map.
  35  *
  36  */
  37
  38 typedef volatile struct {
  39         uint8   config;                 /* 0x00, len, endian, clock, speed, polarity, wakeup */
  40         uint8   response_delay;         /* 0x01, read response delay in bytes (corerev < 3) */
  41         uint8   status_enable;          /* 0x02, status-enable, intr with status, response_delay
  42                                          * function selection, command/data error check
  43                                          */
  44         uint8   reset_bp;               /* 0x03, reset on wlan/bt backplane reset (corerev >= 1) */
  45         uint16  intr_reg;               /* 0x04, Intr status register */
  46         uint16  intr_en_reg;            /* 0x06, Intr mask register */
  47         uint32  status_reg;             /* 0x08, RO, Status bits of last spi transfer */
  48         uint16  f1_info_reg;            /* 0x0c, RO, enabled, ready for data transfer, blocksize */
  49         uint16  f2_info_reg;            /* 0x0e, RO, enabled, ready for data transfer, blocksize */
  50         uint16  f3_info_reg;            /* 0x10, RO, enabled, ready for data transfer, blocksize */
  51         uint32  test_read;              /* 0x14, RO 0xfeedbead signature */
  52         uint32  test_rw;                /* 0x18, RW */
  53         uint8   resp_delay_f0;          /* 0x1c, read resp delay bytes for F0 (corerev >= 3) */
  54         uint8   resp_delay_f1;          /* 0x1d, read resp delay bytes for F1 (corerev >= 3) */
  55         uint8   resp_delay_f2;          /* 0x1e, read resp delay bytes for F2 (corerev >= 3) */
  56         uint8   resp_delay_f3;          /* 0x1f, read resp delay bytes for F3 (corerev >= 3) */
  57 } spi_regs_t;
  58
  59 /* SPI device register offsets */
  60 #define SPID_CONFIG                     0x00
  61 #define SPID_RESPONSE_DELAY             0x01
  62 #define SPID_STATUS_ENABLE              0x02
  63 #define SPID_RESET_BP                   0x03    /* (corerev >= 1) */
  64 #define SPID_INTR_REG                   0x04    /* 16 bits - Interrupt status */
  65 #define SPID_INTR_EN_REG                0x06    /* 16 bits - Interrupt mask */
  66 #define SPID_STATUS_REG                 0x08    /* 32 bits */
  67 #define SPID_F1_INFO_REG                0x0C    /* 16 bits */
  68 #define SPID_F2_INFO_REG                0x0E    /* 16 bits */
  69 #define SPID_F3_INFO_REG                0x10    /* 16 bits */
  70 #define SPID_TEST_READ                  0x14    /* 32 bits */
  71 #define SPID_TEST_RW                    0x18    /* 32 bits */
  72 #define SPID_RESP_DELAY_F0              0x1c    /* 8 bits (corerev >= 3) */
  73 #define SPID_RESP_DELAY_F1              0x1d    /* 8 bits (corerev >= 3) */
  74 #define SPID_RESP_DELAY_F2              0x1e    /* 8 bits (corerev >= 3) */
  75 #define SPID_RESP_DELAY_F3              0x1f    /* 8 bits (corerev >= 3) */
  76
  77 /* Bit masks for SPID_CONFIG device register */
  78 #define WORD_LENGTH_32  0x1     /* 0/1 16/32 bit word length */
  79 #define ENDIAN_BIG      0x2     /* 0/1 Little/Big Endian */
  80 #define CLOCK_PHASE     0x4     /* 0/1 clock phase delay */
  81 #define CLOCK_POLARITY  0x8     /* 0/1 Idle state clock polarity is low/high */
  82 #define HIGH_SPEED_MODE 0x10    /* 1/0 High Speed mode / Normal mode */
  83 #define INTR_POLARITY   0x20    /* 1/0 Interrupt active polarity is high/low */
  84 #define WAKE_UP         0x80    /* 0/1 Wake-up command from Host to WLAN */
  85
  86 /* Bit mask for SPID_RESPONSE_DELAY device register */
  87 #define RESPONSE_DELAY_MASK     0xFF    /* Configurable rd response delay in multiples of 8 bits */
  88
  89 /* Bit mask for SPID_STATUS_ENABLE device register */
  90 #define STATUS_ENABLE           0x1     /* 1/0 Status sent/not sent to host after read/write */
  91 #define INTR_WITH_STATUS        0x2     /* 0/1 Do-not / do-interrupt if status is sent */
  92 #define RESP_DELAY_ALL          0x4     /* Applicability of resp delay to F1 or all func's read */
  93 #define DWORD_PKT_LEN_EN        0x8     /* Packet len denoted in dwords instead of bytes */
  94 #define CMD_ERR_CHK_EN          0x20    /* Command error check enable */
  95 #define DATA_ERR_CHK_EN         0x40    /* Data error check enable */
  96
  97 /* Bit mask for SPID_RESET_BP device register */
  98 #define RESET_ON_WLAN_BP_RESET  0x4     /* enable reset for WLAN backplane */
  99 #define RESET_ON_BT_BP_RESET    0x8     /* enable reset for BT backplane */
 100 #define RESET_SPI               0x80    /* reset the above enabled logic */
 101
 102 /* Bit mask for SPID_INTR_REG device register */
 103 #define DATA_UNAVAILABLE        0x0001  /* Requested data not available; Clear by writing a "1" */
 104 #define F2_F3_FIFO_RD_UNDERFLOW 0x0002
 105 #define F2_F3_FIFO_WR_OVERFLOW  0x0004
 106 #define COMMAND_ERROR           0x0008  /* Cleared by writing 1 */
 107 #define DATA_ERROR              0x0010  /* Cleared by writing 1 */
 108 #define F2_PACKET_AVAILABLE     0x0020
 109 #define F3_PACKET_AVAILABLE     0x0040
 110 #define F1_OVERFLOW             0x0080  /* Due to last write. Bkplane has pending write requests */
 111 #define MISC_INTR0              0x0100
 112 #define MISC_INTR1              0x0200
 113 #define MISC_INTR2              0x0400
 114 #define MISC_INTR3              0x0800
 115 #define MISC_INTR4              0x1000
 116 #define F1_INTR                 0x2000
 117 #define F2_INTR                 0x4000
 118 #define F3_INTR                 0x8000
 119
 120 /* Bit mask for 32bit SPID_STATUS_REG device register */
 121 #define STATUS_DATA_NOT_AVAILABLE       0x00000001
 122 #define STATUS_UNDERFLOW                0x00000002
 123 #define STATUS_OVERFLOW                 0x00000004
 124 #define STATUS_F2_INTR                  0x00000008
 125 #define STATUS_F3_INTR                  0x00000010
 126 #define STATUS_F2_RX_READY              0x00000020
 127 #define STATUS_F3_RX_READY              0x00000040
 128 #define STATUS_HOST_CMD_DATA_ERR        0x00000080
 129 #define STATUS_F2_PKT_AVAILABLE         0x00000100
 130 #define STATUS_F2_PKT_LEN_MASK          0x000FFE00
 131 #define STATUS_F2_PKT_LEN_SHIFT         9
 132 #define STATUS_F3_PKT_AVAILABLE         0x00100000
 133 #define STATUS_F3_PKT_LEN_MASK          0xFFE00000
 134 #define STATUS_F3_PKT_LEN_SHIFT         21
 135
 136 /* Bit mask for 16 bits SPID_F1_INFO_REG device register */
 137 #define F1_ENABLED                      0x0001
 138 #define F1_RDY_FOR_DATA_TRANSFER        0x0002
 139 #define F1_MAX_PKT_SIZE                 0x01FC
 140
 141 /* Bit mask for 16 bits SPID_F2_INFO_REG device register */
 142 #define F2_ENABLED                      0x0001
 143 #define F2_RDY_FOR_DATA_TRANSFER        0x0002
 144 #define F2_MAX_PKT_SIZE                 0x3FFC
 145
 146 /* Bit mask for 16 bits SPID_F3_INFO_REG device register */
 147 #define F3_ENABLED                      0x0001
 148 #define F3_RDY_FOR_DATA_TRANSFER        0x0002
 149 #define F3_MAX_PKT_SIZE                 0x3FFC
 150
 151 /* Bit mask for 32 bits SPID_TEST_READ device register read in 16bit LE mode */
 152 #define TEST_RO_DATA_32BIT_LE           0xFEEDBEAD
 153
 154 /* Maximum number of I/O funcs */
 155 #define SPI_MAX_IOFUNCS         4
 156
 157 #define SPI_MAX_PKT_LEN         (2048*4)
 158
 159 /* Misc defines */
 160 #define SPI_FUNC_0              0
 161 #define SPI_FUNC_1              1
 162 #define SPI_FUNC_2              2
 163 #define SPI_FUNC_3              3
 164
 165 #define WAIT_F2RXFIFORDY        100
 166 #define WAIT_F2RXFIFORDY_DELAY  20
 167
 168 #endif /* _SPI_H */