bcmdhd.100.10.315.x/include/sbhnddma.h

   1 /*
   2  * Generic Broadcom Home Networking Division (HND) DMA engine HW interface
   3  * This supports the following chips: BCM42xx, 44xx, 47xx .
   4  *
   5  * Copyright (C) 1999-2018, Broadcom.
   6  *
   7  *      Unless you and Broadcom execute a separate written software license
   8  * agreement governing use of this software, this software is licensed to you
   9  * under the terms of the GNU General Public License version 2 (the "GPL"),
  10  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
  11  * following added to such license:
  12  *
  13  *      As a special exception, the copyright holders of this software give you
  14  * permission to link this software with independent modules, and to copy and
  15  * distribute the resulting executable under terms of your choice, provided that
  16  * you also meet, for each linked independent module, the terms and conditions of
  17  * the license of that module.  An independent module is a module which is not
  18  * derived from this software.  The special exception does not apply to any
  19  * modifications of the software.
  20  *
  21  *      Notwithstanding the above, under no circumstances may you combine this
  22  * software in any way with any other Broadcom software provided under a license
  23  * other than the GPL, without Broadcom's express prior written consent.
  24  *
  25  *
  26  * <<Broadcom-WL-IPTag/Open:>>
  27  *
  28  * $Id: sbhnddma.h 694506 2017-04-13 05:10:05Z $
  29  */
  30
  31 #ifndef _sbhnddma_h_
  32 #define _sbhnddma_h_
  33
  34 /* DMA structure:
  35  *  support two DMA engines: 32 bits address or 64 bit addressing
  36  *  basic DMA register set is per channel(transmit or receive)
  37  *  a pair of channels is defined for convenience
  38  */
  39
  40 /* 32 bits addressing */
  41
  42 /** dma registers per channel(xmt or rcv) */
  43 typedef volatile struct {
  44         uint32  control;                /**< enable, et al */
  45         uint32  addr;                   /**< descriptor ring base address (4K aligned) */
  46         uint32  ptr;                    /**< last descriptor posted to chip */
  47         uint32  status;                 /**< current active descriptor, et al */
  48 } dma32regs_t;
  49
  50 typedef volatile struct {
  51         dma32regs_t     xmt;            /**< dma tx channel */
  52         dma32regs_t     rcv;            /**< dma rx channel */
  53 } dma32regp_t;
  54
  55 typedef volatile struct {       /* diag access */
  56         uint32  fifoaddr;               /**< diag address */
  57         uint32  fifodatalow;            /**< low 32bits of data */
  58         uint32  fifodatahigh;           /**< high 32bits of data */
  59         uint32  pad;                    /**< reserved */
  60 } dma32diag_t;
  61
  62 /**
  63  * DMA Descriptor
  64  * Descriptors are only read by the hardware, never written back.
  65  */
  66 typedef volatile struct {
  67         uint32  ctrl;           /**< misc control bits & bufcount */
  68         uint32  addr;           /**< data buffer address */
  69 } dma32dd_t;
  70
  71 /** Each descriptor ring must be 4096byte aligned, and fit within a single 4096byte page. */
  72 #define D32RINGALIGN_BITS       12
  73 #define D32MAXRINGSZ            (1 << D32RINGALIGN_BITS)
  74 #define D32RINGALIGN            (1 << D32RINGALIGN_BITS)
  75
  76 #define D32MAXDD        (D32MAXRINGSZ / sizeof (dma32dd_t))
  77
  78 /* transmit channel control */
  79 #define XC_XE           ((uint32)1 << 0)        /**< transmit enable */
  80 #define XC_SE           ((uint32)1 << 1)        /**< transmit suspend request */
  81 #define XC_LE           ((uint32)1 << 2)        /**< loopback enable */
  82 #define XC_FL           ((uint32)1 << 4)        /**< flush request */
  83 #define XC_MR_MASK      0x000001C0              /**< Multiple outstanding reads */
  84 #define XC_MR_SHIFT     6
  85 #define XC_PD           ((uint32)1 << 11)       /**< parity check disable */
  86 #define XC_AE           ((uint32)3 << 16)       /**< address extension bits */
  87 #define XC_AE_SHIFT     16
  88 #define XC_BL_MASK      0x001C0000              /**< BurstLen bits */
  89 #define XC_BL_SHIFT     18
  90 #define XC_PC_MASK      0x00E00000              /**< Prefetch control */
  91 #define XC_PC_SHIFT     21
  92 #define XC_PT_MASK      0x03000000              /**< Prefetch threshold */
  93 #define XC_PT_SHIFT     24
  94
  95 /** Multiple outstanding reads */
  96 #define DMA_MR_1        0
  97 #define DMA_MR_2        1
  98 #define DMA_MR_4        2
  99 #define DMA_MR_8        3
 100 #define DMA_MR_12       4
 101 #define DMA_MR_16       5
 102 #define DMA_MR_20       6
 103 #define DMA_MR_32       7
 104
 105 /** DMA Burst Length in bytes */
 106 #define DMA_BL_16       0
 107 #define DMA_BL_32       1
 108 #define DMA_BL_64       2
 109 #define DMA_BL_128      3
 110 #define DMA_BL_256      4
 111 #define DMA_BL_512      5
 112 #define DMA_BL_1024     6
 113
 114 /** Prefetch control */
 115 #define DMA_PC_0        0
 116 #define DMA_PC_4        1
 117 #define DMA_PC_8        2
 118 #define DMA_PC_16       3
 119 #define DMA_PC_32       4
 120 /* others: reserved */
 121
 122 /** Prefetch threshold */
 123 #define DMA_PT_1        0
 124 #define DMA_PT_2        1
 125 #define DMA_PT_4        2
 126 #define DMA_PT_8        3
 127
 128 /** Channel Switch */
 129 #define DMA_CS_OFF      0
 130 #define DMA_CS_ON       1
 131
 132 /* transmit descriptor table pointer */
 133 #define XP_LD_MASK      0xfff                   /**< last valid descriptor */
 134
 135 /* transmit channel status */
 136 #define XS_CD_MASK      0x0fff                  /**< current descriptor pointer */
 137 #define XS_XS_MASK      0xf000                  /**< transmit state */
 138 #define XS_XS_SHIFT     12
 139 #define XS_XS_DISABLED  0x0000                  /**< disabled */
 140 #define XS_XS_ACTIVE    0x1000                  /**< active */
 141 #define XS_XS_IDLE      0x2000                  /**< idle wait */
 142 #define XS_XS_STOPPED   0x3000                  /**< stopped */
 143 #define XS_XS_SUSP      0x4000                  /**< suspend pending */
 144 #define XS_XE_MASK      0xf0000                 /**< transmit errors */
 145 #define XS_XE_SHIFT     16
 146 #define XS_XE_NOERR     0x00000                 /**< no error */
 147 #define XS_XE_DPE       0x10000                 /**< descriptor protocol error */
 148 #define XS_XE_DFU       0x20000                 /**< data fifo underrun */
 149 #define XS_XE_BEBR      0x30000                 /**< bus error on buffer read */
 150 #define XS_XE_BEDA      0x40000                 /**< bus error on descriptor access */
 151 #define XS_AD_MASK      0xfff00000              /**< active descriptor */
 152 #define XS_AD_SHIFT     20
 153
 154 /* receive channel control */
 155 #define RC_RE           ((uint32)1 << 0)        /**< receive enable */
 156 #define RC_RO_MASK      0xfe                    /**< receive frame offset */
 157 #define RC_RO_SHIFT     1
 158 #define RC_FM           ((uint32)1 << 8)        /**< direct fifo receive (pio) mode */
 159 #define RC_SH           ((uint32)1 << 9)        /**< separate rx header descriptor enable */
 160 #define RC_OC           ((uint32)1 << 10)       /**< overflow continue */
 161 #define RC_PD           ((uint32)1 << 11)       /**< parity check disable */
 162 #define RC_AE           ((uint32)3 << 16)       /**< address extension bits */
 163 #define RC_AE_SHIFT     16
 164 #define RC_BL_MASK      0x001C0000              /**< BurstLen bits */
 165 #define RC_BL_SHIFT     18
 166 #define RC_PC_MASK      0x00E00000              /**< Prefetch control */
 167 #define RC_PC_SHIFT     21
 168 #define RC_PT_MASK      0x03000000              /**< Prefetch threshold */
 169 #define RC_PT_SHIFT     24
 170 #define RC_WAITCMP_MASK 0x00001000
 171 #define RC_WAITCMP_SHIFT 12
 172 /* receive descriptor table pointer */
 173 #define RP_LD_MASK      0xfff                   /**< last valid descriptor */
 174
 175 /* receive channel status */
 176 #define RS_CD_MASK      0x0fff                  /**< current descriptor pointer */
 177 #define RS_RS_MASK      0xf000                  /**< receive state */
 178 #define RS_RS_SHIFT     12
 179 #define RS_RS_DISABLED  0x0000                  /**< disabled */
 180 #define RS_RS_ACTIVE    0x1000                  /**< active */
 181 #define RS_RS_IDLE      0x2000                  /**< idle wait */
 182 #define RS_RS_STOPPED   0x3000                  /**< reserved */
 183 #define RS_RE_MASK      0xf0000                 /**< receive errors */
 184 #define RS_RE_SHIFT     16
 185 #define RS_RE_NOERR     0x00000                 /**< no error */
 186 #define RS_RE_DPE       0x10000                 /**< descriptor protocol error */
 187 #define RS_RE_DFO       0x20000                 /**< data fifo overflow */
 188 #define RS_RE_BEBW      0x30000                 /**< bus error on buffer write */
 189 #define RS_RE_BEDA      0x40000                 /**< bus error on descriptor access */
 190 #define RS_AD_MASK      0xfff00000              /**< active descriptor */
 191 #define RS_AD_SHIFT     20
 192
 193 /* fifoaddr */
 194 #define FA_OFF_MASK     0xffff                  /**< offset */
 195 #define FA_SEL_MASK     0xf0000                 /**< select */
 196 #define FA_SEL_SHIFT    16
 197 #define FA_SEL_XDD      0x00000                 /**< transmit dma data */
 198 #define FA_SEL_XDP      0x10000                 /**< transmit dma pointers */
 199 #define FA_SEL_RDD      0x40000                 /**< receive dma data */
 200 #define FA_SEL_RDP      0x50000                 /**< receive dma pointers */
 201 #define FA_SEL_XFD      0x80000                 /**< transmit fifo data */
 202 #define FA_SEL_XFP      0x90000                 /**< transmit fifo pointers */
 203 #define FA_SEL_RFD      0xc0000                 /**< receive fifo data */
 204 #define FA_SEL_RFP      0xd0000                 /**< receive fifo pointers */
 205 #define FA_SEL_RSD      0xe0000                 /**< receive frame status data */
 206 #define FA_SEL_RSP      0xf0000                 /**< receive frame status pointers */
 207
 208 /* descriptor control flags */
 209 #define CTRL_BC_MASK    0x00001fff              /**< buffer byte count, real data len must <= 4KB */
 210 #define CTRL_AE         ((uint32)3 << 16)       /**< address extension bits */
 211 #define CTRL_AE_SHIFT   16
 212 #define CTRL_PARITY     ((uint32)3 << 18)       /**< parity bit */
 213 #define CTRL_EOT        ((uint32)1 << 28)       /**< end of descriptor table */
 214 #define CTRL_IOC        ((uint32)1 << 29)       /**< interrupt on completion */
 215 #define CTRL_EOF        ((uint32)1 << 30)       /**< end of frame */
 216 #define CTRL_SOF        ((uint32)1 << 31)       /**< start of frame */
 217
 218 /** control flags in the range [27:20] are core-specific and not defined here */
 219 #define CTRL_CORE_MASK  0x0ff00000
 220
 221 /* 64 bits addressing */
 222
 223 /** dma registers per channel(xmt or rcv) */
 224 typedef volatile struct {
 225         uint32  control;        /**< enable, et al */
 226         uint32  ptr;            /**< last descriptor posted to chip */
 227         uint32  addrlow;        /**< descriptor ring base address low 32-bits (8K aligned) */
 228         uint32  addrhigh;       /**< descriptor ring base address bits 63:32 (8K aligned) */
 229         uint32  status0;        /**< current descriptor, xmt state */
 230         uint32  status1;        /**< active descriptor, xmt error */
 231 } dma64regs_t;
 232
 233 typedef volatile struct {
 234         dma64regs_t     tx;             /**< dma64 tx channel */
 235         dma64regs_t     rx;             /**< dma64 rx channel */
 236 } dma64regp_t;
 237
 238 typedef volatile struct {               /**< diag access */
 239         uint32  fifoaddr;               /**< diag address */
 240         uint32  fifodatalow;            /**< low 32bits of data */
 241         uint32  fifodatahigh;           /**< high 32bits of data */
 242         uint32  pad;                    /**< reserved */
 243 } dma64diag_t;
 244
 245 /**
 246  * DMA Descriptor
 247  * Descriptors are only read by the hardware, never written back.
 248  */
 249 typedef volatile struct {
 250         uint32  ctrl1;          /**< misc control bits */
 251         uint32  ctrl2;          /**< buffer count and address extension */
 252         uint32  addrlow;        /**< memory address of the date buffer, bits 31:0 */
 253         uint32  addrhigh;       /**< memory address of the date buffer, bits 63:32 */
 254 } dma64dd_t;
 255
 256 /**
 257  * Each descriptor ring must be 8kB aligned, and fit within a contiguous 8kB physical addresss.
 258  */
 259 #define D64RINGALIGN_BITS       13
 260 #define D64MAXRINGSZ            (1 << D64RINGALIGN_BITS)
 261 #define D64RINGBOUNDARY         (1 << D64RINGALIGN_BITS)
 262
 263 #define D64MAXDD        (D64MAXRINGSZ / sizeof (dma64dd_t))
 264
 265 /** for cores with large descriptor ring support, descriptor ring size can be up to 4096 */
 266 #define D64MAXDD_LARGE          ((1 << 16) / sizeof (dma64dd_t))
 267
 268 /**
 269  * for cores with large descriptor ring support (4k descriptors), descriptor ring cannot cross
 270  * 64K boundary
 271  */
 272 #define D64RINGBOUNDARY_LARGE   (1 << 16)
 273
 274 /*
 275  * Default DMA Burstlen values for USBRev >= 12 and SDIORev >= 11.
 276  * When this field contains the value N, the burst length is 2**(N + 4) bytes.
 277  */
 278 #define D64_DEF_USBBURSTLEN     2
 279 #define D64_DEF_SDIOBURSTLEN    1
 280
 281 #ifndef D64_USBBURSTLEN
 282 #define D64_USBBURSTLEN DMA_BL_64
 283 #endif // endif
 284 #ifndef D64_SDIOBURSTLEN
 285 #define D64_SDIOBURSTLEN        DMA_BL_32
 286 #endif // endif
 287
 288 /* transmit channel control */
 289 #define D64_XC_XE               0x00000001      /**< transmit enable */
 290 #define D64_XC_SE               0x00000002      /**< transmit suspend request */
 291 #define D64_XC_LE               0x00000004      /**< loopback enable */
 292 #define D64_XC_FL               0x00000010      /**< flush request */
 293 #define D64_XC_MR_MASK          0x000001C0      /**< Multiple outstanding reads */
 294 #define D64_XC_MR_SHIFT         6
 295 #define D64_XC_CS_SHIFT         9               /**< channel switch enable */
 296 #define D64_XC_CS_MASK          0x00000200      /**< channel switch enable */
 297 #define D64_XC_PD               0x00000800      /**< parity check disable */
 298 #define D64_XC_AE               0x00030000      /**< address extension bits */
 299 #define D64_XC_AE_SHIFT         16
 300 #define D64_XC_BL_MASK          0x001C0000      /**< BurstLen bits */
 301 #define D64_XC_BL_SHIFT         18
 302 #define D64_XC_PC_MASK          0x00E00000              /**< Prefetch control */
 303 #define D64_XC_PC_SHIFT         21
 304 #define D64_XC_PT_MASK          0x03000000              /**< Prefetch threshold */
 305 #define D64_XC_PT_SHIFT         24
 306 #define D64_XC_CO_MASK          0x04000000      /**< coherent transactions for descriptors */
 307 #define D64_XC_CO_SHIFT         26
 308
 309 /* transmit descriptor table pointer */
 310 #define D64_XP_LD_MASK          0x00001fff      /**< last valid descriptor */
 311
 312 /* transmit channel status */
 313 #define D64_XS0_CD_MASK         (di->d64_xs0_cd_mask)   /**< current descriptor pointer */
 314 #define D64_XS0_XS_MASK         0xf0000000      /**< transmit state */
 315 #define D64_XS0_XS_SHIFT                28
 316 #define D64_XS0_XS_DISABLED     0x00000000      /**< disabled */
 317 #define D64_XS0_XS_ACTIVE       0x10000000      /**< active */
 318 #define D64_XS0_XS_IDLE         0x20000000      /**< idle wait */
 319 #define D64_XS0_XS_STOPPED      0x30000000      /**< stopped */
 320 #define D64_XS0_XS_SUSP         0x40000000      /**< suspend pending */
 321
 322 #define D64_XS1_AD_MASK         (di->d64_xs1_ad_mask)   /**< active descriptor */
 323 #define D64_XS1_XE_MASK         0xf0000000      /**< transmit errors */
 324 #define D64_XS1_XE_SHIFT                28
 325 #define D64_XS1_XE_NOERR        0x00000000      /**< no error */
 326 #define D64_XS1_XE_DPE          0x10000000      /**< descriptor protocol error */
 327 #define D64_XS1_XE_DFU          0x20000000      /**< data fifo underrun */
 328 #define D64_XS1_XE_DTE          0x30000000      /**< data transfer error */
 329 #define D64_XS1_XE_DESRE        0x40000000      /**< descriptor read error */
 330 #define D64_XS1_XE_COREE        0x50000000      /**< core error */
 331
 332 /* receive channel control */
 333 #define D64_RC_RE               0x00000001      /**< receive enable */
 334 #define D64_RC_RO_MASK          0x000000fe      /**< receive frame offset */
 335 #define D64_RC_RO_SHIFT         1
 336 #define D64_RC_FM               0x00000100      /**< direct fifo receive (pio) mode */
 337 #define D64_RC_SH               0x00000200      /**< separate rx header descriptor enable */
 338 #define D64_RC_SHIFT            9       /**< separate rx header descriptor enable */
 339 #define D64_RC_OC               0x00000400      /**< overflow continue */
 340 #define D64_RC_PD               0x00000800      /**< parity check disable */
 341 #define D64_RC_WAITCMP_MASK     0x00001000
 342 #define D64_RC_WAITCMP_SHIFT    12
 343 #define D64_RC_SA               0x00002000      /**< select active */
 344 #define D64_RC_GE               0x00004000      /**< Glom enable */
 345 #define D64_RC_AE               0x00030000      /**< address extension bits */
 346 #define D64_RC_AE_SHIFT         16
 347 #define D64_RC_BL_MASK          0x001C0000      /**< BurstLen bits */
 348 #define D64_RC_BL_SHIFT         18
 349 #define D64_RC_PC_MASK          0x00E00000      /**< Prefetch control */
 350 #define D64_RC_PC_SHIFT         21
 351 #define D64_RC_PT_MASK          0x03000000      /**< Prefetch threshold */
 352 #define D64_RC_PT_SHIFT         24
 353 #define D64_RC_CO_MASK          0x04000000      /**< coherent transactions for descriptors */
 354 #define D64_RC_CO_SHIFT         26
 355 #define D64_RC_ROEXT_MASK       0x08000000      /**< receive frame offset extension bit */
 356 #define D64_RC_ROEXT_SHIFT      27
 357
 358 /* flags for dma controller */
 359 #define DMA_CTRL_PEN            (1 << 0)        /**< partity enable */
 360 #define DMA_CTRL_ROC            (1 << 1)        /**< rx overflow continue */
 361 #define DMA_CTRL_RXMULTI        (1 << 2)        /**< allow rx scatter to multiple descriptors */
 362 #define DMA_CTRL_UNFRAMED       (1 << 3)        /**< Unframed Rx/Tx data */
 363 #define DMA_CTRL_USB_BOUNDRY4KB_WAR (1 << 4)
 364 #define DMA_CTRL_DMA_AVOIDANCE_WAR (1 << 5)     /**< DMA avoidance WAR for 4331 */
 365 #define DMA_CTRL_RXSINGLE       (1 << 6)        /**< always single buffer */
 366 #define DMA_CTRL_SDIO_RXGLOM    (1 << 7)        /**< DMA Rx glome is enabled */
 367 #define DMA_CTRL_DESC_ONLY_FLAG (1 << 8)        /**< For DMA which posts only descriptors,
 368                                                  * no packets
 369                                                  */
 370 #define DMA_CTRL_DESC_CD_WAR    (1 << 9)        /**< WAR for descriptor only DMA's CD not being
 371                                                  * updated correctly by HW in CT mode.
 372                                                  */
 373 #define DMA_CTRL_CS             (1 << 10)       /* channel switch enable */
 374 #define DMA_CTRL_ROEXT          (1 << 11)       /* receive frame offset extension support */
 375 #define DMA_CTRL_RX_ALIGN_8BYTE (1 << 12)       /* RXDMA address 8-byte aligned for 43684A0 */
 376
 377 /* receive descriptor table pointer */
 378 #define D64_RP_LD_MASK          0x00001fff      /**< last valid descriptor */
 379
 380 /* receive channel status */
 381 #define D64_RS0_CD_MASK         (di->d64_rs0_cd_mask)   /**< current descriptor pointer */
 382 #define D64_RS0_RS_MASK         0xf0000000      /**< receive state */
 383 #define D64_RS0_RS_SHIFT                28
 384 #define D64_RS0_RS_DISABLED     0x00000000      /**< disabled */
 385 #define D64_RS0_RS_ACTIVE       0x10000000      /**< active */
 386 #define D64_RS0_RS_IDLE         0x20000000      /**< idle wait */
 387 #define D64_RS0_RS_STOPPED      0x30000000      /**< stopped */
 388 #define D64_RS0_RS_SUSP         0x40000000      /**< suspend pending */
 389
 390 #define D64_RS1_AD_MASK         (di->d64_rs1_ad_mask)   /* active descriptor pointer */
 391 #define D64_RS1_RE_MASK         0xf0000000      /* receive errors */
 392 #define D64_RS1_RE_SHIFT                28
 393 #define D64_RS1_RE_NOERR        0x00000000      /**< no error */
 394 #define D64_RS1_RE_DPO          0x10000000      /**< descriptor protocol error */
 395 #define D64_RS1_RE_DFU          0x20000000      /**< data fifo overflow */
 396 #define D64_RS1_RE_DTE          0x30000000      /**< data transfer error */
 397 #define D64_RS1_RE_DESRE        0x40000000      /**< descriptor read error */
 398 #define D64_RS1_RE_COREE        0x50000000      /**< core error */
 399
 400 /* fifoaddr */
 401 #define D64_FA_OFF_MASK         0xffff          /**< offset */
 402 #define D64_FA_SEL_MASK         0xf0000         /**< select */
 403 #define D64_FA_SEL_SHIFT        16
 404 #define D64_FA_SEL_XDD          0x00000         /**< transmit dma data */
 405 #define D64_FA_SEL_XDP          0x10000         /**< transmit dma pointers */
 406 #define D64_FA_SEL_RDD          0x40000         /**< receive dma data */
 407 #define D64_FA_SEL_RDP          0x50000         /**< receive dma pointers */
 408 #define D64_FA_SEL_XFD          0x80000         /**< transmit fifo data */
 409 #define D64_FA_SEL_XFP          0x90000         /**< transmit fifo pointers */
 410 #define D64_FA_SEL_RFD          0xc0000         /**< receive fifo data */
 411 #define D64_FA_SEL_RFP          0xd0000         /**< receive fifo pointers */
 412 #define D64_FA_SEL_RSD          0xe0000         /**< receive frame status data */
 413 #define D64_FA_SEL_RSP          0xf0000         /**< receive frame status pointers */
 414
 415 /* descriptor control flags 1 */
 416 #define D64_CTRL_COREFLAGS      0x0ff00000              /**< core specific flags */
 417 #define D64_CTRL1_COHERENT      ((uint32)1 << 17)       /* cache coherent per transaction */
 418 #define D64_CTRL1_NOTPCIE       ((uint32)1 << 18)       /**< buirst size control */
 419 #define D64_CTRL1_EOT           ((uint32)1 << 28)       /**< end of descriptor table */
 420 #define D64_CTRL1_IOC           ((uint32)1 << 29)       /**< interrupt on completion */
 421 #define D64_CTRL1_EOF           ((uint32)1 << 30)       /**< end of frame */
 422 #define D64_CTRL1_SOF           ((uint32)1 << 31)       /**< start of frame */
 423
 424 /* descriptor control flags 2 */
 425 #define D64_CTRL2_MAX_LEN       0x0000fff7 /* Max transfer length (buffer byte count) <= 65527 */
 426 #define D64_CTRL2_BC_MASK       0x0000ffff /**< mask for buffer byte count */
 427 #define D64_CTRL2_AE            0x00030000 /**< address extension bits */
 428 #define D64_CTRL2_AE_SHIFT      16
 429 #define D64_CTRL2_PARITY        0x00040000      /* parity bit */
 430
 431 /** control flags in the range [27:20] are core-specific and not defined here */
 432 #define D64_CTRL_CORE_MASK      0x0ff00000
 433
 434 #define D64_RX_FRM_STS_LEN      0x0000ffff      /**< frame length mask */
 435 #define D64_RX_FRM_STS_OVFL     0x00800000      /**< RxOverFlow */
 436 #define D64_RX_FRM_STS_DSCRCNT  0x0f000000 /**< no. of descriptors used - 1, d11corerev >= 22 */
 437 #define D64_RX_FRM_STS_DSCRCNT_SHIFT   24      /* Shift for no .of dma descriptor field */
 438 #define D64_RX_FRM_STS_DATATYPE 0xf0000000      /**< core-dependent data type */
 439
 440 #define BCM_D64_CTRL2_BOUND_DMA_LENGTH(len) \
 441 (((len) > D64_CTRL2_MAX_LEN) ? D64_CTRL2_MAX_LEN : (len))
 442
 443 /** receive frame status */
 444 typedef volatile struct {
 445         uint16 len;
 446         uint16 flags;
 447 } dma_rxh_t;
 448
 449 #endif  /* _sbhnddma_h_ */