bcmdhd.100.10.315.x/include/pcicfg.h

   1 /*
   2  * pcicfg.h: PCI configuration constants and structures.
   3  *
   4  * Copyright (C) 1999-2019, Broadcom.
   5  *
   6  *      Unless you and Broadcom execute a separate written software license
   7  * agreement governing use of this software, this software is licensed to you
   8  * under the terms of the GNU General Public License version 2 (the "GPL"),
   9  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
  10  * following added to such license:
  11  *
  12  *      As a special exception, the copyright holders of this software give you
  13  * permission to link this software with independent modules, and to copy and
  14  * distribute the resulting executable under terms of your choice, provided that
  15  * you also meet, for each linked independent module, the terms and conditions of
  16  * the license of that module.  An independent module is a module which is not
  17  * derived from this software.  The special exception does not apply to any
  18  * modifications of the software.
  19  *
  20  *      Notwithstanding the above, under no circumstances may you combine this
  21  * software in any way with any other Broadcom software provided under a license
  22  * other than the GPL, without Broadcom's express prior written consent.
  23  *
  24  *
  25  * <<Broadcom-WL-IPTag/Open:>>
  26  *
  27  * $Id: pcicfg.h 795237 2018-12-18 03:26:49Z $
  28  */
  29
  30 #ifndef _h_pcicfg_
  31 #define _h_pcicfg_
  32
  33 /* pci config status reg has a bit to indicate that capability ptr is present */
  34
  35 #define PCI_CAPPTR_PRESENT      0x0010
  36
  37 /* A structure for the config registers is nice, but in most
  38  * systems the config space is not memory mapped, so we need
  39  * field offsetts. :-(
  40  */
  41 #define PCI_CFG_VID             0
  42 #define PCI_CFG_DID             2
  43 #define PCI_CFG_CMD             4
  44 #define PCI_CFG_STAT            6
  45 #define PCI_CFG_REV             8
  46 #define PCI_CFG_PROGIF          9
  47 #define PCI_CFG_SUBCL           0xa
  48 #define PCI_CFG_BASECL          0xb
  49 #define PCI_CFG_CLSZ            0xc
  50 #define PCI_CFG_LATTIM          0xd
  51 #define PCI_CFG_HDR             0xe
  52 #define PCI_CFG_BIST            0xf
  53 #define PCI_CFG_BAR0            0x10
  54 /*
  55 * TODO: PCI_CFG_BAR1 is wrongly defined to be 0x14 whereas it should be
  56 * 0x18 as per the PCIe full dongle spec. Need to modify the values below
  57 * correctly at a later point of time
  58 */
  59 #define PCI_CFG_BAR1            0x14
  60 #define PCI_CFG_BAR2            0x18
  61 #define PCI_CFG_BAR3            0x1c
  62 #define PCI_CFG_BAR4            0x20
  63 #define PCI_CFG_BAR5            0x24
  64 #define PCI_CFG_CIS             0x28
  65 #define PCI_CFG_SVID            0x2c
  66 #define PCI_CFG_SSID            0x2e
  67 #define PCI_CFG_ROMBAR          0x30
  68 #define PCI_CFG_CAPPTR          0x34
  69 #define PCI_CFG_INT             0x3c
  70 #define PCI_CFG_PIN             0x3d
  71 #define PCI_CFG_MINGNT          0x3e
  72 #define PCI_CFG_MAXLAT          0x3f
  73 #define PCI_CFG_DEVCTRL         0xd8
  74 #define PCI_CFG_TLCNTRL_5       0x814
  75
  76 /* PCI CAPABILITY DEFINES */
  77 #define PCI_CAP_POWERMGMTCAP_ID         0x01
  78 #define PCI_CAP_MSICAP_ID               0x05
  79 #define PCI_CAP_VENDSPEC_ID             0x09
  80 #define PCI_CAP_PCIECAP_ID              0x10
  81 #define PCI_CAP_MSIXCAP_ID              0x11
  82
  83 /* Data structure to define the Message Signalled Interrupt facility
  84  * Valid for PCI and PCIE configurations
  85  */
  86 typedef struct _pciconfig_cap_msi {
  87         uint8   capID;
  88         uint8   nextptr;
  89         uint16  msgctrl;
  90         uint32  msgaddr;
  91 } pciconfig_cap_msi;
  92 #define MSI_ENABLE      0x1             /* bit 0 of msgctrl */
  93
  94 /* Data structure to define the Power managment facility
  95  * Valid for PCI and PCIE configurations
  96  */
  97 typedef struct _pciconfig_cap_pwrmgmt {
  98         uint8   capID;
  99         uint8   nextptr;
 100         uint16  pme_cap;
 101         uint16  pme_sts_ctrl;
 102         uint8   pme_bridge_ext;
 103         uint8   data;
 104 } pciconfig_cap_pwrmgmt;
 105
 106 #define PME_CAP_PM_STATES (0x1f << 27)  /* Bits 31:27 states that can generate PME */
 107 #define PME_CSR_OFFSET      0x4         /* 4-bytes offset */
 108 #define PME_CSR_PME_EN    (1 << 8)      /* Bit 8 Enable generating of PME */
 109 #define PME_CSR_PME_STAT  (1 << 15)     /* Bit 15 PME got asserted */
 110
 111 /* Data structure to define the PCIE capability */
 112 typedef struct _pciconfig_cap_pcie {
 113         uint8   capID;
 114         uint8   nextptr;
 115         uint16  pcie_cap;
 116         uint32  dev_cap;
 117         uint16  dev_ctrl;
 118         uint16  dev_status;
 119         uint32  link_cap;
 120         uint16  link_ctrl;
 121         uint16  link_status;
 122         uint32  slot_cap;
 123         uint16  slot_ctrl;
 124         uint16  slot_status;
 125         uint16  root_ctrl;
 126         uint16  root_cap;
 127         uint32  root_status;
 128 } pciconfig_cap_pcie;
 129
 130 /* PCIE Enhanced CAPABILITY DEFINES */
 131 #define PCIE_EXTCFG_OFFSET      0x100
 132 #define PCIE_ADVERRREP_CAPID    0x0001
 133 #define PCIE_VC_CAPID           0x0002
 134 #define PCIE_DEVSNUM_CAPID      0x0003
 135 #define PCIE_PWRBUDGET_CAPID    0x0004
 136
 137 /* PCIE Extended configuration */
 138 #define PCIE_ADV_CORR_ERR_MASK  0x114
 139 #define PCIE_ADV_CORR_ERR_MASK_OFFSET   0x14
 140 #define CORR_ERR_RE     (1 << 0) /* Receiver  */
 141 #define CORR_ERR_BT     (1 << 6) /* Bad TLP  */
 142 #define CORR_ERR_BD     (1 << 7) /* Bad DLLP */
 143 #define CORR_ERR_RR     (1 << 8) /* REPLAY_NUM rollover */
 144 #define CORR_ERR_RT     (1 << 12) /* Reply timer timeout */
 145 #define CORR_ERR_AE     (1 << 13) /* Adviosry Non-Fital Error Mask */
 146 #define ALL_CORR_ERRORS (CORR_ERR_RE | CORR_ERR_BT | CORR_ERR_BD | \
 147                          CORR_ERR_RR | CORR_ERR_RT)
 148
 149 /* PCIE Root Control Register bits (Host mode only) */
 150 #define PCIE_RC_CORR_SERR_EN            0x0001
 151 #define PCIE_RC_NONFATAL_SERR_EN        0x0002
 152 #define PCIE_RC_FATAL_SERR_EN           0x0004
 153 #define PCIE_RC_PME_INT_EN              0x0008
 154 #define PCIE_RC_CRS_EN                  0x0010
 155
 156 /* PCIE Root Capability Register bits (Host mode only) */
 157 #define PCIE_RC_CRS_VISIBILITY          0x0001
 158
 159 /* PCIe PMCSR Register bits */
 160 #define PCIE_PMCSR_PMESTAT              0x8000
 161
 162 /* Header to define the PCIE specific capabilities in the extended config space */
 163 typedef struct _pcie_enhanced_caphdr {
 164         uint16  capID;
 165         uint16  cap_ver : 4;
 166         uint16  next_ptr : 12;
 167 } pcie_enhanced_caphdr;
 168
 169 #define PCIE_CFG_PMCSR          0x4C
 170 #define PCI_BAR0_WIN            0x80    /* backplane addres space accessed by BAR0 */
 171 #define PCI_BAR1_WIN            0x84    /* backplane addres space accessed by BAR1 */
 172 #define PCI_SPROM_CONTROL       0x88    /* sprom property control */
 173 #define PCIE_CFG_SUBSYSTEM_CONTROL      0x88    /* used as subsystem control in PCIE devices */
 174 #define PCI_BAR1_CONTROL        0x8c    /* BAR1 region burst control */
 175 #define PCI_INT_STATUS          0x90    /* PCI and other cores interrupts */
 176 #define PCI_INT_MASK            0x94    /* mask of PCI and other cores interrupts */
 177 #define PCI_TO_SB_MB            0x98    /* signal backplane interrupts */
 178 #define PCI_BACKPLANE_ADDR      0xa0    /* address an arbitrary location on the system backplane */
 179 #define PCI_BACKPLANE_DATA      0xa4    /* data at the location specified by above address */
 180 #define PCI_CLK_CTL_ST          0xa8    /* pci config space clock control/status (>=rev14) */
 181 #define PCI_BAR0_WIN2           0xac    /* backplane addres space accessed by second 4KB of BAR0 */
 182 #define PCI_GPIO_IN             0xb0    /* pci config space gpio input (>=rev3) */
 183 #define PCIE_CFG_DEVICE_CAPABILITY      0xb0    /* used as device capability in PCIE devices */
 184 #define PCI_GPIO_OUT            0xb4    /* pci config space gpio output (>=rev3) */
 185 #define PCIE_CFG_DEVICE_CONTROL 0xb4    /* 0xb4 is used as device control in PCIE devices */
 186 #define PCIE_DC_AER_CORR_EN             (1u << 0u)
 187 #define PCIE_DC_AER_NON_FATAL_EN        (1u << 1u)
 188 #define PCIE_DC_AER_FATAL_EN            (1u << 2u)
 189 #define PCIE_DC_AER_UNSUP_EN            (1u << 3u)
 190
 191 #define PCI_BAR0_WIN2_OFFSET            0x1000u
 192 #define PCIE2_BAR0_CORE2_WIN2_OFFSET    0x5000u
 193
 194 #define PCI_GPIO_OUTEN          0xb8    /* pci config space gpio output enable (>=rev3) */
 195 #define PCI_L1SS_CTRL2          0x24c   /* The L1 PM Substates Control register */
 196
 197 /* Private Registers */
 198 #define PCI_STAT_CTRL           0xa80
 199 #define PCI_L0_EVENTCNT         0xa84
 200 #define PCI_L0_STATETMR         0xa88
 201 #define PCI_L1_EVENTCNT         0xa8c
 202 #define PCI_L1_STATETMR         0xa90
 203 #define PCI_L1_1_EVENTCNT       0xa94
 204 #define PCI_L1_1_STATETMR       0xa98
 205 #define PCI_L1_2_EVENTCNT       0xa9c
 206 #define PCI_L1_2_STATETMR       0xaa0
 207 #define PCI_L2_EVENTCNT         0xaa4
 208 #define PCI_L2_STATETMR         0xaa8
 209
 210 #define PCI_LINK_STATUS         0x4dc
 211 #define PCI_LINK_SPEED_MASK     (15u << 0u)
 212 #define PCI_LINK_SPEED_SHIFT    (0)
 213 #define PCIE_LNK_SPEED_GEN1             0x1
 214 #define PCIE_LNK_SPEED_GEN2             0x2
 215 #define PCIE_LNK_SPEED_GEN3             0x3
 216
 217 #define PCI_PL_SPARE    0x1808  /* Config to Increase external clkreq deasserted minimum time */
 218 #define PCI_CONFIG_EXT_CLK_MIN_TIME_MASK        (1u << 31u)
 219 #define PCI_CONFIG_EXT_CLK_MIN_TIME_SHIFT       (31)
 220
 221 #define PCI_ADV_ERR_CAP                 0x100
 222 #define PCI_UC_ERR_STATUS               0x104
 223 #define PCI_UNCORR_ERR_MASK             0x108
 224 #define PCI_UCORR_ERR_SEVR              0x10c
 225 #define PCI_CORR_ERR_STATUS             0x110
 226 #define PCI_CORR_ERR_MASK               0x114
 227 #define PCI_ERR_CAP_CTRL                0x118
 228 #define PCI_TLP_HDR_LOG1                0x11c
 229 #define PCI_TLP_HDR_LOG2                0x120
 230 #define PCI_TLP_HDR_LOG3                0x124
 231 #define PCI_TLP_HDR_LOG4                0x128
 232 #define PCI_TL_CTRL_5                   0x814
 233 #define PCI_TL_HDR_FC_ST                0x980
 234 #define PCI_TL_TGT_CRDT_ST              0x990
 235 #define PCI_TL_SMLOGIC_ST               0x998
 236 #define PCI_DL_ATTN_VEC                 0x1040
 237 #define PCI_DL_STATUS                   0x1048
 238
 239 #define PCI_PHY_CTL_0                   0x1800
 240 #define PCI_SLOW_PMCLK_EXT_RLOCK        (1 << 7)
 241
 242 #define PCI_LINK_STATE_DEBUG    0x1c24
 243 #define PCI_RECOVERY_HIST               0x1ce4
 244 #define PCI_PHY_LTSSM_HIST_0    0x1cec
 245 #define PCI_PHY_LTSSM_HIST_1    0x1cf0
 246 #define PCI_PHY_LTSSM_HIST_2    0x1cf4
 247 #define PCI_PHY_LTSSM_HIST_3    0x1cf8
 248 #define PCI_PHY_DBG_CLKREG_0    0x1e10
 249 #define PCI_PHY_DBG_CLKREG_1    0x1e14
 250 #define PCI_PHY_DBG_CLKREG_2    0x1e18
 251 #define PCI_PHY_DBG_CLKREG_3    0x1e1c
 252
 253 /* Bit settings for PCIE_CFG_SUBSYSTEM_CONTROL register */
 254 #define PCIE_BAR1COHERENTACCEN_BIT      8
 255 #define PCIE_BAR2COHERENTACCEN_BIT      9
 256 #define PCIE_SSRESET_STATUS_BIT         13
 257 #define PCIE_SSRESET_DISABLE_BIT        14
 258 #define PCIE_SSRESET_DIS_ENUM_RST_BIT           15
 259
 260 #define PCIE_BARCOHERENTACCEN_MASK      0x300
 261
 262 /* Bit settings for PCI_UC_ERR_STATUS register */
 263 #define PCI_UC_ERR_URES                 (1 << 20)       /* Unsupported Request Error Status */
 264 #define PCI_UC_ERR_ECRCS                (1 << 19)       /* ECRC Error Status */
 265 #define PCI_UC_ERR_MTLPS                (1 << 18)       /* Malformed TLP Status */
 266 #define PCI_UC_ERR_ROS                  (1 << 17)       /* Receiver Overflow Status */
 267 #define PCI_UC_ERR_UCS                  (1 << 16)       /* Unexpected Completion Status */
 268 #define PCI_UC_ERR_CAS                  (1 << 15)       /* Completer Abort Status */
 269 #define PCI_UC_ERR_CTS                  (1 << 14)       /* Completer Timeout Status */
 270 #define PCI_UC_ERR_FCPES                (1 << 13)       /* Flow Control Protocol Error Status */
 271 #define PCI_UC_ERR_PTLPS                (1 << 12)       /* Poisoned TLP Status */
 272 #define PCI_UC_ERR_DLPES                (1 << 4)        /* Data Link Protocol Error Status */
 273
 274 #define PCI_DL_STATUS_PHY_LINKUP    (1 << 13) /* Status of LINK */
 275
 276 #define PCI_PMCR_REFUP          0x1814  /* Trefup time */
 277 #define PCI_PMCR_TREFUP_LO_MASK         0x3f
 278 #define PCI_PMCR_TREFUP_LO_SHIFT        24
 279 #define PCI_PMCR_TREFUP_LO_BITS         6
 280 #define PCI_PMCR_TREFUP_HI_MASK         0xf
 281 #define PCI_PMCR_TREFUP_HI_SHIFT        5
 282 #define PCI_PMCR_TREFUP_HI_BITS         4
 283 #define PCI_PMCR_TREFUP_MAX                     0x400
 284 #define PCI_PMCR_TREFUP_MAX_SCALE       0x2000
 285
 286 #define PCI_PMCR_REFUP_EXT      0x1818  /* Trefup extend Max */
 287 #define PCI_PMCR_TREFUP_EXT_SHIFT       22
 288 #define PCI_PMCR_TREFUP_EXT_SCALE       3
 289 #define PCI_PMCR_TREFUP_EXT_ON          1
 290 #define PCI_PMCR_TREFUP_EXT_OFF         0
 291
 292 #define PCI_TPOWER_SCALE_MASK 0x3
 293 #define PCI_TPOWER_SCALE_SHIFT 3 /* 0:1 is scale and 2 is rsvd */
 294
 295 #define PCI_BAR0_SHADOW_OFFSET  (2 * 1024)      /* bar0 + 2K accesses sprom shadow (in pci core) */
 296 #define PCI_BAR0_SPROM_OFFSET   (4 * 1024)      /* bar0 + 4K accesses external sprom */
 297 #define PCI_BAR0_PCIREGS_OFFSET (6 * 1024)      /* bar0 + 6K accesses pci core registers */
 298 #define PCI_BAR0_PCISBR_OFFSET  (4 * 1024)      /* pci core SB registers are at the end of the
 299                                                  * 8KB window, so their address is the "regular"
 300                                                  * address plus 4K
 301                                                  */
 302 /*
 303  * PCIE GEN2 changed some of the above locations for
 304  * Bar0WrapperBase, SecondaryBAR0Window and SecondaryBAR0WrapperBase
 305  * BAR0 maps 32K of register space
 306 */
 307 #define PCIE2_BAR0_WIN2         0x70 /* backplane addres space accessed by second 4KB of BAR0 */
 308 #define PCIE2_BAR0_CORE2_WIN    0x74 /* backplane addres space accessed by second 4KB of BAR0 */
 309 #define PCIE2_BAR0_CORE2_WIN2   0x78 /* backplane addres space accessed by second 4KB of BAR0 */
 310 #define PCIE2_BAR0_WINSZ        0x8000
 311
 312 #define PCI_BAR0_WIN2_OFFSET            0x1000u
 313 #define PCI_CORE_ENUM_OFFSET            0x2000u
 314 #define PCI_CC_CORE_ENUM_OFFSET         0x3000u
 315 #define PCI_SEC_BAR0_WIN_OFFSET         0x4000u
 316 #define PCI_SEC_BAR0_WRAP_OFFSET        0x5000u
 317 #define PCI_CORE_ENUM2_OFFSET           0x6000u
 318 #define PCI_CC_CORE_ENUM2_OFFSET        0x7000u
 319 #define PCI_LAST_OFFSET                 0x8000u
 320
 321 #define PCI_BAR0_WINSZ          (16 * 1024)     /* bar0 window size Match with corerev 13 */
 322 /* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
 323 #define PCI_16KB0_PCIREGS_OFFSET (8 * 1024)     /* bar0 + 8K accesses pci/pcie core registers */
 324 #define PCI_16KB0_CCREGS_OFFSET (12 * 1024)     /* bar0 + 12K accesses chipc core registers */
 325 #define PCI_16KBB0_WINSZ        (16 * 1024)     /* bar0 window size */
 326 #define PCI_SECOND_BAR0_OFFSET  (16 * 1024)     /* secondary  bar 0 window */
 327
 328 /* On AI chips we have a second window to map DMP regs are mapped: */
 329 #define PCI_16KB0_WIN2_OFFSET   (4 * 1024)      /* bar0 + 4K is "Window 2" */
 330
 331 /* PCI_INT_STATUS */
 332 #define PCI_SBIM_STATUS_SERR    0x4     /* backplane SBErr interrupt status */
 333
 334 /* PCI_INT_MASK */
 335 #define PCI_SBIM_SHIFT          8       /* backplane core interrupt mask bits offset */
 336 #define PCI_SBIM_MASK           0xff00  /* backplane core interrupt mask */
 337 #define PCI_SBIM_MASK_SERR      0x4     /* backplane SBErr interrupt mask */
 338 #define PCI_CTO_INT_SHIFT       16      /* backplane SBErr interrupt mask */
 339 #define PCI_CTO_INT_MASK        (1 << PCI_CTO_INT_SHIFT)        /* backplane SBErr interrupt mask */
 340
 341 /* PCI_SPROM_CONTROL */
 342 #define SPROM_SZ_MSK            0x02    /* SPROM Size Mask */
 343 #define SPROM_LOCKED            0x08    /* SPROM Locked */
 344 #define SPROM_BLANK             0x04    /* indicating a blank SPROM */
 345 #define SPROM_WRITEEN           0x10    /* SPROM write enable */
 346 #define SPROM_BOOTROM_WE        0x20    /* external bootrom write enable */
 347 #define SPROM_BACKPLANE_EN      0x40    /* Enable indirect backplane access */
 348 #define SPROM_OTPIN_USE         0x80    /* device OTP In use */
 349 #define SPROM_CFG_TO_SB_RST     0x400   /* backplane reset */
 350
 351 /* Bits in PCI command and status regs */
 352 #define PCI_CMD_IO              0x00000001      /* I/O enable */
 353 #define PCI_CMD_MEMORY          0x00000002      /* Memory enable */
 354 #define PCI_CMD_MASTER          0x00000004      /* Master enable */
 355 #define PCI_CMD_SPECIAL         0x00000008      /* Special cycles enable */
 356 #define PCI_CMD_INVALIDATE      0x00000010      /* Invalidate? */
 357 #define PCI_CMD_VGA_PAL         0x00000040      /* VGA Palate */
 358 #define PCI_STAT_TA             0x08000000      /* target abort status */
 359
 360 /* Header types */
 361 #define PCI_HEADER_MULTI        0x80
 362 #define PCI_HEADER_MASK         0x7f
 363 typedef enum {
 364         PCI_HEADER_NORMAL,
 365         PCI_HEADER_BRIDGE,
 366         PCI_HEADER_CARDBUS
 367 } pci_header_types;
 368
 369 #define PCI_CONFIG_SPACE_SIZE   256
 370
 371 #define DWORD_ALIGN(x)  (x & ~(0x03))
 372 #define BYTE_POS(x) (x & 0x3)
 373 #define WORD_POS(x) (x & 0x1)
 374
 375 #define BYTE_SHIFT(x)  (8 * BYTE_POS(x))
 376 #define WORD_SHIFT(x)  (16 * WORD_POS(x))
 377
 378 #define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
 379 #define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
 380
 381 #define read_pci_cfg_byte(a) \
 382         (BYTE_VAL(OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4), a) & 0xff)
 383
 384 #define read_pci_cfg_word(a) \
 385         (WORD_VAL(OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4), a) & 0xffff)
 386
 387 #define write_pci_cfg_byte(a, val) do { \
 388         uint32 tmpval; \
 389         tmpval = (OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4) & ~0xFF << BYTE_POS(a)) | \
 390                 val << BYTE_POS(a); \
 391         OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \
 392         } while (0)
 393
 394 #define write_pci_cfg_word(a, val) do { \
 395         uint32 tmpval; \
 396         tmpval = (OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4) & ~0xFFFF << WORD_POS(a)) | \
 397                 val << WORD_POS(a); \
 398         OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \
 399         } while (0)
 400
 401 #endif  /* _h_pcicfg_ */