SDLX_MSG(("%s: disable_irq_wake\n", __FUNCTION__));
bcmsdh_osinfo->oob_irq_wake_enabled = FALSE;
#else
+/*
err = enable_irq_wake(bcmsdh_osinfo->oob_irq_num);
if (err)
SDLX_MSG(("%s: enable_irq_wake failed with %d\n", __FUNCTION__, err));
else
+*/
bcmsdh_osinfo->oob_irq_wake_enabled = TRUE;
#endif
return 0;
void bcmsdh_oob_intr_unregister(bcmsdh_info_t *bcmsdh)
{
- int err = 0;
+ /*int err = 0;*/
bcmsdh_os_info_t *bcmsdh_osinfo = bcmsdh->os_cxt;
SDLX_MSG(("%s: Enter\n", __FUNCTION__));
SDLX_MSG(("%s: irq is not registered\n", __FUNCTION__));
return;
}
+/*
if (bcmsdh_osinfo->oob_irq_wake_enabled) {
err = disable_irq_wake(bcmsdh_osinfo->oob_irq_num);
if (!err)
bcmsdh_osinfo->oob_irq_wake_enabled = FALSE;
}
+*/
if (bcmsdh_osinfo->oob_irq_enabled) {
disable_irq(bcmsdh_osinfo->oob_irq_num);
bcmsdh_osinfo->oob_irq_enabled = FALSE;
#define FW_BCM4358A3 "fw_bcm4358a3_ag"\r
#define FW_BCM4359B1 "fw_bcm4359b1_ag"\r
#define FW_BCM4359C0 "fw_bcm4359c0_ag"\r
+#define FW_BCM43751 "fw_bcm43751_ag"\r
\r
#define CLM_BCM43013B0 "clm_bcm43013b0"\r
#endif\r
else if (chiprev == BCM4359C0_CHIP_REV)\r
strcpy(&fw_path[i], FW_BCM4359C0);\r
break;\r
+ case BCM43751_CHIP_ID:\r
+ strcpy(&fw_path[i], FW_BCM43751);\r
+ break;\r
#endif\r
#ifdef BCMPCIE\r
case BCM4354_CHIP_ID:\r
(bus->sih->chip == BCM4371_CHIP_ID) ||
(BCM4349_CHIP(bus->sih->chip)) ||
(bus->sih->chip == BCM4350_CHIP_ID) ||
+ (bus->sih->chip == BCM43751_CHIP_ID) ||
(bus->sih->chip == BCM43012_CHIP_ID)) {
core_capext = TRUE;
} else {
if (CHIPID(bus->sih->chip) == BCM43430_CHIP_ID ||
CHIPID(bus->sih->chip) == BCM43018_CHIP_ID ||
CHIPID(bus->sih->chip) == BCM4339_CHIP_ID ||
+ CHIPID(bus->sih->chip) == BCM43751_CHIP_ID ||
CHIPID(bus->sih->chip) == BCM43012_CHIP_ID)
dhdsdio_devcap_set(bus, SDIOD_CCCR_BRCM_CARDCAP_CMD_NODEC);
if (chipid == BCM43012_CHIP_ID)
return TRUE;
+ if (chipid == BCM43751_CHIP_ID)
+ return TRUE;
+
return FALSE;
}
case BCM4347_CHIP_GRPID:
bus->dongle_ram_base = CR4_4347_RAM_BASE;
break;
+ case BCM43751_CHIP_ID:
+ bus->dongle_ram_base = CR4_43751_RAM_BASE;
+ break;
default:
bus->dongle_ram_base = 0;
DHD_ERROR(("%s: WARNING: Using default ram base at 0x%x\n",
#define BCM43455_CHIP_ID 43455 /* 43455 chipcommon chipid */
#define BCM43457_CHIP_ID 43457 /* 43457 chipcommon chipid */
#define BCM43458_CHIP_ID 43458 /* 43458 chipcommon chipid */
+#define BCM43751_CHIP_ID 0x4362 /* 43751 chipcommon chipid */
#define BCM4345_CHIP(chipid) (CHIPID(chipid) == BCM4345_CHIP_ID || \
CHIPID(chipid) == BCM43454_CHIP_ID || \
#define CA7_4365_RAM_BASE (0x200000)
#define CR4_4347_RAM_BASE (0x170000)
+#define CR4_43751_RAM_BASE (0x170000)
/* 4335 chip OTP present & OTP select bits. */
#define SPROM4335_OTP_SELECT 0x00000010