1 /******************************************************************************
5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/etherdevice.h>
32 #include <linux/sched.h>
33 #include <net/mac80211.h>
38 #include "iwl-helpers.h"
40 #define ICT_COUNT (PAGE_SIZE/sizeof(u32))
43 void iwl_free_isr_ict(struct iwl_priv
*priv
)
45 if (priv
->ict_tbl_vir
) {
46 dma_free_coherent(&priv
->pci_dev
->dev
,
47 (sizeof(u32
) * ICT_COUNT
) + PAGE_SIZE
,
48 priv
->ict_tbl_vir
, priv
->ict_tbl_dma
);
49 priv
->ict_tbl_vir
= NULL
;
54 /* allocate dram shared table it is a PAGE_SIZE aligned
55 * also reset all data related to ICT table interrupt.
57 int iwl_alloc_isr_ict(struct iwl_priv
*priv
)
60 if (priv
->cfg
->use_isr_legacy
)
62 /* allocate shrared data table */
63 priv
->ict_tbl_vir
= dma_alloc_coherent(&priv
->pci_dev
->dev
,
64 (sizeof(u32
) * ICT_COUNT
) + PAGE_SIZE
,
65 &priv
->ict_tbl_dma
, GFP_KERNEL
);
66 if (!priv
->ict_tbl_vir
)
69 /* align table to PAGE_SIZE boundry */
70 priv
->aligned_ict_tbl_dma
= ALIGN(priv
->ict_tbl_dma
, PAGE_SIZE
);
72 IWL_DEBUG_ISR(priv
, "ict dma addr %Lx dma aligned %Lx diff %d\n",
73 (unsigned long long)priv
->ict_tbl_dma
,
74 (unsigned long long)priv
->aligned_ict_tbl_dma
,
75 (int)(priv
->aligned_ict_tbl_dma
- priv
->ict_tbl_dma
));
77 priv
->ict_tbl
= priv
->ict_tbl_vir
+
78 (priv
->aligned_ict_tbl_dma
- priv
->ict_tbl_dma
);
80 IWL_DEBUG_ISR(priv
, "ict vir addr %p vir aligned %p diff %d\n",
81 priv
->ict_tbl
, priv
->ict_tbl_vir
,
82 (int)(priv
->aligned_ict_tbl_dma
- priv
->ict_tbl_dma
));
84 /* reset table and index to all 0 */
85 memset(priv
->ict_tbl_vir
,0, (sizeof(u32
) * ICT_COUNT
) + PAGE_SIZE
);
88 /* add periodic RX interrupt */
89 priv
->inta_mask
|= CSR_INT_BIT_RX_PERIODIC
;
93 /* Device is going up inform it about using ICT interrupt table,
94 * also we need to tell the driver to start using ICT interrupt.
96 int iwl_reset_ict(struct iwl_priv
*priv
)
101 if (!priv
->ict_tbl_vir
)
104 spin_lock_irqsave(&priv
->lock
, flags
);
105 iwl_disable_interrupts(priv
);
107 memset(&priv
->ict_tbl
[0], 0, sizeof(u32
) * ICT_COUNT
);
109 val
= priv
->aligned_ict_tbl_dma
>> PAGE_SHIFT
;
111 val
|= CSR_DRAM_INT_TBL_ENABLE
;
112 val
|= CSR_DRAM_INIT_TBL_WRAP_CHECK
;
114 IWL_DEBUG_ISR(priv
, "CSR_DRAM_INT_TBL_REG =0x%X "
115 "aligned dma address %Lx\n",
116 val
, (unsigned long long)priv
->aligned_ict_tbl_dma
);
118 iwl_write32(priv
, CSR_DRAM_INT_TBL_REG
, val
);
119 priv
->use_ict
= true;
121 iwl_write32(priv
, CSR_INT
, priv
->inta_mask
);
122 iwl_enable_interrupts(priv
);
123 spin_unlock_irqrestore(&priv
->lock
, flags
);
128 /* Device is going down disable ict interrupt usage */
129 void iwl_disable_ict(struct iwl_priv
*priv
)
133 spin_lock_irqsave(&priv
->lock
, flags
);
134 priv
->use_ict
= false;
135 spin_unlock_irqrestore(&priv
->lock
, flags
);
138 static irqreturn_t
iwl_isr(int irq
, void *data
)
140 struct iwl_priv
*priv
= data
;
142 #ifdef CONFIG_IWLWIFI_DEBUG
148 spin_lock(&priv
->lock
);
150 /* Disable (but don't clear!) interrupts here to avoid
151 * back-to-back ISRs and sporadic interrupts from our NIC.
152 * If we have something to service, the tasklet will re-enable ints.
153 * If we *don't* have something, we'll re-enable before leaving here. */
154 inta_mask
= iwl_read32(priv
, CSR_INT_MASK
); /* just for debug */
155 iwl_write32(priv
, CSR_INT_MASK
, 0x00000000);
157 /* Discover which interrupts are active/pending */
158 inta
= iwl_read32(priv
, CSR_INT
);
160 /* Ignore interrupt if there's nothing in NIC to service.
161 * This may be due to IRQ shared with another device,
162 * or due to sporadic interrupts thrown from our NIC. */
164 IWL_DEBUG_ISR(priv
, "Ignore interrupt, inta == 0\n");
168 if ((inta
== 0xFFFFFFFF) || ((inta
& 0xFFFFFFF0) == 0xa5a5a5a0)) {
169 /* Hardware disappeared. It might have already raised
171 IWL_WARN(priv
, "HARDWARE GONE?? INTA == 0x%08x\n", inta
);
175 #ifdef CONFIG_IWLWIFI_DEBUG
176 if (iwl_get_debug_level(priv
) & (IWL_DL_ISR
)) {
177 inta_fh
= iwl_read32(priv
, CSR_FH_INT_STATUS
);
178 IWL_DEBUG_ISR(priv
, "ISR inta 0x%08x, enabled 0x%08x, "
179 "fh 0x%08x\n", inta
, inta_mask
, inta_fh
);
184 /* iwl_irq_tasklet() will service interrupts and re-enable them */
186 tasklet_schedule(&priv
->irq_tasklet
);
187 else if (test_bit(STATUS_INT_ENABLED
, &priv
->status
) && !priv
->inta
)
188 iwl_enable_interrupts(priv
);
191 spin_unlock(&priv
->lock
);
195 /* re-enable interrupts here since we don't have anything to service. */
196 /* only Re-enable if diabled by irq and no schedules tasklet. */
197 if (test_bit(STATUS_INT_ENABLED
, &priv
->status
) && !priv
->inta
)
198 iwl_enable_interrupts(priv
);
200 spin_unlock(&priv
->lock
);
204 /* interrupt handler using ict table, with this interrupt driver will
205 * stop using INTA register to get device's interrupt, reading this register
206 * is expensive, device will write interrupts in ICT dram table, increment
207 * index then will fire interrupt to driver, driver will OR all ICT table
208 * entries from current index up to table entry with 0 value. the result is
209 * the interrupt we need to service, driver will set the entries back to 0 and
212 irqreturn_t
iwl_isr_ict(int irq
, void *data
)
214 struct iwl_priv
*priv
= data
;
221 /* dram interrupt table not set yet,
222 * use legacy interrupt.
225 return iwl_isr(irq
, data
);
227 spin_lock(&priv
->lock
);
229 /* Disable (but don't clear!) interrupts here to avoid
230 * back-to-back ISRs and sporadic interrupts from our NIC.
231 * If we have something to service, the tasklet will re-enable ints.
232 * If we *don't* have something, we'll re-enable before leaving here.
234 inta_mask
= iwl_read32(priv
, CSR_INT_MASK
); /* just for debug */
235 iwl_write32(priv
, CSR_INT_MASK
, 0x00000000);
238 /* Ignore interrupt if there's nothing in NIC to service.
239 * This may be due to IRQ shared with another device,
240 * or due to sporadic interrupts thrown from our NIC. */
241 if (!priv
->ict_tbl
[priv
->ict_index
]) {
242 IWL_DEBUG_ISR(priv
, "Ignore interrupt, inta == 0\n");
246 /* read all entries that not 0 start with ict_index */
247 while (priv
->ict_tbl
[priv
->ict_index
]) {
249 val
|= le32_to_cpu(priv
->ict_tbl
[priv
->ict_index
]);
250 IWL_DEBUG_ISR(priv
, "ICT index %d value 0x%08X\n",
252 le32_to_cpu(priv
->ict_tbl
[priv
->ict_index
]));
253 priv
->ict_tbl
[priv
->ict_index
] = 0;
254 priv
->ict_index
= iwl_queue_inc_wrap(priv
->ict_index
,
259 /* We should not get this value, just ignore it. */
260 if (val
== 0xffffffff)
264 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
265 * (bit 15 before shifting it to 31) to clear when using interrupt
266 * coalescing. fortunately, bits 18 and 19 stay set when this happens
267 * so we use them to decide on the real state of the Rx bit.
268 * In order words, bit 15 is set if bit 18 or bit 19 are set.
273 inta
= (0xff & val
) | ((0xff00 & val
) << 16);
274 IWL_DEBUG_ISR(priv
, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
275 inta
, inta_mask
, val
);
277 inta
&= priv
->inta_mask
;
280 /* iwl_irq_tasklet() will service interrupts and re-enable them */
282 tasklet_schedule(&priv
->irq_tasklet
);
283 else if (test_bit(STATUS_INT_ENABLED
, &priv
->status
) && !priv
->inta
) {
284 /* Allow interrupt if was disabled by this handler and
285 * no tasklet was schedules, We should not enable interrupt,
286 * tasklet will enable it.
288 iwl_enable_interrupts(priv
);
291 spin_unlock(&priv
->lock
);
295 /* re-enable interrupts here since we don't have anything to service.
296 * only Re-enable if disabled by irq.
298 if (test_bit(STATUS_INT_ENABLED
, &priv
->status
) && !priv
->inta
)
299 iwl_enable_interrupts(priv
);
301 spin_unlock(&priv
->lock
);