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1 | /****************************************************************************** |
2 | * | |
3 | * GPL LICENSE SUMMARY | |
4 | * | |
5 | * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of version 2 of the GNU General Public License as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
19 | * USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution | |
22 | * in the file called LICENSE.GPL. | |
23 | * | |
24 | * Contact Information: | |
25 | * Intel Linux Wireless <ilw@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | *****************************************************************************/ | |
28 | ||
29 | #include <linux/kernel.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/etherdevice.h> | |
32 | #include <linux/sched.h> | |
33 | #include <net/mac80211.h> | |
34 | ||
35 | #include "iwl-dev.h" | |
36 | #include "iwl-core.h" | |
37 | #include "iwl-agn.h" | |
38 | #include "iwl-helpers.h" | |
39 | ||
40 | #define ICT_COUNT (PAGE_SIZE/sizeof(u32)) | |
41 | ||
42 | /* Free dram table */ | |
43 | void iwl_free_isr_ict(struct iwl_priv *priv) | |
44 | { | |
45 | if (priv->ict_tbl_vir) { | |
46 | dma_free_coherent(&priv->pci_dev->dev, | |
47 | (sizeof(u32) * ICT_COUNT) + PAGE_SIZE, | |
48 | priv->ict_tbl_vir, priv->ict_tbl_dma); | |
49 | priv->ict_tbl_vir = NULL; | |
50 | } | |
51 | } | |
52 | ||
53 | ||
54 | /* allocate dram shared table it is a PAGE_SIZE aligned | |
55 | * also reset all data related to ICT table interrupt. | |
56 | */ | |
57 | int iwl_alloc_isr_ict(struct iwl_priv *priv) | |
58 | { | |
59 | ||
60 | if (priv->cfg->use_isr_legacy) | |
61 | return 0; | |
62 | /* allocate shrared data table */ | |
63 | priv->ict_tbl_vir = dma_alloc_coherent(&priv->pci_dev->dev, | |
64 | (sizeof(u32) * ICT_COUNT) + PAGE_SIZE, | |
65 | &priv->ict_tbl_dma, GFP_KERNEL); | |
66 | if (!priv->ict_tbl_vir) | |
67 | return -ENOMEM; | |
68 | ||
69 | /* align table to PAGE_SIZE boundry */ | |
70 | priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE); | |
71 | ||
72 | IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n", | |
73 | (unsigned long long)priv->ict_tbl_dma, | |
74 | (unsigned long long)priv->aligned_ict_tbl_dma, | |
75 | (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma)); | |
76 | ||
77 | priv->ict_tbl = priv->ict_tbl_vir + | |
78 | (priv->aligned_ict_tbl_dma - priv->ict_tbl_dma); | |
79 | ||
80 | IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n", | |
81 | priv->ict_tbl, priv->ict_tbl_vir, | |
82 | (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma)); | |
83 | ||
84 | /* reset table and index to all 0 */ | |
85 | memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE); | |
86 | priv->ict_index = 0; | |
87 | ||
88 | /* add periodic RX interrupt */ | |
89 | priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC; | |
90 | return 0; | |
91 | } | |
92 | ||
93 | /* Device is going up inform it about using ICT interrupt table, | |
94 | * also we need to tell the driver to start using ICT interrupt. | |
95 | */ | |
96 | int iwl_reset_ict(struct iwl_priv *priv) | |
97 | { | |
98 | u32 val; | |
99 | unsigned long flags; | |
100 | ||
101 | if (!priv->ict_tbl_vir) | |
102 | return 0; | |
103 | ||
104 | spin_lock_irqsave(&priv->lock, flags); | |
105 | iwl_disable_interrupts(priv); | |
106 | ||
107 | memset(&priv->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT); | |
108 | ||
109 | val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT; | |
110 | ||
111 | val |= CSR_DRAM_INT_TBL_ENABLE; | |
112 | val |= CSR_DRAM_INIT_TBL_WRAP_CHECK; | |
113 | ||
114 | IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X " | |
115 | "aligned dma address %Lx\n", | |
116 | val, (unsigned long long)priv->aligned_ict_tbl_dma); | |
117 | ||
118 | iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val); | |
119 | priv->use_ict = true; | |
120 | priv->ict_index = 0; | |
121 | iwl_write32(priv, CSR_INT, priv->inta_mask); | |
122 | iwl_enable_interrupts(priv); | |
123 | spin_unlock_irqrestore(&priv->lock, flags); | |
124 | ||
125 | return 0; | |
126 | } | |
127 | ||
128 | /* Device is going down disable ict interrupt usage */ | |
129 | void iwl_disable_ict(struct iwl_priv *priv) | |
130 | { | |
131 | unsigned long flags; | |
132 | ||
133 | spin_lock_irqsave(&priv->lock, flags); | |
134 | priv->use_ict = false; | |
135 | spin_unlock_irqrestore(&priv->lock, flags); | |
136 | } | |
137 | ||
138 | static irqreturn_t iwl_isr(int irq, void *data) | |
139 | { | |
140 | struct iwl_priv *priv = data; | |
141 | u32 inta, inta_mask; | |
142 | #ifdef CONFIG_IWLWIFI_DEBUG | |
143 | u32 inta_fh; | |
144 | #endif | |
145 | if (!priv) | |
146 | return IRQ_NONE; | |
147 | ||
148 | spin_lock(&priv->lock); | |
149 | ||
150 | /* Disable (but don't clear!) interrupts here to avoid | |
151 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
152 | * If we have something to service, the tasklet will re-enable ints. | |
153 | * If we *don't* have something, we'll re-enable before leaving here. */ | |
154 | inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */ | |
155 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); | |
156 | ||
157 | /* Discover which interrupts are active/pending */ | |
158 | inta = iwl_read32(priv, CSR_INT); | |
159 | ||
160 | /* Ignore interrupt if there's nothing in NIC to service. | |
161 | * This may be due to IRQ shared with another device, | |
162 | * or due to sporadic interrupts thrown from our NIC. */ | |
163 | if (!inta) { | |
164 | IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n"); | |
165 | goto none; | |
166 | } | |
167 | ||
168 | if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { | |
169 | /* Hardware disappeared. It might have already raised | |
170 | * an interrupt */ | |
171 | IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta); | |
172 | goto unplugged; | |
173 | } | |
174 | ||
175 | #ifdef CONFIG_IWLWIFI_DEBUG | |
176 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { | |
177 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
178 | IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, " | |
179 | "fh 0x%08x\n", inta, inta_mask, inta_fh); | |
180 | } | |
181 | #endif | |
182 | ||
183 | priv->inta |= inta; | |
184 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ | |
185 | if (likely(inta)) | |
186 | tasklet_schedule(&priv->irq_tasklet); | |
187 | else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) | |
188 | iwl_enable_interrupts(priv); | |
189 | ||
190 | unplugged: | |
191 | spin_unlock(&priv->lock); | |
192 | return IRQ_HANDLED; | |
193 | ||
194 | none: | |
195 | /* re-enable interrupts here since we don't have anything to service. */ | |
196 | /* only Re-enable if diabled by irq and no schedules tasklet. */ | |
197 | if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) | |
198 | iwl_enable_interrupts(priv); | |
199 | ||
200 | spin_unlock(&priv->lock); | |
201 | return IRQ_NONE; | |
202 | } | |
203 | ||
204 | /* interrupt handler using ict table, with this interrupt driver will | |
205 | * stop using INTA register to get device's interrupt, reading this register | |
206 | * is expensive, device will write interrupts in ICT dram table, increment | |
207 | * index then will fire interrupt to driver, driver will OR all ICT table | |
208 | * entries from current index up to table entry with 0 value. the result is | |
209 | * the interrupt we need to service, driver will set the entries back to 0 and | |
210 | * set index. | |
211 | */ | |
212 | irqreturn_t iwl_isr_ict(int irq, void *data) | |
213 | { | |
214 | struct iwl_priv *priv = data; | |
215 | u32 inta, inta_mask; | |
216 | u32 val = 0; | |
217 | ||
218 | if (!priv) | |
219 | return IRQ_NONE; | |
220 | ||
221 | /* dram interrupt table not set yet, | |
222 | * use legacy interrupt. | |
223 | */ | |
224 | if (!priv->use_ict) | |
225 | return iwl_isr(irq, data); | |
226 | ||
227 | spin_lock(&priv->lock); | |
228 | ||
229 | /* Disable (but don't clear!) interrupts here to avoid | |
230 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
231 | * If we have something to service, the tasklet will re-enable ints. | |
232 | * If we *don't* have something, we'll re-enable before leaving here. | |
233 | */ | |
234 | inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */ | |
235 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); | |
236 | ||
237 | ||
238 | /* Ignore interrupt if there's nothing in NIC to service. | |
239 | * This may be due to IRQ shared with another device, | |
240 | * or due to sporadic interrupts thrown from our NIC. */ | |
241 | if (!priv->ict_tbl[priv->ict_index]) { | |
242 | IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n"); | |
243 | goto none; | |
244 | } | |
245 | ||
246 | /* read all entries that not 0 start with ict_index */ | |
247 | while (priv->ict_tbl[priv->ict_index]) { | |
248 | ||
249 | val |= le32_to_cpu(priv->ict_tbl[priv->ict_index]); | |
250 | IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n", | |
251 | priv->ict_index, | |
252 | le32_to_cpu(priv->ict_tbl[priv->ict_index])); | |
253 | priv->ict_tbl[priv->ict_index] = 0; | |
254 | priv->ict_index = iwl_queue_inc_wrap(priv->ict_index, | |
255 | ICT_COUNT); | |
256 | ||
257 | } | |
258 | ||
259 | /* We should not get this value, just ignore it. */ | |
260 | if (val == 0xffffffff) | |
261 | val = 0; | |
262 | ||
263 | /* | |
264 | * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit | |
265 | * (bit 15 before shifting it to 31) to clear when using interrupt | |
266 | * coalescing. fortunately, bits 18 and 19 stay set when this happens | |
267 | * so we use them to decide on the real state of the Rx bit. | |
268 | * In order words, bit 15 is set if bit 18 or bit 19 are set. | |
269 | */ | |
270 | if (val & 0xC0000) | |
271 | val |= 0x8000; | |
272 | ||
273 | inta = (0xff & val) | ((0xff00 & val) << 16); | |
274 | IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n", | |
275 | inta, inta_mask, val); | |
276 | ||
277 | inta &= priv->inta_mask; | |
278 | priv->inta |= inta; | |
279 | ||
280 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ | |
281 | if (likely(inta)) | |
282 | tasklet_schedule(&priv->irq_tasklet); | |
283 | else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) { | |
284 | /* Allow interrupt if was disabled by this handler and | |
285 | * no tasklet was schedules, We should not enable interrupt, | |
286 | * tasklet will enable it. | |
287 | */ | |
288 | iwl_enable_interrupts(priv); | |
289 | } | |
290 | ||
291 | spin_unlock(&priv->lock); | |
292 | return IRQ_HANDLED; | |
293 | ||
294 | none: | |
295 | /* re-enable interrupts here since we don't have anything to service. | |
296 | * only Re-enable if disabled by irq. | |
297 | */ | |
298 | if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) | |
299 | iwl_enable_interrupts(priv); | |
300 | ||
301 | spin_unlock(&priv->lock); | |
302 | return IRQ_NONE; | |
303 | } |