1 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
3 * This driver supports the memory controllers found on the Intel
4 * processor family Sandy Bridge.
6 * This file may be distributed under the terms of the
7 * GNU General Public License version 2 only.
9 * Copyright (c) 2011 by:
10 * Mauro Carvalho Chehab <mchehab@redhat.com>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/pci_ids.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/edac.h>
20 #include <linux/mmzone.h>
21 #include <linux/smp.h>
22 #include <linux/bitmap.h>
23 #include <linux/math64.h>
24 #include <asm/processor.h>
27 #include "edac_core.h"
30 static LIST_HEAD(sbridge_edac_list
);
31 static DEFINE_MUTEX(sbridge_edac_lock
);
35 * Alter this version for the module when modifications are made
37 #define SBRIDGE_REVISION " Ver: 1.0.0 "
38 #define EDAC_MOD_STR "sbridge_edac"
43 #define sbridge_printk(level, fmt, arg...) \
44 edac_printk(level, "sbridge", fmt, ##arg)
46 #define sbridge_mc_printk(mci, level, fmt, arg...) \
47 edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
50 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
52 #define GET_BITFIELD(v, lo, hi) \
53 (((v) & ((1ULL << ((hi) - (lo) + 1)) - 1) << (lo)) >> (lo))
56 * sbridge Memory Controller Registers
60 * FIXME: For now, let's order by device function, as it makes
61 * easier for driver's development process. This table should be
62 * moved to pci_id.h when submitted upstream
64 #define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0 0x3cf4 /* 12.6 */
65 #define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1 0x3cf6 /* 12.7 */
66 #define PCI_DEVICE_ID_INTEL_SBRIDGE_BR 0x3cf5 /* 13.6 */
67 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0 0x3ca0 /* 14.0 */
68 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA 0x3ca8 /* 15.0 */
69 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS 0x3c71 /* 15.1 */
70 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0 0x3caa /* 15.2 */
71 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1 0x3cab /* 15.3 */
72 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2 0x3cac /* 15.4 */
73 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3 0x3cad /* 15.5 */
74 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO 0x3cb8 /* 17.0 */
77 * Currently, unused, but will be needed in the future
78 * implementations, as they hold the error counters
80 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0 0x3c72 /* 16.2 */
81 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1 0x3c73 /* 16.3 */
82 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2 0x3c76 /* 16.6 */
83 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3 0x3c77 /* 16.7 */
85 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */
86 static const u32 dram_rule
[] = {
87 0x80, 0x88, 0x90, 0x98, 0xa0,
88 0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
90 #define MAX_SAD ARRAY_SIZE(dram_rule)
92 #define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff)
93 #define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3)
94 #define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1)
95 #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
97 static char *get_dram_attr(u32 reg
)
99 switch(DRAM_ATTR(reg
)) {
111 static const u32 interleave_list
[] = {
112 0x84, 0x8c, 0x94, 0x9c, 0xa4,
113 0xac, 0xb4, 0xbc, 0xc4, 0xcc,
115 #define MAX_INTERLEAVE ARRAY_SIZE(interleave_list)
117 #define SAD_PKG0(reg) GET_BITFIELD(reg, 0, 2)
118 #define SAD_PKG1(reg) GET_BITFIELD(reg, 3, 5)
119 #define SAD_PKG2(reg) GET_BITFIELD(reg, 8, 10)
120 #define SAD_PKG3(reg) GET_BITFIELD(reg, 11, 13)
121 #define SAD_PKG4(reg) GET_BITFIELD(reg, 16, 18)
122 #define SAD_PKG5(reg) GET_BITFIELD(reg, 19, 21)
123 #define SAD_PKG6(reg) GET_BITFIELD(reg, 24, 26)
124 #define SAD_PKG7(reg) GET_BITFIELD(reg, 27, 29)
126 static inline int sad_pkg(u32 reg
, int interleave
)
128 switch (interleave
) {
130 return SAD_PKG0(reg
);
132 return SAD_PKG1(reg
);
134 return SAD_PKG2(reg
);
136 return SAD_PKG3(reg
);
138 return SAD_PKG4(reg
);
140 return SAD_PKG5(reg
);
142 return SAD_PKG6(reg
);
144 return SAD_PKG7(reg
);
150 /* Devices 12 Function 7 */
155 #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)
156 #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
158 /* Device 13 Function 6 */
160 #define SAD_TARGET 0xf0
162 #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)
164 #define SAD_CONTROL 0xf4
166 #define NODE_ID(reg) GET_BITFIELD(reg, 0, 2)
168 /* Device 14 function 0 */
170 static const u32 tad_dram_rule
[] = {
171 0x40, 0x44, 0x48, 0x4c,
172 0x50, 0x54, 0x58, 0x5c,
173 0x60, 0x64, 0x68, 0x6c,
175 #define MAX_TAD ARRAY_SIZE(tad_dram_rule)
177 #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
178 #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)
179 #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9)
180 #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7)
181 #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5)
182 #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3)
183 #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1)
185 /* Device 15, function 0 */
189 #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2)
190 #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1)
191 #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0)
193 /* Device 15, function 1 */
195 #define RASENABLES 0xac
196 #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0)
198 /* Device 15, functions 2-5 */
200 static const int mtr_regs
[] = {
204 #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19)
205 #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14)
206 #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13)
207 #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4)
208 #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1)
210 static const u32 tad_ch_nilv_offset
[] = {
211 0x90, 0x94, 0x98, 0x9c,
212 0xa0, 0xa4, 0xa8, 0xac,
213 0xb0, 0xb4, 0xb8, 0xbc,
215 #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29)
216 #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26)
218 static const u32 rir_way_limit
[] = {
219 0x108, 0x10c, 0x110, 0x114, 0x118,
221 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
223 #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31)
224 #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29)
225 #define RIR_LIMIT(reg) ((GET_BITFIELD(reg, 1, 10) << 29)| 0x1fffffff)
227 #define MAX_RIR_WAY 8
229 static const u32 rir_offset
[MAX_RIR_RANGES
][MAX_RIR_WAY
] = {
230 { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
231 { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
232 { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
233 { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
234 { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
237 #define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19)
238 #define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14)
240 /* Device 16, functions 2-7 */
243 * FIXME: Implement the error count reads directly
246 static const u32 correrrcnt
[] = {
247 0x104, 0x108, 0x10c, 0x110,
250 #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31)
251 #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30)
252 #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15)
253 #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14)
255 static const u32 correrrthrsld
[] = {
256 0x11c, 0x120, 0x124, 0x128,
259 #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30)
260 #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14)
263 /* Device 17, function 0 */
265 #define RANK_CFG_A 0x0328
267 #define IS_RDIMM_ENABLED(reg) GET_BITFIELD(reg, 11, 11)
273 #define NUM_CHANNELS 4
274 #define MAX_DIMMS 3 /* Max DIMMS per channel */
275 #define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */
277 struct sbridge_info
{
281 struct sbridge_channel
{
286 struct pci_id_descr
{
293 struct pci_id_table
{
294 const struct pci_id_descr
*descr
;
299 struct list_head list
;
301 u8 node_id
, source_id
;
302 struct pci_dev
**pdev
;
304 struct mem_ctl_info
*mci
;
308 struct pci_dev
*pci_ta
, *pci_ddrio
, *pci_ras
;
309 struct pci_dev
*pci_sad0
, *pci_sad1
, *pci_ha0
;
310 struct pci_dev
*pci_br
;
311 struct pci_dev
*pci_tad
[NUM_CHANNELS
];
313 struct sbridge_dev
*sbridge_dev
;
315 struct sbridge_info info
;
316 struct sbridge_channel channel
[NUM_CHANNELS
];
318 /* Memory type detection */
319 bool is_mirrored
, is_lockstep
, is_close_pg
;
321 /* Fifo double buffers */
322 struct mce mce_entry
[MCE_LOG_LEN
];
323 struct mce mce_outentry
[MCE_LOG_LEN
];
325 /* Fifo in/out counters */
326 unsigned mce_in
, mce_out
;
328 /* Count indicator to show errors not got */
329 unsigned mce_overrun
;
331 /* Memory description */
335 #define PCI_DESCR(device, function, device_id, opt) \
337 .func = (function), \
338 .dev_id = (device_id), \
341 static const struct pci_id_descr pci_dev_descr_sbridge
[] = {
342 /* Processor Home Agent */
343 { PCI_DESCR(14, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0
, 0) },
345 /* Memory controller */
346 { PCI_DESCR(15, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA
, 0) },
347 { PCI_DESCR(15, 1, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS
, 0) },
348 { PCI_DESCR(15, 2, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0
, 0) },
349 { PCI_DESCR(15, 3, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1
, 0) },
350 { PCI_DESCR(15, 4, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2
, 0) },
351 { PCI_DESCR(15, 5, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3
, 0) },
352 { PCI_DESCR(17, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO
, 1) },
354 /* System Address Decoder */
355 { PCI_DESCR(12, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0
, 0) },
356 { PCI_DESCR(12, 7, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1
, 0) },
358 /* Broadcast Registers */
359 { PCI_DESCR(13, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_BR
, 0) },
362 #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
363 static const struct pci_id_table pci_dev_descr_sbridge_table
[] = {
364 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge
),
365 {0,} /* 0 terminated list. */
369 * pci_device_id table for which devices we are looking for
371 static DEFINE_PCI_DEVICE_TABLE(sbridge_pci_tbl
) = {
372 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA
)},
373 {0,} /* 0 terminated list. */
377 /****************************************************************************
378 Ancillary status routines
379 ****************************************************************************/
381 static inline int numrank(u32 mtr
)
383 int ranks
= (1 << RANK_CNT_BITS(mtr
));
386 edac_dbg(0, "Invalid number of ranks: %d (max = 4) raw value = %x (%04x)\n",
387 ranks
, (unsigned int)RANK_CNT_BITS(mtr
), mtr
);
394 static inline int numrow(u32 mtr
)
396 int rows
= (RANK_WIDTH_BITS(mtr
) + 12);
398 if (rows
< 13 || rows
> 18) {
399 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",
400 rows
, (unsigned int)RANK_WIDTH_BITS(mtr
), mtr
);
407 static inline int numcol(u32 mtr
)
409 int cols
= (COL_WIDTH_BITS(mtr
) + 10);
412 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",
413 cols
, (unsigned int)COL_WIDTH_BITS(mtr
), mtr
);
420 static struct sbridge_dev
*get_sbridge_dev(u8 bus
)
422 struct sbridge_dev
*sbridge_dev
;
424 list_for_each_entry(sbridge_dev
, &sbridge_edac_list
, list
) {
425 if (sbridge_dev
->bus
== bus
)
432 static struct sbridge_dev
*alloc_sbridge_dev(u8 bus
,
433 const struct pci_id_table
*table
)
435 struct sbridge_dev
*sbridge_dev
;
437 sbridge_dev
= kzalloc(sizeof(*sbridge_dev
), GFP_KERNEL
);
441 sbridge_dev
->pdev
= kzalloc(sizeof(*sbridge_dev
->pdev
) * table
->n_devs
,
443 if (!sbridge_dev
->pdev
) {
448 sbridge_dev
->bus
= bus
;
449 sbridge_dev
->n_devs
= table
->n_devs
;
450 list_add_tail(&sbridge_dev
->list
, &sbridge_edac_list
);
455 static void free_sbridge_dev(struct sbridge_dev
*sbridge_dev
)
457 list_del(&sbridge_dev
->list
);
458 kfree(sbridge_dev
->pdev
);
462 /****************************************************************************
463 Memory check routines
464 ****************************************************************************/
465 static struct pci_dev
*get_pdev_slot_func(u8 bus
, unsigned slot
,
468 struct sbridge_dev
*sbridge_dev
= get_sbridge_dev(bus
);
474 for (i
= 0; i
< sbridge_dev
->n_devs
; i
++) {
475 if (!sbridge_dev
->pdev
[i
])
478 if (PCI_SLOT(sbridge_dev
->pdev
[i
]->devfn
) == slot
&&
479 PCI_FUNC(sbridge_dev
->pdev
[i
]->devfn
) == func
) {
480 edac_dbg(1, "Associated %02x.%02x.%d with %p\n",
481 bus
, slot
, func
, sbridge_dev
->pdev
[i
]);
482 return sbridge_dev
->pdev
[i
];
490 * check_if_ecc_is_active() - Checks if ECC is active
493 static int check_if_ecc_is_active(const u8 bus
)
495 struct pci_dev
*pdev
= NULL
;
498 pdev
= get_pdev_slot_func(bus
, 15, 0);
500 sbridge_printk(KERN_ERR
, "Couldn't find PCI device "
506 pci_read_config_dword(pdev
, MCMTR
, &mcmtr
);
507 if (!IS_ECC_ENABLED(mcmtr
)) {
508 sbridge_printk(KERN_ERR
, "ECC is disabled. Aborting\n");
514 static int get_dimm_config(struct mem_ctl_info
*mci
)
516 struct sbridge_pvt
*pvt
= mci
->pvt_info
;
517 struct dimm_info
*dimm
;
518 unsigned i
, j
, banks
, ranks
, rows
, cols
, npages
;
524 pci_read_config_dword(pvt
->pci_br
, SAD_TARGET
, ®
);
525 pvt
->sbridge_dev
->source_id
= SOURCE_ID(reg
);
527 pci_read_config_dword(pvt
->pci_br
, SAD_CONTROL
, ®
);
528 pvt
->sbridge_dev
->node_id
= NODE_ID(reg
);
529 edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
530 pvt
->sbridge_dev
->mc
,
531 pvt
->sbridge_dev
->node_id
,
532 pvt
->sbridge_dev
->source_id
);
534 pci_read_config_dword(pvt
->pci_ras
, RASENABLES
, ®
);
535 if (IS_MIRROR_ENABLED(reg
)) {
536 edac_dbg(0, "Memory mirror is enabled\n");
537 pvt
->is_mirrored
= true;
539 edac_dbg(0, "Memory mirror is disabled\n");
540 pvt
->is_mirrored
= false;
543 pci_read_config_dword(pvt
->pci_ta
, MCMTR
, &pvt
->info
.mcmtr
);
544 if (IS_LOCKSTEP_ENABLED(pvt
->info
.mcmtr
)) {
545 edac_dbg(0, "Lockstep is enabled\n");
546 mode
= EDAC_S8ECD8ED
;
547 pvt
->is_lockstep
= true;
549 edac_dbg(0, "Lockstep is disabled\n");
550 mode
= EDAC_S4ECD4ED
;
551 pvt
->is_lockstep
= false;
553 if (IS_CLOSE_PG(pvt
->info
.mcmtr
)) {
554 edac_dbg(0, "address map is on closed page mode\n");
555 pvt
->is_close_pg
= true;
557 edac_dbg(0, "address map is on open page mode\n");
558 pvt
->is_close_pg
= false;
561 if (pvt
->pci_ddrio
) {
562 pci_read_config_dword(pvt
->pci_ddrio
, RANK_CFG_A
, ®
);
563 if (IS_RDIMM_ENABLED(reg
)) {
564 /* FIXME: Can also be LRDIMM */
565 edac_dbg(0, "Memory is registered\n");
568 edac_dbg(0, "Memory is unregistered\n");
572 edac_dbg(0, "Cannot determine memory type\n");
576 /* On all supported DDR3 DIMM types, there are 8 banks available */
579 for (i
= 0; i
< NUM_CHANNELS
; i
++) {
582 for (j
= 0; j
< ARRAY_SIZE(mtr_regs
); j
++) {
583 dimm
= EDAC_DIMM_PTR(mci
->layers
, mci
->dimms
, mci
->n_layers
,
585 pci_read_config_dword(pvt
->pci_tad
[i
],
587 edac_dbg(4, "Channel #%d MTR%d = %x\n", i
, j
, mtr
);
588 if (IS_DIMM_PRESENT(mtr
)) {
589 pvt
->channel
[i
].dimms
++;
591 ranks
= numrank(mtr
);
595 /* DDR3 has 8 I/O banks */
596 size
= ((u64
)rows
* cols
* banks
* ranks
) >> (20 - 3);
597 npages
= MiB_TO_PAGES(size
);
599 edac_dbg(0, "mc#%d: channel %d, dimm %d, %Ld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
600 pvt
->sbridge_dev
->mc
, i
, j
,
602 banks
, ranks
, rows
, cols
);
604 dimm
->nr_pages
= npages
;
606 dimm
->dtype
= (banks
== 8) ? DEV_X8
: DEV_X4
;
608 dimm
->edac_mode
= mode
;
609 snprintf(dimm
->label
, sizeof(dimm
->label
),
610 "CPU_SrcID#%u_Channel#%u_DIMM#%u",
611 pvt
->sbridge_dev
->source_id
, i
, j
);
619 static void get_memory_layout(const struct mem_ctl_info
*mci
)
621 struct sbridge_pvt
*pvt
= mci
->pvt_info
;
622 int i
, j
, k
, n_sads
, n_tads
, sad_interl
;
630 * Step 1) Get TOLM/TOHM ranges
633 /* Address range is 32:28 */
634 pci_read_config_dword(pvt
->pci_sad1
, TOLM
,
636 pvt
->tolm
= GET_TOLM(reg
);
637 tmp_mb
= (1 + pvt
->tolm
) >> 20;
639 gb
= div_u64_rem(tmp_mb
, 1024, &mb
);
640 edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n",
641 gb
, (mb
*1000)/1024, (u64
)pvt
->tolm
);
643 /* Address range is already 45:25 */
644 pci_read_config_dword(pvt
->pci_sad1
, TOHM
,
646 pvt
->tohm
= GET_TOHM(reg
);
647 tmp_mb
= (1 + pvt
->tohm
) >> 20;
649 gb
= div_u64_rem(tmp_mb
, 1024, &mb
);
650 edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n",
651 gb
, (mb
*1000)/1024, (u64
)pvt
->tohm
);
654 * Step 2) Get SAD range and SAD Interleave list
655 * TAD registers contain the interleave wayness. However, it
656 * seems simpler to just discover it indirectly, with the
660 for (n_sads
= 0; n_sads
< MAX_SAD
; n_sads
++) {
661 /* SAD_LIMIT Address range is 45:26 */
662 pci_read_config_dword(pvt
->pci_sad0
, dram_rule
[n_sads
],
664 limit
= SAD_LIMIT(reg
);
666 if (!DRAM_RULE_ENABLE(reg
))
672 tmp_mb
= (limit
+ 1) >> 20;
673 gb
= div_u64_rem(tmp_mb
, 1024, &mb
);
674 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
678 ((u64
)tmp_mb
) << 20L,
679 INTERLEAVE_MODE(reg
) ? "8:6" : "[8:6]XOR[18:16]",
683 pci_read_config_dword(pvt
->pci_sad0
, interleave_list
[n_sads
],
685 sad_interl
= sad_pkg(reg
, 0);
686 for (j
= 0; j
< 8; j
++) {
687 if (j
> 0 && sad_interl
== sad_pkg(reg
, j
))
690 edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
691 n_sads
, j
, sad_pkg(reg
, j
));
696 * Step 3) Get TAD range
699 for (n_tads
= 0; n_tads
< MAX_TAD
; n_tads
++) {
700 pci_read_config_dword(pvt
->pci_ha0
, tad_dram_rule
[n_tads
],
702 limit
= TAD_LIMIT(reg
);
705 tmp_mb
= (limit
+ 1) >> 20;
707 gb
= div_u64_rem(tmp_mb
, 1024, &mb
);
708 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
709 n_tads
, gb
, (mb
*1000)/1024,
710 ((u64
)tmp_mb
) << 20L,
722 * Step 4) Get TAD offsets, per each channel
724 for (i
= 0; i
< NUM_CHANNELS
; i
++) {
725 if (!pvt
->channel
[i
].dimms
)
727 for (j
= 0; j
< n_tads
; j
++) {
728 pci_read_config_dword(pvt
->pci_tad
[i
],
729 tad_ch_nilv_offset
[j
],
731 tmp_mb
= TAD_OFFSET(reg
) >> 20;
732 gb
= div_u64_rem(tmp_mb
, 1024, &mb
);
733 edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
736 ((u64
)tmp_mb
) << 20L,
742 * Step 6) Get RIR Wayness/Limit, per each channel
744 for (i
= 0; i
< NUM_CHANNELS
; i
++) {
745 if (!pvt
->channel
[i
].dimms
)
747 for (j
= 0; j
< MAX_RIR_RANGES
; j
++) {
748 pci_read_config_dword(pvt
->pci_tad
[i
],
752 if (!IS_RIR_VALID(reg
))
755 tmp_mb
= RIR_LIMIT(reg
) >> 20;
756 rir_way
= 1 << RIR_WAY(reg
);
757 gb
= div_u64_rem(tmp_mb
, 1024, &mb
);
758 edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
761 ((u64
)tmp_mb
) << 20L,
765 for (k
= 0; k
< rir_way
; k
++) {
766 pci_read_config_dword(pvt
->pci_tad
[i
],
769 tmp_mb
= RIR_OFFSET(reg
) << 6;
771 gb
= div_u64_rem(tmp_mb
, 1024, &mb
);
772 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
775 ((u64
)tmp_mb
) << 20L,
776 (u32
)RIR_RNK_TGT(reg
),
783 struct mem_ctl_info
*get_mci_for_node_id(u8 node_id
)
785 struct sbridge_dev
*sbridge_dev
;
787 list_for_each_entry(sbridge_dev
, &sbridge_edac_list
, list
) {
788 if (sbridge_dev
->node_id
== node_id
)
789 return sbridge_dev
->mci
;
794 static int get_memory_error_data(struct mem_ctl_info
*mci
,
799 char **area_type
, char *msg
)
801 struct mem_ctl_info
*new_mci
;
802 struct sbridge_pvt
*pvt
= mci
->pvt_info
;
803 int n_rir
, n_sads
, n_tads
, sad_way
, sck_xch
;
804 int sad_interl
, idx
, base_ch
;
806 unsigned sad_interleave
[MAX_INTERLEAVE
];
812 u64 ch_addr
, offset
, limit
, prv
= 0;
816 * Step 0) Check if the address is at special memory ranges
817 * The check bellow is probably enough to fill all cases where
818 * the error is not inside a memory, except for the legacy
819 * range (e. g. VGA addresses). It is unlikely, however, that the
820 * memory controller would generate an error on that range.
822 if ((addr
> (u64
) pvt
->tolm
) && (addr
< (1LL << 32))) {
823 sprintf(msg
, "Error at TOLM area, on addr 0x%08Lx", addr
);
826 if (addr
>= (u64
)pvt
->tohm
) {
827 sprintf(msg
, "Error at MMIOH area, on addr 0x%016Lx", addr
);
834 for (n_sads
= 0; n_sads
< MAX_SAD
; n_sads
++) {
835 pci_read_config_dword(pvt
->pci_sad0
, dram_rule
[n_sads
],
838 if (!DRAM_RULE_ENABLE(reg
))
841 limit
= SAD_LIMIT(reg
);
843 sprintf(msg
, "Can't discover the memory socket");
850 if (n_sads
== MAX_SAD
) {
851 sprintf(msg
, "Can't discover the memory socket");
854 *area_type
= get_dram_attr(reg
);
855 interleave_mode
= INTERLEAVE_MODE(reg
);
857 pci_read_config_dword(pvt
->pci_sad0
, interleave_list
[n_sads
],
859 sad_interl
= sad_pkg(reg
, 0);
860 for (sad_way
= 0; sad_way
< 8; sad_way
++) {
861 if (sad_way
> 0 && sad_interl
== sad_pkg(reg
, sad_way
))
863 sad_interleave
[sad_way
] = sad_pkg(reg
, sad_way
);
864 edac_dbg(0, "SAD interleave #%d: %d\n",
865 sad_way
, sad_interleave
[sad_way
]);
867 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
868 pvt
->sbridge_dev
->mc
,
873 interleave_mode
? "" : "XOR[18:16]");
875 idx
= ((addr
>> 6) ^ (addr
>> 16)) & 7;
877 idx
= (addr
>> 6) & 7;
891 sprintf(msg
, "Can't discover socket interleave");
894 *socket
= sad_interleave
[idx
];
895 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
896 idx
, sad_way
, *socket
);
899 * Move to the proper node structure, in order to access the
900 * right PCI registers
902 new_mci
= get_mci_for_node_id(*socket
);
904 sprintf(msg
, "Struct for socket #%u wasn't initialized",
912 * Step 2) Get memory channel
915 for (n_tads
= 0; n_tads
< MAX_TAD
; n_tads
++) {
916 pci_read_config_dword(pvt
->pci_ha0
, tad_dram_rule
[n_tads
],
918 limit
= TAD_LIMIT(reg
);
920 sprintf(msg
, "Can't discover the memory channel");
927 ch_way
= TAD_CH(reg
) + 1;
928 sck_way
= TAD_SOCK(reg
) + 1;
930 * FIXME: Is it right to always use channel 0 for offsets?
932 pci_read_config_dword(pvt
->pci_tad
[0],
933 tad_ch_nilv_offset
[n_tads
],
939 idx
= addr
>> (6 + sck_way
);
943 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
947 base_ch
= TAD_TGT0(reg
);
950 base_ch
= TAD_TGT1(reg
);
953 base_ch
= TAD_TGT2(reg
);
956 base_ch
= TAD_TGT3(reg
);
959 sprintf(msg
, "Can't discover the TAD target");
962 *channel_mask
= 1 << base_ch
;
964 if (pvt
->is_mirrored
) {
965 *channel_mask
|= 1 << ((base_ch
+ 2) % 4);
969 sck_xch
= 1 << sck_way
* (ch_way
>> 1);
972 sprintf(msg
, "Invalid mirror set. Can't decode addr");
976 sck_xch
= (1 << sck_way
) * ch_way
;
978 if (pvt
->is_lockstep
)
979 *channel_mask
|= 1 << ((base_ch
+ 1) % 4);
981 offset
= TAD_OFFSET(tad_offset
);
983 edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
994 /* Calculate channel address */
995 /* Remove the TAD offset */
998 sprintf(msg
, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
1003 /* Store the low bits [0:6] of the addr */
1004 ch_addr
= addr
& 0x7f;
1005 /* Remove socket wayness and remove 6 bits */
1007 addr
= div_u64(addr
, sck_xch
);
1009 /* Divide by channel way */
1010 addr
= addr
/ ch_way
;
1012 /* Recover the last 6 bits */
1013 ch_addr
|= addr
<< 6;
1016 * Step 3) Decode rank
1018 for (n_rir
= 0; n_rir
< MAX_RIR_RANGES
; n_rir
++) {
1019 pci_read_config_dword(pvt
->pci_tad
[base_ch
],
1020 rir_way_limit
[n_rir
],
1023 if (!IS_RIR_VALID(reg
))
1026 limit
= RIR_LIMIT(reg
);
1027 gb
= div_u64_rem(limit
>> 20, 1024, &mb
);
1028 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
1033 if (ch_addr
<= limit
)
1036 if (n_rir
== MAX_RIR_RANGES
) {
1037 sprintf(msg
, "Can't discover the memory rank for ch addr 0x%08Lx",
1041 rir_way
= RIR_WAY(reg
);
1042 if (pvt
->is_close_pg
)
1043 idx
= (ch_addr
>> 6);
1045 idx
= (ch_addr
>> 13); /* FIXME: Datasheet says to shift by 15 */
1046 idx
%= 1 << rir_way
;
1048 pci_read_config_dword(pvt
->pci_tad
[base_ch
],
1049 rir_offset
[n_rir
][idx
],
1051 *rank
= RIR_RNK_TGT(reg
);
1053 edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
1063 /****************************************************************************
1064 Device initialization routines: put/get, init/exit
1065 ****************************************************************************/
1068 * sbridge_put_all_devices 'put' all the devices that we have
1069 * reserved via 'get'
1071 static void sbridge_put_devices(struct sbridge_dev
*sbridge_dev
)
1076 for (i
= 0; i
< sbridge_dev
->n_devs
; i
++) {
1077 struct pci_dev
*pdev
= sbridge_dev
->pdev
[i
];
1080 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
1082 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
));
1087 static void sbridge_put_all_devices(void)
1089 struct sbridge_dev
*sbridge_dev
, *tmp
;
1091 list_for_each_entry_safe(sbridge_dev
, tmp
, &sbridge_edac_list
, list
) {
1092 sbridge_put_devices(sbridge_dev
);
1093 free_sbridge_dev(sbridge_dev
);
1098 * sbridge_get_all_devices Find and perform 'get' operation on the MCH's
1099 * device/functions we want to reference for this driver
1101 * Need to 'get' device 16 func 1 and func 2
1103 static int sbridge_get_onedevice(struct pci_dev
**prev
,
1105 const struct pci_id_table
*table
,
1106 const unsigned devno
)
1108 struct sbridge_dev
*sbridge_dev
;
1109 const struct pci_id_descr
*dev_descr
= &table
->descr
[devno
];
1111 struct pci_dev
*pdev
= NULL
;
1114 sbridge_printk(KERN_INFO
,
1115 "Seeking for: dev %02x.%d PCI ID %04x:%04x\n",
1116 dev_descr
->dev
, dev_descr
->func
,
1117 PCI_VENDOR_ID_INTEL
, dev_descr
->dev_id
);
1119 pdev
= pci_get_device(PCI_VENDOR_ID_INTEL
,
1120 dev_descr
->dev_id
, *prev
);
1128 if (dev_descr
->optional
)
1134 sbridge_printk(KERN_INFO
,
1135 "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
1136 dev_descr
->dev
, dev_descr
->func
,
1137 PCI_VENDOR_ID_INTEL
, dev_descr
->dev_id
);
1139 /* End of list, leave */
1142 bus
= pdev
->bus
->number
;
1144 sbridge_dev
= get_sbridge_dev(bus
);
1146 sbridge_dev
= alloc_sbridge_dev(bus
, table
);
1154 if (sbridge_dev
->pdev
[devno
]) {
1155 sbridge_printk(KERN_ERR
,
1156 "Duplicated device for "
1157 "dev %02x:%d.%d PCI ID %04x:%04x\n",
1158 bus
, dev_descr
->dev
, dev_descr
->func
,
1159 PCI_VENDOR_ID_INTEL
, dev_descr
->dev_id
);
1164 sbridge_dev
->pdev
[devno
] = pdev
;
1167 if (unlikely(PCI_SLOT(pdev
->devfn
) != dev_descr
->dev
||
1168 PCI_FUNC(pdev
->devfn
) != dev_descr
->func
)) {
1169 sbridge_printk(KERN_ERR
,
1170 "Device PCI ID %04x:%04x "
1171 "has dev %02x:%d.%d instead of dev %02x:%02x.%d\n",
1172 PCI_VENDOR_ID_INTEL
, dev_descr
->dev_id
,
1173 bus
, PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
),
1174 bus
, dev_descr
->dev
, dev_descr
->func
);
1178 /* Be sure that the device is enabled */
1179 if (unlikely(pci_enable_device(pdev
) < 0)) {
1180 sbridge_printk(KERN_ERR
,
1182 "dev %02x:%d.%d PCI ID %04x:%04x\n",
1183 bus
, dev_descr
->dev
, dev_descr
->func
,
1184 PCI_VENDOR_ID_INTEL
, dev_descr
->dev_id
);
1188 edac_dbg(0, "Detected dev %02x:%d.%d PCI ID %04x:%04x\n",
1189 bus
, dev_descr
->dev
, dev_descr
->func
,
1190 PCI_VENDOR_ID_INTEL
, dev_descr
->dev_id
);
1193 * As stated on drivers/pci/search.c, the reference count for
1194 * @from is always decremented if it is not %NULL. So, as we need
1195 * to get all devices up to null, we need to do a get for the device
1204 static int sbridge_get_all_devices(u8
*num_mc
)
1207 struct pci_dev
*pdev
= NULL
;
1208 const struct pci_id_table
*table
= pci_dev_descr_sbridge_table
;
1210 while (table
&& table
->descr
) {
1211 for (i
= 0; i
< table
->n_devs
; i
++) {
1214 rc
= sbridge_get_onedevice(&pdev
, num_mc
,
1221 sbridge_put_all_devices();
1232 static int mci_bind_devs(struct mem_ctl_info
*mci
,
1233 struct sbridge_dev
*sbridge_dev
)
1235 struct sbridge_pvt
*pvt
= mci
->pvt_info
;
1236 struct pci_dev
*pdev
;
1239 for (i
= 0; i
< sbridge_dev
->n_devs
; i
++) {
1240 pdev
= sbridge_dev
->pdev
[i
];
1243 slot
= PCI_SLOT(pdev
->devfn
);
1244 func
= PCI_FUNC(pdev
->devfn
);
1249 pvt
->pci_sad0
= pdev
;
1252 pvt
->pci_sad1
= pdev
;
1270 pvt
->pci_ha0
= pdev
;
1282 pvt
->pci_ras
= pdev
;
1288 pvt
->pci_tad
[func
- 2] = pdev
;
1297 pvt
->pci_ddrio
= pdev
;
1307 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1309 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
),
1313 /* Check if everything were registered */
1314 if (!pvt
->pci_sad0
|| !pvt
->pci_sad1
|| !pvt
->pci_ha0
||
1315 !pvt
-> pci_tad
|| !pvt
->pci_ras
|| !pvt
->pci_ta
)
1318 for (i
= 0; i
< NUM_CHANNELS
; i
++) {
1319 if (!pvt
->pci_tad
[i
])
1325 sbridge_printk(KERN_ERR
, "Some needed devices are missing\n");
1329 sbridge_printk(KERN_ERR
, "Device %d, function %d "
1330 "is out of the expected range\n",
1335 /****************************************************************************
1336 Error check routines
1337 ****************************************************************************/
1340 * While Sandy Bridge has error count registers, SMI BIOS read values from
1341 * and resets the counters. So, they are not reliable for the OS to read
1342 * from them. So, we have no option but to just trust on whatever MCE is
1343 * telling us about the errors.
1345 static void sbridge_mce_output_error(struct mem_ctl_info
*mci
,
1346 const struct mce
*m
)
1348 struct mem_ctl_info
*new_mci
;
1349 struct sbridge_pvt
*pvt
= mci
->pvt_info
;
1350 enum hw_event_mc_err_type tp_event
;
1351 char *type
, *optype
, msg
[256];
1352 bool ripv
= GET_BITFIELD(m
->mcgstatus
, 0, 0);
1353 bool overflow
= GET_BITFIELD(m
->status
, 62, 62);
1354 bool uncorrected_error
= GET_BITFIELD(m
->status
, 61, 61);
1355 bool recoverable
= GET_BITFIELD(m
->status
, 56, 56);
1356 u32 core_err_cnt
= GET_BITFIELD(m
->status
, 38, 52);
1357 u32 mscod
= GET_BITFIELD(m
->status
, 16, 31);
1358 u32 errcode
= GET_BITFIELD(m
->status
, 0, 15);
1359 u32 channel
= GET_BITFIELD(m
->status
, 0, 3);
1360 u32 optypenum
= GET_BITFIELD(m
->status
, 4, 6);
1361 long channel_mask
, first_channel
;
1364 char *area_type
= NULL
;
1366 if (uncorrected_error
) {
1369 tp_event
= HW_EVENT_ERR_FATAL
;
1372 tp_event
= HW_EVENT_ERR_UNCORRECTED
;
1376 tp_event
= HW_EVENT_ERR_CORRECTED
;
1380 * According with Table 15-9 of the Intel Architecture spec vol 3A,
1381 * memory errors should fit in this mask:
1382 * 000f 0000 1mmm cccc (binary)
1384 * f = Correction Report Filtering Bit. If 1, subsequent errors
1388 * If the mask doesn't match, report an error to the parsing logic
1390 if (! ((errcode
& 0xef80) == 0x80)) {
1391 optype
= "Can't parse: it is not a mem";
1393 switch (optypenum
) {
1395 optype
= "generic undef request error";
1398 optype
= "memory read error";
1401 optype
= "memory write error";
1404 optype
= "addr/cmd error";
1407 optype
= "memory scrubbing error";
1410 optype
= "reserved";
1415 rc
= get_memory_error_data(mci
, m
->addr
, &socket
,
1416 &channel_mask
, &rank
, &area_type
, msg
);
1419 new_mci
= get_mci_for_node_id(socket
);
1421 strcpy(msg
, "Error: socket got corrupted!");
1425 pvt
= mci
->pvt_info
;
1427 first_channel
= find_first_bit(&channel_mask
, NUM_CHANNELS
);
1438 * FIXME: On some memory configurations (mirror, lockstep), the
1439 * Memory Controller can't point the error to a single DIMM. The
1440 * EDAC core should be handling the channel mask, in order to point
1441 * to the group of dimm's where the error may be happening.
1443 snprintf(msg
, sizeof(msg
),
1444 "%s%s area:%s err_code:%04x:%04x socket:%d channel_mask:%ld rank:%d",
1445 overflow
? " OVERFLOW" : "",
1446 (uncorrected_error
&& recoverable
) ? " recoverable" : "",
1453 edac_dbg(0, "%s\n", msg
);
1455 /* FIXME: need support for channel mask */
1457 if (channel
== CHANNEL_UNSPECIFIED
)
1460 /* Call the helper to output message */
1461 edac_mc_handle_error(tp_event
, mci
, core_err_cnt
,
1462 m
->addr
>> PAGE_SHIFT
, m
->addr
& ~PAGE_MASK
, 0,
1467 edac_mc_handle_error(tp_event
, mci
, core_err_cnt
, 0, 0, 0,
1474 * sbridge_check_error Retrieve and process errors reported by the
1475 * hardware. Called by the Core module.
1477 static void sbridge_check_error(struct mem_ctl_info
*mci
)
1479 struct sbridge_pvt
*pvt
= mci
->pvt_info
;
1485 * MCE first step: Copy all mce errors into a temporary buffer
1486 * We use a double buffering here, to reduce the risk of
1490 count
= (pvt
->mce_out
+ MCE_LOG_LEN
- pvt
->mce_in
)
1495 m
= pvt
->mce_outentry
;
1496 if (pvt
->mce_in
+ count
> MCE_LOG_LEN
) {
1497 unsigned l
= MCE_LOG_LEN
- pvt
->mce_in
;
1499 memcpy(m
, &pvt
->mce_entry
[pvt
->mce_in
], sizeof(*m
) * l
);
1505 memcpy(m
, &pvt
->mce_entry
[pvt
->mce_in
], sizeof(*m
) * count
);
1507 pvt
->mce_in
+= count
;
1510 if (pvt
->mce_overrun
) {
1511 sbridge_printk(KERN_ERR
, "Lost %d memory errors\n",
1514 pvt
->mce_overrun
= 0;
1518 * MCE second step: parse errors and display
1520 for (i
= 0; i
< count
; i
++)
1521 sbridge_mce_output_error(mci
, &pvt
->mce_outentry
[i
]);
1525 * sbridge_mce_check_error Replicates mcelog routine to get errors
1526 * This routine simply queues mcelog errors, and
1527 * return. The error itself should be handled later
1528 * by sbridge_check_error.
1529 * WARNING: As this routine should be called at NMI time, extra care should
1530 * be taken to avoid deadlocks, and to be as fast as possible.
1532 static int sbridge_mce_check_error(struct notifier_block
*nb
, unsigned long val
,
1535 struct mce
*mce
= (struct mce
*)data
;
1536 struct mem_ctl_info
*mci
;
1537 struct sbridge_pvt
*pvt
;
1539 mci
= get_mci_for_node_id(mce
->socketid
);
1542 pvt
= mci
->pvt_info
;
1545 * Just let mcelog handle it if the error is
1546 * outside the memory controller. A memory error
1547 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
1548 * bit 12 has an special meaning.
1550 if ((mce
->status
& 0xefff) >> 7 != 1)
1553 printk("sbridge: HANDLING MCE MEMORY ERROR\n");
1555 printk("CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
1556 mce
->extcpu
, mce
->mcgstatus
, mce
->bank
, mce
->status
);
1557 printk("TSC %llx ", mce
->tsc
);
1558 printk("ADDR %llx ", mce
->addr
);
1559 printk("MISC %llx ", mce
->misc
);
1561 printk("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
1562 mce
->cpuvendor
, mce
->cpuid
, mce
->time
,
1563 mce
->socketid
, mce
->apicid
);
1565 /* Only handle if it is the right mc controller */
1566 if (cpu_data(mce
->cpu
).phys_proc_id
!= pvt
->sbridge_dev
->mc
)
1570 if ((pvt
->mce_out
+ 1) % MCE_LOG_LEN
== pvt
->mce_in
) {
1576 /* Copy memory error at the ringbuffer */
1577 memcpy(&pvt
->mce_entry
[pvt
->mce_out
], mce
, sizeof(*mce
));
1579 pvt
->mce_out
= (pvt
->mce_out
+ 1) % MCE_LOG_LEN
;
1581 /* Handle fatal errors immediately */
1582 if (mce
->mcgstatus
& 1)
1583 sbridge_check_error(mci
);
1585 /* Advice mcelog that the error were handled */
1589 static struct notifier_block sbridge_mce_dec
= {
1590 .notifier_call
= sbridge_mce_check_error
,
1593 /****************************************************************************
1594 EDAC register/unregister logic
1595 ****************************************************************************/
1597 static void sbridge_unregister_mci(struct sbridge_dev
*sbridge_dev
)
1599 struct mem_ctl_info
*mci
= sbridge_dev
->mci
;
1600 struct sbridge_pvt
*pvt
;
1602 if (unlikely(!mci
|| !mci
->pvt_info
)) {
1603 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev
->pdev
[0]->dev
);
1605 sbridge_printk(KERN_ERR
, "Couldn't find mci handler\n");
1609 pvt
= mci
->pvt_info
;
1611 edac_dbg(0, "MC: mci = %p, dev = %p\n",
1612 mci
, &sbridge_dev
->pdev
[0]->dev
);
1614 /* Remove MC sysfs nodes */
1615 edac_mc_del_mc(mci
->pdev
);
1617 edac_dbg(1, "%s: free mci struct\n", mci
->ctl_name
);
1618 kfree(mci
->ctl_name
);
1620 sbridge_dev
->mci
= NULL
;
1623 static int sbridge_register_mci(struct sbridge_dev
*sbridge_dev
)
1625 struct mem_ctl_info
*mci
;
1626 struct edac_mc_layer layers
[2];
1627 struct sbridge_pvt
*pvt
;
1630 /* Check the number of active and not disabled channels */
1631 rc
= check_if_ecc_is_active(sbridge_dev
->bus
);
1632 if (unlikely(rc
< 0))
1635 /* allocate a new MC control structure */
1636 layers
[0].type
= EDAC_MC_LAYER_CHANNEL
;
1637 layers
[0].size
= NUM_CHANNELS
;
1638 layers
[0].is_virt_csrow
= false;
1639 layers
[1].type
= EDAC_MC_LAYER_SLOT
;
1640 layers
[1].size
= MAX_DIMMS
;
1641 layers
[1].is_virt_csrow
= true;
1642 mci
= edac_mc_alloc(sbridge_dev
->mc
, ARRAY_SIZE(layers
), layers
,
1648 edac_dbg(0, "MC: mci = %p, dev = %p\n",
1649 mci
, &sbridge_dev
->pdev
[0]->dev
);
1651 pvt
= mci
->pvt_info
;
1652 memset(pvt
, 0, sizeof(*pvt
));
1654 /* Associate sbridge_dev and mci for future usage */
1655 pvt
->sbridge_dev
= sbridge_dev
;
1656 sbridge_dev
->mci
= mci
;
1658 mci
->mtype_cap
= MEM_FLAG_DDR3
;
1659 mci
->edac_ctl_cap
= EDAC_FLAG_NONE
;
1660 mci
->edac_cap
= EDAC_FLAG_NONE
;
1661 mci
->mod_name
= "sbridge_edac.c";
1662 mci
->mod_ver
= SBRIDGE_REVISION
;
1663 mci
->ctl_name
= kasprintf(GFP_KERNEL
, "Sandy Bridge Socket#%d", mci
->mc_idx
);
1664 mci
->dev_name
= pci_name(sbridge_dev
->pdev
[0]);
1665 mci
->ctl_page_to_phys
= NULL
;
1667 /* Set the function pointer to an actual operation function */
1668 mci
->edac_check
= sbridge_check_error
;
1670 /* Store pci devices at mci for faster access */
1671 rc
= mci_bind_devs(mci
, sbridge_dev
);
1672 if (unlikely(rc
< 0))
1675 /* Get dimm basic config and the memory layout */
1676 get_dimm_config(mci
);
1677 get_memory_layout(mci
);
1679 /* record ptr to the generic device */
1680 mci
->pdev
= &sbridge_dev
->pdev
[0]->dev
;
1682 /* add this new MC control structure to EDAC's list of MCs */
1683 if (unlikely(edac_mc_add_mc(mci
))) {
1684 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
1692 kfree(mci
->ctl_name
);
1694 sbridge_dev
->mci
= NULL
;
1699 * sbridge_probe Probe for ONE instance of device to see if it is
1702 * 0 for FOUND a device
1703 * < 0 for error code
1706 static int sbridge_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1710 struct sbridge_dev
*sbridge_dev
;
1712 /* get the pci devices we want to reserve for our use */
1713 mutex_lock(&sbridge_edac_lock
);
1716 * All memory controllers are allocated at the first pass.
1718 if (unlikely(probed
>= 1)) {
1719 mutex_unlock(&sbridge_edac_lock
);
1724 rc
= sbridge_get_all_devices(&num_mc
);
1725 if (unlikely(rc
< 0))
1729 list_for_each_entry(sbridge_dev
, &sbridge_edac_list
, list
) {
1730 edac_dbg(0, "Registering MC#%d (%d of %d)\n",
1731 mc
, mc
+ 1, num_mc
);
1732 sbridge_dev
->mc
= mc
++;
1733 rc
= sbridge_register_mci(sbridge_dev
);
1734 if (unlikely(rc
< 0))
1738 sbridge_printk(KERN_INFO
, "Driver loaded.\n");
1740 mutex_unlock(&sbridge_edac_lock
);
1744 list_for_each_entry(sbridge_dev
, &sbridge_edac_list
, list
)
1745 sbridge_unregister_mci(sbridge_dev
);
1747 sbridge_put_all_devices();
1749 mutex_unlock(&sbridge_edac_lock
);
1754 * sbridge_remove destructor for one instance of device
1757 static void sbridge_remove(struct pci_dev
*pdev
)
1759 struct sbridge_dev
*sbridge_dev
;
1764 * we have a trouble here: pdev value for removal will be wrong, since
1765 * it will point to the X58 register used to detect that the machine
1766 * is a Nehalem or upper design. However, due to the way several PCI
1767 * devices are grouped together to provide MC functionality, we need
1768 * to use a different method for releasing the devices
1771 mutex_lock(&sbridge_edac_lock
);
1773 if (unlikely(!probed
)) {
1774 mutex_unlock(&sbridge_edac_lock
);
1778 list_for_each_entry(sbridge_dev
, &sbridge_edac_list
, list
)
1779 sbridge_unregister_mci(sbridge_dev
);
1781 /* Release PCI resources */
1782 sbridge_put_all_devices();
1786 mutex_unlock(&sbridge_edac_lock
);
1789 MODULE_DEVICE_TABLE(pci
, sbridge_pci_tbl
);
1792 * sbridge_driver pci_driver structure for this module
1795 static struct pci_driver sbridge_driver
= {
1796 .name
= "sbridge_edac",
1797 .probe
= sbridge_probe
,
1798 .remove
= sbridge_remove
,
1799 .id_table
= sbridge_pci_tbl
,
1803 * sbridge_init Module entry function
1804 * Try to initialize this module for its devices
1806 static int __init
sbridge_init(void)
1812 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1815 pci_rc
= pci_register_driver(&sbridge_driver
);
1818 mce_register_decode_chain(&sbridge_mce_dec
);
1822 sbridge_printk(KERN_ERR
, "Failed to register device with error %d.\n",
1829 * sbridge_exit() Module exit function
1830 * Unregister the driver
1832 static void __exit
sbridge_exit(void)
1835 pci_unregister_driver(&sbridge_driver
);
1836 mce_unregister_decode_chain(&sbridge_mce_dec
);
1839 module_init(sbridge_init
);
1840 module_exit(sbridge_exit
);
1842 module_param(edac_op_state
, int, 0444);
1843 MODULE_PARM_DESC(edac_op_state
, "EDAC Error Reporting state: 0=Poll,1=NMI");
1845 MODULE_LICENSE("GPL");
1846 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1847 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
1848 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge memory controllers - "