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Merge tag 'v3.10.104' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / edac / sb_edac.c
CommitLineData
eebf11a0
MCC		 1/* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
2 *
3 * This driver supports the memory controllers found on the Intel
4 * processor family Sandy Bridge.
5 *
6 * This file may be distributed under the terms of the
7 * GNU General Public License version 2 only.
8 *
9 * Copyright (c) 2011 by:
10 * Mauro Carvalho Chehab <mchehab@redhat.com>
11 */
12
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/pci.h>
16#include <linux/pci_ids.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/edac.h>
20#include <linux/mmzone.h>
eebf11a0
MCC		 21#include <linux/smp.h>
22#include <linux/bitmap.h>
5b889e37 23#include <linux/math64.h>
eebf11a0 24#include <asm/processor.h>
3d78c9af 25#include <asm/mce.h>
eebf11a0
MCC		 26
27#include "edac_core.h"
28
29/* Static vars */
30static LIST_HEAD(sbridge_edac_list);
31static DEFINE_MUTEX(sbridge_edac_lock);
32static int probed;
33
34/*
35 * Alter this version for the module when modifications are made
36 */
37#define SBRIDGE_REVISION " Ver: 1.0.0 "
38#define EDAC_MOD_STR "sbridge_edac"
39
40/*
41 * Debug macros
42 */
43#define sbridge_printk(level, fmt, arg...) \
44 edac_printk(level, "sbridge", fmt, ##arg)
45
46#define sbridge_mc_printk(mci, level, fmt, arg...) \
47 edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
48
49/*
50 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
51 */
52#define GET_BITFIELD(v, lo, hi) \
53 (((v) & ((1ULL << ((hi) - (lo) + 1)) - 1) << (lo)) >> (lo))
54
55/*
56 * sbridge Memory Controller Registers
57 */
58
59/*
60 * FIXME: For now, let's order by device function, as it makes
15ed103a 61 * easier for driver's development process. This table should be
eebf11a0
MCC		 62 * moved to pci_id.h when submitted upstream
63 */
64#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0 0x3cf4 /* 12.6 */
65#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1 0x3cf6 /* 12.7 */
66#define PCI_DEVICE_ID_INTEL_SBRIDGE_BR 0x3cf5 /* 13.6 */
67#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0 0x3ca0 /* 14.0 */
68#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA 0x3ca8 /* 15.0 */
69#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS 0x3c71 /* 15.1 */
70#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0 0x3caa /* 15.2 */
71#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1 0x3cab /* 15.3 */
72#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2 0x3cac /* 15.4 */
73#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3 0x3cad /* 15.5 */
74#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO 0x3cb8 /* 17.0 */
75
76 /*
77 * Currently, unused, but will be needed in the future
78 * implementations, as they hold the error counters
79 */
80#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0 0x3c72 /* 16.2 */
81#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1 0x3c73 /* 16.3 */
82#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2 0x3c76 /* 16.6 */
83#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3 0x3c77 /* 16.7 */
84
85/* Devices 12 Function 6, Offsets 0x80 to 0xcc */
86static const u32 dram_rule[] = {
87 0x80, 0x88, 0x90, 0x98, 0xa0,
88 0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
89};
90#define MAX_SAD ARRAY_SIZE(dram_rule)
91
92#define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff)
93#define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3)
94#define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1)
95#define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
96
97static char *get_dram_attr(u32 reg)
98{
99 switch(DRAM_ATTR(reg)) {
100 case 0:
101 return "DRAM";
102 case 1:
103 return "MMCFG";
104 case 2:
105 return "NXM";
106 default:
107 return "unknown";
108 }
109}
110
111static const u32 interleave_list[] = {
112 0x84, 0x8c, 0x94, 0x9c, 0xa4,
113 0xac, 0xb4, 0xbc, 0xc4, 0xcc,
114};
115#define MAX_INTERLEAVE ARRAY_SIZE(interleave_list)
116
117#define SAD_PKG0(reg) GET_BITFIELD(reg, 0, 2)
118#define SAD_PKG1(reg) GET_BITFIELD(reg, 3, 5)
119#define SAD_PKG2(reg) GET_BITFIELD(reg, 8, 10)
120#define SAD_PKG3(reg) GET_BITFIELD(reg, 11, 13)
121#define SAD_PKG4(reg) GET_BITFIELD(reg, 16, 18)
122#define SAD_PKG5(reg) GET_BITFIELD(reg, 19, 21)
123#define SAD_PKG6(reg) GET_BITFIELD(reg, 24, 26)
124#define SAD_PKG7(reg) GET_BITFIELD(reg, 27, 29)
125
126static inline int sad_pkg(u32 reg, int interleave)
127{
128 switch (interleave) {
129 case 0:
130 return SAD_PKG0(reg);
131 case 1:
132 return SAD_PKG1(reg);
133 case 2:
134 return SAD_PKG2(reg);
135 case 3:
136 return SAD_PKG3(reg);
137 case 4:
138 return SAD_PKG4(reg);
139 case 5:
140 return SAD_PKG5(reg);
141 case 6:
142 return SAD_PKG6(reg);
143 case 7:
144 return SAD_PKG7(reg);
145 default:
146 return -EINVAL;
147 }
148}
149
150/* Devices 12 Function 7 */
151
152#define TOLM 0x80
153#define TOHM 0x84
154
155#define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)
156#define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
157
158/* Device 13 Function 6 */
159
160#define SAD_TARGET 0xf0
161
162#define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)
163
164#define SAD_CONTROL 0xf4
165
166#define NODE_ID(reg) GET_BITFIELD(reg, 0, 2)
167
168/* Device 14 function 0 */
169
170static const u32 tad_dram_rule[] = {
171 0x40, 0x44, 0x48, 0x4c,
172 0x50, 0x54, 0x58, 0x5c,
173 0x60, 0x64, 0x68, 0x6c,
174};
175#define MAX_TAD ARRAY_SIZE(tad_dram_rule)
176
177#define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
178#define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)
179#define TAD_CH(reg) GET_BITFIELD(reg, 8, 9)
180#define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7)
181#define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5)
182#define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3)
183#define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1)
184
185/* Device 15, function 0 */
186
187#define MCMTR 0x7c
188
189#define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2)
190#define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1)
191#define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0)
192
193/* Device 15, function 1 */
194
195#define RASENABLES 0xac
196#define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0)
197
198/* Device 15, functions 2-5 */
199
200static const int mtr_regs[] = {
201 0x80, 0x84, 0x88,
202};
203
204#define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19)
205#define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14)
206#define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13)
207#define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4)
208#define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1)
209
210static const u32 tad_ch_nilv_offset[] = {
211 0x90, 0x94, 0x98, 0x9c,
212 0xa0, 0xa4, 0xa8, 0xac,
213 0xb0, 0xb4, 0xb8, 0xbc,
214};
215#define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29)
216#define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26)
217
218static const u32 rir_way_limit[] = {
219 0x108, 0x10c, 0x110, 0x114, 0x118,
220};
221#define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
222
223#define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31)
224#define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29)
225#define RIR_LIMIT(reg) ((GET_BITFIELD(reg, 1, 10) << 29)| 0x1fffffff)
226
227#define MAX_RIR_WAY 8
228
229static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
230 { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
231 { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
232 { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
233 { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
234 { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
235};
236
237#define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19)
238#define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14)
239
240/* Device 16, functions 2-7 */
241
242/*
243 * FIXME: Implement the error count reads directly
244 */
245
246static const u32 correrrcnt[] = {
247 0x104, 0x108, 0x10c, 0x110,
248};
249
250#define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31)
251#define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30)
252#define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15)
253#define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14)
254
255static const u32 correrrthrsld[] = {
256 0x11c, 0x120, 0x124, 0x128,
257};
258
259#define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30)
260#define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14)
261
262
263/* Device 17, function 0 */
264
265#define RANK_CFG_A 0x0328
266
267#define IS_RDIMM_ENABLED(reg) GET_BITFIELD(reg, 11, 11)
268
269/*
270 * sbridge structs
271 */
272
ebe7e30a
SJ		 273#define NUM_CHANNELS 4
274#define MAX_DIMMS 3 /* Max DIMMS per channel */
275#define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */
eebf11a0
MCC		 276
277struct sbridge_info {
278 u32 mcmtr;
279};
280
281struct sbridge_channel {
282 u32 ranks;
283 u32 dimms;
284};
285
286struct pci_id_descr {
287 int dev;
288 int func;
289 int dev_id;
290 int optional;
291};
292
293struct pci_id_table {
294 const struct pci_id_descr *descr;
295 int n_devs;
296};
297
298struct sbridge_dev {
299 struct list_head list;
300 u8 bus, mc;
301 u8 node_id, source_id;
302 struct pci_dev **pdev;
303 int n_devs;
304 struct mem_ctl_info *mci;
305};
306
307struct sbridge_pvt {
308 struct pci_dev *pci_ta, *pci_ddrio, *pci_ras;
309 struct pci_dev *pci_sad0, *pci_sad1, *pci_ha0;
310 struct pci_dev *pci_br;
311 struct pci_dev *pci_tad[NUM_CHANNELS];
312
313 struct sbridge_dev *sbridge_dev;
314
315 struct sbridge_info info;
316 struct sbridge_channel channel[NUM_CHANNELS];
317
eebf11a0
MCC		 318 /* Memory type detection */
319 bool is_mirrored, is_lockstep, is_close_pg;
320
eebf11a0
MCC		 321 /* Fifo double buffers */
322 struct mce mce_entry[MCE_LOG_LEN];
323 struct mce mce_outentry[MCE_LOG_LEN];
324
325 /* Fifo in/out counters */
326 unsigned mce_in, mce_out;
327
328 /* Count indicator to show errors not got */
329 unsigned mce_overrun;
330
331 /* Memory description */
332 u64 tolm, tohm;
333};
334
de4772c6
TL		 335#define PCI_DESCR(device, function, device_id, opt) \
336 .dev = (device), \
337 .func = (function), \
338 .dev_id = (device_id), \
339 .optional = opt
eebf11a0
MCC		 340
341static const struct pci_id_descr pci_dev_descr_sbridge[] = {
342 /* Processor Home Agent */
de4772c6 343 { PCI_DESCR(14, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0) },
eebf11a0
MCC		 344
345 /* Memory controller */
de4772c6
TL		 346 { PCI_DESCR(15, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0) },
347 { PCI_DESCR(15, 1, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0) },
348 { PCI_DESCR(15, 2, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0) },
349 { PCI_DESCR(15, 3, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0) },
350 { PCI_DESCR(15, 4, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0) },
351 { PCI_DESCR(15, 5, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0) },
352 { PCI_DESCR(17, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1) },
eebf11a0
MCC		 353
354 /* System Address Decoder */
de4772c6
TL		 355 { PCI_DESCR(12, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0) },
356 { PCI_DESCR(12, 7, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0) },
eebf11a0
MCC		 357
358 /* Broadcast Registers */
de4772c6 359 { PCI_DESCR(13, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0) },
eebf11a0
MCC		 360};
361
362#define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
363static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
364 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge),
365 {0,} /* 0 terminated list. */
366};
367
368/*
369 * pci_device_id table for which devices we are looking for
370 */
36c46f31 371static DEFINE_PCI_DEVICE_TABLE(sbridge_pci_tbl) = {
eebf11a0
MCC		 372 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA)},
373 {0,} /* 0 terminated list. */
374};
375
376
377/****************************************************************************
15ed103a 378 Ancillary status routines
eebf11a0
MCC		 379 ****************************************************************************/
380
381static inline int numrank(u32 mtr)
382{
383 int ranks = (1 << RANK_CNT_BITS(mtr));
384
385 if (ranks > 4) {
956b9ba1
JP		 386 edac_dbg(0, "Invalid number of ranks: %d (max = 4) raw value = %x (%04x)\n",
387 ranks, (unsigned int)RANK_CNT_BITS(mtr), mtr);
eebf11a0
MCC		 388 return -EINVAL;
389 }
390
391 return ranks;
392}
393
394static inline int numrow(u32 mtr)
395{
396 int rows = (RANK_WIDTH_BITS(mtr) + 12);
397
398 if (rows < 13 || rows > 18) {
956b9ba1
JP		 399 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",
400 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
eebf11a0
MCC		 401 return -EINVAL;
402 }
403
404 return 1 << rows;
405}
406
407static inline int numcol(u32 mtr)
408{
409 int cols = (COL_WIDTH_BITS(mtr) + 10);
410
411 if (cols > 12) {
956b9ba1
JP		 412 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",
413 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
eebf11a0
MCC		 414 return -EINVAL;
415 }
416
417 return 1 << cols;
418}
419
420static struct sbridge_dev *get_sbridge_dev(u8 bus)
421{
422 struct sbridge_dev *sbridge_dev;
423
424 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
425 if (sbridge_dev->bus == bus)
426 return sbridge_dev;
427 }
428
429 return NULL;
430}
431
432static struct sbridge_dev *alloc_sbridge_dev(u8 bus,
433 const struct pci_id_table *table)
434{
435 struct sbridge_dev *sbridge_dev;
436
437 sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
438 if (!sbridge_dev)
439 return NULL;
440
441 sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs,
442 GFP_KERNEL);
443 if (!sbridge_dev->pdev) {
444 kfree(sbridge_dev);
445 return NULL;
446 }
447
448 sbridge_dev->bus = bus;
449 sbridge_dev->n_devs = table->n_devs;
450 list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
451
452 return sbridge_dev;
453}
454
455static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
456{
457 list_del(&sbridge_dev->list);
458 kfree(sbridge_dev->pdev);
459 kfree(sbridge_dev);
460}
461
462/****************************************************************************
463 Memory check routines
464 ****************************************************************************/
465static struct pci_dev *get_pdev_slot_func(u8 bus, unsigned slot,
466 unsigned func)
467{
468 struct sbridge_dev *sbridge_dev = get_sbridge_dev(bus);
469 int i;
470
471 if (!sbridge_dev)
472 return NULL;
473
474 for (i = 0; i < sbridge_dev->n_devs; i++) {
475 if (!sbridge_dev->pdev[i])
476 continue;
477
478 if (PCI_SLOT(sbridge_dev->pdev[i]->devfn) == slot &&
479 PCI_FUNC(sbridge_dev->pdev[i]->devfn) == func) {
956b9ba1
JP		 480 edac_dbg(1, "Associated %02x.%02x.%d with %p\n",
481 bus, slot, func, sbridge_dev->pdev[i]);
eebf11a0
MCC		 482 return sbridge_dev->pdev[i];
483 }
484 }
485
486 return NULL;
487}
488
489/**
c36e3e77 490 * check_if_ecc_is_active() - Checks if ECC is active
eebf11a0 491 * bus: Device bus
eebf11a0 492 */
c36e3e77 493static int check_if_ecc_is_active(const u8 bus)
eebf11a0
MCC		 494{
495 struct pci_dev *pdev = NULL;
eebf11a0
MCC		 496 u32 mcmtr;
497
eebf11a0
MCC		 498 pdev = get_pdev_slot_func(bus, 15, 0);
499 if (!pdev) {
500 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
501 "%2x.%02d.%d!!!\n",
502 bus, 15, 0);
503 return -ENODEV;
504 }
505
506 pci_read_config_dword(pdev, MCMTR, &mcmtr);
507 if (!IS_ECC_ENABLED(mcmtr)) {
508 sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n");
509 return -ENODEV;
510 }
eebf11a0
MCC		 511 return 0;
512}
513
084a4fcc 514static int get_dimm_config(struct mem_ctl_info *mci)
eebf11a0
MCC		 515{
516 struct sbridge_pvt *pvt = mci->pvt_info;
c36e3e77 517 struct dimm_info *dimm;
deb09dda
MCC		 518 unsigned i, j, banks, ranks, rows, cols, npages;
519 u64 size;
eebf11a0
MCC		 520 u32 reg;
521 enum edac_type mode;
c6e13b52 522 enum mem_type mtype;
eebf11a0
MCC		 523
524 pci_read_config_dword(pvt->pci_br, SAD_TARGET, &reg);
525 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
526
527 pci_read_config_dword(pvt->pci_br, SAD_CONTROL, &reg);
528 pvt->sbridge_dev->node_id = NODE_ID(reg);
956b9ba1
JP		 529 edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
530 pvt->sbridge_dev->mc,
531 pvt->sbridge_dev->node_id,
532 pvt->sbridge_dev->source_id);
eebf11a0
MCC		 533
534 pci_read_config_dword(pvt->pci_ras, RASENABLES, &reg);
535 if (IS_MIRROR_ENABLED(reg)) {
956b9ba1 536 edac_dbg(0, "Memory mirror is enabled\n");
eebf11a0
MCC		 537 pvt->is_mirrored = true;
538 } else {
956b9ba1 539 edac_dbg(0, "Memory mirror is disabled\n");
eebf11a0
MCC		 540 pvt->is_mirrored = false;
541 }
542
543 pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr);
544 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
956b9ba1 545 edac_dbg(0, "Lockstep is enabled\n");
eebf11a0
MCC		 546 mode = EDAC_S8ECD8ED;
547 pvt->is_lockstep = true;
548 } else {
956b9ba1 549 edac_dbg(0, "Lockstep is disabled\n");
eebf11a0
MCC		 550 mode = EDAC_S4ECD4ED;
551 pvt->is_lockstep = false;
552 }
553 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
956b9ba1 554 edac_dbg(0, "address map is on closed page mode\n");
eebf11a0
MCC		 555 pvt->is_close_pg = true;
556 } else {
956b9ba1 557 edac_dbg(0, "address map is on open page mode\n");
eebf11a0
MCC		 558 pvt->is_close_pg = false;
559 }
560
de4772c6
TL		 561 if (pvt->pci_ddrio) {
562 pci_read_config_dword(pvt->pci_ddrio, RANK_CFG_A, &reg);
563 if (IS_RDIMM_ENABLED(reg)) {
564 /* FIXME: Can also be LRDIMM */
565 edac_dbg(0, "Memory is registered\n");
566 mtype = MEM_RDDR3;
567 } else {
568 edac_dbg(0, "Memory is unregistered\n");
569 mtype = MEM_DDR3;
570 }
eebf11a0 571 } else {
de4772c6
TL		 572 edac_dbg(0, "Cannot determine memory type\n");
573 mtype = MEM_UNKNOWN;
eebf11a0
MCC		 574 }
575
576 /* On all supported DDR3 DIMM types, there are 8 banks available */
577 banks = 8;
578
579 for (i = 0; i < NUM_CHANNELS; i++) {
580 u32 mtr;
581
582 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
c36e3e77
MCC		 583 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
584 i, j, 0);
eebf11a0
MCC		 585 pci_read_config_dword(pvt->pci_tad[i],
586 mtr_regs[j], &mtr);
956b9ba1 587 edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr);
eebf11a0
MCC		 588 if (IS_DIMM_PRESENT(mtr)) {
589 pvt->channel[i].dimms++;
590
591 ranks = numrank(mtr);
592 rows = numrow(mtr);
593 cols = numcol(mtr);
594
595 /* DDR3 has 8 I/O banks */
deb09dda 596 size = ((u64)rows * cols * banks * ranks) >> (20 - 3);
eebf11a0
MCC		 597 npages = MiB_TO_PAGES(size);
598
deb09dda 599 edac_dbg(0, "mc#%d: channel %d, dimm %d, %Ld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
956b9ba1
JP		 600 pvt->sbridge_dev->mc, i, j,
601 size, npages,
602 banks, ranks, rows, cols);
eebf11a0 603
a895bf8b 604 dimm->nr_pages = npages;
084a4fcc
MCC		 605 dimm->grain = 32;
606 dimm->dtype = (banks == 8) ? DEV_X8 : DEV_X4;
607 dimm->mtype = mtype;
608 dimm->edac_mode = mode;
609 snprintf(dimm->label, sizeof(dimm->label),
eebf11a0
MCC		 610 "CPU_SrcID#%u_Channel#%u_DIMM#%u",
611 pvt->sbridge_dev->source_id, i, j);
eebf11a0
MCC		 612 }
613 }
614 }
615
616 return 0;
617}
618
619static void get_memory_layout(const struct mem_ctl_info *mci)
620{
621 struct sbridge_pvt *pvt = mci->pvt_info;
622 int i, j, k, n_sads, n_tads, sad_interl;
623 u32 reg;
624 u64 limit, prv = 0;
625 u64 tmp_mb;
29e7fa7c 626 u32 gb, mb;
eebf11a0
MCC		 627 u32 rir_way;
628
629 /*
630 * Step 1) Get TOLM/TOHM ranges
631 */
632
633 /* Address range is 32:28 */
634 pci_read_config_dword(pvt->pci_sad1, TOLM,
635 &reg);
636 pvt->tolm = GET_TOLM(reg);
637 tmp_mb = (1 + pvt->tolm) >> 20;
638
29e7fa7c
JS		 639 gb = div_u64_rem(tmp_mb, 1024, &mb);
640 edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n",
641 gb, (mb*1000)/1024, (u64)pvt->tolm);
eebf11a0
MCC		 642
643 /* Address range is already 45:25 */
644 pci_read_config_dword(pvt->pci_sad1, TOHM,
645 &reg);
646 pvt->tohm = GET_TOHM(reg);
647 tmp_mb = (1 + pvt->tohm) >> 20;
648
29e7fa7c
JS		 649 gb = div_u64_rem(tmp_mb, 1024, &mb);
650 edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n",
651 gb, (mb*1000)/1024, (u64)pvt->tohm);
eebf11a0
MCC		 652
653 /*
654 * Step 2) Get SAD range and SAD Interleave list
655 * TAD registers contain the interleave wayness. However, it
656 * seems simpler to just discover it indirectly, with the
657 * algorithm bellow.
658 */
659 prv = 0;
660 for (n_sads = 0; n_sads < MAX_SAD; n_sads++) {
661 /* SAD_LIMIT Address range is 45:26 */
662 pci_read_config_dword(pvt->pci_sad0, dram_rule[n_sads],
663 &reg);
664 limit = SAD_LIMIT(reg);
665
666 if (!DRAM_RULE_ENABLE(reg))
667 continue;
668
669 if (limit <= prv)
670 break;
671
672 tmp_mb = (limit + 1) >> 20;
29e7fa7c 673 gb = div_u64_rem(tmp_mb, 1024, &mb);
956b9ba1
JP		 674 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
675 n_sads,
676 get_dram_attr(reg),
29e7fa7c 677 gb, (mb*1000)/1024,
956b9ba1
JP		 678 ((u64)tmp_mb) << 20L,
679 INTERLEAVE_MODE(reg) ? "8:6" : "[8:6]XOR[18:16]",
680 reg);
eebf11a0
MCC		 681 prv = limit;
682
683 pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads],
684 &reg);
685 sad_interl = sad_pkg(reg, 0);
686 for (j = 0; j < 8; j++) {
687 if (j > 0 && sad_interl == sad_pkg(reg, j))
688 break;
689
956b9ba1
JP		 690 edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
691 n_sads, j, sad_pkg(reg, j));
eebf11a0
MCC		 692 }
693 }
694
695 /*
696 * Step 3) Get TAD range
697 */
698 prv = 0;
699 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
700 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
701 &reg);
702 limit = TAD_LIMIT(reg);
703 if (limit <= prv)
704 break;
705 tmp_mb = (limit + 1) >> 20;
706
29e7fa7c 707 gb = div_u64_rem(tmp_mb, 1024, &mb);
956b9ba1 708 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
29e7fa7c 709 n_tads, gb, (mb*1000)/1024,
956b9ba1
JP		 710 ((u64)tmp_mb) << 20L,
711 (u32)TAD_SOCK(reg),
712 (u32)TAD_CH(reg),
713 (u32)TAD_TGT0(reg),
714 (u32)TAD_TGT1(reg),
715 (u32)TAD_TGT2(reg),
716 (u32)TAD_TGT3(reg),
717 reg);
7fae0db4 718 prv = limit;
eebf11a0
MCC		 719 }
720
721 /*
722 * Step 4) Get TAD offsets, per each channel
723 */
724 for (i = 0; i < NUM_CHANNELS; i++) {
725 if (!pvt->channel[i].dimms)
726 continue;
727 for (j = 0; j < n_tads; j++) {
728 pci_read_config_dword(pvt->pci_tad[i],
729 tad_ch_nilv_offset[j],
730 &reg);
731 tmp_mb = TAD_OFFSET(reg) >> 20;
29e7fa7c 732 gb = div_u64_rem(tmp_mb, 1024, &mb);
956b9ba1
JP		 733 edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
734 i, j,
29e7fa7c 735 gb, (mb*1000)/1024,
956b9ba1
JP		 736 ((u64)tmp_mb) << 20L,
737 reg);
eebf11a0
MCC		 738 }
739 }
740
741 /*
742 * Step 6) Get RIR Wayness/Limit, per each channel
743 */
744 for (i = 0; i < NUM_CHANNELS; i++) {
745 if (!pvt->channel[i].dimms)
746 continue;
747 for (j = 0; j < MAX_RIR_RANGES; j++) {
748 pci_read_config_dword(pvt->pci_tad[i],
749 rir_way_limit[j],
750 &reg);
751
752 if (!IS_RIR_VALID(reg))
753 continue;
754
755 tmp_mb = RIR_LIMIT(reg) >> 20;
756 rir_way = 1 << RIR_WAY(reg);
29e7fa7c 757 gb = div_u64_rem(tmp_mb, 1024, &mb);
956b9ba1
JP		 758 edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
759 i, j,
29e7fa7c 760 gb, (mb*1000)/1024,
956b9ba1
JP		 761 ((u64)tmp_mb) << 20L,
762 rir_way,
763 reg);
eebf11a0
MCC		 764
765 for (k = 0; k < rir_way; k++) {
766 pci_read_config_dword(pvt->pci_tad[i],
767 rir_offset[j][k],
768 &reg);
769 tmp_mb = RIR_OFFSET(reg) << 6;
770
29e7fa7c 771 gb = div_u64_rem(tmp_mb, 1024, &mb);
956b9ba1
JP		 772 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
773 i, j, k,
29e7fa7c 774 gb, (mb*1000)/1024,
956b9ba1
JP		 775 ((u64)tmp_mb) << 20L,
776 (u32)RIR_RNK_TGT(reg),
777 reg);
eebf11a0
MCC		 778 }
779 }
780 }
781}
782
783struct mem_ctl_info *get_mci_for_node_id(u8 node_id)
784{
785 struct sbridge_dev *sbridge_dev;
786
787 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
788 if (sbridge_dev->node_id == node_id)
789 return sbridge_dev->mci;
790 }
791 return NULL;
792}
793
794static int get_memory_error_data(struct mem_ctl_info *mci,
795 u64 addr,
796 u8 *socket,
797 long *channel_mask,
798 u8 *rank,
e17a2f42 799 char **area_type, char *msg)
eebf11a0
MCC		 800{
801 struct mem_ctl_info *new_mci;
802 struct sbridge_pvt *pvt = mci->pvt_info;
eebf11a0
MCC		 803 int n_rir, n_sads, n_tads, sad_way, sck_xch;
804 int sad_interl, idx, base_ch;
805 int interleave_mode;
806 unsigned sad_interleave[MAX_INTERLEAVE];
807 u32 reg;
808 u8 ch_way,sck_way;
809 u32 tad_offset;
810 u32 rir_way;
29e7fa7c 811 u32 mb, gb;
eebf11a0
MCC		 812 u64 ch_addr, offset, limit, prv = 0;
813
814
815 /*
816 * Step 0) Check if the address is at special memory ranges
817 * The check bellow is probably enough to fill all cases where
818 * the error is not inside a memory, except for the legacy
819 * range (e. g. VGA addresses). It is unlikely, however, that the
820 * memory controller would generate an error on that range.
821 */
5b889e37 822 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
eebf11a0 823 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
eebf11a0
MCC		 824 return -EINVAL;
825 }
826 if (addr >= (u64)pvt->tohm) {
827 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
eebf11a0
MCC		 828 return -EINVAL;
829 }
830
831 /*
832 * Step 1) Get socket
833 */
834 for (n_sads = 0; n_sads < MAX_SAD; n_sads++) {
835 pci_read_config_dword(pvt->pci_sad0, dram_rule[n_sads],
836 &reg);
837
838 if (!DRAM_RULE_ENABLE(reg))
839 continue;
840
841 limit = SAD_LIMIT(reg);
842 if (limit <= prv) {
843 sprintf(msg, "Can't discover the memory socket");
eebf11a0
MCC		 844 return -EINVAL;
845 }
846 if (addr <= limit)
847 break;
848 prv = limit;
849 }
850 if (n_sads == MAX_SAD) {
851 sprintf(msg, "Can't discover the memory socket");
eebf11a0
MCC		 852 return -EINVAL;
853 }
e17a2f42 854 *area_type = get_dram_attr(reg);
eebf11a0
MCC		 855 interleave_mode = INTERLEAVE_MODE(reg);
856
857 pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads],
858 &reg);
859 sad_interl = sad_pkg(reg, 0);
860 for (sad_way = 0; sad_way < 8; sad_way++) {
861 if (sad_way > 0 && sad_interl == sad_pkg(reg, sad_way))
862 break;
863 sad_interleave[sad_way] = sad_pkg(reg, sad_way);
956b9ba1
JP		 864 edac_dbg(0, "SAD interleave #%d: %d\n",
865 sad_way, sad_interleave[sad_way]);
eebf11a0 866 }
956b9ba1
JP		 867 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
868 pvt->sbridge_dev->mc,
869 n_sads,
870 addr,
871 limit,
872 sad_way + 7,
873 interleave_mode ? "" : "XOR[18:16]");
eebf11a0
MCC		 874 if (interleave_mode)
875 idx = ((addr >> 6) ^ (addr >> 16)) & 7;
876 else
877 idx = (addr >> 6) & 7;
878 switch (sad_way) {
879 case 1:
880 idx = 0;
881 break;
882 case 2:
883 idx = idx & 1;
884 break;
885 case 4:
886 idx = idx & 3;
887 break;
888 case 8:
889 break;
890 default:
891 sprintf(msg, "Can't discover socket interleave");
eebf11a0
MCC		 892 return -EINVAL;
893 }
894 *socket = sad_interleave[idx];
956b9ba1
JP		 895 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
896 idx, sad_way, *socket);
eebf11a0
MCC		 897
898 /*
899 * Move to the proper node structure, in order to access the
900 * right PCI registers
901 */
902 new_mci = get_mci_for_node_id(*socket);
903 if (!new_mci) {
904 sprintf(msg, "Struct for socket #%u wasn't initialized",
905 *socket);
eebf11a0
MCC		 906 return -EINVAL;
907 }
908 mci = new_mci;
909 pvt = mci->pvt_info;
910
911 /*
912 * Step 2) Get memory channel
913 */
914 prv = 0;
915 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
916 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
917 &reg);
918 limit = TAD_LIMIT(reg);
919 if (limit <= prv) {
920 sprintf(msg, "Can't discover the memory channel");
eebf11a0
MCC		 921 return -EINVAL;
922 }
923 if (addr <= limit)
924 break;
925 prv = limit;
926 }
927 ch_way = TAD_CH(reg) + 1;
928 sck_way = TAD_SOCK(reg) + 1;
929 /*
930 * FIXME: Is it right to always use channel 0 for offsets?
931 */
932 pci_read_config_dword(pvt->pci_tad[0],
933 tad_ch_nilv_offset[n_tads],
934 &tad_offset);
935
936 if (ch_way == 3)
937 idx = addr >> 6;
938 else
939 idx = addr >> (6 + sck_way);
940 idx = idx % ch_way;
941
942 /*
943 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
944 */
945 switch (idx) {
946 case 0:
947 base_ch = TAD_TGT0(reg);
948 break;
949 case 1:
950 base_ch = TAD_TGT1(reg);
951 break;
952 case 2:
953 base_ch = TAD_TGT2(reg);
954 break;
955 case 3:
956 base_ch = TAD_TGT3(reg);
957 break;
958 default:
959 sprintf(msg, "Can't discover the TAD target");
eebf11a0
MCC		 960 return -EINVAL;
961 }
962 *channel_mask = 1 << base_ch;
963
964 if (pvt->is_mirrored) {
965 *channel_mask |= 1 << ((base_ch + 2) % 4);
966 switch(ch_way) {
967 case 2:
968 case 4:
969 sck_xch = 1 << sck_way * (ch_way >> 1);
970 break;
971 default:
972 sprintf(msg, "Invalid mirror set. Can't decode addr");
eebf11a0
MCC		 973 return -EINVAL;
974 }
975 } else
976 sck_xch = (1 << sck_way) * ch_way;
977
978 if (pvt->is_lockstep)
979 *channel_mask |= 1 << ((base_ch + 1) % 4);
980
981 offset = TAD_OFFSET(tad_offset);
982
956b9ba1
JP		 983 edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
984 n_tads,
985 addr,
986 limit,
987 (u32)TAD_SOCK(reg),
988 ch_way,
989 offset,
990 idx,
991 base_ch,
992 *channel_mask);
eebf11a0
MCC		 993
994 /* Calculate channel address */
995 /* Remove the TAD offset */
996
997 if (offset > addr) {
998 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
999 offset, addr);
eebf11a0
MCC		 1000 return -EINVAL;
1001 }
1002 addr -= offset;
1003 /* Store the low bits [0:6] of the addr */
1004 ch_addr = addr & 0x7f;
1005 /* Remove socket wayness and remove 6 bits */
1006 addr >>= 6;
5b889e37 1007 addr = div_u64(addr, sck_xch);
eebf11a0
MCC		 1008#if 0
1009 /* Divide by channel way */
1010 addr = addr / ch_way;
1011#endif
1012 /* Recover the last 6 bits */
1013 ch_addr |= addr << 6;
1014
1015 /*
1016 * Step 3) Decode rank
1017 */
1018 for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
1019 pci_read_config_dword(pvt->pci_tad[base_ch],
1020 rir_way_limit[n_rir],
1021 &reg);
1022
1023 if (!IS_RIR_VALID(reg))
1024 continue;
1025
1026 limit = RIR_LIMIT(reg);
29e7fa7c 1027 gb = div_u64_rem(limit >> 20, 1024, &mb);
956b9ba1
JP		 1028 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
1029 n_rir,
29e7fa7c 1030 gb, (mb*1000)/1024,
956b9ba1
JP		 1031 limit,
1032 1 << RIR_WAY(reg));
eebf11a0
MCC		 1033 if (ch_addr <= limit)
1034 break;
1035 }
1036 if (n_rir == MAX_RIR_RANGES) {
1037 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
1038 ch_addr);
eebf11a0
MCC		 1039 return -EINVAL;
1040 }
1041 rir_way = RIR_WAY(reg);
1042 if (pvt->is_close_pg)
1043 idx = (ch_addr >> 6);
1044 else
1045 idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */
1046 idx %= 1 << rir_way;
1047
1048 pci_read_config_dword(pvt->pci_tad[base_ch],
1049 rir_offset[n_rir][idx],
1050 &reg);
1051 *rank = RIR_RNK_TGT(reg);
1052
956b9ba1
JP		 1053 edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
1054 n_rir,
1055 ch_addr,
1056 limit,
1057 rir_way,
1058 idx);
eebf11a0
MCC		 1059
1060 return 0;
1061}
1062
1063/****************************************************************************
1064 Device initialization routines: put/get, init/exit
1065 ****************************************************************************/
1066
1067/*
1068 * sbridge_put_all_devices 'put' all the devices that we have
1069 * reserved via 'get'
1070 */
1071static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
1072{
1073 int i;
1074
956b9ba1 1075 edac_dbg(0, "\n");
eebf11a0
MCC		 1076 for (i = 0; i < sbridge_dev->n_devs; i++) {
1077 struct pci_dev *pdev = sbridge_dev->pdev[i];
1078 if (!pdev)
1079 continue;
956b9ba1
JP		 1080 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
1081 pdev->bus->number,
1082 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
eebf11a0
MCC		 1083 pci_dev_put(pdev);
1084 }
1085}
1086
1087static void sbridge_put_all_devices(void)
1088{
1089 struct sbridge_dev *sbridge_dev, *tmp;
1090
1091 list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
1092 sbridge_put_devices(sbridge_dev);
1093 free_sbridge_dev(sbridge_dev);
1094 }
1095}
1096
1097/*
1098 * sbridge_get_all_devices Find and perform 'get' operation on the MCH's
1099 * device/functions we want to reference for this driver
1100 *
1101 * Need to 'get' device 16 func 1 and func 2
1102 */
1103static int sbridge_get_onedevice(struct pci_dev **prev,
1104 u8 *num_mc,
1105 const struct pci_id_table *table,
1106 const unsigned devno)
1107{
1108 struct sbridge_dev *sbridge_dev;
1109 const struct pci_id_descr *dev_descr = &table->descr[devno];
1110
1111 struct pci_dev *pdev = NULL;
1112 u8 bus = 0;
1113
1114 sbridge_printk(KERN_INFO,
1115 "Seeking for: dev %02x.%d PCI ID %04x:%04x\n",
1116 dev_descr->dev, dev_descr->func,
1117 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1118
1119 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1120 dev_descr->dev_id, *prev);
1121
1122 if (!pdev) {
1123 if (*prev) {
1124 *prev = pdev;
1125 return 0;
1126 }
1127
1128 if (dev_descr->optional)
1129 return 0;
1130
1131 if (devno == 0)
1132 return -ENODEV;
1133
1134 sbridge_printk(KERN_INFO,
1135 "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
1136 dev_descr->dev, dev_descr->func,
1137 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1138
1139 /* End of list, leave */
1140 return -ENODEV;
1141 }
1142 bus = pdev->bus->number;
1143
1144 sbridge_dev = get_sbridge_dev(bus);
1145 if (!sbridge_dev) {
1146 sbridge_dev = alloc_sbridge_dev(bus, table);
1147 if (!sbridge_dev) {
1148 pci_dev_put(pdev);
1149 return -ENOMEM;
1150 }
1151 (*num_mc)++;
1152 }
1153
1154 if (sbridge_dev->pdev[devno]) {
1155 sbridge_printk(KERN_ERR,
1156 "Duplicated device for "
1157 "dev %02x:%d.%d PCI ID %04x:%04x\n",
1158 bus, dev_descr->dev, dev_descr->func,
1159 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1160 pci_dev_put(pdev);
1161 return -ENODEV;
1162 }
1163
1164 sbridge_dev->pdev[devno] = pdev;
1165
1166 /* Sanity check */
1167 if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev ||
1168 PCI_FUNC(pdev->devfn) != dev_descr->func)) {
1169 sbridge_printk(KERN_ERR,
1170 "Device PCI ID %04x:%04x "
1171 "has dev %02x:%d.%d instead of dev %02x:%02x.%d\n",
1172 PCI_VENDOR_ID_INTEL, dev_descr->dev_id,
1173 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1174 bus, dev_descr->dev, dev_descr->func);
1175 return -ENODEV;
1176 }
1177
1178 /* Be sure that the device is enabled */
1179 if (unlikely(pci_enable_device(pdev) < 0)) {
1180 sbridge_printk(KERN_ERR,
1181 "Couldn't enable "
1182 "dev %02x:%d.%d PCI ID %04x:%04x\n",
1183 bus, dev_descr->dev, dev_descr->func,
1184 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1185 return -ENODEV;
1186 }
1187
956b9ba1
JP		 1188 edac_dbg(0, "Detected dev %02x:%d.%d PCI ID %04x:%04x\n",
1189 bus, dev_descr->dev, dev_descr->func,
1190 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
eebf11a0
MCC		 1191
1192 /*
1193 * As stated on drivers/pci/search.c, the reference count for
1194 * @from is always decremented if it is not %NULL. So, as we need
1195 * to get all devices up to null, we need to do a get for the device
1196 */
1197 pci_dev_get(pdev);
1198
1199 *prev = pdev;
1200
1201 return 0;
1202}
1203
1204static int sbridge_get_all_devices(u8 *num_mc)
1205{
1206 int i, rc;
1207 struct pci_dev *pdev = NULL;
1208 const struct pci_id_table *table = pci_dev_descr_sbridge_table;
1209
1210 while (table && table->descr) {
1211 for (i = 0; i < table->n_devs; i++) {
1212 pdev = NULL;
1213 do {
1214 rc = sbridge_get_onedevice(&pdev, num_mc,
1215 table, i);
1216 if (rc < 0) {
1217 if (i == 0) {
1218 i = table->n_devs;
1219 break;
1220 }
1221 sbridge_put_all_devices();
1222 return -ENODEV;
1223 }
1224 } while (pdev);
1225 }
1226 table++;
1227 }
1228
1229 return 0;
1230}
1231
1232static int mci_bind_devs(struct mem_ctl_info *mci,
1233 struct sbridge_dev *sbridge_dev)
1234{
1235 struct sbridge_pvt *pvt = mci->pvt_info;
1236 struct pci_dev *pdev;
1237 int i, func, slot;
1238
1239 for (i = 0; i < sbridge_dev->n_devs; i++) {
1240 pdev = sbridge_dev->pdev[i];
1241 if (!pdev)
1242 continue;
1243 slot = PCI_SLOT(pdev->devfn);
1244 func = PCI_FUNC(pdev->devfn);
1245 switch (slot) {
1246 case 12:
1247 switch (func) {
1248 case 6:
1249 pvt->pci_sad0 = pdev;
1250 break;
1251 case 7:
1252 pvt->pci_sad1 = pdev;
1253 break;
1254 default:
1255 goto error;
1256 }
1257 break;
1258 case 13:
1259 switch (func) {
1260 case 6:
1261 pvt->pci_br = pdev;
1262 break;
1263 default:
1264 goto error;
1265 }
1266 break;
1267 case 14:
1268 switch (func) {
1269 case 0:
1270 pvt->pci_ha0 = pdev;
1271 break;
1272 default:
1273 goto error;
1274 }
1275 break;
1276 case 15:
1277 switch (func) {
1278 case 0:
1279 pvt->pci_ta = pdev;
1280 break;
1281 case 1:
1282 pvt->pci_ras = pdev;
1283 break;
1284 case 2:
1285 case 3:
1286 case 4:
1287 case 5:
1288 pvt->pci_tad[func - 2] = pdev;
1289 break;
1290 default:
1291 goto error;
1292 }
1293 break;
1294 case 17:
1295 switch (func) {
1296 case 0:
1297 pvt->pci_ddrio = pdev;
1298 break;
1299 default:
1300 goto error;
1301 }
1302 break;
1303 default:
1304 goto error;
1305 }
1306
956b9ba1
JP		 1307 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1308 sbridge_dev->bus,
1309 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1310 pdev);
eebf11a0
MCC		 1311 }
1312
1313 /* Check if everything were registered */
1314 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
de4772c6 1315 !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta)
eebf11a0
MCC		 1316 goto enodev;
1317
1318 for (i = 0; i < NUM_CHANNELS; i++) {
1319 if (!pvt->pci_tad[i])
1320 goto enodev;
1321 }
1322 return 0;
1323
1324enodev:
1325 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1326 return -ENODEV;
1327
1328error:
1329 sbridge_printk(KERN_ERR, "Device %d, function %d "
1330 "is out of the expected range\n",
1331 slot, func);
1332 return -EINVAL;
1333}
1334
1335/****************************************************************************
1336 Error check routines
1337 ****************************************************************************/
1338
1339/*
1340 * While Sandy Bridge has error count registers, SMI BIOS read values from
1341 * and resets the counters. So, they are not reliable for the OS to read
1342 * from them. So, we have no option but to just trust on whatever MCE is
1343 * telling us about the errors.
1344 */
1345static void sbridge_mce_output_error(struct mem_ctl_info *mci,
1346 const struct mce *m)
1347{
1348 struct mem_ctl_info *new_mci;
1349 struct sbridge_pvt *pvt = mci->pvt_info;
c36e3e77 1350 enum hw_event_mc_err_type tp_event;
e17a2f42 1351 char *type, *optype, msg[256];
eebf11a0
MCC		 1352 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
1353 bool overflow = GET_BITFIELD(m->status, 62, 62);
1354 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
1355 bool recoverable = GET_BITFIELD(m->status, 56, 56);
1356 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
1357 u32 mscod = GET_BITFIELD(m->status, 16, 31);
1358 u32 errcode = GET_BITFIELD(m->status, 0, 15);
1359 u32 channel = GET_BITFIELD(m->status, 0, 3);
1360 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
1361 long channel_mask, first_channel;
1362 u8 rank, socket;
c36e3e77 1363 int rc, dimm;
e17a2f42 1364 char *area_type = NULL;
eebf11a0 1365
c36e3e77
MCC		 1366 if (uncorrected_error) {
1367 if (ripv) {
1368 type = "FATAL";
1369 tp_event = HW_EVENT_ERR_FATAL;
1370 } else {
1371 type = "NON_FATAL";
1372 tp_event = HW_EVENT_ERR_UNCORRECTED;
1373 }
1374 } else {
1375 type = "CORRECTED";
1376 tp_event = HW_EVENT_ERR_CORRECTED;
1377 }
eebf11a0
MCC		 1378
1379 /*
15ed103a 1380 * According with Table 15-9 of the Intel Architecture spec vol 3A,
eebf11a0
MCC		 1381 * memory errors should fit in this mask:
1382 * 000f 0000 1mmm cccc (binary)
1383 * where:
1384 * f = Correction Report Filtering Bit. If 1, subsequent errors
1385 * won't be shown
1386 * mmm = error type
1387 * cccc = channel
1388 * If the mask doesn't match, report an error to the parsing logic
1389 */
1390 if (! ((errcode & 0xef80) == 0x80)) {
1391 optype = "Can't parse: it is not a mem";
1392 } else {
1393 switch (optypenum) {
1394 case 0:
c36e3e77 1395 optype = "generic undef request error";
eebf11a0
MCC		 1396 break;
1397 case 1:
c36e3e77 1398 optype = "memory read error";
eebf11a0
MCC		 1399 break;
1400 case 2:
c36e3e77 1401 optype = "memory write error";
eebf11a0
MCC		 1402 break;
1403 case 3:
c36e3e77 1404 optype = "addr/cmd error";
eebf11a0
MCC		 1405 break;
1406 case 4:
c36e3e77 1407 optype = "memory scrubbing error";
eebf11a0
MCC		 1408 break;
1409 default:
1410 optype = "reserved";
1411 break;
1412 }
1413 }
1414
1415 rc = get_memory_error_data(mci, m->addr, &socket,
e17a2f42 1416 &channel_mask, &rank, &area_type, msg);
eebf11a0 1417 if (rc < 0)
c36e3e77 1418 goto err_parsing;
eebf11a0
MCC		 1419 new_mci = get_mci_for_node_id(socket);
1420 if (!new_mci) {
c36e3e77
MCC		 1421 strcpy(msg, "Error: socket got corrupted!");
1422 goto err_parsing;
eebf11a0
MCC		 1423 }
1424 mci = new_mci;
1425 pvt = mci->pvt_info;
1426
1427 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
1428
1429 if (rank < 4)
1430 dimm = 0;
1431 else if (rank < 8)
1432 dimm = 1;
1433 else
1434 dimm = 2;
1435
eebf11a0
MCC		 1436
1437 /*
e17a2f42
MCC		 1438 * FIXME: On some memory configurations (mirror, lockstep), the
1439 * Memory Controller can't point the error to a single DIMM. The
1440 * EDAC core should be handling the channel mask, in order to point
1441 * to the group of dimm's where the error may be happening.
eebf11a0 1442 */
c36e3e77 1443 snprintf(msg, sizeof(msg),
c1053839 1444 "%s%s area:%s err_code:%04x:%04x socket:%d channel_mask:%ld rank:%d",
e17a2f42
MCC		 1445 overflow ? " OVERFLOW" : "",
1446 (uncorrected_error && recoverable) ? " recoverable" : "",
1447 area_type,
1448 mscod, errcode,
1449 socket,
1450 channel_mask,
1451 rank);
eebf11a0 1452
956b9ba1 1453 edac_dbg(0, "%s\n", msg);
eebf11a0 1454
c36e3e77
MCC		 1455 /* FIXME: need support for channel mask */
1456
ebe7e30a
SJ		 1457 if (channel == CHANNEL_UNSPECIFIED)
1458 channel = -1;
1459
eebf11a0 1460 /* Call the helper to output message */
c1053839 1461 edac_mc_handle_error(tp_event, mci, core_err_cnt,
c36e3e77
MCC		 1462 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
1463 channel, dimm, -1,
03f7eae8 1464 optype, msg);
c36e3e77
MCC		 1465 return;
1466err_parsing:
c1053839 1467 edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0,
c36e3e77 1468 -1, -1, -1,
03f7eae8 1469 msg, "");
eebf11a0 1470
eebf11a0
MCC		 1471}
1472
1473/*
1474 * sbridge_check_error Retrieve and process errors reported by the
1475 * hardware. Called by the Core module.
1476 */
1477static void sbridge_check_error(struct mem_ctl_info *mci)
1478{
1479 struct sbridge_pvt *pvt = mci->pvt_info;
1480 int i;
1481 unsigned count = 0;
1482 struct mce *m;
1483
1484 /*
1485 * MCE first step: Copy all mce errors into a temporary buffer
1486 * We use a double buffering here, to reduce the risk of
1487 * loosing an error.
1488 */
1489 smp_rmb();
1490 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
1491 % MCE_LOG_LEN;
1492 if (!count)
1493 return;
1494
1495 m = pvt->mce_outentry;
1496 if (pvt->mce_in + count > MCE_LOG_LEN) {
1497 unsigned l = MCE_LOG_LEN - pvt->mce_in;
1498
1499 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
1500 smp_wmb();
1501 pvt->mce_in = 0;
1502 count -= l;
1503 m += l;
1504 }
1505 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
1506 smp_wmb();
1507 pvt->mce_in += count;
1508
1509 smp_rmb();
1510 if (pvt->mce_overrun) {
1511 sbridge_printk(KERN_ERR, "Lost %d memory errors\n",
1512 pvt->mce_overrun);
1513 smp_wmb();
1514 pvt->mce_overrun = 0;
1515 }
1516
1517 /*
1518 * MCE second step: parse errors and display
1519 */
1520 for (i = 0; i < count; i++)
1521 sbridge_mce_output_error(mci, &pvt->mce_outentry[i]);
1522}
1523
1524/*
1525 * sbridge_mce_check_error Replicates mcelog routine to get errors
1526 * This routine simply queues mcelog errors, and
1527 * return. The error itself should be handled later
1528 * by sbridge_check_error.
1529 * WARNING: As this routine should be called at NMI time, extra care should
1530 * be taken to avoid deadlocks, and to be as fast as possible.
1531 */
3d78c9af
MCC		 1532static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
1533 void *data)
eebf11a0 1534{
3d78c9af
MCC		 1535 struct mce *mce = (struct mce *)data;
1536 struct mem_ctl_info *mci;
1537 struct sbridge_pvt *pvt;
1538
1539 mci = get_mci_for_node_id(mce->socketid);
1540 if (!mci)
8d418eb3 1541 return NOTIFY_DONE;
3d78c9af 1542 pvt = mci->pvt_info;
eebf11a0
MCC		 1543
1544 /*
1545 * Just let mcelog handle it if the error is
1546 * outside the memory controller. A memory error
1547 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
1548 * bit 12 has an special meaning.
1549 */
1550 if ((mce->status & 0xefff) >> 7 != 1)
3d78c9af 1551 return NOTIFY_DONE;
eebf11a0
MCC		 1552
1553 printk("sbridge: HANDLING MCE MEMORY ERROR\n");
1554
1555 printk("CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
1556 mce->extcpu, mce->mcgstatus, mce->bank, mce->status);
1557 printk("TSC %llx ", mce->tsc);
1558 printk("ADDR %llx ", mce->addr);
1559 printk("MISC %llx ", mce->misc);
1560
1561 printk("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
1562 mce->cpuvendor, mce->cpuid, mce->time,
1563 mce->socketid, mce->apicid);
1564
eebf11a0
MCC		 1565 /* Only handle if it is the right mc controller */
1566 if (cpu_data(mce->cpu).phys_proc_id != pvt->sbridge_dev->mc)
3d78c9af 1567 return NOTIFY_DONE;
eebf11a0
MCC		 1568
1569 smp_rmb();
1570 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
1571 smp_wmb();
1572 pvt->mce_overrun++;
3d78c9af 1573 return NOTIFY_DONE;
eebf11a0
MCC		 1574 }
1575
1576 /* Copy memory error at the ringbuffer */
1577 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
1578 smp_wmb();
1579 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
1580
1581 /* Handle fatal errors immediately */
1582 if (mce->mcgstatus & 1)
1583 sbridge_check_error(mci);
1584
1585 /* Advice mcelog that the error were handled */
3d78c9af 1586 return NOTIFY_STOP;
eebf11a0
MCC		 1587}
1588
3d78c9af
MCC		 1589static struct notifier_block sbridge_mce_dec = {
1590 .notifier_call = sbridge_mce_check_error,
1591};
1592
eebf11a0
MCC		 1593/****************************************************************************
1594 EDAC register/unregister logic
1595 ****************************************************************************/
1596
1597static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
1598{
1599 struct mem_ctl_info *mci = sbridge_dev->mci;
1600 struct sbridge_pvt *pvt;
1601
1602 if (unlikely(!mci || !mci->pvt_info)) {
956b9ba1 1603 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);
eebf11a0
MCC		 1604
1605 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
1606 return;
1607 }
1608
1609 pvt = mci->pvt_info;
1610
956b9ba1
JP		 1611 edac_dbg(0, "MC: mci = %p, dev = %p\n",
1612 mci, &sbridge_dev->pdev[0]->dev);
eebf11a0 1613
eebf11a0 1614 /* Remove MC sysfs nodes */
fd687502 1615 edac_mc_del_mc(mci->pdev);
eebf11a0 1616
956b9ba1 1617 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
eebf11a0
MCC		 1618 kfree(mci->ctl_name);
1619 edac_mc_free(mci);
1620 sbridge_dev->mci = NULL;
1621}
1622
1623static int sbridge_register_mci(struct sbridge_dev *sbridge_dev)
1624{
1625 struct mem_ctl_info *mci;
c36e3e77 1626 struct edac_mc_layer layers[2];
eebf11a0 1627 struct sbridge_pvt *pvt;
c36e3e77 1628 int rc;
eebf11a0
MCC		 1629
1630 /* Check the number of active and not disabled channels */
c36e3e77 1631 rc = check_if_ecc_is_active(sbridge_dev->bus);
eebf11a0
MCC		 1632 if (unlikely(rc < 0))
1633 return rc;
1634
1635 /* allocate a new MC control structure */
c36e3e77
MCC		 1636 layers[0].type = EDAC_MC_LAYER_CHANNEL;
1637 layers[0].size = NUM_CHANNELS;
1638 layers[0].is_virt_csrow = false;
1639 layers[1].type = EDAC_MC_LAYER_SLOT;
1640 layers[1].size = MAX_DIMMS;
1641 layers[1].is_virt_csrow = true;
ca0907b9 1642 mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
c36e3e77
MCC		 1643 sizeof(*pvt));
1644
eebf11a0
MCC		 1645 if (unlikely(!mci))
1646 return -ENOMEM;
1647
956b9ba1
JP		 1648 edac_dbg(0, "MC: mci = %p, dev = %p\n",
1649 mci, &sbridge_dev->pdev[0]->dev);
eebf11a0
MCC		 1650
1651 pvt = mci->pvt_info;
1652 memset(pvt, 0, sizeof(*pvt));
1653
1654 /* Associate sbridge_dev and mci for future usage */
1655 pvt->sbridge_dev = sbridge_dev;
1656 sbridge_dev->mci = mci;
1657
1658 mci->mtype_cap = MEM_FLAG_DDR3;
1659 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1660 mci->edac_cap = EDAC_FLAG_NONE;
1661 mci->mod_name = "sbridge_edac.c";
1662 mci->mod_ver = SBRIDGE_REVISION;
1663 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
1664 mci->dev_name = pci_name(sbridge_dev->pdev[0]);
1665 mci->ctl_page_to_phys = NULL;
1666
1667 /* Set the function pointer to an actual operation function */
1668 mci->edac_check = sbridge_check_error;
1669
1670 /* Store pci devices at mci for faster access */
1671 rc = mci_bind_devs(mci, sbridge_dev);
1672 if (unlikely(rc < 0))
1673 goto fail0;
1674
1675 /* Get dimm basic config and the memory layout */
1676 get_dimm_config(mci);
1677 get_memory_layout(mci);
1678
1679 /* record ptr to the generic device */
fd687502 1680 mci->pdev = &sbridge_dev->pdev[0]->dev;
eebf11a0
MCC		 1681
1682 /* add this new MC control structure to EDAC's list of MCs */
1683 if (unlikely(edac_mc_add_mc(mci))) {
956b9ba1 1684 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
eebf11a0
MCC		 1685 rc = -EINVAL;
1686 goto fail0;
1687 }
1688
eebf11a0 1689 return 0;
eebf11a0
MCC		 1690
1691fail0:
1692 kfree(mci->ctl_name);
1693 edac_mc_free(mci);
1694 sbridge_dev->mci = NULL;
1695 return rc;
1696}
1697
1698/*
1699 * sbridge_probe Probe for ONE instance of device to see if it is
1700 * present.
1701 * return:
1702 * 0 for FOUND a device
1703 * < 0 for error code
1704 */
1705
9b3c6e85 1706static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id)
eebf11a0
MCC		 1707{
1708 int rc;
1709 u8 mc, num_mc = 0;
1710 struct sbridge_dev *sbridge_dev;
1711
1712 /* get the pci devices we want to reserve for our use */
1713 mutex_lock(&sbridge_edac_lock);
1714
1715 /*
1716 * All memory controllers are allocated at the first pass.
1717 */
1718 if (unlikely(probed >= 1)) {
1719 mutex_unlock(&sbridge_edac_lock);
1720 return -ENODEV;
1721 }
1722 probed++;
1723
1724 rc = sbridge_get_all_devices(&num_mc);
1725 if (unlikely(rc < 0))
1726 goto fail0;
1727 mc = 0;
1728
1729 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
956b9ba1
JP		 1730 edac_dbg(0, "Registering MC#%d (%d of %d)\n",
1731 mc, mc + 1, num_mc);
eebf11a0
MCC		 1732 sbridge_dev->mc = mc++;
1733 rc = sbridge_register_mci(sbridge_dev);
1734 if (unlikely(rc < 0))
1735 goto fail1;
1736 }
1737
1738 sbridge_printk(KERN_INFO, "Driver loaded.\n");
1739
1740 mutex_unlock(&sbridge_edac_lock);
1741 return 0;
1742
1743fail1:
1744 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
1745 sbridge_unregister_mci(sbridge_dev);
1746
1747 sbridge_put_all_devices();
1748fail0:
1749 mutex_unlock(&sbridge_edac_lock);
1750 return rc;
1751}
1752
1753/*
1754 * sbridge_remove destructor for one instance of device
1755 *
1756 */
9b3c6e85 1757static void sbridge_remove(struct pci_dev *pdev)
eebf11a0
MCC		 1758{
1759 struct sbridge_dev *sbridge_dev;
1760
956b9ba1 1761 edac_dbg(0, "\n");
eebf11a0
MCC		 1762
1763 /*
1764 * we have a trouble here: pdev value for removal will be wrong, since
1765 * it will point to the X58 register used to detect that the machine
1766 * is a Nehalem or upper design. However, due to the way several PCI
1767 * devices are grouped together to provide MC functionality, we need
1768 * to use a different method for releasing the devices
1769 */
1770
1771 mutex_lock(&sbridge_edac_lock);
1772
1773 if (unlikely(!probed)) {
1774 mutex_unlock(&sbridge_edac_lock);
1775 return;
1776 }
1777
1778 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
1779 sbridge_unregister_mci(sbridge_dev);
1780
1781 /* Release PCI resources */
1782 sbridge_put_all_devices();
1783
1784 probed--;
1785
1786 mutex_unlock(&sbridge_edac_lock);
1787}
1788
1789MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl);
1790
1791/*
1792 * sbridge_driver pci_driver structure for this module
1793 *
1794 */
1795static struct pci_driver sbridge_driver = {
1796 .name = "sbridge_edac",
1797 .probe = sbridge_probe,
9b3c6e85 1798 .remove = sbridge_remove,
eebf11a0
MCC		 1799 .id_table = sbridge_pci_tbl,
1800};
1801
1802/*
1803 * sbridge_init Module entry function
1804 * Try to initialize this module for its devices
1805 */
1806static int __init sbridge_init(void)
1807{
1808 int pci_rc;
1809
956b9ba1 1810 edac_dbg(2, "\n");
eebf11a0
MCC		 1811
1812 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1813 opstate_init();
1814
1815 pci_rc = pci_register_driver(&sbridge_driver);
1816
e35fca47
CG		 1817 if (pci_rc >= 0) {
1818 mce_register_decode_chain(&sbridge_mce_dec);
eebf11a0 1819 return 0;
e35fca47 1820 }
eebf11a0
MCC		 1821
1822 sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
1823 pci_rc);
1824
1825 return pci_rc;
1826}
1827
1828/*
1829 * sbridge_exit() Module exit function
1830 * Unregister the driver
1831 */
1832static void __exit sbridge_exit(void)
1833{
956b9ba1 1834 edac_dbg(2, "\n");
eebf11a0 1835 pci_unregister_driver(&sbridge_driver);
e35fca47 1836 mce_unregister_decode_chain(&sbridge_mce_dec);
eebf11a0
MCC		 1837}
1838
1839module_init(sbridge_init);
1840module_exit(sbridge_exit);
1841
1842module_param(edac_op_state, int, 0444);
1843MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
1844
1845MODULE_LICENSE("GPL");
1846MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1847MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
1848MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge memory controllers - "
1849 SBRIDGE_REVISION);
kernel source for telekom puls (alcatel/mediatek)