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[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / spi / pxa2xx_spi.c
CommitLineData
e0c9905e
SS		 1/*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/device.h>
22#include <linux/ioport.h>
23#include <linux/errno.h>
24#include <linux/interrupt.h>
25#include <linux/platform_device.h>
26#include <linux/dma-mapping.h>
27#include <linux/spi/spi.h>
28#include <linux/workqueue.h>
e0c9905e 29#include <linux/delay.h>
2f1a74e5 30#include <linux/clk.h>
e0c9905e
SS		 31
32#include <asm/io.h>
33#include <asm/irq.h>
e0c9905e
SS		 34#include <asm/delay.h>
35#include <asm/dma.h>
36
a09e64fb
RK		 37#include <mach/hardware.h>
38#include <mach/pxa-regs.h>
39#include <mach/regs-ssp.h>
40#include <mach/ssp.h>
41#include <mach/pxa2xx_spi.h>
e0c9905e
SS		 42
43MODULE_AUTHOR("Stephen Street");
037cdafe 44MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
e0c9905e 45MODULE_LICENSE("GPL");
7e38c3c4 46MODULE_ALIAS("platform:pxa2xx-spi");
e0c9905e
SS		 47
48#define MAX_BUSES 3
49
50#define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
51#define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
52#define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
53
b97c74bd
NF		 54/*
55 * for testing SSCR1 changes that require SSP restart, basically
56 * everything except the service and interrupt enables, the pxa270 developer
57 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
58 * list, but the PXA255 dev man says all bits without really meaning the
59 * service and interrupt enables
60 */
61#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
8d94cc50 62 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
b97c74bd
NF		 63 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
64 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
65 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
66 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
8d94cc50 67
e0c9905e 68#define DEFINE_SSP_REG(reg, off) \
cf43369d
DB		 69static inline u32 read_##reg(void const __iomem *p) \
70{ return __raw_readl(p + (off)); } \
71\
72static inline void write_##reg(u32 v, void __iomem *p) \
73{ __raw_writel(v, p + (off)); }
e0c9905e
SS		 74
75DEFINE_SSP_REG(SSCR0, 0x00)
76DEFINE_SSP_REG(SSCR1, 0x04)
77DEFINE_SSP_REG(SSSR, 0x08)
78DEFINE_SSP_REG(SSITR, 0x0c)
79DEFINE_SSP_REG(SSDR, 0x10)
80DEFINE_SSP_REG(SSTO, 0x28)
81DEFINE_SSP_REG(SSPSP, 0x2c)
82
83#define START_STATE ((void*)0)
84#define RUNNING_STATE ((void*)1)
85#define DONE_STATE ((void*)2)
86#define ERROR_STATE ((void*)-1)
87
88#define QUEUE_RUNNING 0
89#define QUEUE_STOPPED 1
90
91struct driver_data {
92 /* Driver model hookup */
93 struct platform_device *pdev;
94
2f1a74e5 95 /* SSP Info */
96 struct ssp_device *ssp;
97
e0c9905e
SS		 98 /* SPI framework hookup */
99 enum pxa_ssp_type ssp_type;
100 struct spi_master *master;
101
102 /* PXA hookup */
103 struct pxa2xx_spi_master *master_info;
104
105 /* DMA setup stuff */
106 int rx_channel;
107 int tx_channel;
108 u32 *null_dma_buf;
109
110 /* SSP register addresses */
cf43369d 111 void __iomem *ioaddr;
e0c9905e
SS		 112 u32 ssdr_physical;
113
114 /* SSP masks*/
115 u32 dma_cr1;
116 u32 int_cr1;
117 u32 clear_sr;
118 u32 mask_sr;
119
120 /* Driver message queue */
121 struct workqueue_struct *workqueue;
122 struct work_struct pump_messages;
123 spinlock_t lock;
124 struct list_head queue;
125 int busy;
126 int run;
127
128 /* Message Transfer pump */
129 struct tasklet_struct pump_transfers;
130
131 /* Current message transfer state info */
132 struct spi_message* cur_msg;
133 struct spi_transfer* cur_transfer;
134 struct chip_data *cur_chip;
135 size_t len;
136 void *tx;
137 void *tx_end;
138 void *rx;
139 void *rx_end;
140 int dma_mapped;
141 dma_addr_t rx_dma;
142 dma_addr_t tx_dma;
143 size_t rx_map_len;
144 size_t tx_map_len;
9708c121
SS		 145 u8 n_bytes;
146 u32 dma_width;
e0c9905e 147 int cs_change;
8d94cc50
SS		 148 int (*write)(struct driver_data *drv_data);
149 int (*read)(struct driver_data *drv_data);
e0c9905e
SS		 150 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
151 void (*cs_control)(u32 command);
152};
153
154struct chip_data {
155 u32 cr0;
156 u32 cr1;
e0c9905e
SS		 157 u32 psp;
158 u32 timeout;
159 u8 n_bytes;
160 u32 dma_width;
161 u32 dma_burst_size;
162 u32 threshold;
163 u32 dma_threshold;
164 u8 enable_dma;
9708c121
SS		 165 u8 bits_per_word;
166 u32 speed_hz;
8d94cc50
SS		 167 int (*write)(struct driver_data *drv_data);
168 int (*read)(struct driver_data *drv_data);
e0c9905e
SS		 169 void (*cs_control)(u32 command);
170};
171
6d5aefb8 172static void pump_messages(struct work_struct *work);
e0c9905e
SS		 173
174static int flush(struct driver_data *drv_data)
175{
176 unsigned long limit = loops_per_jiffy << 1;
177
cf43369d 178 void __iomem *reg = drv_data->ioaddr;
e0c9905e
SS		 179
180 do {
181 while (read_SSSR(reg) & SSSR_RNE) {
182 read_SSDR(reg);
183 }
184 } while ((read_SSSR(reg) & SSSR_BSY) && limit--);
185 write_SSSR(SSSR_ROR, reg);
186
187 return limit;
188}
189
e0c9905e
SS		 190static void null_cs_control(u32 command)
191{
192}
193
8d94cc50 194static int null_writer(struct driver_data *drv_data)
e0c9905e 195{
cf43369d 196 void __iomem *reg = drv_data->ioaddr;
9708c121 197 u8 n_bytes = drv_data->n_bytes;
e0c9905e 198
8d94cc50
SS		 199 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
200 || (drv_data->tx == drv_data->tx_end))
201 return 0;
202
203 write_SSDR(0, reg);
204 drv_data->tx += n_bytes;
205
206 return 1;
e0c9905e
SS		 207}
208
8d94cc50 209static int null_reader(struct driver_data *drv_data)
e0c9905e 210{
cf43369d 211 void __iomem *reg = drv_data->ioaddr;
9708c121 212 u8 n_bytes = drv_data->n_bytes;
e0c9905e
SS		 213
214 while ((read_SSSR(reg) & SSSR_RNE)
8d94cc50 215 && (drv_data->rx < drv_data->rx_end)) {
e0c9905e
SS		 216 read_SSDR(reg);
217 drv_data->rx += n_bytes;
218 }
8d94cc50
SS		 219
220 return drv_data->rx == drv_data->rx_end;
e0c9905e
SS		 221}
222
8d94cc50 223static int u8_writer(struct driver_data *drv_data)
e0c9905e 224{
cf43369d 225 void __iomem *reg = drv_data->ioaddr;
e0c9905e 226
8d94cc50
SS		 227 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
228 || (drv_data->tx == drv_data->tx_end))
229 return 0;
230
231 write_SSDR(*(u8 *)(drv_data->tx), reg);
232 ++drv_data->tx;
233
234 return 1;
e0c9905e
SS		 235}
236
8d94cc50 237static int u8_reader(struct driver_data *drv_data)
e0c9905e 238{
cf43369d 239 void __iomem *reg = drv_data->ioaddr;
e0c9905e
SS		 240
241 while ((read_SSSR(reg) & SSSR_RNE)
8d94cc50 242 && (drv_data->rx < drv_data->rx_end)) {
e0c9905e
SS		 243 *(u8 *)(drv_data->rx) = read_SSDR(reg);
244 ++drv_data->rx;
245 }
8d94cc50
SS		 246
247 return drv_data->rx == drv_data->rx_end;
e0c9905e
SS		 248}
249
8d94cc50 250static int u16_writer(struct driver_data *drv_data)
e0c9905e 251{
cf43369d 252 void __iomem *reg = drv_data->ioaddr;
e0c9905e 253
8d94cc50
SS		 254 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
255 || (drv_data->tx == drv_data->tx_end))
256 return 0;
257
258 write_SSDR(*(u16 *)(drv_data->tx), reg);
259 drv_data->tx += 2;
260
261 return 1;
e0c9905e
SS		 262}
263
8d94cc50 264static int u16_reader(struct driver_data *drv_data)
e0c9905e 265{
cf43369d 266 void __iomem *reg = drv_data->ioaddr;
e0c9905e
SS		 267
268 while ((read_SSSR(reg) & SSSR_RNE)
8d94cc50 269 && (drv_data->rx < drv_data->rx_end)) {
e0c9905e
SS		 270 *(u16 *)(drv_data->rx) = read_SSDR(reg);
271 drv_data->rx += 2;
272 }
8d94cc50
SS		 273
274 return drv_data->rx == drv_data->rx_end;
e0c9905e 275}
8d94cc50
SS		 276
277static int u32_writer(struct driver_data *drv_data)
e0c9905e 278{
cf43369d 279 void __iomem *reg = drv_data->ioaddr;
e0c9905e 280
8d94cc50
SS		 281 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
282 || (drv_data->tx == drv_data->tx_end))
283 return 0;
284
285 write_SSDR(*(u32 *)(drv_data->tx), reg);
286 drv_data->tx += 4;
287
288 return 1;
e0c9905e
SS		 289}
290
8d94cc50 291static int u32_reader(struct driver_data *drv_data)
e0c9905e 292{
cf43369d 293 void __iomem *reg = drv_data->ioaddr;
e0c9905e
SS		 294
295 while ((read_SSSR(reg) & SSSR_RNE)
8d94cc50 296 && (drv_data->rx < drv_data->rx_end)) {
e0c9905e
SS		 297 *(u32 *)(drv_data->rx) = read_SSDR(reg);
298 drv_data->rx += 4;
299 }
8d94cc50
SS		 300
301 return drv_data->rx == drv_data->rx_end;
e0c9905e
SS		 302}
303
304static void *next_transfer(struct driver_data *drv_data)
305{
306 struct spi_message *msg = drv_data->cur_msg;
307 struct spi_transfer *trans = drv_data->cur_transfer;
308
309 /* Move to next transfer */
310 if (trans->transfer_list.next != &msg->transfers) {
311 drv_data->cur_transfer =
312 list_entry(trans->transfer_list.next,
313 struct spi_transfer,
314 transfer_list);
315 return RUNNING_STATE;
316 } else
317 return DONE_STATE;
318}
319
320static int map_dma_buffers(struct driver_data *drv_data)
321{
322 struct spi_message *msg = drv_data->cur_msg;
323 struct device *dev = &msg->spi->dev;
324
325 if (!drv_data->cur_chip->enable_dma)
326 return 0;
327
328 if (msg->is_dma_mapped)
329 return drv_data->rx_dma && drv_data->tx_dma;
330
331 if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
332 return 0;
333
334 /* Modify setup if rx buffer is null */
335 if (drv_data->rx == NULL) {
336 *drv_data->null_dma_buf = 0;
337 drv_data->rx = drv_data->null_dma_buf;
338 drv_data->rx_map_len = 4;
339 } else
340 drv_data->rx_map_len = drv_data->len;
341
342
343 /* Modify setup if tx buffer is null */
344 if (drv_data->tx == NULL) {
345 *drv_data->null_dma_buf = 0;
346 drv_data->tx = drv_data->null_dma_buf;
347 drv_data->tx_map_len = 4;
348 } else
349 drv_data->tx_map_len = drv_data->len;
350
351 /* Stream map the rx buffer */
352 drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
353 drv_data->rx_map_len,
354 DMA_FROM_DEVICE);
8d8bb39b 355 if (dma_mapping_error(dev, drv_data->rx_dma))
e0c9905e
SS		 356 return 0;
357
358 /* Stream map the tx buffer */
359 drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
360 drv_data->tx_map_len,
361 DMA_TO_DEVICE);
362
8d8bb39b 363 if (dma_mapping_error(dev, drv_data->tx_dma)) {
e0c9905e
SS		 364 dma_unmap_single(dev, drv_data->rx_dma,
365 drv_data->rx_map_len, DMA_FROM_DEVICE);
366 return 0;
367 }
368
369 return 1;
370}
371
372static void unmap_dma_buffers(struct driver_data *drv_data)
373{
374 struct device *dev;
375
376 if (!drv_data->dma_mapped)
377 return;
378
379 if (!drv_data->cur_msg->is_dma_mapped) {
380 dev = &drv_data->cur_msg->spi->dev;
381 dma_unmap_single(dev, drv_data->rx_dma,
382 drv_data->rx_map_len, DMA_FROM_DEVICE);
383 dma_unmap_single(dev, drv_data->tx_dma,
384 drv_data->tx_map_len, DMA_TO_DEVICE);
385 }
386
387 drv_data->dma_mapped = 0;
388}
389
390/* caller already set message->status; dma and pio irqs are blocked */
5daa3ba0 391static void giveback(struct driver_data *drv_data)
e0c9905e
SS		 392{
393 struct spi_transfer* last_transfer;
5daa3ba0
SS		 394 unsigned long flags;
395 struct spi_message *msg;
e0c9905e 396
5daa3ba0
SS		 397 spin_lock_irqsave(&drv_data->lock, flags);
398 msg = drv_data->cur_msg;
399 drv_data->cur_msg = NULL;
400 drv_data->cur_transfer = NULL;
401 drv_data->cur_chip = NULL;
402 queue_work(drv_data->workqueue, &drv_data->pump_messages);
403 spin_unlock_irqrestore(&drv_data->lock, flags);
404
405 last_transfer = list_entry(msg->transfers.prev,
e0c9905e
SS		 406 struct spi_transfer,
407 transfer_list);
408
409 if (!last_transfer->cs_change)
410 drv_data->cs_control(PXA2XX_CS_DEASSERT);
411
5daa3ba0
SS		 412 msg->state = NULL;
413 if (msg->complete)
414 msg->complete(msg->context);
e0c9905e
SS		 415}
416
cf43369d 417static int wait_ssp_rx_stall(void const __iomem *ioaddr)
e0c9905e
SS		 418{
419 unsigned long limit = loops_per_jiffy << 1;
420
421 while ((read_SSSR(ioaddr) & SSSR_BSY) && limit--)
422 cpu_relax();
423
424 return limit;
425}
426
427static int wait_dma_channel_stop(int channel)
428{
429 unsigned long limit = loops_per_jiffy << 1;
430
431 while (!(DCSR(channel) & DCSR_STOPSTATE) && limit--)
432 cpu_relax();
433
434 return limit;
435}
436
cf43369d 437static void dma_error_stop(struct driver_data *drv_data, const char *msg)
e0c9905e 438{
cf43369d 439 void __iomem *reg = drv_data->ioaddr;
e0c9905e 440
8d94cc50
SS		 441 /* Stop and reset */
442 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
443 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
444 write_SSSR(drv_data->clear_sr, reg);
445 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
446 if (drv_data->ssp_type != PXA25x_SSP)
447 write_SSTO(0, reg);
448 flush(drv_data);
449 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
e0c9905e 450
8d94cc50 451 unmap_dma_buffers(drv_data);
e0c9905e 452
8d94cc50 453 dev_err(&drv_data->pdev->dev, "%s\n", msg);
e0c9905e 454
8d94cc50
SS		 455 drv_data->cur_msg->state = ERROR_STATE;
456 tasklet_schedule(&drv_data->pump_transfers);
457}
458
459static void dma_transfer_complete(struct driver_data *drv_data)
460{
cf43369d 461 void __iomem *reg = drv_data->ioaddr;
8d94cc50
SS		 462 struct spi_message *msg = drv_data->cur_msg;
463
464 /* Clear and disable interrupts on SSP and DMA channels*/
465 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
466 write_SSSR(drv_data->clear_sr, reg);
467 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
468 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
469
470 if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
471 dev_err(&drv_data->pdev->dev,
472 "dma_handler: dma rx channel stop failed\n");
473
474 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
475 dev_err(&drv_data->pdev->dev,
476 "dma_transfer: ssp rx stall failed\n");
477
478 unmap_dma_buffers(drv_data);
479
480 /* update the buffer pointer for the amount completed in dma */
481 drv_data->rx += drv_data->len -
482 (DCMD(drv_data->rx_channel) & DCMD_LENGTH);
483
484 /* read trailing data from fifo, it does not matter how many
485 * bytes are in the fifo just read until buffer is full
486 * or fifo is empty, which ever occurs first */
487 drv_data->read(drv_data);
488
489 /* return count of what was actually read */
490 msg->actual_length += drv_data->len -
491 (drv_data->rx_end - drv_data->rx);
492
493 /* Release chip select if requested, transfer delays are
494 * handled in pump_transfers */
495 if (drv_data->cs_change)
496 drv_data->cs_control(PXA2XX_CS_DEASSERT);
497
498 /* Move to next transfer */
499 msg->state = next_transfer(drv_data);
500
501 /* Schedule transfer tasklet */
502 tasklet_schedule(&drv_data->pump_transfers);
503}
504
505static void dma_handler(int channel, void *data)
506{
507 struct driver_data *drv_data = data;
508 u32 irq_status = DCSR(channel) & DMA_INT_MASK;
509
510 if (irq_status & DCSR_BUSERR) {
e0c9905e
SS		 511
512 if (channel == drv_data->tx_channel)
8d94cc50
SS		 513 dma_error_stop(drv_data,
514 "dma_handler: "
515 "bad bus address on tx channel");
e0c9905e 516 else
8d94cc50
SS		 517 dma_error_stop(drv_data,
518 "dma_handler: "
519 "bad bus address on rx channel");
520 return;
e0c9905e
SS		 521 }
522
523 /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
8d94cc50
SS		 524 if ((channel == drv_data->tx_channel)
525 && (irq_status & DCSR_ENDINTR)
526 && (drv_data->ssp_type == PXA25x_SSP)) {
e0c9905e
SS		 527
528 /* Wait for rx to stall */
529 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
530 dev_err(&drv_data->pdev->dev,
531 "dma_handler: ssp rx stall failed\n");
532
8d94cc50
SS		 533 /* finish this transfer, start the next */
534 dma_transfer_complete(drv_data);
e0c9905e
SS		 535 }
536}
537
538static irqreturn_t dma_transfer(struct driver_data *drv_data)
539{
540 u32 irq_status;
cf43369d 541 void __iomem *reg = drv_data->ioaddr;
e0c9905e
SS		 542
543 irq_status = read_SSSR(reg) & drv_data->mask_sr;
544 if (irq_status & SSSR_ROR) {
8d94cc50 545 dma_error_stop(drv_data, "dma_transfer: fifo overrun");
e0c9905e
SS		 546 return IRQ_HANDLED;
547 }
548
549 /* Check for false positive timeout */
8d94cc50
SS		 550 if ((irq_status & SSSR_TINT)
551 && (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
e0c9905e
SS		 552 write_SSSR(SSSR_TINT, reg);
553 return IRQ_HANDLED;
554 }
555
556 if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {
557
8d94cc50
SS		 558 /* Clear and disable timeout interrupt, do the rest in
559 * dma_transfer_complete */
e0c9905e
SS		 560 if (drv_data->ssp_type != PXA25x_SSP)
561 write_SSTO(0, reg);
e0c9905e 562
8d94cc50
SS		 563 /* finish this transfer, start the next */
564 dma_transfer_complete(drv_data);
e0c9905e
SS		 565
566 return IRQ_HANDLED;
567 }
568
569 /* Opps problem detected */
570 return IRQ_NONE;
571}
572
8d94cc50 573static void int_error_stop(struct driver_data *drv_data, const char* msg)
e0c9905e 574{
cf43369d 575 void __iomem *reg = drv_data->ioaddr;
e0c9905e 576
8d94cc50
SS		 577 /* Stop and reset SSP */
578 write_SSSR(drv_data->clear_sr, reg);
579 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
580 if (drv_data->ssp_type != PXA25x_SSP)
581 write_SSTO(0, reg);
582 flush(drv_data);
583 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
e0c9905e 584
8d94cc50 585 dev_err(&drv_data->pdev->dev, "%s\n", msg);
e0c9905e 586
8d94cc50
SS		 587 drv_data->cur_msg->state = ERROR_STATE;
588 tasklet_schedule(&drv_data->pump_transfers);
589}
5daa3ba0 590
8d94cc50
SS		 591static void int_transfer_complete(struct driver_data *drv_data)
592{
cf43369d 593 void __iomem *reg = drv_data->ioaddr;
e0c9905e 594
8d94cc50
SS		 595 /* Stop SSP */
596 write_SSSR(drv_data->clear_sr, reg);
597 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
598 if (drv_data->ssp_type != PXA25x_SSP)
599 write_SSTO(0, reg);
e0c9905e 600
8d94cc50
SS		 601 /* Update total byte transfered return count actual bytes read */
602 drv_data->cur_msg->actual_length += drv_data->len -
603 (drv_data->rx_end - drv_data->rx);
e0c9905e 604
8d94cc50
SS		 605 /* Release chip select if requested, transfer delays are
606 * handled in pump_transfers */
607 if (drv_data->cs_change)
608 drv_data->cs_control(PXA2XX_CS_DEASSERT);
e0c9905e 609
8d94cc50
SS		 610 /* Move to next transfer */
611 drv_data->cur_msg->state = next_transfer(drv_data);
e0c9905e 612
8d94cc50
SS		 613 /* Schedule transfer tasklet */
614 tasklet_schedule(&drv_data->pump_transfers);
615}
e0c9905e 616
8d94cc50
SS		 617static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
618{
cf43369d 619 void __iomem *reg = drv_data->ioaddr;
e0c9905e 620
8d94cc50
SS		 621 u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
622 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
e0c9905e 623
8d94cc50 624 u32 irq_status = read_SSSR(reg) & irq_mask;
e0c9905e 625
8d94cc50
SS		 626 if (irq_status & SSSR_ROR) {
627 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
628 return IRQ_HANDLED;
629 }
e0c9905e 630
8d94cc50
SS		 631 if (irq_status & SSSR_TINT) {
632 write_SSSR(SSSR_TINT, reg);
633 if (drv_data->read(drv_data)) {
634 int_transfer_complete(drv_data);
635 return IRQ_HANDLED;
636 }
637 }
e0c9905e 638
8d94cc50
SS		 639 /* Drain rx fifo, Fill tx fifo and prevent overruns */
640 do {
641 if (drv_data->read(drv_data)) {
642 int_transfer_complete(drv_data);
643 return IRQ_HANDLED;
644 }
645 } while (drv_data->write(drv_data));
e0c9905e 646
8d94cc50
SS		 647 if (drv_data->read(drv_data)) {
648 int_transfer_complete(drv_data);
649 return IRQ_HANDLED;
650 }
e0c9905e 651
8d94cc50
SS		 652 if (drv_data->tx == drv_data->tx_end) {
653 write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg);
654 /* PXA25x_SSP has no timeout, read trailing bytes */
655 if (drv_data->ssp_type == PXA25x_SSP) {
656 if (!wait_ssp_rx_stall(reg))
657 {
658 int_error_stop(drv_data, "interrupt_transfer: "
659 "rx stall failed");
660 return IRQ_HANDLED;
661 }
662 if (!drv_data->read(drv_data))
663 {
664 int_error_stop(drv_data,
665 "interrupt_transfer: "
666 "trailing byte read failed");
667 return IRQ_HANDLED;
668 }
669 int_transfer_complete(drv_data);
e0c9905e 670 }
e0c9905e
SS		 671 }
672
5daa3ba0
SS		 673 /* We did something */
674 return IRQ_HANDLED;
e0c9905e
SS		 675}
676
7d12e780 677static irqreturn_t ssp_int(int irq, void *dev_id)
e0c9905e 678{
c7bec5ab 679 struct driver_data *drv_data = dev_id;
cf43369d 680 void __iomem *reg = drv_data->ioaddr;
e0c9905e
SS		 681
682 if (!drv_data->cur_msg) {
5daa3ba0
SS		 683
684 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
685 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
686 if (drv_data->ssp_type != PXA25x_SSP)
687 write_SSTO(0, reg);
688 write_SSSR(drv_data->clear_sr, reg);
689
e0c9905e 690 dev_err(&drv_data->pdev->dev, "bad message state "
8d94cc50 691 "in interrupt handler\n");
5daa3ba0 692
e0c9905e
SS		 693 /* Never fail */
694 return IRQ_HANDLED;
695 }
696
697 return drv_data->transfer_handler(drv_data);
698}
699
cf43369d
DB		 700static int set_dma_burst_and_threshold(struct chip_data *chip,
701 struct spi_device *spi,
8d94cc50
SS		 702 u8 bits_per_word, u32 *burst_code,
703 u32 *threshold)
704{
705 struct pxa2xx_spi_chip *chip_info =
706 (struct pxa2xx_spi_chip *)spi->controller_data;
707 int bytes_per_word;
708 int burst_bytes;
709 int thresh_words;
710 int req_burst_size;
711 int retval = 0;
712
713 /* Set the threshold (in registers) to equal the same amount of data
714 * as represented by burst size (in bytes). The computation below
715 * is (burst_size rounded up to nearest 8 byte, word or long word)
716 * divided by (bytes/register); the tx threshold is the inverse of
717 * the rx, so that there will always be enough data in the rx fifo
718 * to satisfy a burst, and there will always be enough space in the
719 * tx fifo to accept a burst (a tx burst will overwrite the fifo if
720 * there is not enough space), there must always remain enough empty
721 * space in the rx fifo for any data loaded to the tx fifo.
722 * Whenever burst_size (in bytes) equals bits/word, the fifo threshold
723 * will be 8, or half the fifo;
724 * The threshold can only be set to 2, 4 or 8, but not 16, because
725 * to burst 16 to the tx fifo, the fifo would have to be empty;
726 * however, the minimum fifo trigger level is 1, and the tx will
727 * request service when the fifo is at this level, with only 15 spaces.
728 */
729
730 /* find bytes/word */
731 if (bits_per_word <= 8)
732 bytes_per_word = 1;
733 else if (bits_per_word <= 16)
734 bytes_per_word = 2;
735 else
736 bytes_per_word = 4;
737
738 /* use struct pxa2xx_spi_chip->dma_burst_size if available */
739 if (chip_info)
740 req_burst_size = chip_info->dma_burst_size;
741 else {
742 switch (chip->dma_burst_size) {
743 default:
744 /* if the default burst size is not set,
745 * do it now */
746 chip->dma_burst_size = DCMD_BURST8;
747 case DCMD_BURST8:
748 req_burst_size = 8;
749 break;
750 case DCMD_BURST16:
751 req_burst_size = 16;
752 break;
753 case DCMD_BURST32:
754 req_burst_size = 32;
755 break;
756 }
757 }
758 if (req_burst_size <= 8) {
759 *burst_code = DCMD_BURST8;
760 burst_bytes = 8;
761 } else if (req_burst_size <= 16) {
762 if (bytes_per_word == 1) {
763 /* don't burst more than 1/2 the fifo */
764 *burst_code = DCMD_BURST8;
765 burst_bytes = 8;
766 retval = 1;
767 } else {
768 *burst_code = DCMD_BURST16;
769 burst_bytes = 16;
770 }
771 } else {
772 if (bytes_per_word == 1) {
773 /* don't burst more than 1/2 the fifo */
774 *burst_code = DCMD_BURST8;
775 burst_bytes = 8;
776 retval = 1;
777 } else if (bytes_per_word == 2) {
778 /* don't burst more than 1/2 the fifo */
779 *burst_code = DCMD_BURST16;
780 burst_bytes = 16;
781 retval = 1;
782 } else {
783 *burst_code = DCMD_BURST32;
784 burst_bytes = 32;
785 }
786 }
787
788 thresh_words = burst_bytes / bytes_per_word;
789
790 /* thresh_words will be between 2 and 8 */
791 *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)
792 | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);
793
794 return retval;
795}
796
2f1a74e5 797static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate)
798{
799 unsigned long ssp_clk = clk_get_rate(ssp->clk);
800
801 if (ssp->type == PXA25x_SSP)
802 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
803 else
804 return ((ssp_clk / rate - 1) & 0xfff) << 8;
805}
806
e0c9905e
SS		 807static void pump_transfers(unsigned long data)
808{
809 struct driver_data *drv_data = (struct driver_data *)data;
810 struct spi_message *message = NULL;
811 struct spi_transfer *transfer = NULL;
812 struct spi_transfer *previous = NULL;
813 struct chip_data *chip = NULL;
2f1a74e5 814 struct ssp_device *ssp = drv_data->ssp;
cf43369d 815 void __iomem *reg = drv_data->ioaddr;
9708c121
SS		 816 u32 clk_div = 0;
817 u8 bits = 0;
818 u32 speed = 0;
819 u32 cr0;
8d94cc50
SS		 820 u32 cr1;
821 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
822 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
e0c9905e
SS		 823
824 /* Get current state information */
825 message = drv_data->cur_msg;
826 transfer = drv_data->cur_transfer;
827 chip = drv_data->cur_chip;
828
829 /* Handle for abort */
830 if (message->state == ERROR_STATE) {
831 message->status = -EIO;
5daa3ba0 832 giveback(drv_data);
e0c9905e
SS		 833 return;
834 }
835
836 /* Handle end of message */
837 if (message->state == DONE_STATE) {
838 message->status = 0;
5daa3ba0 839 giveback(drv_data);
e0c9905e
SS		 840 return;
841 }
842
843 /* Delay if requested at end of transfer*/
844 if (message->state == RUNNING_STATE) {
845 previous = list_entry(transfer->transfer_list.prev,
846 struct spi_transfer,
847 transfer_list);
848 if (previous->delay_usecs)
849 udelay(previous->delay_usecs);
850 }
851
8d94cc50
SS		 852 /* Check transfer length */
853 if (transfer->len > 8191)
854 {
855 dev_warn(&drv_data->pdev->dev, "pump_transfers: transfer "
856 "length greater than 8191\n");
857 message->status = -EINVAL;
858 giveback(drv_data);
859 return;
860 }
861
e0c9905e
SS		 862 /* Setup the transfer state based on the type of transfer */
863 if (flush(drv_data) == 0) {
864 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
865 message->status = -EIO;
5daa3ba0 866 giveback(drv_data);
e0c9905e
SS		 867 return;
868 }
9708c121
SS		 869 drv_data->n_bytes = chip->n_bytes;
870 drv_data->dma_width = chip->dma_width;
e0c9905e
SS		 871 drv_data->cs_control = chip->cs_control;
872 drv_data->tx = (void *)transfer->tx_buf;
873 drv_data->tx_end = drv_data->tx + transfer->len;
874 drv_data->rx = transfer->rx_buf;
875 drv_data->rx_end = drv_data->rx + transfer->len;
876 drv_data->rx_dma = transfer->rx_dma;
877 drv_data->tx_dma = transfer->tx_dma;
8d94cc50 878 drv_data->len = transfer->len & DCMD_LENGTH;
e0c9905e
SS		 879 drv_data->write = drv_data->tx ? chip->write : null_writer;
880 drv_data->read = drv_data->rx ? chip->read : null_reader;
881 drv_data->cs_change = transfer->cs_change;
9708c121
SS		 882
883 /* Change speed and bit per word on a per transfer */
8d94cc50 884 cr0 = chip->cr0;
9708c121
SS		 885 if (transfer->speed_hz || transfer->bits_per_word) {
886
9708c121
SS		 887 bits = chip->bits_per_word;
888 speed = chip->speed_hz;
889
890 if (transfer->speed_hz)
891 speed = transfer->speed_hz;
892
893 if (transfer->bits_per_word)
894 bits = transfer->bits_per_word;
895
2f1a74e5 896 clk_div = ssp_get_clk_div(ssp, speed);
9708c121
SS		 897
898 if (bits <= 8) {
899 drv_data->n_bytes = 1;
900 drv_data->dma_width = DCMD_WIDTH1;
901 drv_data->read = drv_data->read != null_reader ?
902 u8_reader : null_reader;
903 drv_data->write = drv_data->write != null_writer ?
904 u8_writer : null_writer;
905 } else if (bits <= 16) {
906 drv_data->n_bytes = 2;
907 drv_data->dma_width = DCMD_WIDTH2;
908 drv_data->read = drv_data->read != null_reader ?
909 u16_reader : null_reader;
910 drv_data->write = drv_data->write != null_writer ?
911 u16_writer : null_writer;
912 } else if (bits <= 32) {
913 drv_data->n_bytes = 4;
914 drv_data->dma_width = DCMD_WIDTH4;
915 drv_data->read = drv_data->read != null_reader ?
916 u32_reader : null_reader;
917 drv_data->write = drv_data->write != null_writer ?
918 u32_writer : null_writer;
919 }
8d94cc50
SS		 920 /* if bits/word is changed in dma mode, then must check the
921 * thresholds and burst also */
922 if (chip->enable_dma) {
923 if (set_dma_burst_and_threshold(chip, message->spi,
924 bits, &dma_burst,
925 &dma_thresh))
926 if (printk_ratelimit())
927 dev_warn(&message->spi->dev,
928 "pump_transfer: "
929 "DMA burst size reduced to "
930 "match bits_per_word\n");
931 }
9708c121
SS		 932
933 cr0 = clk_div
934 | SSCR0_Motorola
5daa3ba0 935 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
9708c121
SS		 936 | SSCR0_SSE
937 | (bits > 16 ? SSCR0_EDSS : 0);
9708c121
SS		 938 }
939
e0c9905e
SS		 940 message->state = RUNNING_STATE;
941
942 /* Try to map dma buffer and do a dma transfer if successful */
943 if ((drv_data->dma_mapped = map_dma_buffers(drv_data))) {
944
945 /* Ensure we have the correct interrupt handler */
946 drv_data->transfer_handler = dma_transfer;
947
948 /* Setup rx DMA Channel */
949 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
950 DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
951 DTADR(drv_data->rx_channel) = drv_data->rx_dma;
952 if (drv_data->rx == drv_data->null_dma_buf)
953 /* No target address increment */
954 DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
9708c121 955 | drv_data->dma_width
8d94cc50 956 | dma_burst
e0c9905e
SS		 957 | drv_data->len;
958 else
959 DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
960 | DCMD_FLOWSRC
9708c121 961 | drv_data->dma_width
8d94cc50 962 | dma_burst
e0c9905e
SS		 963 | drv_data->len;
964
965 /* Setup tx DMA Channel */
966 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
967 DSADR(drv_data->tx_channel) = drv_data->tx_dma;
968 DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
969 if (drv_data->tx == drv_data->null_dma_buf)
970 /* No source address increment */
971 DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
9708c121 972 | drv_data->dma_width
8d94cc50 973 | dma_burst
e0c9905e
SS		 974 | drv_data->len;
975 else
976 DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
977 | DCMD_FLOWTRG
9708c121 978 | drv_data->dma_width
8d94cc50 979 | dma_burst
e0c9905e
SS		 980 | drv_data->len;
981
982 /* Enable dma end irqs on SSP to detect end of transfer */
983 if (drv_data->ssp_type == PXA25x_SSP)
984 DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
985
8d94cc50
SS		 986 /* Clear status and start DMA engine */
987 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
e0c9905e
SS		 988 write_SSSR(drv_data->clear_sr, reg);
989 DCSR(drv_data->rx_channel) |= DCSR_RUN;
990 DCSR(drv_data->tx_channel) |= DCSR_RUN;
e0c9905e
SS		 991 } else {
992 /* Ensure we have the correct interrupt handler */
993 drv_data->transfer_handler = interrupt_transfer;
994
8d94cc50
SS		 995 /* Clear status */
996 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
e0c9905e 997 write_SSSR(drv_data->clear_sr, reg);
8d94cc50
SS		 998 }
999
1000 /* see if we need to reload the config registers */
1001 if ((read_SSCR0(reg) != cr0)
1002 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
1003 (cr1 & SSCR1_CHANGE_MASK)) {
1004
b97c74bd 1005 /* stop the SSP, and update the other bits */
8d94cc50 1006 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
e0c9905e
SS		 1007 if (drv_data->ssp_type != PXA25x_SSP)
1008 write_SSTO(chip->timeout, reg);
b97c74bd
NF		 1009 /* first set CR1 without interrupt and service enables */
1010 write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
1011 /* restart the SSP */
8d94cc50 1012 write_SSCR0(cr0, reg);
b97c74bd 1013
8d94cc50
SS		 1014 } else {
1015 if (drv_data->ssp_type != PXA25x_SSP)
1016 write_SSTO(chip->timeout, reg);
e0c9905e 1017 }
b97c74bd
NF		 1018
1019 /* FIXME, need to handle cs polarity,
1020 * this driver uses struct pxa2xx_spi_chip.cs_control to
1021 * specify a CS handling function, and it ignores most
1022 * struct spi_device.mode[s], including SPI_CS_HIGH */
1023 drv_data->cs_control(PXA2XX_CS_ASSERT);
1024
1025 /* after chip select, release the data by enabling service
1026 * requests and interrupts, without changing any mode bits */
1027 write_SSCR1(cr1, reg);
e0c9905e
SS		 1028}
1029
6d5aefb8 1030static void pump_messages(struct work_struct *work)
e0c9905e 1031{
6d5aefb8
DH		 1032 struct driver_data *drv_data =
1033 container_of(work, struct driver_data, pump_messages);
e0c9905e
SS		 1034 unsigned long flags;
1035
1036 /* Lock queue and check for queue work */
1037 spin_lock_irqsave(&drv_data->lock, flags);
1038 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
1039 drv_data->busy = 0;
1040 spin_unlock_irqrestore(&drv_data->lock, flags);
1041 return;
1042 }
1043
1044 /* Make sure we are not already running a message */
1045 if (drv_data->cur_msg) {
1046 spin_unlock_irqrestore(&drv_data->lock, flags);
1047 return;
1048 }
1049
1050 /* Extract head of queue */
1051 drv_data->cur_msg = list_entry(drv_data->queue.next,
1052 struct spi_message, queue);
1053 list_del_init(&drv_data->cur_msg->queue);
e0c9905e
SS		 1054
1055 /* Initial message state*/
1056 drv_data->cur_msg->state = START_STATE;
1057 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1058 struct spi_transfer,
1059 transfer_list);
1060
8d94cc50
SS		 1061 /* prepare to setup the SSP, in pump_transfers, using the per
1062 * chip configuration */
e0c9905e 1063 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
e0c9905e
SS		 1064
1065 /* Mark as busy and launch transfers */
1066 tasklet_schedule(&drv_data->pump_transfers);
5daa3ba0
SS		 1067
1068 drv_data->busy = 1;
1069 spin_unlock_irqrestore(&drv_data->lock, flags);
e0c9905e
SS		 1070}
1071
1072static int transfer(struct spi_device *spi, struct spi_message *msg)
1073{
1074 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1075 unsigned long flags;
1076
1077 spin_lock_irqsave(&drv_data->lock, flags);
1078
1079 if (drv_data->run == QUEUE_STOPPED) {
1080 spin_unlock_irqrestore(&drv_data->lock, flags);
1081 return -ESHUTDOWN;
1082 }
1083
1084 msg->actual_length = 0;
1085 msg->status = -EINPROGRESS;
1086 msg->state = START_STATE;
1087
1088 list_add_tail(&msg->queue, &drv_data->queue);
1089
1090 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1091 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1092
1093 spin_unlock_irqrestore(&drv_data->lock, flags);
1094
1095 return 0;
1096}
1097
dccd573b
DB		 1098/* the spi->mode bits understood by this driver: */
1099#define MODEBITS (SPI_CPOL | SPI_CPHA)
1100
e0c9905e
SS		 1101static int setup(struct spi_device *spi)
1102{
1103 struct pxa2xx_spi_chip *chip_info = NULL;
1104 struct chip_data *chip;
1105 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
2f1a74e5 1106 struct ssp_device *ssp = drv_data->ssp;
e0c9905e
SS		 1107 unsigned int clk_div;
1108
1109 if (!spi->bits_per_word)
1110 spi->bits_per_word = 8;
1111
1112 if (drv_data->ssp_type != PXA25x_SSP
8d94cc50
SS		 1113 && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
1114 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1115 "b/w not 4-32 for type non-PXA25x_SSP\n",
1116 drv_data->ssp_type, spi->bits_per_word);
e0c9905e 1117 return -EINVAL;
8d94cc50
SS		 1118 }
1119 else if (drv_data->ssp_type == PXA25x_SSP
1120 && (spi->bits_per_word < 4
1121 || spi->bits_per_word > 16)) {
1122 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1123 "b/w not 4-16 for type PXA25x_SSP\n",
1124 drv_data->ssp_type, spi->bits_per_word);
e0c9905e 1125 return -EINVAL;
8d94cc50 1126 }
e0c9905e 1127
dccd573b
DB		 1128 if (spi->mode & ~MODEBITS) {
1129 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
1130 spi->mode & ~MODEBITS);
1131 return -EINVAL;
1132 }
1133
8d94cc50 1134 /* Only alloc on first setup */
e0c9905e 1135 chip = spi_get_ctldata(spi);
8d94cc50 1136 if (!chip) {
e0c9905e 1137 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
8d94cc50
SS		 1138 if (!chip) {
1139 dev_err(&spi->dev,
1140 "failed setup: can't allocate chip data\n");
e0c9905e 1141 return -ENOMEM;
8d94cc50 1142 }
e0c9905e
SS		 1143
1144 chip->cs_control = null_cs_control;
1145 chip->enable_dma = 0;
8d94cc50 1146 chip->timeout = 1000;
e0c9905e
SS		 1147 chip->threshold = SSCR1_RxTresh(1) | SSCR1_TxTresh(1);
1148 chip->dma_burst_size = drv_data->master_info->enable_dma ?
1149 DCMD_BURST8 : 0;
e0c9905e
SS		 1150 }
1151
8d94cc50
SS		 1152 /* protocol drivers may change the chip settings, so...
1153 * if chip_info exists, use it */
1154 chip_info = spi->controller_data;
1155
e0c9905e 1156 /* chip_info isn't always needed */
8d94cc50 1157 chip->cr1 = 0;
e0c9905e
SS		 1158 if (chip_info) {
1159 if (chip_info->cs_control)
1160 chip->cs_control = chip_info->cs_control;
1161
8d94cc50 1162 chip->timeout = chip_info->timeout;
e0c9905e 1163
8d94cc50
SS		 1164 chip->threshold = (SSCR1_RxTresh(chip_info->rx_threshold) &
1165 SSCR1_RFT) |
1166 (SSCR1_TxTresh(chip_info->tx_threshold) &
1167 SSCR1_TFT);
e0c9905e
SS		 1168
1169 chip->enable_dma = chip_info->dma_burst_size != 0
1170 && drv_data->master_info->enable_dma;
1171 chip->dma_threshold = 0;
1172
e0c9905e
SS		 1173 if (chip_info->enable_loopback)
1174 chip->cr1 = SSCR1_LBM;
1175 }
1176
8d94cc50
SS		 1177 /* set dma burst and threshold outside of chip_info path so that if
1178 * chip_info goes away after setting chip->enable_dma, the
1179 * burst and threshold can still respond to changes in bits_per_word */
1180 if (chip->enable_dma) {
1181 /* set up legal burst and threshold for dma */
1182 if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word,
1183 &chip->dma_burst_size,
1184 &chip->dma_threshold)) {
1185 dev_warn(&spi->dev, "in setup: DMA burst size reduced "
1186 "to match bits_per_word\n");
1187 }
1188 }
1189
2f1a74e5 1190 clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz);
9708c121 1191 chip->speed_hz = spi->max_speed_hz;
e0c9905e
SS		 1192
1193 chip->cr0 = clk_div
1194 | SSCR0_Motorola
5daa3ba0
SS		 1195 | SSCR0_DataSize(spi->bits_per_word > 16 ?
1196 spi->bits_per_word - 16 : spi->bits_per_word)
e0c9905e
SS		 1197 | SSCR0_SSE
1198 | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
7f6ee1ad
JC		 1199 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1200 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1201 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
e0c9905e
SS		 1202
1203 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1204 if (drv_data->ssp_type != PXA25x_SSP)
2f1a74e5 1205 dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n",
e0c9905e 1206 spi->bits_per_word,
2f1a74e5 1207 clk_get_rate(ssp->clk)
e0c9905e
SS		 1208 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1209 spi->mode & 0x3);
1210 else
2f1a74e5 1211 dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n",
e0c9905e 1212 spi->bits_per_word,
2f1a74e5 1213 clk_get_rate(ssp->clk)
e0c9905e
SS		 1214 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1215 spi->mode & 0x3);
1216
1217 if (spi->bits_per_word <= 8) {
1218 chip->n_bytes = 1;
1219 chip->dma_width = DCMD_WIDTH1;
1220 chip->read = u8_reader;
1221 chip->write = u8_writer;
1222 } else if (spi->bits_per_word <= 16) {
1223 chip->n_bytes = 2;
1224 chip->dma_width = DCMD_WIDTH2;
1225 chip->read = u16_reader;
1226 chip->write = u16_writer;
1227 } else if (spi->bits_per_word <= 32) {
1228 chip->cr0 |= SSCR0_EDSS;
1229 chip->n_bytes = 4;
1230 chip->dma_width = DCMD_WIDTH4;
1231 chip->read = u32_reader;
1232 chip->write = u32_writer;
1233 } else {
1234 dev_err(&spi->dev, "invalid wordsize\n");
e0c9905e
SS		 1235 return -ENODEV;
1236 }
9708c121 1237 chip->bits_per_word = spi->bits_per_word;
e0c9905e
SS		 1238
1239 spi_set_ctldata(spi, chip);
1240
1241 return 0;
1242}
1243
0ffa0285 1244static void cleanup(struct spi_device *spi)
e0c9905e 1245{
0ffa0285 1246 struct chip_data *chip = spi_get_ctldata(spi);
e0c9905e
SS		 1247
1248 kfree(chip);
1249}
1250
d1e44d9c 1251static int __init init_queue(struct driver_data *drv_data)
e0c9905e
SS		 1252{
1253 INIT_LIST_HEAD(&drv_data->queue);
1254 spin_lock_init(&drv_data->lock);
1255
1256 drv_data->run = QUEUE_STOPPED;
1257 drv_data->busy = 0;
1258
1259 tasklet_init(&drv_data->pump_transfers,
1260 pump_transfers, (unsigned long)drv_data);
1261
6d5aefb8 1262 INIT_WORK(&drv_data->pump_messages, pump_messages);
e0c9905e 1263 drv_data->workqueue = create_singlethread_workqueue(
49dce689 1264 drv_data->master->dev.parent->bus_id);
e0c9905e
SS		 1265 if (drv_data->workqueue == NULL)
1266 return -EBUSY;
1267
1268 return 0;
1269}
1270
1271static int start_queue(struct driver_data *drv_data)
1272{
1273 unsigned long flags;
1274
1275 spin_lock_irqsave(&drv_data->lock, flags);
1276
1277 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1278 spin_unlock_irqrestore(&drv_data->lock, flags);
1279 return -EBUSY;
1280 }
1281
1282 drv_data->run = QUEUE_RUNNING;
1283 drv_data->cur_msg = NULL;
1284 drv_data->cur_transfer = NULL;
1285 drv_data->cur_chip = NULL;
1286 spin_unlock_irqrestore(&drv_data->lock, flags);
1287
1288 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1289
1290 return 0;
1291}
1292
1293static int stop_queue(struct driver_data *drv_data)
1294{
1295 unsigned long flags;
1296 unsigned limit = 500;
1297 int status = 0;
1298
1299 spin_lock_irqsave(&drv_data->lock, flags);
1300
1301 /* This is a bit lame, but is optimized for the common execution path.
1302 * A wait_queue on the drv_data->busy could be used, but then the common
1303 * execution path (pump_messages) would be required to call wake_up or
1304 * friends on every SPI message. Do this instead */
1305 drv_data->run = QUEUE_STOPPED;
1306 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1307 spin_unlock_irqrestore(&drv_data->lock, flags);
1308 msleep(10);
1309 spin_lock_irqsave(&drv_data->lock, flags);
1310 }
1311
1312 if (!list_empty(&drv_data->queue) || drv_data->busy)
1313 status = -EBUSY;
1314
1315 spin_unlock_irqrestore(&drv_data->lock, flags);
1316
1317 return status;
1318}
1319
1320static int destroy_queue(struct driver_data *drv_data)
1321{
1322 int status;
1323
1324 status = stop_queue(drv_data);
8d94cc50
SS		 1325 /* we are unloading the module or failing to load (only two calls
1326 * to this routine), and neither call can handle a return value.
1327 * However, destroy_workqueue calls flush_workqueue, and that will
1328 * block until all work is done. If the reason that stop_queue
1329 * timed out is that the work will never finish, then it does no
1330 * good to call destroy_workqueue, so return anyway. */
e0c9905e
SS		 1331 if (status != 0)
1332 return status;
1333
1334 destroy_workqueue(drv_data->workqueue);
1335
1336 return 0;
1337}
1338
d1e44d9c 1339static int __init pxa2xx_spi_probe(struct platform_device *pdev)
e0c9905e
SS		 1340{
1341 struct device *dev = &pdev->dev;
1342 struct pxa2xx_spi_master *platform_info;
1343 struct spi_master *master;
cf43369d 1344 struct driver_data *drv_data = NULL;
2f1a74e5 1345 struct ssp_device *ssp;
e0c9905e
SS		 1346 int status = 0;
1347
1348 platform_info = dev->platform_data;
1349
2f1a74e5 1350 ssp = ssp_request(pdev->id, pdev->name);
1351 if (ssp == NULL) {
1352 dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id);
e0c9905e
SS		 1353 return -ENODEV;
1354 }
1355
1356 /* Allocate master with space for drv_data and null dma buffer */
1357 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1358 if (!master) {
1359 dev_err(&pdev->dev, "can not alloc spi_master\n");
2f1a74e5 1360 ssp_free(ssp);
e0c9905e
SS		 1361 return -ENOMEM;
1362 }
1363 drv_data = spi_master_get_devdata(master);
1364 drv_data->master = master;
1365 drv_data->master_info = platform_info;
1366 drv_data->pdev = pdev;
2f1a74e5 1367 drv_data->ssp = ssp;
e0c9905e
SS		 1368
1369 master->bus_num = pdev->id;
1370 master->num_chipselect = platform_info->num_chipselect;
1371 master->cleanup = cleanup;
1372 master->setup = setup;
1373 master->transfer = transfer;
1374
2f1a74e5 1375 drv_data->ssp_type = ssp->type;
e0c9905e
SS		 1376 drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
1377 sizeof(struct driver_data)), 8);
1378
2f1a74e5 1379 drv_data->ioaddr = ssp->mmio_base;
1380 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1381 if (ssp->type == PXA25x_SSP) {
e0c9905e
SS		 1382 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1383 drv_data->dma_cr1 = 0;
1384 drv_data->clear_sr = SSSR_ROR;
1385 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1386 } else {
1387 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1388 drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
1389 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1390 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1391 }
1392
2f1a74e5 1393 status = request_irq(ssp->irq, ssp_int, 0, dev->bus_id, drv_data);
e0c9905e
SS		 1394 if (status < 0) {
1395 dev_err(&pdev->dev, "can not get IRQ\n");
1396 goto out_error_master_alloc;
1397 }
1398
1399 /* Setup DMA if requested */
1400 drv_data->tx_channel = -1;
1401 drv_data->rx_channel = -1;
1402 if (platform_info->enable_dma) {
1403
1404 /* Get two DMA channels (rx and tx) */
1405 drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
1406 DMA_PRIO_HIGH,
1407 dma_handler,
1408 drv_data);
1409 if (drv_data->rx_channel < 0) {
1410 dev_err(dev, "problem (%d) requesting rx channel\n",
1411 drv_data->rx_channel);
1412 status = -ENODEV;
1413 goto out_error_irq_alloc;
1414 }
1415 drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
1416 DMA_PRIO_MEDIUM,
1417 dma_handler,
1418 drv_data);
1419 if (drv_data->tx_channel < 0) {
1420 dev_err(dev, "problem (%d) requesting tx channel\n",
1421 drv_data->tx_channel);
1422 status = -ENODEV;
1423 goto out_error_dma_alloc;
1424 }
1425
2f1a74e5 1426 DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel;
1427 DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel;
e0c9905e
SS		 1428 }
1429
1430 /* Enable SOC clock */
2f1a74e5 1431 clk_enable(ssp->clk);
e0c9905e
SS		 1432
1433 /* Load default SSP configuration */
1434 write_SSCR0(0, drv_data->ioaddr);
1435 write_SSCR1(SSCR1_RxTresh(4) | SSCR1_TxTresh(12), drv_data->ioaddr);
1436 write_SSCR0(SSCR0_SerClkDiv(2)
1437 | SSCR0_Motorola
1438 | SSCR0_DataSize(8),
1439 drv_data->ioaddr);
1440 if (drv_data->ssp_type != PXA25x_SSP)
1441 write_SSTO(0, drv_data->ioaddr);
1442 write_SSPSP(0, drv_data->ioaddr);
1443
1444 /* Initial and start queue */
1445 status = init_queue(drv_data);
1446 if (status != 0) {
1447 dev_err(&pdev->dev, "problem initializing queue\n");
1448 goto out_error_clock_enabled;
1449 }
1450 status = start_queue(drv_data);
1451 if (status != 0) {
1452 dev_err(&pdev->dev, "problem starting queue\n");
1453 goto out_error_clock_enabled;
1454 }
1455
1456 /* Register with the SPI framework */
1457 platform_set_drvdata(pdev, drv_data);
1458 status = spi_register_master(master);
1459 if (status != 0) {
1460 dev_err(&pdev->dev, "problem registering spi master\n");
1461 goto out_error_queue_alloc;
1462 }
1463
1464 return status;
1465
1466out_error_queue_alloc:
1467 destroy_queue(drv_data);
1468
1469out_error_clock_enabled:
2f1a74e5 1470 clk_disable(ssp->clk);
e0c9905e
SS		 1471
1472out_error_dma_alloc:
1473 if (drv_data->tx_channel != -1)
1474 pxa_free_dma(drv_data->tx_channel);
1475 if (drv_data->rx_channel != -1)
1476 pxa_free_dma(drv_data->rx_channel);
1477
1478out_error_irq_alloc:
2f1a74e5 1479 free_irq(ssp->irq, drv_data);
e0c9905e
SS		 1480
1481out_error_master_alloc:
1482 spi_master_put(master);
2f1a74e5 1483 ssp_free(ssp);
e0c9905e
SS		 1484 return status;
1485}
1486
1487static int pxa2xx_spi_remove(struct platform_device *pdev)
1488{
1489 struct driver_data *drv_data = platform_get_drvdata(pdev);
2f1a74e5 1490 struct ssp_device *ssp = drv_data->ssp;
e0c9905e
SS		 1491 int status = 0;
1492
1493 if (!drv_data)
1494 return 0;
1495
1496 /* Remove the queue */
1497 status = destroy_queue(drv_data);
1498 if (status != 0)
8d94cc50
SS		 1499 /* the kernel does not check the return status of this
1500 * this routine (mod->exit, within the kernel). Therefore
1501 * nothing is gained by returning from here, the module is
1502 * going away regardless, and we should not leave any more
1503 * resources allocated than necessary. We cannot free the
1504 * message memory in drv_data->queue, but we can release the
1505 * resources below. I think the kernel should honor -EBUSY
1506 * returns but... */
1507 dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not "
1508 "complete, message memory not freed\n");
e0c9905e
SS		 1509
1510 /* Disable the SSP at the peripheral and SOC level */
1511 write_SSCR0(0, drv_data->ioaddr);
2f1a74e5 1512 clk_disable(ssp->clk);
e0c9905e
SS		 1513
1514 /* Release DMA */
1515 if (drv_data->master_info->enable_dma) {
2f1a74e5 1516 DRCMR(ssp->drcmr_rx) = 0;
1517 DRCMR(ssp->drcmr_tx) = 0;
e0c9905e
SS		 1518 pxa_free_dma(drv_data->tx_channel);
1519 pxa_free_dma(drv_data->rx_channel);
1520 }
1521
1522 /* Release IRQ */
2f1a74e5 1523 free_irq(ssp->irq, drv_data);
1524
1525 /* Release SSP */
1526 ssp_free(ssp);
e0c9905e
SS		 1527
1528 /* Disconnect from the SPI framework */
1529 spi_unregister_master(drv_data->master);
1530
1531 /* Prevent double remove */
1532 platform_set_drvdata(pdev, NULL);
1533
1534 return 0;
1535}
1536
1537static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1538{
1539 int status = 0;
1540
1541 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1542 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1543}
1544
1545#ifdef CONFIG_PM
e0c9905e
SS		 1546
1547static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1548{
1549 struct driver_data *drv_data = platform_get_drvdata(pdev);
2f1a74e5 1550 struct ssp_device *ssp = drv_data->ssp;
e0c9905e
SS		 1551 int status = 0;
1552
e0c9905e
SS		 1553 status = stop_queue(drv_data);
1554 if (status != 0)
1555 return status;
1556 write_SSCR0(0, drv_data->ioaddr);
2f1a74e5 1557 clk_disable(ssp->clk);
e0c9905e
SS		 1558
1559 return 0;
1560}
1561
1562static int pxa2xx_spi_resume(struct platform_device *pdev)
1563{
1564 struct driver_data *drv_data = platform_get_drvdata(pdev);
2f1a74e5 1565 struct ssp_device *ssp = drv_data->ssp;
e0c9905e
SS		 1566 int status = 0;
1567
1568 /* Enable the SSP clock */
0cf942d7 1569 clk_enable(ssp->clk);
e0c9905e
SS		 1570
1571 /* Start the queue running */
1572 status = start_queue(drv_data);
1573 if (status != 0) {
1574 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1575 return status;
1576 }
1577
1578 return 0;
1579}
1580#else
1581#define pxa2xx_spi_suspend NULL
1582#define pxa2xx_spi_resume NULL
1583#endif /* CONFIG_PM */
1584
1585static struct platform_driver driver = {
1586 .driver = {
1587 .name = "pxa2xx-spi",
e0c9905e
SS		 1588 .owner = THIS_MODULE,
1589 },
d1e44d9c 1590 .remove = pxa2xx_spi_remove,
e0c9905e
SS		 1591 .shutdown = pxa2xx_spi_shutdown,
1592 .suspend = pxa2xx_spi_suspend,
1593 .resume = pxa2xx_spi_resume,
1594};
1595
1596static int __init pxa2xx_spi_init(void)
1597{
d1e44d9c 1598 return platform_driver_probe(&driver, pxa2xx_spi_probe);
e0c9905e
SS		 1599}
1600module_init(pxa2xx_spi_init);
1601
1602static void __exit pxa2xx_spi_exit(void)
1603{
1604 platform_driver_unregister(&driver);
1605}
1606module_exit(pxa2xx_spi_exit);
kernel source for telekom puls (alcatel/mediatek)