[SCSI] libiscsi: add debug printks for iscsi command completion path
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / mvsas / mv_sas.c
CommitLineData
b5762948 1/*
20b09c29
AY
2 * Marvell 88SE64xx/88SE94xx main function
3 *
4 * Copyright 2007 Red Hat, Inc.
5 * Copyright 2008 Marvell. <kewei@marvell.com>
6 *
7 * This file is licensed under GPLv2.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; version 2 of the
12 * License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * USA
23*/
b5762948 24
dd4969a8 25#include "mv_sas.h"
b5762948 26
dd4969a8
JG
27static int mvs_find_tag(struct mvs_info *mvi, struct sas_task *task, u32 *tag)
28{
29 if (task->lldd_task) {
30 struct mvs_slot_info *slot;
31 slot = (struct mvs_slot_info *) task->lldd_task;
20b09c29 32 *tag = slot->slot_tag;
dd4969a8
JG
33 return 1;
34 }
35 return 0;
36}
8f261aaf 37
20b09c29 38void mvs_tag_clear(struct mvs_info *mvi, u32 tag)
dd4969a8
JG
39{
40 void *bitmap = (void *) &mvi->tags;
41 clear_bit(tag, bitmap);
42}
8f261aaf 43
20b09c29 44void mvs_tag_free(struct mvs_info *mvi, u32 tag)
dd4969a8
JG
45{
46 mvs_tag_clear(mvi, tag);
47}
8f261aaf 48
20b09c29 49void mvs_tag_set(struct mvs_info *mvi, unsigned int tag)
dd4969a8
JG
50{
51 void *bitmap = (void *) &mvi->tags;
52 set_bit(tag, bitmap);
53}
8f261aaf 54
20b09c29 55inline int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out)
dd4969a8
JG
56{
57 unsigned int index, tag;
58 void *bitmap = (void *) &mvi->tags;
b5762948 59
20b09c29 60 index = find_first_zero_bit(bitmap, mvi->tags_num);
dd4969a8 61 tag = index;
20b09c29 62 if (tag >= mvi->tags_num)
dd4969a8
JG
63 return -SAS_QUEUE_FULL;
64 mvs_tag_set(mvi, tag);
65 *tag_out = tag;
66 return 0;
67}
b5762948 68
dd4969a8
JG
69void mvs_tag_init(struct mvs_info *mvi)
70{
71 int i;
20b09c29 72 for (i = 0; i < mvi->tags_num; ++i)
dd4969a8
JG
73 mvs_tag_clear(mvi, i);
74}
b5762948 75
20b09c29 76void mvs_hexdump(u32 size, u8 *data, u32 baseaddr)
8f261aaf
KW
77{
78 u32 i;
79 u32 run;
80 u32 offset;
81
82 offset = 0;
83 while (size) {
20b09c29 84 printk(KERN_DEBUG"%08X : ", baseaddr + offset);
8f261aaf
KW
85 if (size >= 16)
86 run = 16;
87 else
88 run = size;
89 size -= run;
90 for (i = 0; i < 16; i++) {
91 if (i < run)
20b09c29 92 printk(KERN_DEBUG"%02X ", (u32)data[i]);
8f261aaf 93 else
20b09c29 94 printk(KERN_DEBUG" ");
8f261aaf 95 }
20b09c29 96 printk(KERN_DEBUG": ");
8f261aaf 97 for (i = 0; i < run; i++)
20b09c29
AY
98 printk(KERN_DEBUG"%c",
99 isalnum(data[i]) ? data[i] : '.');
100 printk(KERN_DEBUG"\n");
8f261aaf
KW
101 data = &data[16];
102 offset += run;
103 }
20b09c29 104 printk(KERN_DEBUG"\n");
8f261aaf
KW
105}
106
20b09c29 107#if (_MV_DUMP > 1)
8f261aaf
KW
108static void mvs_hba_sb_dump(struct mvs_info *mvi, u32 tag,
109 enum sas_protocol proto)
110{
8f261aaf 111 u32 offset;
8f261aaf
KW
112 struct mvs_slot_info *slot = &mvi->slot_info[tag];
113
114 offset = slot->cmd_size + MVS_OAF_SZ +
20b09c29
AY
115 MVS_CHIP_DISP->prd_size() * slot->n_elem;
116 dev_printk(KERN_DEBUG, mvi->dev, "+---->Status buffer[%d] :\n",
8f261aaf
KW
117 tag);
118 mvs_hexdump(32, (u8 *) slot->response,
119 (u32) slot->buf_dma + offset);
8f261aaf 120}
ee1f1c2e 121#endif
8f261aaf
KW
122
123static void mvs_hba_memory_dump(struct mvs_info *mvi, u32 tag,
124 enum sas_protocol proto)
125{
20b09c29 126#if (_MV_DUMP > 1)
ee1f1c2e 127 u32 sz, w_ptr;
8f261aaf 128 u64 addr;
8f261aaf
KW
129 struct mvs_slot_info *slot = &mvi->slot_info[tag];
130
131 /*Delivery Queue */
20b09c29 132 sz = MVS_CHIP_SLOT_SZ;
ee1f1c2e 133 w_ptr = slot->tx;
20b09c29
AY
134 addr = mvi->tx_dma;
135 dev_printk(KERN_DEBUG, mvi->dev,
ee1f1c2e 136 "Delivery Queue Size=%04d , WRT_PTR=%04X\n", sz, w_ptr);
20b09c29 137 dev_printk(KERN_DEBUG, mvi->dev,
8f261aaf
KW
138 "Delivery Queue Base Address=0x%llX (PA)"
139 "(tx_dma=0x%llX), Entry=%04d\n",
20b09c29 140 addr, (unsigned long long)mvi->tx_dma, w_ptr);
8f261aaf
KW
141 mvs_hexdump(sizeof(u32), (u8 *)(&mvi->tx[mvi->tx_prod]),
142 (u32) mvi->tx_dma + sizeof(u32) * w_ptr);
143 /*Command List */
ee1f1c2e 144 addr = mvi->slot_dma;
20b09c29 145 dev_printk(KERN_DEBUG, mvi->dev,
8f261aaf
KW
146 "Command List Base Address=0x%llX (PA)"
147 "(slot_dma=0x%llX), Header=%03d\n",
20b09c29
AY
148 addr, (unsigned long long)slot->buf_dma, tag);
149 dev_printk(KERN_DEBUG, mvi->dev, "Command Header[%03d]:\n", tag);
8f261aaf
KW
150 /*mvs_cmd_hdr */
151 mvs_hexdump(sizeof(struct mvs_cmd_hdr), (u8 *)(&mvi->slot[tag]),
152 (u32) mvi->slot_dma + tag * sizeof(struct mvs_cmd_hdr));
153 /*1.command table area */
20b09c29 154 dev_printk(KERN_DEBUG, mvi->dev, "+---->Command Table :\n");
8f261aaf
KW
155 mvs_hexdump(slot->cmd_size, (u8 *) slot->buf, (u32) slot->buf_dma);
156 /*2.open address frame area */
20b09c29 157 dev_printk(KERN_DEBUG, mvi->dev, "+---->Open Address Frame :\n");
8f261aaf
KW
158 mvs_hexdump(MVS_OAF_SZ, (u8 *) slot->buf + slot->cmd_size,
159 (u32) slot->buf_dma + slot->cmd_size);
160 /*3.status buffer */
161 mvs_hba_sb_dump(mvi, tag, proto);
162 /*4.PRD table */
20b09c29
AY
163 dev_printk(KERN_DEBUG, mvi->dev, "+---->PRD table :\n");
164 mvs_hexdump(MVS_CHIP_DISP->prd_size() * slot->n_elem,
8f261aaf
KW
165 (u8 *) slot->buf + slot->cmd_size + MVS_OAF_SZ,
166 (u32) slot->buf_dma + slot->cmd_size + MVS_OAF_SZ);
167#endif
168}
169
170static void mvs_hba_cq_dump(struct mvs_info *mvi)
171{
ee1f1c2e 172#if (_MV_DUMP > 2)
8f261aaf
KW
173 u64 addr;
174 void __iomem *regs = mvi->regs;
8f261aaf
KW
175 u32 entry = mvi->rx_cons + 1;
176 u32 rx_desc = le32_to_cpu(mvi->rx[entry]);
177
178 /*Completion Queue */
179 addr = mr32(RX_HI) << 16 << 16 | mr32(RX_LO);
20b09c29 180 dev_printk(KERN_DEBUG, mvi->dev, "Completion Task = 0x%p\n",
ee1f1c2e 181 mvi->slot_info[rx_desc & RXQ_SLOT_MASK].task);
20b09c29 182 dev_printk(KERN_DEBUG, mvi->dev,
8f261aaf
KW
183 "Completion List Base Address=0x%llX (PA), "
184 "CQ_Entry=%04d, CQ_WP=0x%08X\n",
185 addr, entry - 1, mvi->rx[0]);
186 mvs_hexdump(sizeof(u32), (u8 *)(&rx_desc),
187 mvi->rx_dma + sizeof(u32) * entry);
188#endif
189}
190
20b09c29 191void mvs_get_sas_addr(void *buf, u32 buflen)
8f261aaf 192{
20b09c29
AY
193 /*memcpy(buf, "\x50\x05\x04\x30\x11\xab\x64\x40", 8);*/
194}
8f261aaf 195
20b09c29
AY
196struct mvs_info *mvs_find_dev_mvi(struct domain_device *dev)
197{
198 unsigned long i = 0, j = 0, hi = 0;
199 struct sas_ha_struct *sha = dev->port->ha;
200 struct mvs_info *mvi = NULL;
201 struct asd_sas_phy *phy;
202
203 while (sha->sas_port[i]) {
204 if (sha->sas_port[i] == dev->port) {
205 phy = container_of(sha->sas_port[i]->phy_list.next,
206 struct asd_sas_phy, port_phy_el);
207 j = 0;
208 while (sha->sas_phy[j]) {
209 if (sha->sas_phy[j] == phy)
210 break;
211 j++;
212 }
213 break;
214 }
215 i++;
216 }
217 hi = j/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
218 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
8f261aaf 219
20b09c29 220 return mvi;
8f261aaf 221
20b09c29 222}
8f261aaf 223
20b09c29
AY
224/* FIXME */
225int mvs_find_dev_phyno(struct domain_device *dev, int *phyno)
226{
227 unsigned long i = 0, j = 0, n = 0, num = 0;
9870d9a2
AY
228 struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
229 struct mvs_info *mvi = mvi_dev->mvi_info;
20b09c29
AY
230 struct sas_ha_struct *sha = dev->port->ha;
231
232 while (sha->sas_port[i]) {
233 if (sha->sas_port[i] == dev->port) {
234 struct asd_sas_phy *phy;
235 list_for_each_entry(phy,
236 &sha->sas_port[i]->phy_list, port_phy_el) {
237 j = 0;
238 while (sha->sas_phy[j]) {
239 if (sha->sas_phy[j] == phy)
240 break;
241 j++;
242 }
243 phyno[n] = (j >= mvi->chip->n_phy) ?
244 (j - mvi->chip->n_phy) : j;
245 num++;
246 n++;
dd4969a8 247 }
dd4969a8
JG
248 break;
249 }
20b09c29
AY
250 i++;
251 }
252 return num;
253}
254
255static inline void mvs_free_reg_set(struct mvs_info *mvi,
256 struct mvs_device *dev)
257{
258 if (!dev) {
259 mv_printk("device has been free.\n");
260 return;
261 }
262 if (dev->runing_req != 0)
263 return;
264 if (dev->taskfileset == MVS_ID_NOT_MAPPED)
265 return;
266 MVS_CHIP_DISP->free_reg_set(mvi, &dev->taskfileset);
267}
268
269static inline u8 mvs_assign_reg_set(struct mvs_info *mvi,
270 struct mvs_device *dev)
271{
272 if (dev->taskfileset != MVS_ID_NOT_MAPPED)
273 return 0;
274 return MVS_CHIP_DISP->assign_reg_set(mvi, &dev->taskfileset);
275}
276
277void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard)
278{
279 u32 no;
280 for_each_phy(phy_mask, phy_mask, no) {
281 if (!(phy_mask & 1))
282 continue;
283 MVS_CHIP_DISP->phy_reset(mvi, no, hard);
284 }
285}
286
287/* FIXME: locking? */
288int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
289 void *funcdata)
290{
291 int rc = 0, phy_id = sas_phy->id;
292 u32 tmp, i = 0, hi;
293 struct sas_ha_struct *sha = sas_phy->ha;
294 struct mvs_info *mvi = NULL;
295
296 while (sha->sas_phy[i]) {
297 if (sha->sas_phy[i] == sas_phy)
298 break;
299 i++;
300 }
301 hi = i/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
302 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
303
304 switch (func) {
305 case PHY_FUNC_SET_LINK_RATE:
306 MVS_CHIP_DISP->phy_set_link_rate(mvi, phy_id, funcdata);
307 break;
8f261aaf 308
dd4969a8 309 case PHY_FUNC_HARD_RESET:
20b09c29 310 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_id);
dd4969a8
JG
311 if (tmp & PHY_RST_HARD)
312 break;
20b09c29 313 MVS_CHIP_DISP->phy_reset(mvi, phy_id, 1);
dd4969a8 314 break;
b5762948 315
dd4969a8 316 case PHY_FUNC_LINK_RESET:
20b09c29
AY
317 MVS_CHIP_DISP->phy_enable(mvi, phy_id);
318 MVS_CHIP_DISP->phy_reset(mvi, phy_id, 0);
dd4969a8 319 break;
b5762948 320
dd4969a8 321 case PHY_FUNC_DISABLE:
20b09c29
AY
322 MVS_CHIP_DISP->phy_disable(mvi, phy_id);
323 break;
dd4969a8
JG
324 case PHY_FUNC_RELEASE_SPINUP_HOLD:
325 default:
326 rc = -EOPNOTSUPP;
b5762948 327 }
20b09c29 328 msleep(200);
b5762948
JG
329 return rc;
330}
331
20b09c29
AY
332void __devinit mvs_set_sas_addr(struct mvs_info *mvi, int port_id,
333 u32 off_lo, u32 off_hi, u64 sas_addr)
334{
335 u32 lo = (u32)sas_addr;
336 u32 hi = (u32)(sas_addr>>32);
337
338 MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_lo);
339 MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, lo);
340 MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_hi);
341 MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, hi);
342}
343
dd4969a8 344static void mvs_bytes_dmaed(struct mvs_info *mvi, int i)
ee1f1c2e 345{
dd4969a8 346 struct mvs_phy *phy = &mvi->phy[i];
20b09c29
AY
347 struct asd_sas_phy *sas_phy = &phy->sas_phy;
348 struct sas_ha_struct *sas_ha;
dd4969a8
JG
349 if (!phy->phy_attached)
350 return;
351
20b09c29
AY
352 if (!(phy->att_dev_info & PORT_DEV_TRGT_MASK)
353 && phy->phy_type & PORT_TYPE_SAS) {
354 return;
355 }
356
357 sas_ha = mvi->sas;
358 sas_ha->notify_phy_event(sas_phy, PHYE_OOB_DONE);
359
dd4969a8
JG
360 if (sas_phy->phy) {
361 struct sas_phy *sphy = sas_phy->phy;
362
363 sphy->negotiated_linkrate = sas_phy->linkrate;
364 sphy->minimum_linkrate = phy->minimum_linkrate;
365 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
366 sphy->maximum_linkrate = phy->maximum_linkrate;
20b09c29 367 sphy->maximum_linkrate_hw = MVS_CHIP_DISP->phy_max_link_rate();
ee1f1c2e 368 }
ee1f1c2e 369
dd4969a8
JG
370 if (phy->phy_type & PORT_TYPE_SAS) {
371 struct sas_identify_frame *id;
b5762948 372
dd4969a8
JG
373 id = (struct sas_identify_frame *)phy->frame_rcvd;
374 id->dev_type = phy->identify.device_type;
375 id->initiator_bits = SAS_PROTOCOL_ALL;
376 id->target_bits = phy->identify.target_port_protocols;
377 } else if (phy->phy_type & PORT_TYPE_SATA) {
20b09c29 378 /*Nothing*/
dd4969a8 379 }
20b09c29
AY
380 mv_dprintk("phy %d byte dmaded.\n", i + mvi->id * mvi->chip->n_phy);
381
382 sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
383
384 mvi->sas->notify_port_event(sas_phy,
dd4969a8 385 PORTE_BYTES_DMAED);
ee1f1c2e
KW
386}
387
20b09c29
AY
388int mvs_slave_alloc(struct scsi_device *scsi_dev)
389{
390 struct domain_device *dev = sdev_to_domain_dev(scsi_dev);
391 if (dev_is_sata(dev)) {
392 /* We don't need to rescan targets
393 * if REPORT_LUNS request is failed
394 */
395 if (scsi_dev->lun > 0)
396 return -ENXIO;
397 scsi_dev->tagged_supported = 1;
398 }
399
400 return sas_slave_alloc(scsi_dev);
401}
402
dd4969a8 403int mvs_slave_configure(struct scsi_device *sdev)
ee1f1c2e 404{
dd4969a8
JG
405 struct domain_device *dev = sdev_to_domain_dev(sdev);
406 int ret = sas_slave_configure(sdev);
b5762948 407
dd4969a8
JG
408 if (ret)
409 return ret;
dd4969a8 410 if (dev_is_sata(dev)) {
20b09c29
AY
411 /* may set PIO mode */
412 #if MV_DISABLE_NCQ
413 struct ata_port *ap = dev->sata_dev.ap;
414 struct ata_device *adev = ap->link.device;
415 adev->flags |= ATA_DFLAG_NCQ_OFF;
dd4969a8 416 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, 1);
20b09c29 417 #endif
dd4969a8 418 }
ee1f1c2e 419 return 0;
b5762948
JG
420}
421
dd4969a8 422void mvs_scan_start(struct Scsi_Host *shost)
b5762948 423{
20b09c29
AY
424 int i, j;
425 unsigned short core_nr;
426 struct mvs_info *mvi;
427 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
428
429 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
dd4969a8 430
20b09c29
AY
431 for (j = 0; j < core_nr; j++) {
432 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
433 for (i = 0; i < mvi->chip->n_phy; ++i)
434 mvs_bytes_dmaed(mvi, i);
dd4969a8 435 }
b5762948
JG
436}
437
dd4969a8 438int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time)
b5762948 439{
dd4969a8
JG
440 /* give the phy enabling interrupt event time to come in (1s
441 * is empirically about all it takes) */
442 if (time < HZ)
443 return 0;
444 /* Wait for discovery to finish */
445 scsi_flush_work(shost);
446 return 1;
b5762948
JG
447}
448
dd4969a8
JG
449static int mvs_task_prep_smp(struct mvs_info *mvi,
450 struct mvs_task_exec_info *tei)
b5762948 451{
dd4969a8
JG
452 int elem, rc, i;
453 struct sas_task *task = tei->task;
454 struct mvs_cmd_hdr *hdr = tei->hdr;
20b09c29
AY
455 struct domain_device *dev = task->dev;
456 struct asd_sas_port *sas_port = dev->port;
dd4969a8
JG
457 struct scatterlist *sg_req, *sg_resp;
458 u32 req_len, resp_len, tag = tei->tag;
459 void *buf_tmp;
460 u8 *buf_oaf;
461 dma_addr_t buf_tmp_dma;
20b09c29 462 void *buf_prd;
dd4969a8 463 struct mvs_slot_info *slot = &mvi->slot_info[tag];
dd4969a8
JG
464 u32 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
465#if _MV_DUMP
466 u8 *buf_cmd;
467 void *from;
468#endif
469 /*
470 * DMA-map SMP request, response buffers
471 */
472 sg_req = &task->smp_task.smp_req;
20b09c29 473 elem = dma_map_sg(mvi->dev, sg_req, 1, PCI_DMA_TODEVICE);
dd4969a8
JG
474 if (!elem)
475 return -ENOMEM;
476 req_len = sg_dma_len(sg_req);
b5762948 477
dd4969a8 478 sg_resp = &task->smp_task.smp_resp;
20b09c29 479 elem = dma_map_sg(mvi->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
dd4969a8
JG
480 if (!elem) {
481 rc = -ENOMEM;
482 goto err_out;
483 }
20b09c29 484 resp_len = SB_RFB_MAX;
b5762948 485
dd4969a8
JG
486 /* must be in dwords */
487 if ((req_len & 0x3) || (resp_len & 0x3)) {
488 rc = -EINVAL;
489 goto err_out_2;
b5762948
JG
490 }
491
dd4969a8
JG
492 /*
493 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
494 */
b5762948 495
20b09c29 496 /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ***** */
dd4969a8
JG
497 buf_tmp = slot->buf;
498 buf_tmp_dma = slot->buf_dma;
b5762948 499
dd4969a8
JG
500#if _MV_DUMP
501 buf_cmd = buf_tmp;
502 hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
503 buf_tmp += req_len;
504 buf_tmp_dma += req_len;
505 slot->cmd_size = req_len;
506#else
507 hdr->cmd_tbl = cpu_to_le64(sg_dma_address(sg_req));
508#endif
b5762948 509
dd4969a8
JG
510 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
511 buf_oaf = buf_tmp;
512 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
b5762948 513
dd4969a8
JG
514 buf_tmp += MVS_OAF_SZ;
515 buf_tmp_dma += MVS_OAF_SZ;
b5762948 516
20b09c29 517 /* region 3: PRD table *********************************** */
dd4969a8
JG
518 buf_prd = buf_tmp;
519 if (tei->n_elem)
520 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
521 else
522 hdr->prd_tbl = 0;
b5762948 523
20b09c29 524 i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
dd4969a8
JG
525 buf_tmp += i;
526 buf_tmp_dma += i;
b5762948 527
dd4969a8
JG
528 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
529 slot->response = buf_tmp;
530 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
20b09c29
AY
531 if (mvi->flags & MVF_FLAG_SOC)
532 hdr->reserved[0] = 0;
b5762948 533
dd4969a8
JG
534 /*
535 * Fill in TX ring and command slot header
536 */
537 slot->tx = mvi->tx_prod;
538 mvi->tx[mvi->tx_prod] = cpu_to_le32((TXQ_CMD_SMP << TXQ_CMD_SHIFT) |
539 TXQ_MODE_I | tag |
540 (sas_port->phy_mask << TXQ_PHY_SHIFT));
b5762948 541
dd4969a8
JG
542 hdr->flags |= flags;
543 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | ((req_len - 4) / 4));
544 hdr->tags = cpu_to_le32(tag);
545 hdr->data_len = 0;
b5762948 546
dd4969a8 547 /* generate open address frame hdr (first 12 bytes) */
20b09c29
AY
548 /* initiator, SMP, ftype 1h */
549 buf_oaf[0] = (1 << 7) | (PROTOCOL_SMP << 4) | 0x01;
550 buf_oaf[1] = dev->linkrate & 0xf;
dd4969a8 551 *(u16 *)(buf_oaf + 2) = 0xFFFF; /* SAS SPEC */
20b09c29 552 memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
dd4969a8
JG
553
554 /* fill in PRD (scatter/gather) table, if any */
20b09c29 555 MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
b5762948 556
dd4969a8
JG
557#if _MV_DUMP
558 /* copy cmd table */
559 from = kmap_atomic(sg_page(sg_req), KM_IRQ0);
560 memcpy(buf_cmd, from + sg_req->offset, req_len);
561 kunmap_atomic(from, KM_IRQ0);
562#endif
b5762948
JG
563 return 0;
564
dd4969a8 565err_out_2:
20b09c29 566 dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_resp, 1,
dd4969a8 567 PCI_DMA_FROMDEVICE);
b5762948 568err_out:
20b09c29 569 dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_req, 1,
dd4969a8 570 PCI_DMA_TODEVICE);
8f261aaf 571 return rc;
8f261aaf
KW
572}
573
dd4969a8 574static u32 mvs_get_ncq_tag(struct sas_task *task, u32 *tag)
8f261aaf 575{
dd4969a8 576 struct ata_queued_cmd *qc = task->uldd_task;
8f261aaf 577
dd4969a8
JG
578 if (qc) {
579 if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
580 qc->tf.command == ATA_CMD_FPDMA_READ) {
581 *tag = qc->tag;
582 return 1;
583 }
8f261aaf 584 }
8f261aaf 585
dd4969a8 586 return 0;
8f261aaf
KW
587}
588
dd4969a8
JG
589static int mvs_task_prep_ata(struct mvs_info *mvi,
590 struct mvs_task_exec_info *tei)
b5762948
JG
591{
592 struct sas_task *task = tei->task;
593 struct domain_device *dev = task->dev;
20b09c29
AY
594 struct mvs_device *mvi_dev =
595 (struct mvs_device *)dev->lldd_dev;
b5762948
JG
596 struct mvs_cmd_hdr *hdr = tei->hdr;
597 struct asd_sas_port *sas_port = dev->port;
8f261aaf 598 struct mvs_slot_info *slot;
20b09c29
AY
599 void *buf_prd;
600 u32 tag = tei->tag, hdr_tag;
601 u32 flags, del_q;
b5762948
JG
602 void *buf_tmp;
603 u8 *buf_cmd, *buf_oaf;
604 dma_addr_t buf_tmp_dma;
8f261aaf
KW
605 u32 i, req_len, resp_len;
606 const u32 max_resp_len = SB_RFB_MAX;
607
20b09c29
AY
608 if (mvs_assign_reg_set(mvi, mvi_dev) == MVS_ID_NOT_MAPPED) {
609 mv_dprintk("Have not enough regiset for dev %d.\n",
610 mvi_dev->device_id);
8f261aaf 611 return -EBUSY;
20b09c29 612 }
8f261aaf
KW
613 slot = &mvi->slot_info[tag];
614 slot->tx = mvi->tx_prod;
20b09c29
AY
615 del_q = TXQ_MODE_I | tag |
616 (TXQ_CMD_STP << TXQ_CMD_SHIFT) |
617 (sas_port->phy_mask << TXQ_PHY_SHIFT) |
618 (mvi_dev->taskfileset << TXQ_SRS_SHIFT);
619 mvi->tx[mvi->tx_prod] = cpu_to_le32(del_q);
620
621#ifndef DISABLE_HOTPLUG_DMA_FIX
622 if (task->data_dir == DMA_FROM_DEVICE)
623 flags = (MVS_CHIP_DISP->prd_count() << MCH_PRD_LEN_SHIFT);
624 else
625 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
626#else
627 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
628#endif
b5762948
JG
629 if (task->ata_task.use_ncq)
630 flags |= MCH_FPDMA;
8f261aaf
KW
631 if (dev->sata_dev.command_set == ATAPI_COMMAND_SET) {
632 if (task->ata_task.fis.command != ATA_CMD_ID_ATAPI)
633 flags |= MCH_ATAPI;
634 }
635
b5762948
JG
636 /* FIXME: fill in port multiplier number */
637
638 hdr->flags = cpu_to_le32(flags);
8f261aaf
KW
639
640 /* FIXME: the low order order 5 bits for the TAG if enable NCQ */
20b09c29
AY
641 if (task->ata_task.use_ncq && mvs_get_ncq_tag(task, &hdr_tag))
642 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4e52fc0a 643 else
20b09c29
AY
644 hdr_tag = tag;
645
646 hdr->tags = cpu_to_le32(hdr_tag);
647
b5762948
JG
648 hdr->data_len = cpu_to_le32(task->total_xfer_len);
649
650 /*
651 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
652 */
b5762948 653
8f261aaf
KW
654 /* region 1: command table area (MVS_ATA_CMD_SZ bytes) ************** */
655 buf_cmd = buf_tmp = slot->buf;
b5762948
JG
656 buf_tmp_dma = slot->buf_dma;
657
658 hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
659
660 buf_tmp += MVS_ATA_CMD_SZ;
661 buf_tmp_dma += MVS_ATA_CMD_SZ;
8f261aaf
KW
662#if _MV_DUMP
663 slot->cmd_size = MVS_ATA_CMD_SZ;
664#endif
b5762948 665
8f261aaf 666 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
b5762948
JG
667 /* used for STP. unused for SATA? */
668 buf_oaf = buf_tmp;
669 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
670
671 buf_tmp += MVS_OAF_SZ;
672 buf_tmp_dma += MVS_OAF_SZ;
673
8f261aaf 674 /* region 3: PRD table ********************************************* */
b5762948 675 buf_prd = buf_tmp;
20b09c29 676
8f261aaf
KW
677 if (tei->n_elem)
678 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
679 else
680 hdr->prd_tbl = 0;
20b09c29 681 i = MVS_CHIP_DISP->prd_size() * MVS_CHIP_DISP->prd_count();
b5762948 682
b5762948
JG
683 buf_tmp += i;
684 buf_tmp_dma += i;
685
8f261aaf 686 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
b5762948
JG
687 /* FIXME: probably unused, for SATA. kept here just in case
688 * we get a STP/SATA error information record
689 */
690 slot->response = buf_tmp;
691 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
20b09c29
AY
692 if (mvi->flags & MVF_FLAG_SOC)
693 hdr->reserved[0] = 0;
b5762948 694
8f261aaf 695 req_len = sizeof(struct host_to_dev_fis);
b5762948 696 resp_len = MVS_SLOT_BUF_SZ - MVS_ATA_CMD_SZ -
8f261aaf 697 sizeof(struct mvs_err_info) - i;
b5762948
JG
698
699 /* request, response lengths */
8f261aaf 700 resp_len = min(resp_len, max_resp_len);
b5762948
JG
701 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
702
20b09c29
AY
703 if (likely(!task->ata_task.device_control_reg_update))
704 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
b5762948 705 /* fill in command FIS and ATAPI CDB */
8f261aaf
KW
706 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
707 if (dev->sata_dev.command_set == ATAPI_COMMAND_SET)
708 memcpy(buf_cmd + STP_ATAPI_CMD,
709 task->ata_task.atapi_packet, 16);
710
711 /* generate open address frame hdr (first 12 bytes) */
20b09c29
AY
712 /* initiator, STP, ftype 1h */
713 buf_oaf[0] = (1 << 7) | (PROTOCOL_STP << 4) | 0x1;
714 buf_oaf[1] = dev->linkrate & 0xf;
715 *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
716 memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
b5762948
JG
717
718 /* fill in PRD (scatter/gather) table, if any */
20b09c29
AY
719 MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
720#ifndef DISABLE_HOTPLUG_DMA_FIX
721 if (task->data_dir == DMA_FROM_DEVICE)
722 MVS_CHIP_DISP->dma_fix(mvi->bulk_buffer_dma,
723 TRASH_BUCKET_SIZE, tei->n_elem, buf_prd);
724#endif
b5762948
JG
725 return 0;
726}
727
728static int mvs_task_prep_ssp(struct mvs_info *mvi,
20b09c29
AY
729 struct mvs_task_exec_info *tei, int is_tmf,
730 struct mvs_tmf_task *tmf)
b5762948
JG
731{
732 struct sas_task *task = tei->task;
b5762948 733 struct mvs_cmd_hdr *hdr = tei->hdr;
8f261aaf 734 struct mvs_port *port = tei->port;
20b09c29
AY
735 struct domain_device *dev = task->dev;
736 struct mvs_device *mvi_dev =
737 (struct mvs_device *)dev->lldd_dev;
738 struct asd_sas_port *sas_port = dev->port;
b5762948 739 struct mvs_slot_info *slot;
20b09c29 740 void *buf_prd;
b5762948
JG
741 struct ssp_frame_hdr *ssp_hdr;
742 void *buf_tmp;
743 u8 *buf_cmd, *buf_oaf, fburst = 0;
744 dma_addr_t buf_tmp_dma;
745 u32 flags;
8f261aaf
KW
746 u32 resp_len, req_len, i, tag = tei->tag;
747 const u32 max_resp_len = SB_RFB_MAX;
20b09c29 748 u32 phy_mask;
b5762948
JG
749
750 slot = &mvi->slot_info[tag];
751
20b09c29
AY
752 phy_mask = ((port->wide_port_phymap) ? port->wide_port_phymap :
753 sas_port->phy_mask) & TXQ_PHY_MASK;
754
8f261aaf
KW
755 slot->tx = mvi->tx_prod;
756 mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
757 (TXQ_CMD_SSP << TXQ_CMD_SHIFT) |
4e52fc0a 758 (phy_mask << TXQ_PHY_SHIFT));
b5762948
JG
759
760 flags = MCH_RETRY;
761 if (task->ssp_task.enable_first_burst) {
762 flags |= MCH_FBURST;
763 fburst = (1 << 7);
764 }
2b288133
AY
765 if (is_tmf)
766 flags |= (MCH_SSP_FR_TASK << MCH_SSP_FR_TYPE_SHIFT);
767 else
768 flags |= (MCH_SSP_FR_CMD << MCH_SSP_FR_TYPE_SHIFT);
769 hdr->flags = cpu_to_le32(flags | (tei->n_elem << MCH_PRD_LEN_SHIFT));
b5762948
JG
770 hdr->tags = cpu_to_le32(tag);
771 hdr->data_len = cpu_to_le32(task->total_xfer_len);
772
773 /*
774 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
775 */
b5762948 776
8f261aaf
KW
777 /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ************** */
778 buf_cmd = buf_tmp = slot->buf;
b5762948
JG
779 buf_tmp_dma = slot->buf_dma;
780
781 hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
782
783 buf_tmp += MVS_SSP_CMD_SZ;
784 buf_tmp_dma += MVS_SSP_CMD_SZ;
8f261aaf
KW
785#if _MV_DUMP
786 slot->cmd_size = MVS_SSP_CMD_SZ;
787#endif
b5762948 788
8f261aaf 789 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
b5762948
JG
790 buf_oaf = buf_tmp;
791 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
792
793 buf_tmp += MVS_OAF_SZ;
794 buf_tmp_dma += MVS_OAF_SZ;
795
8f261aaf 796 /* region 3: PRD table ********************************************* */
b5762948 797 buf_prd = buf_tmp;
8f261aaf
KW
798 if (tei->n_elem)
799 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
800 else
801 hdr->prd_tbl = 0;
b5762948 802
20b09c29 803 i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
b5762948
JG
804 buf_tmp += i;
805 buf_tmp_dma += i;
806
8f261aaf 807 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
b5762948
JG
808 slot->response = buf_tmp;
809 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
20b09c29
AY
810 if (mvi->flags & MVF_FLAG_SOC)
811 hdr->reserved[0] = 0;
b5762948 812
b5762948 813 resp_len = MVS_SLOT_BUF_SZ - MVS_SSP_CMD_SZ - MVS_OAF_SZ -
8f261aaf
KW
814 sizeof(struct mvs_err_info) - i;
815 resp_len = min(resp_len, max_resp_len);
816
817 req_len = sizeof(struct ssp_frame_hdr) + 28;
b5762948
JG
818
819 /* request, response lengths */
820 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
821
822 /* generate open address frame hdr (first 12 bytes) */
20b09c29
AY
823 /* initiator, SSP, ftype 1h */
824 buf_oaf[0] = (1 << 7) | (PROTOCOL_SSP << 4) | 0x1;
825 buf_oaf[1] = dev->linkrate & 0xf;
826 *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
827 memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
b5762948 828
8f261aaf
KW
829 /* fill in SSP frame header (Command Table.SSP frame header) */
830 ssp_hdr = (struct ssp_frame_hdr *)buf_cmd;
20b09c29
AY
831
832 if (is_tmf)
833 ssp_hdr->frame_type = SSP_TASK;
834 else
835 ssp_hdr->frame_type = SSP_COMMAND;
836
837 memcpy(ssp_hdr->hashed_dest_addr, dev->hashed_sas_addr,
b5762948
JG
838 HASHED_SAS_ADDR_SIZE);
839 memcpy(ssp_hdr->hashed_src_addr,
20b09c29 840 dev->hashed_sas_addr, HASHED_SAS_ADDR_SIZE);
b5762948
JG
841 ssp_hdr->tag = cpu_to_be16(tag);
842
20b09c29 843 /* fill in IU for TASK and Command Frame */
b5762948
JG
844 buf_cmd += sizeof(*ssp_hdr);
845 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
b5762948 846
20b09c29
AY
847 if (ssp_hdr->frame_type != SSP_TASK) {
848 buf_cmd[9] = fburst | task->ssp_task.task_attr |
849 (task->ssp_task.task_prio << 3);
850 memcpy(buf_cmd + 12, &task->ssp_task.cdb, 16);
851 } else{
852 buf_cmd[10] = tmf->tmf;
853 switch (tmf->tmf) {
854 case TMF_ABORT_TASK:
855 case TMF_QUERY_TASK:
856 buf_cmd[12] =
857 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
858 buf_cmd[13] =
859 tmf->tag_of_task_to_be_managed & 0xff;
860 break;
861 default:
862 break;
863 }
b5762948 864 }
20b09c29
AY
865 /* fill in PRD (scatter/gather) table, if any */
866 MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
b5762948
JG
867 return 0;
868}
869
20b09c29
AY
870#define DEV_IS_GONE(mvi_dev) ((!mvi_dev || (mvi_dev->dev_type == NO_DEVICE)))
871static int mvs_task_exec(struct sas_task *task, const int num, gfp_t gfp_flags,
0b84b709
AY
872 struct completion *completion,int is_tmf,
873 struct mvs_tmf_task *tmf)
b5762948 874{
8f261aaf 875 struct domain_device *dev = task->dev;
9870d9a2
AY
876 struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
877 struct mvs_info *mvi = mvi_dev->mvi_info;
b5762948 878 struct mvs_task_exec_info tei;
8f261aaf 879 struct sas_task *t = task;
4e52fc0a 880 struct mvs_slot_info *slot;
8f261aaf 881 u32 tag = 0xdeadbeef, rc, n_elem = 0;
8f261aaf 882 u32 n = num, pass = 0;
20b09c29 883 unsigned long flags = 0;
b5762948 884
20b09c29
AY
885 if (!dev->port) {
886 struct task_status_struct *tsm = &t->task_status;
887
888 tsm->resp = SAS_TASK_UNDELIVERED;
889 tsm->stat = SAS_PHY_DOWN;
890 t->task_done(t);
891 return 0;
892 }
893
0b84b709 894 spin_lock_irqsave(&mvi->lock, flags);
8f261aaf 895 do {
4e52fc0a 896 dev = t->dev;
20b09c29
AY
897 mvi_dev = (struct mvs_device *)dev->lldd_dev;
898 if (DEV_IS_GONE(mvi_dev)) {
899 if (mvi_dev)
900 mv_dprintk("device %d not ready.\n",
901 mvi_dev->device_id);
902 else
903 mv_dprintk("device %016llx not ready.\n",
904 SAS_ADDR(dev->sas_addr));
905
906 rc = SAS_PHY_DOWN;
907 goto out_done;
908 }
909
910 if (dev->port->id >= mvi->chip->n_phy)
911 tei.port = &mvi->port[dev->port->id - mvi->chip->n_phy];
912 else
913 tei.port = &mvi->port[dev->port->id];
b5762948 914
dd4969a8
JG
915 if (!tei.port->port_attached) {
916 if (sas_protocol_ata(t->task_proto)) {
20b09c29
AY
917 mv_dprintk("port %d does not"
918 "attached device.\n", dev->port->id);
dd4969a8
JG
919 rc = SAS_PHY_DOWN;
920 goto out_done;
921 } else {
922 struct task_status_struct *ts = &t->task_status;
923 ts->resp = SAS_TASK_UNDELIVERED;
924 ts->stat = SAS_PHY_DOWN;
925 t->task_done(t);
926 if (n > 1)
927 t = list_entry(t->list.next,
928 struct sas_task, list);
929 continue;
930 }
931 }
932
933 if (!sas_protocol_ata(t->task_proto)) {
934 if (t->num_scatter) {
20b09c29
AY
935 n_elem = dma_map_sg(mvi->dev,
936 t->scatter,
dd4969a8
JG
937 t->num_scatter,
938 t->data_dir);
939 if (!n_elem) {
940 rc = -ENOMEM;
941 goto err_out;
942 }
943 }
944 } else {
945 n_elem = t->num_scatter;
946 }
947
948 rc = mvs_tag_alloc(mvi, &tag);
949 if (rc)
950 goto err_out;
951
952 slot = &mvi->slot_info[tag];
20b09c29
AY
953
954
dd4969a8
JG
955 t->lldd_task = NULL;
956 slot->n_elem = n_elem;
20b09c29 957 slot->slot_tag = tag;
dd4969a8 958 memset(slot->buf, 0, MVS_SLOT_BUF_SZ);
20b09c29 959
dd4969a8
JG
960 tei.task = t;
961 tei.hdr = &mvi->slot[tag];
962 tei.tag = tag;
963 tei.n_elem = n_elem;
dd4969a8
JG
964 switch (t->task_proto) {
965 case SAS_PROTOCOL_SMP:
966 rc = mvs_task_prep_smp(mvi, &tei);
967 break;
968 case SAS_PROTOCOL_SSP:
20b09c29 969 rc = mvs_task_prep_ssp(mvi, &tei, is_tmf, tmf);
dd4969a8
JG
970 break;
971 case SAS_PROTOCOL_SATA:
972 case SAS_PROTOCOL_STP:
973 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
974 rc = mvs_task_prep_ata(mvi, &tei);
975 break;
976 default:
20b09c29 977 dev_printk(KERN_ERR, mvi->dev,
dd4969a8
JG
978 "unknown sas_task proto: 0x%x\n",
979 t->task_proto);
980 rc = -EINVAL;
981 break;
982 }
983
20b09c29
AY
984 if (rc) {
985 mv_dprintk("rc is %x\n", rc);
dd4969a8 986 goto err_out_tag;
20b09c29 987 }
dd4969a8
JG
988 slot->task = t;
989 slot->port = tei.port;
990 t->lldd_task = (void *) slot;
20b09c29 991 list_add_tail(&slot->entry, &tei.port->list);
dd4969a8 992 /* TODO: select normal or high priority */
dd4969a8
JG
993 spin_lock(&t->task_state_lock);
994 t->task_state_flags |= SAS_TASK_AT_INITIATOR;
995 spin_unlock(&t->task_state_lock);
996
997 mvs_hba_memory_dump(mvi, tag, t->task_proto);
20b09c29 998 mvi_dev->runing_req++;
dd4969a8
JG
999 ++pass;
1000 mvi->tx_prod = (mvi->tx_prod + 1) & (MVS_CHIP_SLOT_SZ - 1);
1001 if (n > 1)
1002 t = list_entry(t->list.next, struct sas_task, list);
1003 } while (--n);
dd4969a8
JG
1004 rc = 0;
1005 goto out_done;
1006
1007err_out_tag:
1008 mvs_tag_free(mvi, tag);
1009err_out:
20b09c29
AY
1010
1011 dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
dd4969a8
JG
1012 if (!sas_protocol_ata(t->task_proto))
1013 if (n_elem)
20b09c29 1014 dma_unmap_sg(mvi->dev, t->scatter, n_elem,
dd4969a8
JG
1015 t->data_dir);
1016out_done:
20b09c29
AY
1017 if (likely(pass)) {
1018 MVS_CHIP_DISP->start_delivery(mvi,
1019 (mvi->tx_prod - 1) & (MVS_CHIP_SLOT_SZ - 1));
1020 }
0b84b709 1021 spin_unlock_irqrestore(&mvi->lock, flags);
dd4969a8
JG
1022 return rc;
1023}
1024
20b09c29
AY
1025int mvs_queue_command(struct sas_task *task, const int num,
1026 gfp_t gfp_flags)
1027{
0b84b709 1028 return mvs_task_exec(task, num, gfp_flags, NULL, 0, NULL);
20b09c29
AY
1029}
1030
dd4969a8
JG
1031static void mvs_slot_free(struct mvs_info *mvi, u32 rx_desc)
1032{
1033 u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
1034 mvs_tag_clear(mvi, slot_idx);
1035}
1036
1037static void mvs_slot_task_free(struct mvs_info *mvi, struct sas_task *task,
1038 struct mvs_slot_info *slot, u32 slot_idx)
1039{
20b09c29
AY
1040 if (!slot->task)
1041 return;
dd4969a8
JG
1042 if (!sas_protocol_ata(task->task_proto))
1043 if (slot->n_elem)
20b09c29 1044 dma_unmap_sg(mvi->dev, task->scatter,
dd4969a8
JG
1045 slot->n_elem, task->data_dir);
1046
1047 switch (task->task_proto) {
1048 case SAS_PROTOCOL_SMP:
20b09c29 1049 dma_unmap_sg(mvi->dev, &task->smp_task.smp_resp, 1,
dd4969a8 1050 PCI_DMA_FROMDEVICE);
20b09c29 1051 dma_unmap_sg(mvi->dev, &task->smp_task.smp_req, 1,
dd4969a8
JG
1052 PCI_DMA_TODEVICE);
1053 break;
1054
1055 case SAS_PROTOCOL_SATA:
1056 case SAS_PROTOCOL_STP:
1057 case SAS_PROTOCOL_SSP:
1058 default:
1059 /* do nothing */
1060 break;
1061 }
20b09c29 1062 list_del_init(&slot->entry);
dd4969a8
JG
1063 task->lldd_task = NULL;
1064 slot->task = NULL;
1065 slot->port = NULL;
20b09c29
AY
1066 slot->slot_tag = 0xFFFFFFFF;
1067 mvs_slot_free(mvi, slot_idx);
dd4969a8
JG
1068}
1069
1070static void mvs_update_wideport(struct mvs_info *mvi, int i)
1071{
1072 struct mvs_phy *phy = &mvi->phy[i];
1073 struct mvs_port *port = phy->port;
1074 int j, no;
1075
20b09c29
AY
1076 for_each_phy(port->wide_port_phymap, j, no) {
1077 if (j & 1) {
1078 MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
1079 PHYR_WIDE_PORT);
1080 MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
dd4969a8
JG
1081 port->wide_port_phymap);
1082 } else {
20b09c29
AY
1083 MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
1084 PHYR_WIDE_PORT);
1085 MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
1086 0);
dd4969a8 1087 }
20b09c29 1088 }
dd4969a8
JG
1089}
1090
1091static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i)
1092{
1093 u32 tmp;
1094 struct mvs_phy *phy = &mvi->phy[i];
20b09c29 1095 struct mvs_port *port = phy->port;
dd4969a8 1096
20b09c29 1097 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, i);
dd4969a8
JG
1098 if ((tmp & PHY_READY_MASK) && !(phy->irq_status & PHYEV_POOF)) {
1099 if (!port)
1100 phy->phy_attached = 1;
1101 return tmp;
1102 }
1103
1104 if (port) {
1105 if (phy->phy_type & PORT_TYPE_SAS) {
1106 port->wide_port_phymap &= ~(1U << i);
1107 if (!port->wide_port_phymap)
1108 port->port_attached = 0;
1109 mvs_update_wideport(mvi, i);
1110 } else if (phy->phy_type & PORT_TYPE_SATA)
1111 port->port_attached = 0;
dd4969a8
JG
1112 phy->port = NULL;
1113 phy->phy_attached = 0;
1114 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1115 }
1116 return 0;
1117}
1118
1119static void *mvs_get_d2h_reg(struct mvs_info *mvi, int i, void *buf)
1120{
1121 u32 *s = (u32 *) buf;
1122
1123 if (!s)
1124 return NULL;
1125
20b09c29
AY
1126 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3);
1127 s[3] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
dd4969a8 1128
20b09c29
AY
1129 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2);
1130 s[2] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
dd4969a8 1131
20b09c29
AY
1132 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1);
1133 s[1] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
dd4969a8 1134
20b09c29
AY
1135 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
1136 s[0] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
1137
1138 /* Workaround: take some ATAPI devices for ATA */
1139 if (((s[1] & 0x00FFFFFF) == 0x00EB1401) && (*(u8 *)&s[3] == 0x01))
1140 s[1] = 0x00EB1401 | (*((u8 *)&s[1] + 3) & 0x10);
dd4969a8
JG
1141
1142 return (void *)s;
1143}
1144
1145static u32 mvs_is_sig_fis_received(u32 irq_status)
1146{
1147 return irq_status & PHYEV_SIG_FIS;
1148}
1149
20b09c29 1150void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st)
dd4969a8
JG
1151{
1152 struct mvs_phy *phy = &mvi->phy[i];
20b09c29 1153 struct sas_identify_frame *id;
b5762948 1154
20b09c29 1155 id = (struct sas_identify_frame *)phy->frame_rcvd;
b5762948 1156
dd4969a8 1157 if (get_st) {
20b09c29 1158 phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, i);
dd4969a8
JG
1159 phy->phy_status = mvs_is_phy_ready(mvi, i);
1160 }
8f261aaf 1161
dd4969a8 1162 if (phy->phy_status) {
20b09c29
AY
1163 int oob_done = 0;
1164 struct asd_sas_phy *sas_phy = &mvi->phy[i].sas_phy;
b5762948 1165
20b09c29
AY
1166 oob_done = MVS_CHIP_DISP->oob_done(mvi, i);
1167
1168 MVS_CHIP_DISP->fix_phy_info(mvi, i, id);
1169 if (phy->phy_type & PORT_TYPE_SATA) {
1170 phy->identify.target_port_protocols = SAS_PROTOCOL_STP;
1171 if (mvs_is_sig_fis_received(phy->irq_status)) {
1172 phy->phy_attached = 1;
1173 phy->att_dev_sas_addr =
1174 i + mvi->id * mvi->chip->n_phy;
1175 if (oob_done)
1176 sas_phy->oob_mode = SATA_OOB_MODE;
1177 phy->frame_rcvd_size =
1178 sizeof(struct dev_to_host_fis);
1179 mvs_get_d2h_reg(mvi, i, (void *)id);
1180 } else {
1181 u32 tmp;
1182 dev_printk(KERN_DEBUG, mvi->dev,
1183 "Phy%d : No sig fis\n", i);
1184 tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, i);
1185 MVS_CHIP_DISP->write_port_irq_mask(mvi, i,
1186 tmp | PHYEV_SIG_FIS);
1187 phy->phy_attached = 0;
1188 phy->phy_type &= ~PORT_TYPE_SATA;
1189 MVS_CHIP_DISP->phy_reset(mvi, i, 0);
1190 goto out_done;
1191 }
1192 } else if (phy->phy_type & PORT_TYPE_SAS
1193 || phy->att_dev_info & PORT_SSP_INIT_MASK) {
1194 phy->phy_attached = 1;
dd4969a8 1195 phy->identify.device_type =
20b09c29 1196 phy->att_dev_info & PORT_DEV_TYPE_MASK;
b5762948 1197
dd4969a8
JG
1198 if (phy->identify.device_type == SAS_END_DEV)
1199 phy->identify.target_port_protocols =
1200 SAS_PROTOCOL_SSP;
1201 else if (phy->identify.device_type != NO_DEVICE)
1202 phy->identify.target_port_protocols =
1203 SAS_PROTOCOL_SMP;
20b09c29 1204 if (oob_done)
dd4969a8
JG
1205 sas_phy->oob_mode = SAS_OOB_MODE;
1206 phy->frame_rcvd_size =
1207 sizeof(struct sas_identify_frame);
dd4969a8 1208 }
20b09c29
AY
1209 memcpy(sas_phy->attached_sas_addr,
1210 &phy->att_dev_sas_addr, SAS_ADDR_SIZE);
b5762948 1211
20b09c29
AY
1212 if (MVS_CHIP_DISP->phy_work_around)
1213 MVS_CHIP_DISP->phy_work_around(mvi, i);
dd4969a8 1214 }
20b09c29
AY
1215 mv_dprintk("port %d attach dev info is %x\n",
1216 i + mvi->id * mvi->chip->n_phy, phy->att_dev_info);
1217 mv_dprintk("port %d attach sas addr is %llx\n",
1218 i + mvi->id * mvi->chip->n_phy, phy->att_dev_sas_addr);
4e52fc0a 1219out_done:
dd4969a8 1220 if (get_st)
20b09c29 1221 MVS_CHIP_DISP->write_port_irq_stat(mvi, i, phy->irq_status);
b5762948
JG
1222}
1223
20b09c29 1224static void mvs_port_notify_formed(struct asd_sas_phy *sas_phy, int lock)
8f261aaf 1225{
dd4969a8 1226 struct sas_ha_struct *sas_ha = sas_phy->ha;
20b09c29 1227 struct mvs_info *mvi = NULL; int i = 0, hi;
dd4969a8 1228 struct mvs_phy *phy = sas_phy->lldd_phy;
20b09c29
AY
1229 struct asd_sas_port *sas_port = sas_phy->port;
1230 struct mvs_port *port;
1231 unsigned long flags = 0;
1232 if (!sas_port)
1233 return;
8f261aaf 1234
20b09c29
AY
1235 while (sas_ha->sas_phy[i]) {
1236 if (sas_ha->sas_phy[i] == sas_phy)
1237 break;
1238 i++;
1239 }
1240 hi = i/((struct mvs_prv_info *)sas_ha->lldd_ha)->n_phy;
1241 mvi = ((struct mvs_prv_info *)sas_ha->lldd_ha)->mvi[hi];
1242 if (sas_port->id >= mvi->chip->n_phy)
1243 port = &mvi->port[sas_port->id - mvi->chip->n_phy];
1244 else
1245 port = &mvi->port[sas_port->id];
1246 if (lock)
1247 spin_lock_irqsave(&mvi->lock, flags);
dd4969a8
JG
1248 port->port_attached = 1;
1249 phy->port = port;
dd4969a8
JG
1250 if (phy->phy_type & PORT_TYPE_SAS) {
1251 port->wide_port_phymap = sas_port->phy_mask;
20b09c29 1252 mv_printk("set wide port phy map %x\n", sas_port->phy_mask);
dd4969a8 1253 mvs_update_wideport(mvi, sas_phy->id);
8f261aaf 1254 }
20b09c29
AY
1255 if (lock)
1256 spin_unlock_irqrestore(&mvi->lock, flags);
dd4969a8
JG
1257}
1258
20b09c29 1259static void mvs_port_notify_deformed(struct asd_sas_phy *sas_phy, int lock)
dd4969a8 1260{
20b09c29 1261 /*Nothing*/
dd4969a8
JG
1262}
1263
dd4969a8 1264
20b09c29
AY
1265void mvs_port_formed(struct asd_sas_phy *sas_phy)
1266{
1267 mvs_port_notify_formed(sas_phy, 1);
dd4969a8
JG
1268}
1269
20b09c29 1270void mvs_port_deformed(struct asd_sas_phy *sas_phy)
dd4969a8 1271{
20b09c29
AY
1272 mvs_port_notify_deformed(sas_phy, 1);
1273}
8f261aaf 1274
20b09c29
AY
1275struct mvs_device *mvs_alloc_dev(struct mvs_info *mvi)
1276{
1277 u32 dev;
1278 for (dev = 0; dev < MVS_MAX_DEVICES; dev++) {
1279 if (mvi->devices[dev].dev_type == NO_DEVICE) {
1280 mvi->devices[dev].device_id = dev;
1281 return &mvi->devices[dev];
1282 }
8f261aaf 1283 }
8121ed42 1284
20b09c29
AY
1285 if (dev == MVS_MAX_DEVICES)
1286 mv_printk("max support %d devices, ignore ..\n",
1287 MVS_MAX_DEVICES);
1288
1289 return NULL;
8f261aaf
KW
1290}
1291
20b09c29 1292void mvs_free_dev(struct mvs_device *mvi_dev)
b5762948 1293{
20b09c29
AY
1294 u32 id = mvi_dev->device_id;
1295 memset(mvi_dev, 0, sizeof(*mvi_dev));
1296 mvi_dev->device_id = id;
1297 mvi_dev->dev_type = NO_DEVICE;
1298 mvi_dev->dev_status = MVS_DEV_NORMAL;
1299 mvi_dev->taskfileset = MVS_ID_NOT_MAPPED;
1300}
b5762948 1301
20b09c29
AY
1302int mvs_dev_found_notify(struct domain_device *dev, int lock)
1303{
1304 unsigned long flags = 0;
1305 int res = 0;
1306 struct mvs_info *mvi = NULL;
1307 struct domain_device *parent_dev = dev->parent;
1308 struct mvs_device *mvi_device;
b5762948 1309
20b09c29 1310 mvi = mvs_find_dev_mvi(dev);
b5762948 1311
20b09c29
AY
1312 if (lock)
1313 spin_lock_irqsave(&mvi->lock, flags);
1314
1315 mvi_device = mvs_alloc_dev(mvi);
1316 if (!mvi_device) {
1317 res = -1;
1318 goto found_out;
b5762948 1319 }
20b09c29
AY
1320 dev->lldd_dev = (void *)mvi_device;
1321 mvi_device->dev_type = dev->dev_type;
9870d9a2 1322 mvi_device->mvi_info = mvi;
20b09c29
AY
1323 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) {
1324 int phy_id;
1325 u8 phy_num = parent_dev->ex_dev.num_phys;
1326 struct ex_phy *phy;
1327 for (phy_id = 0; phy_id < phy_num; phy_id++) {
1328 phy = &parent_dev->ex_dev.ex_phy[phy_id];
1329 if (SAS_ADDR(phy->attached_sas_addr) ==
1330 SAS_ADDR(dev->sas_addr)) {
1331 mvi_device->attached_phy = phy_id;
1332 break;
1333 }
1334 }
b5762948 1335
20b09c29
AY
1336 if (phy_id == phy_num) {
1337 mv_printk("Error: no attached dev:%016llx"
1338 "at ex:%016llx.\n",
1339 SAS_ADDR(dev->sas_addr),
1340 SAS_ADDR(parent_dev->sas_addr));
1341 res = -1;
1342 }
dd4969a8 1343 }
b5762948 1344
20b09c29
AY
1345found_out:
1346 if (lock)
1347 spin_unlock_irqrestore(&mvi->lock, flags);
1348 return res;
1349}
b5762948 1350
20b09c29
AY
1351int mvs_dev_found(struct domain_device *dev)
1352{
1353 return mvs_dev_found_notify(dev, 1);
1354}
b5762948 1355
20b09c29
AY
1356void mvs_dev_gone_notify(struct domain_device *dev, int lock)
1357{
1358 unsigned long flags = 0;
20b09c29 1359 struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
9870d9a2 1360 struct mvs_info *mvi = mvi_dev->mvi_info;
b5762948 1361
20b09c29
AY
1362 if (lock)
1363 spin_lock_irqsave(&mvi->lock, flags);
b5762948 1364
20b09c29
AY
1365 if (mvi_dev) {
1366 mv_dprintk("found dev[%d:%x] is gone.\n",
1367 mvi_dev->device_id, mvi_dev->dev_type);
1368 mvs_free_reg_set(mvi, mvi_dev);
1369 mvs_free_dev(mvi_dev);
1370 } else {
1371 mv_dprintk("found dev has gone.\n");
b5762948 1372 }
20b09c29 1373 dev->lldd_dev = NULL;
b5762948 1374
20b09c29
AY
1375 if (lock)
1376 spin_unlock_irqrestore(&mvi->lock, flags);
b5762948
JG
1377}
1378
b5762948 1379
20b09c29
AY
1380void mvs_dev_gone(struct domain_device *dev)
1381{
1382 mvs_dev_gone_notify(dev, 1);
1383}
b5762948 1384
20b09c29
AY
1385static struct sas_task *mvs_alloc_task(void)
1386{
1387 struct sas_task *task = kzalloc(sizeof(struct sas_task), GFP_KERNEL);
1388
1389 if (task) {
1390 INIT_LIST_HEAD(&task->list);
1391 spin_lock_init(&task->task_state_lock);
1392 task->task_state_flags = SAS_TASK_STATE_PENDING;
1393 init_timer(&task->timer);
1394 init_completion(&task->completion);
b5762948 1395 }
20b09c29 1396 return task;
dd4969a8 1397}
b5762948 1398
20b09c29 1399static void mvs_free_task(struct sas_task *task)
dd4969a8 1400{
20b09c29
AY
1401 if (task) {
1402 BUG_ON(!list_empty(&task->list));
1403 kfree(task);
b5762948 1404 }
20b09c29 1405}
b5762948 1406
20b09c29
AY
1407static void mvs_task_done(struct sas_task *task)
1408{
1409 if (!del_timer(&task->timer))
1410 return;
1411 complete(&task->completion);
b5762948 1412}
b5762948 1413
20b09c29 1414static void mvs_tmf_timedout(unsigned long data)
b5762948 1415{
20b09c29 1416 struct sas_task *task = (struct sas_task *)data;
8f261aaf 1417
20b09c29
AY
1418 task->task_state_flags |= SAS_TASK_STATE_ABORTED;
1419 complete(&task->completion);
1420}
8f261aaf 1421
20b09c29
AY
1422/* XXX */
1423#define MVS_TASK_TIMEOUT 20
1424static int mvs_exec_internal_tmf_task(struct domain_device *dev,
1425 void *parameter, u32 para_len, struct mvs_tmf_task *tmf)
1426{
1427 int res, retry;
1428 struct sas_task *task = NULL;
8f261aaf 1429
20b09c29
AY
1430 for (retry = 0; retry < 3; retry++) {
1431 task = mvs_alloc_task();
1432 if (!task)
1433 return -ENOMEM;
8f261aaf 1434
20b09c29
AY
1435 task->dev = dev;
1436 task->task_proto = dev->tproto;
8f261aaf 1437
20b09c29
AY
1438 memcpy(&task->ssp_task, parameter, para_len);
1439 task->task_done = mvs_task_done;
8f261aaf 1440
20b09c29
AY
1441 task->timer.data = (unsigned long) task;
1442 task->timer.function = mvs_tmf_timedout;
1443 task->timer.expires = jiffies + MVS_TASK_TIMEOUT*HZ;
1444 add_timer(&task->timer);
8f261aaf 1445
0b84b709 1446 res = mvs_task_exec(task, 1, GFP_KERNEL, NULL, 1, tmf);
8f261aaf 1447
20b09c29
AY
1448 if (res) {
1449 del_timer(&task->timer);
1450 mv_printk("executing internel task failed:%d\n", res);
1451 goto ex_err;
1452 }
8f261aaf 1453
20b09c29
AY
1454 wait_for_completion(&task->completion);
1455 res = -TMF_RESP_FUNC_FAILED;
1456 /* Even TMF timed out, return direct. */
1457 if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
1458 if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
1459 mv_printk("TMF task[%x] timeout.\n", tmf->tmf);
1460 goto ex_err;
1461 }
1462 }
8f261aaf 1463
20b09c29
AY
1464 if (task->task_status.resp == SAS_TASK_COMPLETE &&
1465 task->task_status.stat == SAM_GOOD) {
1466 res = TMF_RESP_FUNC_COMPLETE;
1467 break;
1468 }
b5762948 1469
20b09c29
AY
1470 if (task->task_status.resp == SAS_TASK_COMPLETE &&
1471 task->task_status.stat == SAS_DATA_UNDERRUN) {
1472 /* no error, but return the number of bytes of
1473 * underrun */
1474 res = task->task_status.residual;
1475 break;
1476 }
b5762948 1477
20b09c29
AY
1478 if (task->task_status.resp == SAS_TASK_COMPLETE &&
1479 task->task_status.stat == SAS_DATA_OVERRUN) {
1480 mv_dprintk("blocked task error.\n");
1481 res = -EMSGSIZE;
1482 break;
1483 } else {
1484 mv_dprintk(" task to dev %016llx response: 0x%x "
1485 "status 0x%x\n",
1486 SAS_ADDR(dev->sas_addr),
1487 task->task_status.resp,
1488 task->task_status.stat);
1489 mvs_free_task(task);
1490 task = NULL;
b5762948 1491
dd4969a8 1492 }
dd4969a8 1493 }
20b09c29
AY
1494ex_err:
1495 BUG_ON(retry == 3 && task != NULL);
1496 if (task != NULL)
1497 mvs_free_task(task);
1498 return res;
dd4969a8 1499}
b5762948 1500
20b09c29
AY
1501static int mvs_debug_issue_ssp_tmf(struct domain_device *dev,
1502 u8 *lun, struct mvs_tmf_task *tmf)
dd4969a8 1503{
20b09c29
AY
1504 struct sas_ssp_task ssp_task;
1505 DECLARE_COMPLETION_ONSTACK(completion);
1506 if (!(dev->tproto & SAS_PROTOCOL_SSP))
1507 return TMF_RESP_FUNC_ESUPP;
b5762948 1508
20b09c29 1509 strncpy((u8 *)&ssp_task.LUN, lun, 8);
b5762948 1510
20b09c29
AY
1511 return mvs_exec_internal_tmf_task(dev, &ssp_task,
1512 sizeof(ssp_task), tmf);
1513}
8f261aaf 1514
8f261aaf 1515
20b09c29
AY
1516/* Standard mandates link reset for ATA (type 0)
1517 and hard reset for SSP (type 1) , only for RECOVERY */
1518static int mvs_debug_I_T_nexus_reset(struct domain_device *dev)
1519{
1520 int rc;
1521 struct sas_phy *phy = sas_find_local_phy(dev);
1522 int reset_type = (dev->dev_type == SATA_DEV ||
1523 (dev->tproto & SAS_PROTOCOL_STP)) ? 0 : 1;
1524 rc = sas_phy_reset(phy, reset_type);
1525 msleep(2000);
1526 return rc;
1527}
8f261aaf 1528
20b09c29
AY
1529/* mandatory SAM-3 */
1530int mvs_lu_reset(struct domain_device *dev, u8 *lun)
1531{
1532 unsigned long flags;
1533 int i, phyno[WIDE_PORT_MAX_PHY], num , rc = TMF_RESP_FUNC_FAILED;
1534 struct mvs_tmf_task tmf_task;
20b09c29 1535 struct mvs_device * mvi_dev = (struct mvs_device *)dev->lldd_dev;
9870d9a2 1536 struct mvs_info *mvi = mvi_dev->mvi_info;
20b09c29
AY
1537
1538 tmf_task.tmf = TMF_LU_RESET;
1539 mvi_dev->dev_status = MVS_DEV_EH;
1540 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
1541 if (rc == TMF_RESP_FUNC_COMPLETE) {
1542 num = mvs_find_dev_phyno(dev, phyno);
1543 spin_lock_irqsave(&mvi->lock, flags);
1544 for (i = 0; i < num; i++)
1545 mvs_release_task(mvi, phyno[i], dev);
1546 spin_unlock_irqrestore(&mvi->lock, flags);
dd4969a8 1547 }
20b09c29
AY
1548 /* If failed, fall-through I_T_Nexus reset */
1549 mv_printk("%s for device[%x]:rc= %d\n", __func__,
1550 mvi_dev->device_id, rc);
1551 return rc;
1552}
8f261aaf 1553
20b09c29
AY
1554int mvs_I_T_nexus_reset(struct domain_device *dev)
1555{
1556 unsigned long flags;
1557 int i, phyno[WIDE_PORT_MAX_PHY], num , rc = TMF_RESP_FUNC_FAILED;
9870d9a2
AY
1558 struct mvs_device * mvi_dev = (struct mvs_device *)dev->lldd_dev;
1559 struct mvs_info *mvi = mvi_dev->mvi_info;
20b09c29
AY
1560
1561 if (mvi_dev->dev_status != MVS_DEV_EH)
1562 return TMF_RESP_FUNC_COMPLETE;
1563 rc = mvs_debug_I_T_nexus_reset(dev);
1564 mv_printk("%s for device[%x]:rc= %d\n",
1565 __func__, mvi_dev->device_id, rc);
1566
1567 /* housekeeper */
1568 num = mvs_find_dev_phyno(dev, phyno);
1569 spin_lock_irqsave(&mvi->lock, flags);
1570 for (i = 0; i < num; i++)
1571 mvs_release_task(mvi, phyno[i], dev);
1572 spin_unlock_irqrestore(&mvi->lock, flags);
1573
1574 return rc;
1575}
1576/* optional SAM-3 */
1577int mvs_query_task(struct sas_task *task)
1578{
1579 u32 tag;
1580 struct scsi_lun lun;
1581 struct mvs_tmf_task tmf_task;
1582 int rc = TMF_RESP_FUNC_FAILED;
1583
1584 if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
1585 struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
1586 struct domain_device *dev = task->dev;
9870d9a2
AY
1587 struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
1588 struct mvs_info *mvi = mvi_dev->mvi_info;
20b09c29
AY
1589
1590 int_to_scsilun(cmnd->device->lun, &lun);
1591 rc = mvs_find_tag(mvi, task, &tag);
1592 if (rc == 0) {
1593 rc = TMF_RESP_FUNC_FAILED;
dd4969a8 1594 return rc;
20b09c29 1595 }
8f261aaf 1596
20b09c29
AY
1597 tmf_task.tmf = TMF_QUERY_TASK;
1598 tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
8f261aaf 1599
20b09c29
AY
1600 rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
1601 switch (rc) {
1602 /* The task is still in Lun, release it then */
1603 case TMF_RESP_FUNC_SUCC:
1604 /* The task is not in Lun or failed, reset the phy */
1605 case TMF_RESP_FUNC_FAILED:
1606 case TMF_RESP_FUNC_COMPLETE:
1607 break;
1608 }
dd4969a8 1609 }
20b09c29
AY
1610 mv_printk("%s:rc= %d\n", __func__, rc);
1611 return rc;
8f261aaf
KW
1612}
1613
20b09c29
AY
1614/* mandatory SAM-3, still need free task/slot info */
1615int mvs_abort_task(struct sas_task *task)
8f261aaf 1616{
20b09c29
AY
1617 struct scsi_lun lun;
1618 struct mvs_tmf_task tmf_task;
1619 struct domain_device *dev = task->dev;
9870d9a2
AY
1620 struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
1621 struct mvs_info *mvi = mvi_dev->mvi_info;
20b09c29
AY
1622 int rc = TMF_RESP_FUNC_FAILED;
1623 unsigned long flags;
1624 u32 tag;
9870d9a2 1625
20b09c29
AY
1626 if (mvi->exp_req)
1627 mvi->exp_req--;
1628 spin_lock_irqsave(&task->task_state_lock, flags);
1629 if (task->task_state_flags & SAS_TASK_STATE_DONE) {
1630 spin_unlock_irqrestore(&task->task_state_lock, flags);
1631 rc = TMF_RESP_FUNC_COMPLETE;
1632 goto out;
dd4969a8 1633 }
20b09c29
AY
1634 spin_unlock_irqrestore(&task->task_state_lock, flags);
1635 if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
1636 struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
1637
1638 int_to_scsilun(cmnd->device->lun, &lun);
1639 rc = mvs_find_tag(mvi, task, &tag);
1640 if (rc == 0) {
1641 mv_printk("No such tag in %s\n", __func__);
1642 rc = TMF_RESP_FUNC_FAILED;
1643 return rc;
1644 }
8f261aaf 1645
20b09c29
AY
1646 tmf_task.tmf = TMF_ABORT_TASK;
1647 tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
8f261aaf 1648
20b09c29 1649 rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
8f261aaf 1650
20b09c29
AY
1651 /* if successful, clear the task and callback forwards.*/
1652 if (rc == TMF_RESP_FUNC_COMPLETE) {
1653 u32 slot_no;
1654 struct mvs_slot_info *slot;
8f261aaf 1655
20b09c29
AY
1656 if (task->lldd_task) {
1657 slot = (struct mvs_slot_info *)task->lldd_task;
1658 slot_no = (u32) (slot - mvi->slot_info);
1659 mvs_slot_complete(mvi, slot_no, 1);
1660 }
1661 }
1662 } else if (task->task_proto & SAS_PROTOCOL_SATA ||
1663 task->task_proto & SAS_PROTOCOL_STP) {
1664 /* to do free register_set */
1665 } else {
1666 /* SMP */
8f261aaf 1667
20b09c29
AY
1668 }
1669out:
1670 if (rc != TMF_RESP_FUNC_COMPLETE)
1671 mv_printk("%s:rc= %d\n", __func__, rc);
dd4969a8 1672 return rc;
8f261aaf
KW
1673}
1674
20b09c29 1675int mvs_abort_task_set(struct domain_device *dev, u8 *lun)
8f261aaf 1676{
20b09c29
AY
1677 int rc = TMF_RESP_FUNC_FAILED;
1678 struct mvs_tmf_task tmf_task;
8f261aaf 1679
20b09c29
AY
1680 tmf_task.tmf = TMF_ABORT_TASK_SET;
1681 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
dd4969a8 1682
20b09c29 1683 return rc;
8f261aaf
KW
1684}
1685
20b09c29 1686int mvs_clear_aca(struct domain_device *dev, u8 *lun)
8f261aaf 1687{
20b09c29
AY
1688 int rc = TMF_RESP_FUNC_FAILED;
1689 struct mvs_tmf_task tmf_task;
8f261aaf 1690
20b09c29
AY
1691 tmf_task.tmf = TMF_CLEAR_ACA;
1692 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
8f261aaf 1693
20b09c29
AY
1694 return rc;
1695}
8f261aaf 1696
20b09c29
AY
1697int mvs_clear_task_set(struct domain_device *dev, u8 *lun)
1698{
1699 int rc = TMF_RESP_FUNC_FAILED;
1700 struct mvs_tmf_task tmf_task;
8f261aaf 1701
20b09c29
AY
1702 tmf_task.tmf = TMF_CLEAR_TASK_SET;
1703 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
8f261aaf 1704
20b09c29 1705 return rc;
dd4969a8 1706}
8f261aaf 1707
20b09c29
AY
1708static int mvs_sata_done(struct mvs_info *mvi, struct sas_task *task,
1709 u32 slot_idx, int err)
dd4969a8 1710{
20b09c29
AY
1711 struct mvs_device *mvi_dev = (struct mvs_device *)task->dev->lldd_dev;
1712 struct task_status_struct *tstat = &task->task_status;
1713 struct ata_task_resp *resp = (struct ata_task_resp *)tstat->buf;
1714 int stat = SAM_GOOD;
e9ff91b6 1715
8f261aaf 1716
20b09c29
AY
1717 resp->frame_len = sizeof(struct dev_to_host_fis);
1718 memcpy(&resp->ending_fis[0],
1719 SATA_RECEIVED_D2H_FIS(mvi_dev->taskfileset),
1720 sizeof(struct dev_to_host_fis));
1721 tstat->buf_valid_size = sizeof(*resp);
1722 if (unlikely(err))
1723 stat = SAS_PROTO_RESPONSE;
1724 return stat;
8f261aaf
KW
1725}
1726
20b09c29
AY
1727static int mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
1728 u32 slot_idx)
8f261aaf 1729{
20b09c29
AY
1730 struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
1731 int stat;
1732 u32 err_dw0 = le32_to_cpu(*(u32 *) (slot->response));
1733 u32 tfs = 0;
1734 enum mvs_port_type type = PORT_TYPE_SAS;
8f261aaf 1735
20b09c29
AY
1736 if (err_dw0 & CMD_ISS_STPD)
1737 MVS_CHIP_DISP->issue_stop(mvi, type, tfs);
1738
1739 MVS_CHIP_DISP->command_active(mvi, slot_idx);
b5762948 1740
20b09c29 1741 stat = SAM_CHECK_COND;
dd4969a8 1742 switch (task->task_proto) {
dd4969a8 1743 case SAS_PROTOCOL_SSP:
20b09c29
AY
1744 stat = SAS_ABORTED_TASK;
1745 break;
1746 case SAS_PROTOCOL_SMP:
1747 stat = SAM_CHECK_COND;
dd4969a8 1748 break;
20b09c29 1749
dd4969a8
JG
1750 case SAS_PROTOCOL_SATA:
1751 case SAS_PROTOCOL_STP:
20b09c29
AY
1752 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1753 {
1754 if (err_dw0 == 0x80400002)
1755 mv_printk("find reserved error, why?\n");
1756
1757 task->ata_task.use_ncq = 0;
1758 stat = SAS_PROTO_RESPONSE;
1759 mvs_sata_done(mvi, task, slot_idx, 1);
1760
dd4969a8 1761 }
20b09c29 1762 break;
dd4969a8
JG
1763 default:
1764 break;
1765 }
1766
20b09c29 1767 return stat;
e9ff91b6
KW
1768}
1769
20b09c29 1770int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags)
b5762948 1771{
20b09c29
AY
1772 u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
1773 struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
1774 struct sas_task *task = slot->task;
1775 struct mvs_device *mvi_dev = NULL;
1776 struct task_status_struct *tstat;
1777
1778 bool aborted;
1779 void *to;
1780 enum exec_status sts;
1781
1782 if (mvi->exp_req)
1783 mvi->exp_req--;
1784 if (unlikely(!task || !task->lldd_task))
1785 return -1;
1786
1787 tstat = &task->task_status;
1788 mvi_dev = (struct mvs_device *)task->dev->lldd_dev;
b5762948 1789
20b09c29
AY
1790 mvs_hba_cq_dump(mvi);
1791
1792 spin_lock(&task->task_state_lock);
1793 task->task_state_flags &=
1794 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1795 task->task_state_flags |= SAS_TASK_STATE_DONE;
1796 /* race condition*/
1797 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
1798 spin_unlock(&task->task_state_lock);
1799
1800 memset(tstat, 0, sizeof(*tstat));
1801 tstat->resp = SAS_TASK_COMPLETE;
1802
1803 if (unlikely(aborted)) {
1804 tstat->stat = SAS_ABORTED_TASK;
1805 if (mvi_dev)
1806 mvi_dev->runing_req--;
1807 if (sas_protocol_ata(task->task_proto))
1808 mvs_free_reg_set(mvi, mvi_dev);
1809
1810 mvs_slot_task_free(mvi, task, slot, slot_idx);
1811 return -1;
b5762948
JG
1812 }
1813
20b09c29
AY
1814 if (unlikely(!mvi_dev || !slot->port->port_attached || flags)) {
1815 mv_dprintk("port has not device.\n");
1816 tstat->stat = SAS_PHY_DOWN;
1817 goto out;
1818 }
b5762948 1819
20b09c29
AY
1820 /*
1821 if (unlikely((rx_desc & RXQ_ERR) || (*(u64 *) slot->response))) {
1822 mv_dprintk("Find device[%016llx] RXQ_ERR %X,
1823 err info:%016llx\n",
1824 SAS_ADDR(task->dev->sas_addr),
1825 rx_desc, (u64)(*(u64 *) slot->response));
b5762948 1826 }
20b09c29
AY
1827 */
1828
1829 /* error info record present */
1830 if (unlikely((rx_desc & RXQ_ERR) && (*(u64 *) slot->response))) {
1831 tstat->stat = mvs_slot_err(mvi, task, slot_idx);
1832 goto out;
b5762948
JG
1833 }
1834
20b09c29
AY
1835 switch (task->task_proto) {
1836 case SAS_PROTOCOL_SSP:
1837 /* hw says status == 0, datapres == 0 */
1838 if (rx_desc & RXQ_GOOD) {
1839 tstat->stat = SAM_GOOD;
1840 tstat->resp = SAS_TASK_COMPLETE;
1841 }
1842 /* response frame present */
1843 else if (rx_desc & RXQ_RSP) {
1844 struct ssp_response_iu *iu = slot->response +
1845 sizeof(struct mvs_err_info);
1846 sas_ssp_task_response(mvi->dev, task, iu);
1847 } else
1848 tstat->stat = SAM_CHECK_COND;
1849 break;
b5762948 1850
20b09c29
AY
1851 case SAS_PROTOCOL_SMP: {
1852 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1853 tstat->stat = SAM_GOOD;
1854 to = kmap_atomic(sg_page(sg_resp), KM_IRQ0);
1855 memcpy(to + sg_resp->offset,
1856 slot->response + sizeof(struct mvs_err_info),
1857 sg_dma_len(sg_resp));
1858 kunmap_atomic(to, KM_IRQ0);
1859 break;
1860 }
8f261aaf 1861
20b09c29
AY
1862 case SAS_PROTOCOL_SATA:
1863 case SAS_PROTOCOL_STP:
1864 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: {
1865 tstat->stat = mvs_sata_done(mvi, task, slot_idx, 0);
1866 break;
1867 }
b5762948 1868
20b09c29
AY
1869 default:
1870 tstat->stat = SAM_CHECK_COND;
1871 break;
1872 }
b5762948 1873
20b09c29 1874out:
0f980a87 1875 if (mvi_dev) {
20b09c29 1876 mvi_dev->runing_req--;
0f980a87
AY
1877 if (sas_protocol_ata(task->task_proto))
1878 mvs_free_reg_set(mvi, mvi_dev);
1879 }
20b09c29
AY
1880 mvs_slot_task_free(mvi, task, slot, slot_idx);
1881 sts = tstat->stat;
8f261aaf 1882
20b09c29
AY
1883 spin_unlock(&mvi->lock);
1884 if (task->task_done)
1885 task->task_done(task);
1886 else
1887 mv_dprintk("why has not task_done.\n");
1888 spin_lock(&mvi->lock);
b5762948 1889
20b09c29
AY
1890 return sts;
1891}
b5762948 1892
20b09c29
AY
1893void mvs_release_task(struct mvs_info *mvi,
1894 int phy_no, struct domain_device *dev)
1895{
1896 int i = 0; u32 slot_idx;
1897 struct mvs_phy *phy;
1898 struct mvs_port *port;
1899 struct mvs_slot_info *slot, *slot2;
b5762948 1900
20b09c29
AY
1901 phy = &mvi->phy[phy_no];
1902 port = phy->port;
1903 if (!port)
1904 return;
b5762948 1905
20b09c29
AY
1906 list_for_each_entry_safe(slot, slot2, &port->list, entry) {
1907 struct sas_task *task;
1908 slot_idx = (u32) (slot - mvi->slot_info);
1909 task = slot->task;
b5762948 1910
20b09c29
AY
1911 if (dev && task->dev != dev)
1912 continue;
8f261aaf 1913
20b09c29
AY
1914 mv_printk("Release slot [%x] tag[%x], task [%p]:\n",
1915 slot_idx, slot->slot_tag, task);
b5762948 1916
20b09c29
AY
1917 if (task->task_proto & SAS_PROTOCOL_SSP) {
1918 mv_printk("attached with SSP task CDB[");
1919 for (i = 0; i < 16; i++)
1920 mv_printk(" %02x", task->ssp_task.cdb[i]);
1921 mv_printk(" ]\n");
1922 }
b5762948 1923
20b09c29 1924 mvs_slot_complete(mvi, slot_idx, 1);
b5762948 1925 }
20b09c29 1926}
b5762948 1927
20b09c29
AY
1928static void mvs_phy_disconnected(struct mvs_phy *phy)
1929{
1930 phy->phy_attached = 0;
1931 phy->att_dev_info = 0;
1932 phy->att_dev_sas_addr = 0;
1933}
1934
1935static void mvs_work_queue(struct work_struct *work)
1936{
1937 struct delayed_work *dw = container_of(work, struct delayed_work, work);
1938 struct mvs_wq *mwq = container_of(dw, struct mvs_wq, work_q);
1939 struct mvs_info *mvi = mwq->mvi;
1940 unsigned long flags;
b5762948 1941
20b09c29
AY
1942 spin_lock_irqsave(&mvi->lock, flags);
1943 if (mwq->handler & PHY_PLUG_EVENT) {
1944 u32 phy_no = (unsigned long) mwq->data;
1945 struct sas_ha_struct *sas_ha = mvi->sas;
1946 struct mvs_phy *phy = &mvi->phy[phy_no];
1947 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1948
1949 if (phy->phy_event & PHY_PLUG_OUT) {
1950 u32 tmp;
1951 struct sas_identify_frame *id;
1952 id = (struct sas_identify_frame *)phy->frame_rcvd;
1953 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no);
1954 phy->phy_event &= ~PHY_PLUG_OUT;
1955 if (!(tmp & PHY_READY_MASK)) {
1956 sas_phy_disconnected(sas_phy);
1957 mvs_phy_disconnected(phy);
1958 sas_ha->notify_phy_event(sas_phy,
1959 PHYE_LOSS_OF_SIGNAL);
1960 mv_dprintk("phy%d Removed Device\n", phy_no);
1961 } else {
1962 MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
1963 mvs_update_phyinfo(mvi, phy_no, 1);
1964 mvs_bytes_dmaed(mvi, phy_no);
1965 mvs_port_notify_formed(sas_phy, 0);
1966 mv_dprintk("phy%d Attached Device\n", phy_no);
1967 }
1968 }
1969 }
1970 list_del(&mwq->entry);
1971 spin_unlock_irqrestore(&mvi->lock, flags);
1972 kfree(mwq);
1973}
8f261aaf 1974
20b09c29
AY
1975static int mvs_handle_event(struct mvs_info *mvi, void *data, int handler)
1976{
1977 struct mvs_wq *mwq;
1978 int ret = 0;
1979
1980 mwq = kmalloc(sizeof(struct mvs_wq), GFP_ATOMIC);
1981 if (mwq) {
1982 mwq->mvi = mvi;
1983 mwq->data = data;
1984 mwq->handler = handler;
1985 MV_INIT_DELAYED_WORK(&mwq->work_q, mvs_work_queue, mwq);
1986 list_add_tail(&mwq->entry, &mvi->wq_list);
1987 schedule_delayed_work(&mwq->work_q, HZ * 2);
1988 } else
1989 ret = -ENOMEM;
1990
1991 return ret;
1992}
b5762948 1993
20b09c29
AY
1994static void mvs_sig_time_out(unsigned long tphy)
1995{
1996 struct mvs_phy *phy = (struct mvs_phy *)tphy;
1997 struct mvs_info *mvi = phy->mvi;
1998 u8 phy_no;
1999
2000 for (phy_no = 0; phy_no < mvi->chip->n_phy; phy_no++) {
2001 if (&mvi->phy[phy_no] == phy) {
2002 mv_dprintk("Get signature time out, reset phy %d\n",
2003 phy_no+mvi->id*mvi->chip->n_phy);
2004 MVS_CHIP_DISP->phy_reset(mvi, phy_no, 1);
2005 }
b5762948 2006 }
20b09c29 2007}
b5762948 2008
20b09c29
AY
2009static void mvs_sig_remove_timer(struct mvs_phy *phy)
2010{
2011 if (phy->timer.function)
2012 del_timer(&phy->timer);
2013 phy->timer.function = NULL;
2014}
b5762948 2015
20b09c29
AY
2016void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
2017{
2018 u32 tmp;
2019 struct sas_ha_struct *sas_ha = mvi->sas;
2020 struct mvs_phy *phy = &mvi->phy[phy_no];
2021 struct asd_sas_phy *sas_phy = &phy->sas_phy;
8f261aaf 2022
20b09c29
AY
2023 phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, phy_no);
2024 mv_dprintk("port %d ctrl sts=0x%X.\n", phy_no+mvi->id*mvi->chip->n_phy,
2025 MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no));
2026 mv_dprintk("Port %d irq sts = 0x%X\n", phy_no+mvi->id*mvi->chip->n_phy,
2027 phy->irq_status);
8f261aaf 2028
20b09c29
AY
2029 /*
2030 * events is port event now ,
2031 * we need check the interrupt status which belongs to per port.
2032 */
b5762948 2033
20b09c29
AY
2034 if (phy->irq_status & PHYEV_DCDR_ERR)
2035 mv_dprintk("port %d STP decoding error.\n",
2036 phy_no+mvi->id*mvi->chip->n_phy);
2037
2038 if (phy->irq_status & PHYEV_POOF) {
2039 if (!(phy->phy_event & PHY_PLUG_OUT)) {
2040 int dev_sata = phy->phy_type & PORT_TYPE_SATA;
2041 int ready;
2042 mvs_release_task(mvi, phy_no, NULL);
2043 phy->phy_event |= PHY_PLUG_OUT;
2044 mvs_handle_event(mvi,
2045 (void *)(unsigned long)phy_no,
2046 PHY_PLUG_EVENT);
2047 ready = mvs_is_phy_ready(mvi, phy_no);
2048 if (!ready)
2049 mv_dprintk("phy%d Unplug Notice\n",
2050 phy_no +
2051 mvi->id * mvi->chip->n_phy);
2052 if (ready || dev_sata) {
2053 if (MVS_CHIP_DISP->stp_reset)
2054 MVS_CHIP_DISP->stp_reset(mvi,
2055 phy_no);
2056 else
2057 MVS_CHIP_DISP->phy_reset(mvi,
2058 phy_no, 0);
2059 return;
2060 }
2061 }
2062 }
b5762948 2063
20b09c29
AY
2064 if (phy->irq_status & PHYEV_COMWAKE) {
2065 tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, phy_no);
2066 MVS_CHIP_DISP->write_port_irq_mask(mvi, phy_no,
2067 tmp | PHYEV_SIG_FIS);
2068 if (phy->timer.function == NULL) {
2069 phy->timer.data = (unsigned long)phy;
2070 phy->timer.function = mvs_sig_time_out;
2071 phy->timer.expires = jiffies + 10*HZ;
2072 add_timer(&phy->timer);
2073 }
2074 }
2075 if (phy->irq_status & (PHYEV_SIG_FIS | PHYEV_ID_DONE)) {
2076 phy->phy_status = mvs_is_phy_ready(mvi, phy_no);
2077 mvs_sig_remove_timer(phy);
2078 mv_dprintk("notify plug in on phy[%d]\n", phy_no);
2079 if (phy->phy_status) {
2080 mdelay(10);
2081 MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
2082 if (phy->phy_type & PORT_TYPE_SATA) {
2083 tmp = MVS_CHIP_DISP->read_port_irq_mask(
2084 mvi, phy_no);
2085 tmp &= ~PHYEV_SIG_FIS;
2086 MVS_CHIP_DISP->write_port_irq_mask(mvi,
2087 phy_no, tmp);
2088 }
2089 mvs_update_phyinfo(mvi, phy_no, 0);
2090 mvs_bytes_dmaed(mvi, phy_no);
2091 /* whether driver is going to handle hot plug */
2092 if (phy->phy_event & PHY_PLUG_OUT) {
2093 mvs_port_notify_formed(sas_phy, 0);
2094 phy->phy_event &= ~PHY_PLUG_OUT;
2095 }
2096 } else {
2097 mv_dprintk("plugin interrupt but phy%d is gone\n",
2098 phy_no + mvi->id*mvi->chip->n_phy);
2099 }
2100 } else if (phy->irq_status & PHYEV_BROAD_CH) {
2101 mv_dprintk("port %d broadcast change.\n",
2102 phy_no + mvi->id*mvi->chip->n_phy);
2103 /* exception for Samsung disk drive*/
2104 mdelay(1000);
2105 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2106 }
2107 MVS_CHIP_DISP->write_port_irq_stat(mvi, phy_no, phy->irq_status);
b5762948
JG
2108}
2109
20b09c29 2110int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
b5762948 2111{
20b09c29
AY
2112 u32 rx_prod_idx, rx_desc;
2113 bool attn = false;
b5762948 2114
20b09c29
AY
2115 /* the first dword in the RX ring is special: it contains
2116 * a mirror of the hardware's RX producer index, so that
2117 * we don't have to stall the CPU reading that register.
2118 * The actual RX ring is offset by one dword, due to this.
2119 */
2120 rx_prod_idx = mvi->rx_cons;
2121 mvi->rx_cons = le32_to_cpu(mvi->rx[0]);
2122 if (mvi->rx_cons == 0xfff) /* h/w hasn't touched RX ring yet */
2123 return 0;
b5762948 2124
20b09c29
AY
2125 /* The CMPL_Q may come late, read from register and try again
2126 * note: if coalescing is enabled,
2127 * it will need to read from register every time for sure
2128 */
2129 if (unlikely(mvi->rx_cons == rx_prod_idx))
2130 mvi->rx_cons = MVS_CHIP_DISP->rx_update(mvi) & RX_RING_SZ_MASK;
2131
2132 if (mvi->rx_cons == rx_prod_idx)
2133 return 0;
2134
2135 while (mvi->rx_cons != rx_prod_idx) {
2136 /* increment our internal RX consumer pointer */
2137 rx_prod_idx = (rx_prod_idx + 1) & (MVS_RX_RING_SZ - 1);
2138 rx_desc = le32_to_cpu(mvi->rx[rx_prod_idx + 1]);
2139
2140 if (likely(rx_desc & RXQ_DONE))
2141 mvs_slot_complete(mvi, rx_desc, 0);
2142 if (rx_desc & RXQ_ATTN) {
2143 attn = true;
2144 } else if (rx_desc & RXQ_ERR) {
2145 if (!(rx_desc & RXQ_DONE))
2146 mvs_slot_complete(mvi, rx_desc, 0);
2147 } else if (rx_desc & RXQ_SLOT_RESET) {
2148 mvs_slot_free(mvi, rx_desc);
2149 }
2150 }
2151
2152 if (attn && self_clear)
2153 MVS_CHIP_DISP->int_full(mvi);
2154 return 0;
b5762948
JG
2155}
2156