[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pci / intr_remapping.c

#include <linux/interrupt.h>
#include <linux/dmar.h>
#include <linux/spinlock.h>
#include <linux/jiffies.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <asm/io_apic.h>
#include <asm/smp.h>
#include <asm/cpu.h>
#include <linux/intel-iommu.h>
#include "intr_remapping.h"

static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
static int ir_ioapic_num;
int intr_remapping_enabled;

struct irq_2_iommu {
	struct intel_iommu *iommu;
	u16 irte_index;
	u16 sub_handle;
	u8  irte_mask;
};

#ifdef CONFIG_SPARSE_IRQ
static struct irq_2_iommu *get_one_free_irq_2_iommu(int cpu)
{
	struct irq_2_iommu *iommu;
	int node;

	node = cpu_to_node(cpu);

	iommu = kzalloc_node(sizeof(*iommu), GFP_ATOMIC, node);
	printk(KERN_DEBUG "alloc irq_2_iommu on cpu %d node %d\n", cpu, node);

	return iommu;
}

static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
{
	struct irq_desc *desc;

	desc = irq_to_desc(irq);

	if (WARN_ON_ONCE(!desc))
		return NULL;

	return desc->irq_2_iommu;
}

static struct irq_2_iommu *irq_2_iommu_alloc_cpu(unsigned int irq, int cpu)
{
	struct irq_desc *desc;
	struct irq_2_iommu *irq_iommu;

	/*
	 * alloc irq desc if not allocated already.
	 */
	desc = irq_to_desc_alloc_cpu(irq, cpu);
	if (!desc) {
		printk(KERN_INFO "can not get irq_desc for %d\n", irq);
		return NULL;
	}

	irq_iommu = desc->irq_2_iommu;

	if (!irq_iommu)
		desc->irq_2_iommu = get_one_free_irq_2_iommu(cpu);

	return desc->irq_2_iommu;
}

static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
{
	return irq_2_iommu_alloc_cpu(irq, boot_cpu_id);
}

#else /* !CONFIG_SPARSE_IRQ */

static struct irq_2_iommu irq_2_iommuX[NR_IRQS];

static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
{
	if (irq < nr_irqs)
		return &irq_2_iommuX[irq];

	return NULL;
}
static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
{
	return irq_2_iommu(irq);
}
#endif

static DEFINE_SPINLOCK(irq_2_ir_lock);

static struct irq_2_iommu *valid_irq_2_iommu(unsigned int irq)
{
	struct irq_2_iommu *irq_iommu;

	irq_iommu = irq_2_iommu(irq);

	if (!irq_iommu)
		return NULL;

	if (!irq_iommu->iommu)
		return NULL;

	return irq_iommu;
}

int irq_remapped(int irq)
{
	return valid_irq_2_iommu(irq) != NULL;
}

int get_irte(int irq, struct irte *entry)
{
	int index;
	struct irq_2_iommu *irq_iommu;

	if (!entry)
		return -1;

	spin_lock(&irq_2_ir_lock);
	irq_iommu = valid_irq_2_iommu(irq);
	if (!irq_iommu) {
		spin_unlock(&irq_2_ir_lock);
		return -1;
	}

	index = irq_iommu->irte_index + irq_iommu->sub_handle;
	*entry = *(irq_iommu->iommu->ir_table->base + index);

	spin_unlock(&irq_2_ir_lock);
	return 0;
}

int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
{
	struct ir_table *table = iommu->ir_table;
	struct irq_2_iommu *irq_iommu;
	u16 index, start_index;
	unsigned int mask = 0;
	int i;

	if (!count)
		return -1;

#ifndef CONFIG_SPARSE_IRQ
	/* protect irq_2_iommu_alloc later */
	if (irq >= nr_irqs)
		return -1;
#endif

	/*
	 * start the IRTE search from index 0.
	 */
	index = start_index = 0;

	if (count > 1) {
		count = __roundup_pow_of_two(count);
		mask = ilog2(count);
	}

	if (mask > ecap_max_handle_mask(iommu->ecap)) {
		printk(KERN_ERR
		       "Requested mask %x exceeds the max invalidation handle"
		       " mask value %Lx\n", mask,
		       ecap_max_handle_mask(iommu->ecap));
		return -1;
	}

	spin_lock(&irq_2_ir_lock);
	do {
		for (i = index; i < index + count; i++)
			if  (table->base[i].present)
				break;
		/* empty index found */
		if (i == index + count)
			break;

		index = (index + count) % INTR_REMAP_TABLE_ENTRIES;

		if (index == start_index) {
			spin_unlock(&irq_2_ir_lock);
			printk(KERN_ERR "can't allocate an IRTE\n");
			return -1;
		}
	} while (1);

	for (i = index; i < index + count; i++)
		table->base[i].present = 1;

	irq_iommu = irq_2_iommu_alloc(irq);
	if (!irq_iommu) {
		spin_unlock(&irq_2_ir_lock);
		printk(KERN_ERR "can't allocate irq_2_iommu\n");
		return -1;
	}

	irq_iommu->iommu = iommu;
	irq_iommu->irte_index =  index;
	irq_iommu->sub_handle = 0;
	irq_iommu->irte_mask = mask;

	spin_unlock(&irq_2_ir_lock);

	return index;
}

static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
{
	struct qi_desc desc;

	desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
		   | QI_IEC_SELECTIVE;
	desc.high = 0;

	return qi_submit_sync(&desc, iommu);
}

int map_irq_to_irte_handle(int irq, u16 *sub_handle)
{
	int index;
	struct irq_2_iommu *irq_iommu;

	spin_lock(&irq_2_ir_lock);
	irq_iommu = valid_irq_2_iommu(irq);
	if (!irq_iommu) {
		spin_unlock(&irq_2_ir_lock);
		return -1;
	}

	*sub_handle = irq_iommu->sub_handle;
	index = irq_iommu->irte_index;
	spin_unlock(&irq_2_ir_lock);
	return index;
}

int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
{
	struct irq_2_iommu *irq_iommu;

	spin_lock(&irq_2_ir_lock);

	irq_iommu = irq_2_iommu_alloc(irq);

	if (!irq_iommu) {
		spin_unlock(&irq_2_ir_lock);
		printk(KERN_ERR "can't allocate irq_2_iommu\n");
		return -1;
	}

	irq_iommu->iommu = iommu;
	irq_iommu->irte_index = index;
	irq_iommu->sub_handle = subhandle;
	irq_iommu->irte_mask = 0;

	spin_unlock(&irq_2_ir_lock);

	return 0;
}

int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index)
{
	struct irq_2_iommu *irq_iommu;

	spin_lock(&irq_2_ir_lock);
	irq_iommu = valid_irq_2_iommu(irq);
	if (!irq_iommu) {
		spin_unlock(&irq_2_ir_lock);
		return -1;
	}

	irq_iommu->iommu = NULL;
	irq_iommu->irte_index = 0;
	irq_iommu->sub_handle = 0;
	irq_2_iommu(irq)->irte_mask = 0;

	spin_unlock(&irq_2_ir_lock);

	return 0;
}

int modify_irte(int irq, struct irte *irte_modified)
{
	int rc;
	int index;
	struct irte *irte;
	struct intel_iommu *iommu;
	struct irq_2_iommu *irq_iommu;

	spin_lock(&irq_2_ir_lock);
	irq_iommu = valid_irq_2_iommu(irq);
	if (!irq_iommu) {
		spin_unlock(&irq_2_ir_lock);
		return -1;
	}

	iommu = irq_iommu->iommu;

	index = irq_iommu->irte_index + irq_iommu->sub_handle;
	irte = &iommu->ir_table->base[index];

	set_64bit((unsigned long *)irte, irte_modified->low | (1 << 1));
	__iommu_flush_cache(iommu, irte, sizeof(*irte));

	rc = qi_flush_iec(iommu, index, 0);
	spin_unlock(&irq_2_ir_lock);

	return rc;
}

int flush_irte(int irq)
{
	int rc;
	int index;
	struct intel_iommu *iommu;
	struct irq_2_iommu *irq_iommu;

	spin_lock(&irq_2_ir_lock);
	irq_iommu = valid_irq_2_iommu(irq);
	if (!irq_iommu) {
		spin_unlock(&irq_2_ir_lock);
		return -1;
	}

	iommu = irq_iommu->iommu;

	index = irq_iommu->irte_index + irq_iommu->sub_handle;

	rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask);
	spin_unlock(&irq_2_ir_lock);

	return rc;
}

struct intel_iommu *map_ioapic_to_ir(int apic)
{
	int i;

	for (i = 0; i < MAX_IO_APICS; i++)
		if (ir_ioapic[i].id == apic)
			return ir_ioapic[i].iommu;
	return NULL;
}

struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
{
	struct dmar_drhd_unit *drhd;

	drhd = dmar_find_matched_drhd_unit(dev);
	if (!drhd)
		return NULL;

	return drhd->iommu;
}

int free_irte(int irq)
{
	int rc = 0;
	int index, i;
	struct irte *irte;
	struct intel_iommu *iommu;
	struct irq_2_iommu *irq_iommu;

	spin_lock(&irq_2_ir_lock);
	irq_iommu = valid_irq_2_iommu(irq);
	if (!irq_iommu) {
		spin_unlock(&irq_2_ir_lock);
		return -1;
	}

	iommu = irq_iommu->iommu;

	index = irq_iommu->irte_index + irq_iommu->sub_handle;
	irte = &iommu->ir_table->base[index];

	if (!irq_iommu->sub_handle) {
		for (i = 0; i < (1 << irq_iommu->irte_mask); i++)
			set_64bit((unsigned long *)irte, 0);
		rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask);
	}

	irq_iommu->iommu = NULL;
	irq_iommu->irte_index = 0;
	irq_iommu->sub_handle = 0;
	irq_iommu->irte_mask = 0;

	spin_unlock(&irq_2_ir_lock);

	return rc;
}

static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
{
	u64 addr;
	u32 cmd, sts;
	unsigned long flags;

	addr = virt_to_phys((void *)iommu->ir_table->base);

	spin_lock_irqsave(&iommu->register_lock, flags);

	dmar_writeq(iommu->reg + DMAR_IRTA_REG,
		    (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);

	/* Set interrupt-remapping table pointer */
	cmd = iommu->gcmd | DMA_GCMD_SIRTP;
	writel(cmd, iommu->reg + DMAR_GCMD_REG);

	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
		      readl, (sts & DMA_GSTS_IRTPS), sts);
	spin_unlock_irqrestore(&iommu->register_lock, flags);

	/*
	 * global invalidation of interrupt entry cache before enabling
	 * interrupt-remapping.
	 */
	qi_global_iec(iommu);

	spin_lock_irqsave(&iommu->register_lock, flags);

	/* Enable interrupt-remapping */
	cmd = iommu->gcmd | DMA_GCMD_IRE;
	iommu->gcmd |= DMA_GCMD_IRE;
	writel(cmd, iommu->reg + DMAR_GCMD_REG);

	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
		      readl, (sts & DMA_GSTS_IRES), sts);

	spin_unlock_irqrestore(&iommu->register_lock, flags);
}


static int setup_intr_remapping(struct intel_iommu *iommu, int mode)
{
	struct ir_table *ir_table;
	struct page *pages;

	ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table),
					     GFP_KERNEL);

	if (!iommu->ir_table)
		return -ENOMEM;

	pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, INTR_REMAP_PAGE_ORDER);

	if (!pages) {
		printk(KERN_ERR "failed to allocate pages of order %d\n",
		       INTR_REMAP_PAGE_ORDER);
		kfree(iommu->ir_table);
		return -ENOMEM;
	}

	ir_table->base = page_address(pages);

	iommu_set_intr_remapping(iommu, mode);
	return 0;
}

int __init enable_intr_remapping(int eim)
{
	struct dmar_drhd_unit *drhd;
	int setup = 0;

	/*
	 * check for the Interrupt-remapping support
	 */
	for_each_drhd_unit(drhd) {
		struct intel_iommu *iommu = drhd->iommu;

		if (!ecap_ir_support(iommu->ecap))
			continue;

		if (eim && !ecap_eim_support(iommu->ecap)) {
			printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
			       " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
			return -1;
		}
	}

	/*
	 * Enable queued invalidation for all the DRHD's.
	 */
	for_each_drhd_unit(drhd) {
		int ret;
		struct intel_iommu *iommu = drhd->iommu;
		ret = dmar_enable_qi(iommu);

		if (ret) {
			printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
			       " invalidation, ecap %Lx, ret %d\n",
			       drhd->reg_base_addr, iommu->ecap, ret);
			return -1;
		}
	}

	/*
	 * Setup Interrupt-remapping for all the DRHD's now.
	 */
	for_each_drhd_unit(drhd) {
		struct intel_iommu *iommu = drhd->iommu;

		if (!ecap_ir_support(iommu->ecap))
			continue;

		if (setup_intr_remapping(iommu, eim))
			goto error;

		setup = 1;
	}

	if (!setup)
		goto error;

	intr_remapping_enabled = 1;

	return 0;

error:
	/*
	 * handle error condition gracefully here!
	 */
	return -1;
}

static int ir_parse_ioapic_scope(struct acpi_dmar_header *header,
				 struct intel_iommu *iommu)
{
	struct acpi_dmar_hardware_unit *drhd;
	struct acpi_dmar_device_scope *scope;
	void *start, *end;

	drhd = (struct acpi_dmar_hardware_unit *)header;

	start = (void *)(drhd + 1);
	end = ((void *)drhd) + header->length;

	while (start < end) {
		scope = start;
		if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
			if (ir_ioapic_num == MAX_IO_APICS) {
				printk(KERN_WARNING "Exceeded Max IO APICS\n");
				return -1;
			}

			printk(KERN_INFO "IOAPIC id %d under DRHD base"
			       " 0x%Lx\n", scope->enumeration_id,
			       drhd->address);

			ir_ioapic[ir_ioapic_num].iommu = iommu;
			ir_ioapic[ir_ioapic_num].id = scope->enumeration_id;
			ir_ioapic_num++;
		}
		start += scope->length;
	}

	return 0;
}

/*
 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
 * hardware unit.
 */
int __init parse_ioapics_under_ir(void)
{
	struct dmar_drhd_unit *drhd;
	int ir_supported = 0;

	for_each_drhd_unit(drhd) {
		struct intel_iommu *iommu = drhd->iommu;

		if (ecap_ir_support(iommu->ecap)) {
			if (ir_parse_ioapic_scope(drhd->hdr, iommu))
				return -1;

			ir_supported = 1;
		}
	}

	if (ir_supported && ir_ioapic_num != nr_ioapics) {
		printk(KERN_WARNING
		       "Not all IO-APIC's listed under remapping hardware\n");
		return -1;
	}

	return ir_supported;
}
Commit	Line	Data
5aeecaf4	1	#include <linux/interrupt.h>
ad3ad3f6	2	#include <linux/dmar.h>
2ae21010 SS	3	#include <linux/spinlock.h>
	4	#include <linux/jiffies.h>
	5	#include <linux/pci.h>
b6fcb33a	6	#include <linux/irq.h>
ad3ad3f6	7	#include <asm/io_apic.h>
17483a1f	8	#include <asm/smp.h>
6d652ea1	9	#include <asm/cpu.h>
38717946	10	#include <linux/intel-iommu.h>
ad3ad3f6 SS	11	#include "intr_remapping.h"
	12
	13	static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
	14	static int ir_ioapic_num;
2ae21010 SS	15	int intr_remapping_enabled;
2ae21010 SS	16
5aeecaf4	17	struct irq_2_iommu {
b6fcb33a SS	18	struct intel_iommu *iommu;
	19	u16 irte_index;
	20	u16 sub_handle;
	21	u8 irte_mask;
5aeecaf4 YL	22	};
5aeecaf4 YL	23
0b8f1efa YL	24	#ifdef CONFIG_SPARSE_IRQ
	25	static struct irq_2_iommu *get_one_free_irq_2_iommu(int cpu)
	26	{
	27	struct irq_2_iommu *iommu;
	28	int node;
	29
	30	node = cpu_to_node(cpu);
	31
	32	iommu = kzalloc_node(sizeof(*iommu), GFP_ATOMIC, node);
	33	printk(KERN_DEBUG "alloc irq_2_iommu on cpu %d node %d\n", cpu, node);
	34
	35	return iommu;
	36	}
e420dfb4 YL	37
	38	static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
	39	{
0b8f1efa YL	40	struct irq_desc *desc;
	41
	42	desc = irq_to_desc(irq);
	43
	44	if (WARN_ON_ONCE(!desc))
	45	return NULL;
	46
	47	return desc->irq_2_iommu;
	48	}
	49
	50	static struct irq_2_iommu *irq_2_iommu_alloc_cpu(unsigned int irq, int cpu)
	51	{
	52	struct irq_desc *desc;
	53	struct irq_2_iommu *irq_iommu;
	54
	55	/*
	56	* alloc irq desc if not allocated already.
	57	*/
	58	desc = irq_to_desc_alloc_cpu(irq, cpu);
	59	if (!desc) {
	60	printk(KERN_INFO "can not get irq_desc for %d\n", irq);
	61	return NULL;
	62	}
	63
	64	irq_iommu = desc->irq_2_iommu;
	65
	66	if (!irq_iommu)
	67	desc->irq_2_iommu = get_one_free_irq_2_iommu(cpu);
	68
	69	return desc->irq_2_iommu;
	70	}
	71
	72	static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
	73	{
	74	return irq_2_iommu_alloc_cpu(irq, boot_cpu_id);
e420dfb4	75	}
d6c88a50	76
0b8f1efa YL	77	#else /* !CONFIG_SPARSE_IRQ */
	78
	79	static struct irq_2_iommu irq_2_iommuX[NR_IRQS];
	80
	81	static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
	82	{
	83	if (irq < nr_irqs)
	84	return &irq_2_iommuX[irq];
	85
	86	return NULL;
	87	}
e420dfb4 YL	88	static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
	89	{
	90	return irq_2_iommu(irq);
	91	}
0b8f1efa	92	#endif
b6fcb33a SS	93
	94	static DEFINE_SPINLOCK(irq_2_ir_lock);
	95
e420dfb4	96	static struct irq_2_iommu *valid_irq_2_iommu(unsigned int irq)
b6fcb33a	97	{
e420dfb4 YL	98	struct irq_2_iommu *irq_iommu;
	99
	100	irq_iommu = irq_2_iommu(irq);
b6fcb33a	101
e420dfb4 YL	102	if (!irq_iommu)
e420dfb4 YL	103	return NULL;
b6fcb33a	104
e420dfb4 YL	105	if (!irq_iommu->iommu)
e420dfb4 YL	106	return NULL;
b6fcb33a	107
e420dfb4 YL	108	return irq_iommu;
e420dfb4 YL	109	}
b6fcb33a	110
e420dfb4 YL	111	int irq_remapped(int irq)
	112	{
	113	return valid_irq_2_iommu(irq) != NULL;
b6fcb33a SS	114	}
	115
	116	int get_irte(int irq, struct irte *entry)
	117	{
	118	int index;
e420dfb4	119	struct irq_2_iommu *irq_iommu;
b6fcb33a	120
e420dfb4	121	if (!entry)
b6fcb33a SS	122	return -1;
	123
	124	spin_lock(&irq_2_ir_lock);
e420dfb4 YL	125	irq_iommu = valid_irq_2_iommu(irq);
e420dfb4 YL	126	if (!irq_iommu) {
b6fcb33a SS	127	spin_unlock(&irq_2_ir_lock);
	128	return -1;
	129	}
	130
e420dfb4 YL	131	index = irq_iommu->irte_index + irq_iommu->sub_handle;
e420dfb4 YL	132	entry = (irq_iommu->iommu->ir_table->base + index);
b6fcb33a SS	133
	134	spin_unlock(&irq_2_ir_lock);
	135	return 0;
	136	}
	137
	138	int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
	139	{
	140	struct ir_table *table = iommu->ir_table;
e420dfb4	141	struct irq_2_iommu *irq_iommu;
b6fcb33a SS	142	u16 index, start_index;
	143	unsigned int mask = 0;
	144	int i;
	145
	146	if (!count)
	147	return -1;
	148
0b8f1efa	149	#ifndef CONFIG_SPARSE_IRQ
e420dfb4 YL	150	/* protect irq_2_iommu_alloc later */
	151	if (irq >= nr_irqs)
	152	return -1;
0b8f1efa	153	#endif
e420dfb4	154
b6fcb33a SS	155	/*
	156	* start the IRTE search from index 0.
	157	*/
	158	index = start_index = 0;
	159
	160	if (count > 1) {
	161	count = __roundup_pow_of_two(count);
	162	mask = ilog2(count);
	163	}
	164
	165	if (mask > ecap_max_handle_mask(iommu->ecap)) {
	166	printk(KERN_ERR
	167	"Requested mask %x exceeds the max invalidation handle"
	168	" mask value %Lx\n", mask,
	169	ecap_max_handle_mask(iommu->ecap));
	170	return -1;
	171	}
	172
	173	spin_lock(&irq_2_ir_lock);
	174	do {
	175	for (i = index; i < index + count; i++)
	176	if (table->base[i].present)
	177	break;
	178	/* empty index found */
	179	if (i == index + count)
	180	break;
	181
	182	index = (index + count) % INTR_REMAP_TABLE_ENTRIES;
	183
	184	if (index == start_index) {
	185	spin_unlock(&irq_2_ir_lock);
	186	printk(KERN_ERR "can't allocate an IRTE\n");
	187	return -1;
	188	}
	189	} while (1);
	190
	191	for (i = index; i < index + count; i++)
	192	table->base[i].present = 1;
	193
e420dfb4	194	irq_iommu = irq_2_iommu_alloc(irq);
0b8f1efa YL	195	if (!irq_iommu) {
	196	spin_unlock(&irq_2_ir_lock);
	197	printk(KERN_ERR "can't allocate irq_2_iommu\n");
	198	return -1;
	199	}
	200
e420dfb4 YL	201	irq_iommu->iommu = iommu;
	202	irq_iommu->irte_index = index;
	203	irq_iommu->sub_handle = 0;
	204	irq_iommu->irte_mask = mask;
b6fcb33a SS	205
	206	spin_unlock(&irq_2_ir_lock);
	207
	208	return index;
	209	}
	210
704126ad	211	static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
b6fcb33a SS	212	{
	213	struct qi_desc desc;
	214
	215	desc.low = QI_IEC_IIDEX(index) \| QI_IEC_TYPE \| QI_IEC_IM(mask)
	216	\| QI_IEC_SELECTIVE;
	217	desc.high = 0;
	218
704126ad	219	return qi_submit_sync(&desc, iommu);
b6fcb33a SS	220	}
	221
	222	int map_irq_to_irte_handle(int irq, u16 *sub_handle)
	223	{
	224	int index;
e420dfb4	225	struct irq_2_iommu *irq_iommu;
b6fcb33a SS	226
b6fcb33a SS	227	spin_lock(&irq_2_ir_lock);
e420dfb4 YL	228	irq_iommu = valid_irq_2_iommu(irq);
e420dfb4 YL	229	if (!irq_iommu) {
b6fcb33a SS	230	spin_unlock(&irq_2_ir_lock);
	231	return -1;
	232	}
	233
e420dfb4 YL	234	*sub_handle = irq_iommu->sub_handle;
e420dfb4 YL	235	index = irq_iommu->irte_index;
b6fcb33a SS	236	spin_unlock(&irq_2_ir_lock);
	237	return index;
	238	}
	239
	240	int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
	241	{
e420dfb4 YL	242	struct irq_2_iommu *irq_iommu;
e420dfb4 YL	243
b6fcb33a	244	spin_lock(&irq_2_ir_lock);
b6fcb33a	245
7ddfb650	246	irq_iommu = irq_2_iommu_alloc(irq);
b6fcb33a	247
0b8f1efa YL	248	if (!irq_iommu) {
	249	spin_unlock(&irq_2_ir_lock);
	250	printk(KERN_ERR "can't allocate irq_2_iommu\n");
	251	return -1;
	252	}
	253
e420dfb4 YL	254	irq_iommu->iommu = iommu;
	255	irq_iommu->irte_index = index;
	256	irq_iommu->sub_handle = subhandle;
	257	irq_iommu->irte_mask = 0;
b6fcb33a SS	258
	259	spin_unlock(&irq_2_ir_lock);
	260
	261	return 0;
	262	}
	263
	264	int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index)
	265	{
e420dfb4 YL	266	struct irq_2_iommu *irq_iommu;
e420dfb4 YL	267
b6fcb33a	268	spin_lock(&irq_2_ir_lock);
e420dfb4 YL	269	irq_iommu = valid_irq_2_iommu(irq);
e420dfb4 YL	270	if (!irq_iommu) {
b6fcb33a SS	271	spin_unlock(&irq_2_ir_lock);
	272	return -1;
	273	}
	274
e420dfb4 YL	275	irq_iommu->iommu = NULL;
	276	irq_iommu->irte_index = 0;
	277	irq_iommu->sub_handle = 0;
	278	irq_2_iommu(irq)->irte_mask = 0;
b6fcb33a SS	279
	280	spin_unlock(&irq_2_ir_lock);
	281
	282	return 0;
	283	}
	284
	285	int modify_irte(int irq, struct irte *irte_modified)
	286	{
704126ad	287	int rc;
b6fcb33a SS	288	int index;
	289	struct irte *irte;
	290	struct intel_iommu *iommu;
e420dfb4	291	struct irq_2_iommu *irq_iommu;
b6fcb33a SS	292
b6fcb33a SS	293	spin_lock(&irq_2_ir_lock);
e420dfb4 YL	294	irq_iommu = valid_irq_2_iommu(irq);
e420dfb4 YL	295	if (!irq_iommu) {
b6fcb33a SS	296	spin_unlock(&irq_2_ir_lock);
	297	return -1;
	298	}
	299
e420dfb4	300	iommu = irq_iommu->iommu;
b6fcb33a	301
e420dfb4	302	index = irq_iommu->irte_index + irq_iommu->sub_handle;
b6fcb33a SS	303	irte = &iommu->ir_table->base[index];
	304
	305	set_64bit((unsigned long *)irte, irte_modified->low \| (1 << 1));
	306	__iommu_flush_cache(iommu, irte, sizeof(*irte));
	307
704126ad	308	rc = qi_flush_iec(iommu, index, 0);
b6fcb33a	309	spin_unlock(&irq_2_ir_lock);
704126ad YZ	310
704126ad YZ	311	return rc;
b6fcb33a SS	312	}
	313
	314	int flush_irte(int irq)
	315	{
704126ad	316	int rc;
b6fcb33a SS	317	int index;
b6fcb33a SS	318	struct intel_iommu *iommu;
e420dfb4	319	struct irq_2_iommu *irq_iommu;
b6fcb33a SS	320
b6fcb33a SS	321	spin_lock(&irq_2_ir_lock);
e420dfb4 YL	322	irq_iommu = valid_irq_2_iommu(irq);
e420dfb4 YL	323	if (!irq_iommu) {
b6fcb33a SS	324	spin_unlock(&irq_2_ir_lock);
	325	return -1;
	326	}
	327
e420dfb4	328	iommu = irq_iommu->iommu;
b6fcb33a	329
e420dfb4	330	index = irq_iommu->irte_index + irq_iommu->sub_handle;
b6fcb33a	331
704126ad	332	rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask);
b6fcb33a SS	333	spin_unlock(&irq_2_ir_lock);
b6fcb33a SS	334
704126ad	335	return rc;
b6fcb33a SS	336	}
b6fcb33a SS	337
89027d35 SS	338	struct intel_iommu *map_ioapic_to_ir(int apic)
	339	{
	340	int i;
	341
	342	for (i = 0; i < MAX_IO_APICS; i++)
	343	if (ir_ioapic[i].id == apic)
	344	return ir_ioapic[i].iommu;
	345	return NULL;
	346	}
	347
75c46fa6 SS	348	struct intel_iommu map_dev_to_ir(struct pci_dev dev)
	349	{
	350	struct dmar_drhd_unit *drhd;
	351
	352	drhd = dmar_find_matched_drhd_unit(dev);
	353	if (!drhd)
	354	return NULL;
	355
	356	return drhd->iommu;
	357	}
	358
b6fcb33a SS	359	int free_irte(int irq)
b6fcb33a SS	360	{
704126ad	361	int rc = 0;
b6fcb33a SS	362	int index, i;
	363	struct irte *irte;
	364	struct intel_iommu *iommu;
e420dfb4	365	struct irq_2_iommu *irq_iommu;
b6fcb33a SS	366
b6fcb33a SS	367	spin_lock(&irq_2_ir_lock);
e420dfb4 YL	368	irq_iommu = valid_irq_2_iommu(irq);
e420dfb4 YL	369	if (!irq_iommu) {
b6fcb33a SS	370	spin_unlock(&irq_2_ir_lock);
	371	return -1;
	372	}
	373
e420dfb4	374	iommu = irq_iommu->iommu;
b6fcb33a	375
e420dfb4	376	index = irq_iommu->irte_index + irq_iommu->sub_handle;
b6fcb33a SS	377	irte = &iommu->ir_table->base[index];
b6fcb33a SS	378
e420dfb4 YL	379	if (!irq_iommu->sub_handle) {
e420dfb4 YL	380	for (i = 0; i < (1 << irq_iommu->irte_mask); i++)
b6fcb33a	381	set_64bit((unsigned long *)irte, 0);
704126ad	382	rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask);
b6fcb33a SS	383	}
b6fcb33a SS	384
e420dfb4 YL	385	irq_iommu->iommu = NULL;
	386	irq_iommu->irte_index = 0;
	387	irq_iommu->sub_handle = 0;
	388	irq_iommu->irte_mask = 0;
b6fcb33a SS	389
	390	spin_unlock(&irq_2_ir_lock);
	391
704126ad	392	return rc;
b6fcb33a SS	393	}
b6fcb33a SS	394
2ae21010 SS	395	static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
	396	{
	397	u64 addr;
	398	u32 cmd, sts;
	399	unsigned long flags;
	400
	401	addr = virt_to_phys((void *)iommu->ir_table->base);
	402
	403	spin_lock_irqsave(&iommu->register_lock, flags);
	404
	405	dmar_writeq(iommu->reg + DMAR_IRTA_REG,
	406	(addr) \| IR_X2APIC_MODE(mode) \| INTR_REMAP_TABLE_REG_SIZE);
	407
	408	/* Set interrupt-remapping table pointer */
	409	cmd = iommu->gcmd \| DMA_GCMD_SIRTP;
	410	writel(cmd, iommu->reg + DMAR_GCMD_REG);
	411
	412	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
	413	readl, (sts & DMA_GSTS_IRTPS), sts);
	414	spin_unlock_irqrestore(&iommu->register_lock, flags);
	415
	416	/*
	417	* global invalidation of interrupt entry cache before enabling
	418	* interrupt-remapping.
	419	*/
	420	qi_global_iec(iommu);
	421
	422	spin_lock_irqsave(&iommu->register_lock, flags);
	423
	424	/* Enable interrupt-remapping */
	425	cmd = iommu->gcmd \| DMA_GCMD_IRE;
	426	iommu->gcmd \|= DMA_GCMD_IRE;
	427	writel(cmd, iommu->reg + DMAR_GCMD_REG);
	428
	429	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
	430	readl, (sts & DMA_GSTS_IRES), sts);
	431
	432	spin_unlock_irqrestore(&iommu->register_lock, flags);
	433	}
	434
	435
	436	static int setup_intr_remapping(struct intel_iommu *iommu, int mode)
	437	{
	438	struct ir_table *ir_table;
	439	struct page *pages;
	440
	441	ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table),
	442	GFP_KERNEL);
	443
	444	if (!iommu->ir_table)
	445	return -ENOMEM;
	446
	447	pages = alloc_pages(GFP_KERNEL \| __GFP_ZERO, INTR_REMAP_PAGE_ORDER);
	448
	449	if (!pages) {
	450	printk(KERN_ERR "failed to allocate pages of order %d\n",
	451	INTR_REMAP_PAGE_ORDER);
	452	kfree(iommu->ir_table);
	453	return -ENOMEM;
	454	}
	455
	456	ir_table->base = page_address(pages);
	457
	458	iommu_set_intr_remapping(iommu, mode);
459	return 0;
460	}
461
462	int __init enable_intr_remapping(int eim)
463	{
464	struct dmar_drhd_unit *drhd;
465	int setup = 0;
466
467	/*
468	* check for the Interrupt-remapping support
469	*/
470	for_each_drhd_unit(drhd) {
471	struct intel_iommu *iommu = drhd->iommu;
472
473	if (!ecap_ir_support(iommu->ecap))
474	continue;
475
476	if (eim && !ecap_eim_support(iommu->ecap)) {
477	printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
478	" ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
479	return -1;
480	}
481	}
482
483	/*
484	* Enable queued invalidation for all the DRHD's.
485	*/
486	for_each_drhd_unit(drhd) {
487	int ret;
488	struct intel_iommu *iommu = drhd->iommu;
489	ret = dmar_enable_qi(iommu);
490
491	if (ret) {
492	printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
493	" invalidation, ecap %Lx, ret %d\n",
494	drhd->reg_base_addr, iommu->ecap, ret);
495	return -1;
496	}
497	}
498
499	/*
500	* Setup Interrupt-remapping for all the DRHD's now.
501	*/
502	for_each_drhd_unit(drhd) {
503	struct intel_iommu *iommu = drhd->iommu;
504
505	if (!ecap_ir_support(iommu->ecap))
506	continue;
507
508	if (setup_intr_remapping(iommu, eim))
509	goto error;
510
511	setup = 1;
512	}
513
514	if (!setup)
515	goto error;
516
517	intr_remapping_enabled = 1;
518
519	return 0;
520
521	error:
522	/*
523	* handle error condition gracefully here!
524	*/
525	return -1;
526	}
ad3ad3f6 SS	527
	528	static int ir_parse_ioapic_scope(struct acpi_dmar_header *header,
	529	struct intel_iommu *iommu)
	530	{
	531	struct acpi_dmar_hardware_unit *drhd;
	532	struct acpi_dmar_device_scope *scope;
	533	void start, end;
	534
	535	drhd = (struct acpi_dmar_hardware_unit *)header;
	536
	537	start = (void *)(drhd + 1);
	538	end = ((void *)drhd) + header->length;
	539
	540	while (start < end) {
	541	scope = start;
	542	if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
	543	if (ir_ioapic_num == MAX_IO_APICS) {
	544	printk(KERN_WARNING "Exceeded Max IO APICS\n");
	545	return -1;
	546	}
	547
	548	printk(KERN_INFO "IOAPIC id %d under DRHD base"
	549	" 0x%Lx\n", scope->enumeration_id,
	550	drhd->address);
	551
	552	ir_ioapic[ir_ioapic_num].iommu = iommu;
	553	ir_ioapic[ir_ioapic_num].id = scope->enumeration_id;
	554	ir_ioapic_num++;
	555	}
	556	start += scope->length;
	557	}
	558
	559	return 0;
	560	}
	561
	562	/*
	563	* Finds the assocaition between IOAPIC's and its Interrupt-remapping
	564	* hardware unit.
	565	*/
	566	int __init parse_ioapics_under_ir(void)
	567	{
	568	struct dmar_drhd_unit *drhd;
	569	int ir_supported = 0;
	570
	571	for_each_drhd_unit(drhd) {
	572	struct intel_iommu *iommu = drhd->iommu;
	573
	574	if (ecap_ir_support(iommu->ecap)) {
	575	if (ir_parse_ioapic_scope(drhd->hdr, iommu))
	576	return -1;
	577
	578	ir_supported = 1;
	579	}
	580	}
	581
	582	if (ir_supported && ir_ioapic_num != nr_ioapics) {
	583	printk(KERN_WARNING
	584	"Not all IO-APIC's listed under remapping hardware\n");
	585	return -1;
	586	}
	587
	588	return ir_supported;
	589	}