x64, x2apic/intr-remap: Interrupt remapping infrastructure
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pci / intr_remapping.c
CommitLineData
ad3ad3f6 1#include <linux/dmar.h>
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2#include <linux/spinlock.h>
3#include <linux/jiffies.h>
4#include <linux/pci.h>
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5#include <asm/io_apic.h>
6#include "intel-iommu.h"
7#include "intr_remapping.h"
8
9static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
10static int ir_ioapic_num;
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11int intr_remapping_enabled;
12
13static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
14{
15 u64 addr;
16 u32 cmd, sts;
17 unsigned long flags;
18
19 addr = virt_to_phys((void *)iommu->ir_table->base);
20
21 spin_lock_irqsave(&iommu->register_lock, flags);
22
23 dmar_writeq(iommu->reg + DMAR_IRTA_REG,
24 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
25
26 /* Set interrupt-remapping table pointer */
27 cmd = iommu->gcmd | DMA_GCMD_SIRTP;
28 writel(cmd, iommu->reg + DMAR_GCMD_REG);
29
30 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
31 readl, (sts & DMA_GSTS_IRTPS), sts);
32 spin_unlock_irqrestore(&iommu->register_lock, flags);
33
34 /*
35 * global invalidation of interrupt entry cache before enabling
36 * interrupt-remapping.
37 */
38 qi_global_iec(iommu);
39
40 spin_lock_irqsave(&iommu->register_lock, flags);
41
42 /* Enable interrupt-remapping */
43 cmd = iommu->gcmd | DMA_GCMD_IRE;
44 iommu->gcmd |= DMA_GCMD_IRE;
45 writel(cmd, iommu->reg + DMAR_GCMD_REG);
46
47 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
48 readl, (sts & DMA_GSTS_IRES), sts);
49
50 spin_unlock_irqrestore(&iommu->register_lock, flags);
51}
52
53
54static int setup_intr_remapping(struct intel_iommu *iommu, int mode)
55{
56 struct ir_table *ir_table;
57 struct page *pages;
58
59 ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table),
60 GFP_KERNEL);
61
62 if (!iommu->ir_table)
63 return -ENOMEM;
64
65 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, INTR_REMAP_PAGE_ORDER);
66
67 if (!pages) {
68 printk(KERN_ERR "failed to allocate pages of order %d\n",
69 INTR_REMAP_PAGE_ORDER);
70 kfree(iommu->ir_table);
71 return -ENOMEM;
72 }
73
74 ir_table->base = page_address(pages);
75
76 iommu_set_intr_remapping(iommu, mode);
77 return 0;
78}
79
80int __init enable_intr_remapping(int eim)
81{
82 struct dmar_drhd_unit *drhd;
83 int setup = 0;
84
85 /*
86 * check for the Interrupt-remapping support
87 */
88 for_each_drhd_unit(drhd) {
89 struct intel_iommu *iommu = drhd->iommu;
90
91 if (!ecap_ir_support(iommu->ecap))
92 continue;
93
94 if (eim && !ecap_eim_support(iommu->ecap)) {
95 printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
96 " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
97 return -1;
98 }
99 }
100
101 /*
102 * Enable queued invalidation for all the DRHD's.
103 */
104 for_each_drhd_unit(drhd) {
105 int ret;
106 struct intel_iommu *iommu = drhd->iommu;
107 ret = dmar_enable_qi(iommu);
108
109 if (ret) {
110 printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
111 " invalidation, ecap %Lx, ret %d\n",
112 drhd->reg_base_addr, iommu->ecap, ret);
113 return -1;
114 }
115 }
116
117 /*
118 * Setup Interrupt-remapping for all the DRHD's now.
119 */
120 for_each_drhd_unit(drhd) {
121 struct intel_iommu *iommu = drhd->iommu;
122
123 if (!ecap_ir_support(iommu->ecap))
124 continue;
125
126 if (setup_intr_remapping(iommu, eim))
127 goto error;
128
129 setup = 1;
130 }
131
132 if (!setup)
133 goto error;
134
135 intr_remapping_enabled = 1;
136
137 return 0;
138
139error:
140 /*
141 * handle error condition gracefully here!
142 */
143 return -1;
144}
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145
146static int ir_parse_ioapic_scope(struct acpi_dmar_header *header,
147 struct intel_iommu *iommu)
148{
149 struct acpi_dmar_hardware_unit *drhd;
150 struct acpi_dmar_device_scope *scope;
151 void *start, *end;
152
153 drhd = (struct acpi_dmar_hardware_unit *)header;
154
155 start = (void *)(drhd + 1);
156 end = ((void *)drhd) + header->length;
157
158 while (start < end) {
159 scope = start;
160 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
161 if (ir_ioapic_num == MAX_IO_APICS) {
162 printk(KERN_WARNING "Exceeded Max IO APICS\n");
163 return -1;
164 }
165
166 printk(KERN_INFO "IOAPIC id %d under DRHD base"
167 " 0x%Lx\n", scope->enumeration_id,
168 drhd->address);
169
170 ir_ioapic[ir_ioapic_num].iommu = iommu;
171 ir_ioapic[ir_ioapic_num].id = scope->enumeration_id;
172 ir_ioapic_num++;
173 }
174 start += scope->length;
175 }
176
177 return 0;
178}
179
180/*
181 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
182 * hardware unit.
183 */
184int __init parse_ioapics_under_ir(void)
185{
186 struct dmar_drhd_unit *drhd;
187 int ir_supported = 0;
188
189 for_each_drhd_unit(drhd) {
190 struct intel_iommu *iommu = drhd->iommu;
191
192 if (ecap_ir_support(iommu->ecap)) {
193 if (ir_parse_ioapic_scope(drhd->hdr, iommu))
194 return -1;
195
196 ir_supported = 1;
197 }
198 }
199
200 if (ir_supported && ir_ioapic_num != nr_ioapics) {
201 printk(KERN_WARNING
202 "Not all IO-APIC's listed under remapping hardware\n");
203 return -1;
204 }
205
206 return ir_supported;
207}