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mmc: sdhci: add support for programmable clock mode
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
d129bceb 19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
11763609 21#include <linux/scatterlist.h>
9bea3c85 22#include <linux/regulator/consumer.h>
d129bceb 23
2f730fec
PO		 24#include <linux/leds.h>
25
22113efd 26#include <linux/mmc/mmc.h>
d129bceb 27#include <linux/mmc/host.h>
d129bceb 28
d129bceb
PO		 29#include "sdhci.h"
30
31#define DRIVER_NAME "sdhci"
d129bceb 32
d129bceb 33#define DBG(f, x...) \
c6563178 34 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 35
f9134319
PO		 36#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
37 defined(CONFIG_MMC_SDHCI_MODULE))
38#define SDHCI_USE_LEDS_CLASS
39#endif
40
b513ea25
AN		 41#define MAX_TUNING_LOOP 40
42
df673b22 43static unsigned int debug_quirks = 0;
67435274 44
d129bceb
PO		 45static void sdhci_finish_data(struct sdhci_host *);
46
47static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
48static void sdhci_finish_command(struct sdhci_host *);
49
50static void sdhci_dumpregs(struct sdhci_host *host)
51{
412ab659
PR		 52 printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
53 mmc_hostname(host->mmc));
d129bceb
PO		 54
55 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 56 sdhci_readl(host, SDHCI_DMA_ADDRESS),
57 sdhci_readw(host, SDHCI_HOST_VERSION));
d129bceb 58 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 59 sdhci_readw(host, SDHCI_BLOCK_SIZE),
60 sdhci_readw(host, SDHCI_BLOCK_COUNT));
d129bceb 61 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 62 sdhci_readl(host, SDHCI_ARGUMENT),
63 sdhci_readw(host, SDHCI_TRANSFER_MODE));
d129bceb 64 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 65 sdhci_readl(host, SDHCI_PRESENT_STATE),
66 sdhci_readb(host, SDHCI_HOST_CONTROL));
d129bceb 67 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 68 sdhci_readb(host, SDHCI_POWER_CONTROL),
69 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
d129bceb 70 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 71 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
72 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
d129bceb 73 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 74 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
75 sdhci_readl(host, SDHCI_INT_STATUS));
d129bceb 76 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 77 sdhci_readl(host, SDHCI_INT_ENABLE),
78 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
d129bceb 79 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 80 sdhci_readw(host, SDHCI_ACMD12_ERR),
81 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
e8120ad1 82 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 83 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1
PR		 84 sdhci_readl(host, SDHCI_CAPABILITIES_1));
85 printk(KERN_DEBUG DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
86 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 87 sdhci_readl(host, SDHCI_MAX_CURRENT));
f2119df6
AN		 88 printk(KERN_DEBUG DRIVER_NAME ": Host ctl2: 0x%08x\n",
89 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 90
be3f4ae0
BD		 91 if (host->flags & SDHCI_USE_ADMA)
92 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
93 readl(host->ioaddr + SDHCI_ADMA_ERROR),
94 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
95
d129bceb
PO		 96 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
97}
98
99/*****************************************************************************\
100 * *
101 * Low level functions *
102 * *
103\*****************************************************************************/
104
7260cf5e
AV		 105static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
106{
107 u32 ier;
108
109 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
110 ier &= ~clear;
111 ier |= set;
112 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
113 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
114}
115
116static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
117{
118 sdhci_clear_set_irqs(host, 0, irqs);
119}
120
121static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
122{
123 sdhci_clear_set_irqs(host, irqs, 0);
124}
125
126static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
127{
128 u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
129
68d1fb7e
AV		 130 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
131 return;
132
7260cf5e
AV		 133 if (enable)
134 sdhci_unmask_irqs(host, irqs);
135 else
136 sdhci_mask_irqs(host, irqs);
137}
138
139static void sdhci_enable_card_detection(struct sdhci_host *host)
140{
141 sdhci_set_card_detection(host, true);
142}
143
144static void sdhci_disable_card_detection(struct sdhci_host *host)
145{
146 sdhci_set_card_detection(host, false);
147}
148
d129bceb
PO		 149static void sdhci_reset(struct sdhci_host *host, u8 mask)
150{
e16514d8 151 unsigned long timeout;
063a9dbb 152 u32 uninitialized_var(ier);
e16514d8 153
b8c86fc5 154 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 155 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 156 SDHCI_CARD_PRESENT))
157 return;
158 }
159
063a9dbb
AV		 160 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
161 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
162
393c1a34
PR		 163 if (host->ops->platform_reset_enter)
164 host->ops->platform_reset_enter(host, mask);
165
4e4141a5 166 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 167
e16514d8 168 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 169 host->clock = 0;
170
e16514d8
PO		 171 /* Wait max 100 ms */
172 timeout = 100;
173
174 /* hw clears the bit when it's done */
4e4141a5 175 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 176 if (timeout == 0) {
acf1da45 177 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
e16514d8
PO		 178 mmc_hostname(host->mmc), (int)mask);
179 sdhci_dumpregs(host);
180 return;
181 }
182 timeout--;
183 mdelay(1);
d129bceb 184 }
063a9dbb 185
393c1a34
PR		 186 if (host->ops->platform_reset_exit)
187 host->ops->platform_reset_exit(host, mask);
188
063a9dbb
AV		 189 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
190 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
d129bceb
PO		 191}
192
2f4cbb3d
NP		 193static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
194
195static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 196{
2f4cbb3d
NP		 197 if (soft)
198 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
199 else
200 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 201
7260cf5e
AV		 202 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
203 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 204 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
205 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 206 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
2f4cbb3d
NP		 207
208 if (soft) {
209 /* force clock reconfiguration */
210 host->clock = 0;
211 sdhci_set_ios(host->mmc, &host->mmc->ios);
212 }
7260cf5e 213}
d129bceb 214
7260cf5e
AV		 215static void sdhci_reinit(struct sdhci_host *host)
216{
2f4cbb3d 217 sdhci_init(host, 0);
7260cf5e 218 sdhci_enable_card_detection(host);
d129bceb
PO		 219}
220
221static void sdhci_activate_led(struct sdhci_host *host)
222{
223 u8 ctrl;
224
4e4141a5 225 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 226 ctrl |= SDHCI_CTRL_LED;
4e4141a5 227 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 228}
229
230static void sdhci_deactivate_led(struct sdhci_host *host)
231{
232 u8 ctrl;
233
4e4141a5 234 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 235 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 236 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 237}
238
f9134319 239#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 240static void sdhci_led_control(struct led_classdev *led,
241 enum led_brightness brightness)
242{
243 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
244 unsigned long flags;
245
246 spin_lock_irqsave(&host->lock, flags);
247
248 if (brightness == LED_OFF)
249 sdhci_deactivate_led(host);
250 else
251 sdhci_activate_led(host);
252
253 spin_unlock_irqrestore(&host->lock, flags);
254}
255#endif
256
d129bceb
PO		 257/*****************************************************************************\
258 * *
259 * Core functions *
260 * *
261\*****************************************************************************/
262
a406f5a3 263static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 264{
7659150c
PO		 265 unsigned long flags;
266 size_t blksize, len, chunk;
7244b85b 267 u32 uninitialized_var(scratch);
7659150c 268 u8 *buf;
d129bceb 269
a406f5a3 270 DBG("PIO reading\n");
d129bceb 271
a406f5a3 272 blksize = host->data->blksz;
7659150c 273 chunk = 0;
d129bceb 274
7659150c 275 local_irq_save(flags);
d129bceb 276
a406f5a3 277 while (blksize) {
7659150c
PO		 278 if (!sg_miter_next(&host->sg_miter))
279 BUG();
d129bceb 280
7659150c 281 len = min(host->sg_miter.length, blksize);
d129bceb 282
7659150c
PO		 283 blksize -= len;
284 host->sg_miter.consumed = len;
14d836e7 285
7659150c 286 buf = host->sg_miter.addr;
d129bceb 287
7659150c
PO		 288 while (len) {
289 if (chunk == 0) {
4e4141a5 290 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 291 chunk = 4;
a406f5a3 292 }
7659150c
PO		 293
294 *buf = scratch & 0xFF;
295
296 buf++;
297 scratch >>= 8;
298 chunk--;
299 len--;
d129bceb 300 }
a406f5a3 301 }
7659150c
PO		 302
303 sg_miter_stop(&host->sg_miter);
304
305 local_irq_restore(flags);
a406f5a3 306}
d129bceb 307
a406f5a3
PO		 308static void sdhci_write_block_pio(struct sdhci_host *host)
309{
7659150c
PO		 310 unsigned long flags;
311 size_t blksize, len, chunk;
312 u32 scratch;
313 u8 *buf;
d129bceb 314
a406f5a3
PO		 315 DBG("PIO writing\n");
316
317 blksize = host->data->blksz;
7659150c
PO		 318 chunk = 0;
319 scratch = 0;
d129bceb 320
7659150c 321 local_irq_save(flags);
d129bceb 322
a406f5a3 323 while (blksize) {
7659150c
PO		 324 if (!sg_miter_next(&host->sg_miter))
325 BUG();
a406f5a3 326
7659150c
PO		 327 len = min(host->sg_miter.length, blksize);
328
329 blksize -= len;
330 host->sg_miter.consumed = len;
331
332 buf = host->sg_miter.addr;
d129bceb 333
7659150c
PO		 334 while (len) {
335 scratch |= (u32)*buf << (chunk * 8);
336
337 buf++;
338 chunk++;
339 len--;
340
341 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 342 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 343 chunk = 0;
344 scratch = 0;
d129bceb 345 }
d129bceb
PO		 346 }
347 }
7659150c
PO		 348
349 sg_miter_stop(&host->sg_miter);
350
351 local_irq_restore(flags);
a406f5a3
PO		 352}
353
354static void sdhci_transfer_pio(struct sdhci_host *host)
355{
356 u32 mask;
357
358 BUG_ON(!host->data);
359
7659150c 360 if (host->blocks == 0)
a406f5a3
PO		 361 return;
362
363 if (host->data->flags & MMC_DATA_READ)
364 mask = SDHCI_DATA_AVAILABLE;
365 else
366 mask = SDHCI_SPACE_AVAILABLE;
367
4a3cba32
PO		 368 /*
369 * Some controllers (JMicron JMB38x) mess up the buffer bits
370 * for transfers < 4 bytes. As long as it is just one block,
371 * we can ignore the bits.
372 */
373 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
374 (host->data->blocks == 1))
375 mask = ~0;
376
4e4141a5 377 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 378 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
379 udelay(100);
380
a406f5a3
PO		 381 if (host->data->flags & MMC_DATA_READ)
382 sdhci_read_block_pio(host);
383 else
384 sdhci_write_block_pio(host);
d129bceb 385
7659150c
PO		 386 host->blocks--;
387 if (host->blocks == 0)
a406f5a3 388 break;
a406f5a3 389 }
d129bceb 390
a406f5a3 391 DBG("PIO transfer complete.\n");
d129bceb
PO		 392}
393
2134a922
PO		 394static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
395{
396 local_irq_save(*flags);
397 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
398}
399
400static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
401{
402 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
403 local_irq_restore(*flags);
404}
405
118cd17d
BD		 406static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
407{
9e506f35
BD		 408 __le32 *dataddr = (__le32 __force *)(desc + 4);
409 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 410
9e506f35
BD		 411 /* SDHCI specification says ADMA descriptors should be 4 byte
412 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 413
9e506f35
BD		 414 cmdlen[0] = cpu_to_le16(cmd);
415 cmdlen[1] = cpu_to_le16(len);
416
417 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 418}
419
8f1934ce 420static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 421 struct mmc_data *data)
422{
423 int direction;
424
425 u8 *desc;
426 u8 *align;
427 dma_addr_t addr;
428 dma_addr_t align_addr;
429 int len, offset;
430
431 struct scatterlist *sg;
432 int i;
433 char *buffer;
434 unsigned long flags;
435
436 /*
437 * The spec does not specify endianness of descriptor table.
438 * We currently guess that it is LE.
439 */
440
441 if (data->flags & MMC_DATA_READ)
442 direction = DMA_FROM_DEVICE;
443 else
444 direction = DMA_TO_DEVICE;
445
446 /*
447 * The ADMA descriptor table is mapped further down as we
448 * need to fill it with data first.
449 */
450
451 host->align_addr = dma_map_single(mmc_dev(host->mmc),
452 host->align_buffer, 128 * 4, direction);
8d8bb39b 453 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 454 goto fail;
2134a922
PO		 455 BUG_ON(host->align_addr & 0x3);
456
457 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
458 data->sg, data->sg_len, direction);
8f1934ce
PO		 459 if (host->sg_count == 0)
460 goto unmap_align;
2134a922
PO		 461
462 desc = host->adma_desc;
463 align = host->align_buffer;
464
465 align_addr = host->align_addr;
466
467 for_each_sg(data->sg, sg, host->sg_count, i) {
468 addr = sg_dma_address(sg);
469 len = sg_dma_len(sg);
470
471 /*
472 * The SDHCI specification states that ADMA
473 * addresses must be 32-bit aligned. If they
474 * aren't, then we use a bounce buffer for
475 * the (up to three) bytes that screw up the
476 * alignment.
477 */
478 offset = (4 - (addr & 0x3)) & 0x3;
479 if (offset) {
480 if (data->flags & MMC_DATA_WRITE) {
481 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 482 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 483 memcpy(align, buffer, offset);
484 sdhci_kunmap_atomic(buffer, &flags);
485 }
486
118cd17d
BD		 487 /* tran, valid */
488 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 489
490 BUG_ON(offset > 65536);
491
2134a922
PO		 492 align += 4;
493 align_addr += 4;
494
495 desc += 8;
496
497 addr += offset;
498 len -= offset;
499 }
500
2134a922
PO		 501 BUG_ON(len > 65536);
502
118cd17d
BD		 503 /* tran, valid */
504 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 505 desc += 8;
506
507 /*
508 * If this triggers then we have a calculation bug
509 * somewhere. :/
510 */
511 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
512 }
513
70764a90
TA		 514 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
515 /*
516 * Mark the last descriptor as the terminating descriptor
517 */
518 if (desc != host->adma_desc) {
519 desc -= 8;
520 desc[0] |= 0x2; /* end */
521 }
522 } else {
523 /*
524 * Add a terminating entry.
525 */
2134a922 526
70764a90
TA		 527 /* nop, end, valid */
528 sdhci_set_adma_desc(desc, 0, 0, 0x3);
529 }
2134a922
PO		 530
531 /*
532 * Resync align buffer as we might have changed it.
533 */
534 if (data->flags & MMC_DATA_WRITE) {
535 dma_sync_single_for_device(mmc_dev(host->mmc),
536 host->align_addr, 128 * 4, direction);
537 }
538
539 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
540 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 541 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 542 goto unmap_entries;
2134a922 543 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 544
545 return 0;
546
547unmap_entries:
548 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
549 data->sg_len, direction);
550unmap_align:
551 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
552 128 * 4, direction);
553fail:
554 return -EINVAL;
2134a922
PO		 555}
556
557static void sdhci_adma_table_post(struct sdhci_host *host,
558 struct mmc_data *data)
559{
560 int direction;
561
562 struct scatterlist *sg;
563 int i, size;
564 u8 *align;
565 char *buffer;
566 unsigned long flags;
567
568 if (data->flags & MMC_DATA_READ)
569 direction = DMA_FROM_DEVICE;
570 else
571 direction = DMA_TO_DEVICE;
572
573 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
574 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
575
576 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
577 128 * 4, direction);
578
579 if (data->flags & MMC_DATA_READ) {
580 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
581 data->sg_len, direction);
582
583 align = host->align_buffer;
584
585 for_each_sg(data->sg, sg, host->sg_count, i) {
586 if (sg_dma_address(sg) & 0x3) {
587 size = 4 - (sg_dma_address(sg) & 0x3);
588
589 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 590 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 591 memcpy(buffer, align, size);
592 sdhci_kunmap_atomic(buffer, &flags);
593
594 align += 4;
595 }
596 }
597 }
598
599 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
600 data->sg_len, direction);
601}
602
a3c7778f 603static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 604{
1c8cde92 605 u8 count;
a3c7778f 606 struct mmc_data *data = cmd->data;
1c8cde92 607 unsigned target_timeout, current_timeout;
d129bceb 608
ee53ab5d
PO		 609 /*
610 * If the host controller provides us with an incorrect timeout
611 * value, just skip the check and use 0xE. The hardware may take
612 * longer to time out, but that's much better than having a too-short
613 * timeout value.
614 */
11a2f1b7 615 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 616 return 0xE;
e538fbe8 617
a3c7778f
AW		 618 /* Unspecified timeout, assume max */
619 if (!data && !cmd->cmd_timeout_ms)
620 return 0xE;
d129bceb 621
a3c7778f
AW		 622 /* timeout in us */
623 if (!data)
624 target_timeout = cmd->cmd_timeout_ms * 1000;
625 else
626 target_timeout = data->timeout_ns / 1000 +
627 data->timeout_clks / host->clock;
81b39802 628
4b01681c
MB		 629 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
630 host->timeout_clk = host->clock / 1000;
631
1c8cde92
PO		 632 /*
633 * Figure out needed cycles.
634 * We do this in steps in order to fit inside a 32 bit int.
635 * The first step is the minimum timeout, which will have a
636 * minimum resolution of 6 bits:
637 * (1) 2^13*1000 > 2^22,
638 * (2) host->timeout_clk < 2^16
639 * =>
640 * (1) / (2) > 2^6
641 */
4b01681c 642 BUG_ON(!host->timeout_clk);
1c8cde92
PO		 643 count = 0;
644 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
645 while (current_timeout < target_timeout) {
646 count++;
647 current_timeout <<= 1;
648 if (count >= 0xF)
649 break;
650 }
651
652 if (count >= 0xF) {
a3c7778f
AW		 653 printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n",
654 mmc_hostname(host->mmc), cmd->opcode);
1c8cde92
PO		 655 count = 0xE;
656 }
657
ee53ab5d
PO		 658 return count;
659}
660
6aa943ab
AV		 661static void sdhci_set_transfer_irqs(struct sdhci_host *host)
662{
663 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
664 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
665
666 if (host->flags & SDHCI_REQ_USE_DMA)
667 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
668 else
669 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
670}
671
a3c7778f 672static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 673{
674 u8 count;
2134a922 675 u8 ctrl;
a3c7778f 676 struct mmc_data *data = cmd->data;
8f1934ce 677 int ret;
ee53ab5d
PO		 678
679 WARN_ON(host->data);
680
a3c7778f
AW		 681 if (data || (cmd->flags & MMC_RSP_BUSY)) {
682 count = sdhci_calc_timeout(host, cmd);
683 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
684 }
685
686 if (!data)
ee53ab5d
PO		 687 return;
688
689 /* Sanity checks */
690 BUG_ON(data->blksz * data->blocks > 524288);
691 BUG_ON(data->blksz > host->mmc->max_blk_size);
692 BUG_ON(data->blocks > 65535);
693
694 host->data = data;
695 host->data_early = 0;
f6a03cbf 696 host->data->bytes_xfered = 0;
ee53ab5d 697
a13abc7b 698 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 699 host->flags |= SDHCI_REQ_USE_DMA;
700
2134a922
PO		 701 /*
702 * FIXME: This doesn't account for merging when mapping the
703 * scatterlist.
704 */
705 if (host->flags & SDHCI_REQ_USE_DMA) {
706 int broken, i;
707 struct scatterlist *sg;
708
709 broken = 0;
710 if (host->flags & SDHCI_USE_ADMA) {
711 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
712 broken = 1;
713 } else {
714 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
715 broken = 1;
716 }
717
718 if (unlikely(broken)) {
719 for_each_sg(data->sg, sg, data->sg_len, i) {
720 if (sg->length & 0x3) {
721 DBG("Reverting to PIO because of "
722 "transfer size (%d)\n",
723 sg->length);
724 host->flags &= ~SDHCI_REQ_USE_DMA;
725 break;
726 }
727 }
728 }
c9fddbc4
PO		 729 }
730
731 /*
732 * The assumption here being that alignment is the same after
733 * translation to device address space.
734 */
2134a922
PO		 735 if (host->flags & SDHCI_REQ_USE_DMA) {
736 int broken, i;
737 struct scatterlist *sg;
738
739 broken = 0;
740 if (host->flags & SDHCI_USE_ADMA) {
741 /*
742 * As we use 3 byte chunks to work around
743 * alignment problems, we need to check this
744 * quirk.
745 */
746 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
747 broken = 1;
748 } else {
749 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
750 broken = 1;
751 }
752
753 if (unlikely(broken)) {
754 for_each_sg(data->sg, sg, data->sg_len, i) {
755 if (sg->offset & 0x3) {
756 DBG("Reverting to PIO because of "
757 "bad alignment\n");
758 host->flags &= ~SDHCI_REQ_USE_DMA;
759 break;
760 }
761 }
762 }
763 }
764
8f1934ce
PO		 765 if (host->flags & SDHCI_REQ_USE_DMA) {
766 if (host->flags & SDHCI_USE_ADMA) {
767 ret = sdhci_adma_table_pre(host, data);
768 if (ret) {
769 /*
770 * This only happens when someone fed
771 * us an invalid request.
772 */
773 WARN_ON(1);
ebd6d357 774 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 775 } else {
4e4141a5
AV		 776 sdhci_writel(host, host->adma_addr,
777 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 778 }
779 } else {
c8b3e02e 780 int sg_cnt;
8f1934ce 781
c8b3e02e 782 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 783 data->sg, data->sg_len,
784 (data->flags & MMC_DATA_READ) ?
785 DMA_FROM_DEVICE :
786 DMA_TO_DEVICE);
c8b3e02e 787 if (sg_cnt == 0) {
8f1934ce
PO		 788 /*
789 * This only happens when someone fed
790 * us an invalid request.
791 */
792 WARN_ON(1);
ebd6d357 793 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 794 } else {
719a61b4 795 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 796 sdhci_writel(host, sg_dma_address(data->sg),
797 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 798 }
799 }
800 }
801
2134a922
PO		 802 /*
803 * Always adjust the DMA selection as some controllers
804 * (e.g. JMicron) can't do PIO properly when the selection
805 * is ADMA.
806 */
807 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 808 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 809 ctrl &= ~SDHCI_CTRL_DMA_MASK;
810 if ((host->flags & SDHCI_REQ_USE_DMA) &&
811 (host->flags & SDHCI_USE_ADMA))
812 ctrl |= SDHCI_CTRL_ADMA32;
813 else
814 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 815 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 816 }
817
8f1934ce 818 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 819 int flags;
820
821 flags = SG_MITER_ATOMIC;
822 if (host->data->flags & MMC_DATA_READ)
823 flags |= SG_MITER_TO_SG;
824 else
825 flags |= SG_MITER_FROM_SG;
826 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 827 host->blocks = data->blocks;
d129bceb 828 }
c7fa9963 829
6aa943ab
AV		 830 sdhci_set_transfer_irqs(host);
831
f6a03cbf
MV		 832 /* Set the DMA boundary value and block size */
833 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
834 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 835 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 836}
837
838static void sdhci_set_transfer_mode(struct sdhci_host *host,
839 struct mmc_data *data)
840{
841 u16 mode;
842
c7fa9963
PO		 843 if (data == NULL)
844 return;
845
e538fbe8
PO		 846 WARN_ON(!host->data);
847
c7fa9963 848 mode = SDHCI_TRNS_BLK_CNT_EN;
c4512f79
JH		 849 if (data->blocks > 1) {
850 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
851 mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12;
852 else
853 mode |= SDHCI_TRNS_MULTI;
854 }
c7fa9963
PO		 855 if (data->flags & MMC_DATA_READ)
856 mode |= SDHCI_TRNS_READ;
c9fddbc4 857 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 858 mode |= SDHCI_TRNS_DMA;
859
4e4141a5 860 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 861}
862
863static void sdhci_finish_data(struct sdhci_host *host)
864{
865 struct mmc_data *data;
d129bceb
PO		 866
867 BUG_ON(!host->data);
868
869 data = host->data;
870 host->data = NULL;
871
c9fddbc4 872 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 873 if (host->flags & SDHCI_USE_ADMA)
874 sdhci_adma_table_post(host, data);
875 else {
876 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
877 data->sg_len, (data->flags & MMC_DATA_READ) ?
878 DMA_FROM_DEVICE : DMA_TO_DEVICE);
879 }
d129bceb
PO		 880 }
881
882 /*
c9b74c5b
PO		 883 * The specification states that the block count register must
884 * be updated, but it does not specify at what point in the
885 * data flow. That makes the register entirely useless to read
886 * back so we have to assume that nothing made it to the card
887 * in the event of an error.
d129bceb 888 */
c9b74c5b
PO		 889 if (data->error)
890 data->bytes_xfered = 0;
d129bceb 891 else
c9b74c5b 892 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 893
d129bceb
PO		 894 if (data->stop) {
895 /*
896 * The controller needs a reset of internal state machines
897 * upon error conditions.
898 */
17b0429d 899 if (data->error) {
d129bceb
PO		 900 sdhci_reset(host, SDHCI_RESET_CMD);
901 sdhci_reset(host, SDHCI_RESET_DATA);
902 }
903
904 sdhci_send_command(host, data->stop);
905 } else
906 tasklet_schedule(&host->finish_tasklet);
907}
908
909static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
910{
911 int flags;
fd2208d7 912 u32 mask;
7cb2c76f 913 unsigned long timeout;
d129bceb
PO		 914
915 WARN_ON(host->cmd);
916
d129bceb 917 /* Wait max 10 ms */
7cb2c76f 918 timeout = 10;
fd2208d7
PO		 919
920 mask = SDHCI_CMD_INHIBIT;
921 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
922 mask |= SDHCI_DATA_INHIBIT;
923
924 /* We shouldn't wait for data inihibit for stop commands, even
925 though they might use busy signaling */
926 if (host->mrq->data && (cmd == host->mrq->data->stop))
927 mask &= ~SDHCI_DATA_INHIBIT;
928
4e4141a5 929 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 930 if (timeout == 0) {
d129bceb 931 printk(KERN_ERR "%s: Controller never released "
acf1da45 932 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 933 sdhci_dumpregs(host);
17b0429d 934 cmd->error = -EIO;
d129bceb
PO		 935 tasklet_schedule(&host->finish_tasklet);
936 return;
937 }
7cb2c76f
PO		 938 timeout--;
939 mdelay(1);
940 }
d129bceb
PO		 941
942 mod_timer(&host->timer, jiffies + 10 * HZ);
943
944 host->cmd = cmd;
945
a3c7778f 946 sdhci_prepare_data(host, cmd);
d129bceb 947
4e4141a5 948 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 949
c7fa9963
PO		 950 sdhci_set_transfer_mode(host, cmd->data);
951
d129bceb 952 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
acf1da45 953 printk(KERN_ERR "%s: Unsupported response type!\n",
d129bceb 954 mmc_hostname(host->mmc));
17b0429d 955 cmd->error = -EINVAL;
d129bceb
PO		 956 tasklet_schedule(&host->finish_tasklet);
957 return;
958 }
959
960 if (!(cmd->flags & MMC_RSP_PRESENT))
961 flags = SDHCI_CMD_RESP_NONE;
962 else if (cmd->flags & MMC_RSP_136)
963 flags = SDHCI_CMD_RESP_LONG;
964 else if (cmd->flags & MMC_RSP_BUSY)
965 flags = SDHCI_CMD_RESP_SHORT_BUSY;
966 else
967 flags = SDHCI_CMD_RESP_SHORT;
968
969 if (cmd->flags & MMC_RSP_CRC)
970 flags |= SDHCI_CMD_CRC;
971 if (cmd->flags & MMC_RSP_OPCODE)
972 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 973
974 /* CMD19 is special in that the Data Present Select should be set */
975 if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
d129bceb
PO		 976 flags |= SDHCI_CMD_DATA;
977
4e4141a5 978 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 979}
980
981static void sdhci_finish_command(struct sdhci_host *host)
982{
983 int i;
984
985 BUG_ON(host->cmd == NULL);
986
987 if (host->cmd->flags & MMC_RSP_PRESENT) {
988 if (host->cmd->flags & MMC_RSP_136) {
989 /* CRC is stripped so we need to do some shifting. */
990 for (i = 0;i < 4;i++) {
4e4141a5 991 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 992 SDHCI_RESPONSE + (3-i)*4) << 8;
993 if (i != 3)
994 host->cmd->resp[i] |=
4e4141a5 995 sdhci_readb(host,
d129bceb
PO		 996 SDHCI_RESPONSE + (3-i)*4-1);
997 }
998 } else {
4e4141a5 999 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1000 }
1001 }
1002
17b0429d 1003 host->cmd->error = 0;
d129bceb 1004
e538fbe8
PO		 1005 if (host->data && host->data_early)
1006 sdhci_finish_data(host);
1007
1008 if (!host->cmd->data)
d129bceb
PO		 1009 tasklet_schedule(&host->finish_tasklet);
1010
1011 host->cmd = NULL;
1012}
1013
1014static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1015{
c3ed3877
AN		 1016 int div = 0; /* Initialized for compiler warning */
1017 u16 clk = 0;
7cb2c76f 1018 unsigned long timeout;
d129bceb
PO		 1019
1020 if (clock == host->clock)
1021 return;
1022
8114634c
AV		 1023 if (host->ops->set_clock) {
1024 host->ops->set_clock(host, clock);
1025 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1026 return;
1027 }
1028
4e4141a5 1029 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1030
1031 if (clock == 0)
1032 goto out;
1033
85105c53 1034 if (host->version >= SDHCI_SPEC_300) {
c3ed3877
AN		 1035 /*
1036 * Check if the Host Controller supports Programmable Clock
1037 * Mode.
1038 */
1039 if (host->clk_mul) {
1040 u16 ctrl;
1041
1042 /*
1043 * We need to figure out whether the Host Driver needs
1044 * to select Programmable Clock Mode, or the value can
1045 * be set automatically by the Host Controller based on
1046 * the Preset Value registers.
1047 */
1048 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1049 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1050 for (div = 1; div <= 1024; div++) {
1051 if (((host->max_clk * host->clk_mul) /
1052 div) <= clock)
1053 break;
1054 }
1055 /*
1056 * Set Programmable Clock Mode in the Clock
1057 * Control register.
1058 */
1059 clk = SDHCI_PROG_CLOCK_MODE;
1060 div--;
1061 }
1062 } else {
1063 /* Version 3.00 divisors must be a multiple of 2. */
1064 if (host->max_clk <= clock)
1065 div = 1;
1066 else {
1067 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1068 div += 2) {
1069 if ((host->max_clk / div) <= clock)
1070 break;
1071 }
85105c53 1072 }
c3ed3877 1073 div >>= 1;
85105c53
ZG		 1074 }
1075 } else {
1076 /* Version 2.00 divisors must be a power of 2. */
0397526d 1077 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1078 if ((host->max_clk / div) <= clock)
1079 break;
1080 }
c3ed3877 1081 div >>= 1;
d129bceb 1082 }
d129bceb 1083
c3ed3877 1084 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1085 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1086 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1087 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1088 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1089
27f6cb16
CB		 1090 /* Wait max 20 ms */
1091 timeout = 20;
4e4141a5 1092 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1093 & SDHCI_CLOCK_INT_STABLE)) {
1094 if (timeout == 0) {
acf1da45
PO		 1095 printk(KERN_ERR "%s: Internal clock never "
1096 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1097 sdhci_dumpregs(host);
1098 return;
1099 }
7cb2c76f
PO		 1100 timeout--;
1101 mdelay(1);
1102 }
d129bceb
PO		 1103
1104 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1105 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1106
1107out:
1108 host->clock = clock;
1109}
1110
146ad66e
PO		 1111static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1112{
8364248a 1113 u8 pwr = 0;
146ad66e 1114
8364248a 1115 if (power != (unsigned short)-1) {
ae628903
PO		 1116 switch (1 << power) {
1117 case MMC_VDD_165_195:
1118 pwr = SDHCI_POWER_180;
1119 break;
1120 case MMC_VDD_29_30:
1121 case MMC_VDD_30_31:
1122 pwr = SDHCI_POWER_300;
1123 break;
1124 case MMC_VDD_32_33:
1125 case MMC_VDD_33_34:
1126 pwr = SDHCI_POWER_330;
1127 break;
1128 default:
1129 BUG();
1130 }
1131 }
1132
1133 if (host->pwr == pwr)
146ad66e
PO		 1134 return;
1135
ae628903
PO		 1136 host->pwr = pwr;
1137
1138 if (pwr == 0) {
4e4141a5 1139 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
ae628903 1140 return;
9e9dc5f2
DS		 1141 }
1142
1143 /*
1144 * Spec says that we should clear the power reg before setting
1145 * a new value. Some controllers don't seem to like this though.
1146 */
b8c86fc5 1147 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1148 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1149
e08c1694 1150 /*
c71f6512 1151 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1152 * and set turn on power at the same time, so set the voltage first.
1153 */
11a2f1b7 1154 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1155 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1156
ae628903 1157 pwr |= SDHCI_POWER_ON;
146ad66e 1158
ae628903 1159 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697
HW		 1160
1161 /*
1162 * Some controllers need an extra 10ms delay of 10ms before they
1163 * can apply clock after applying power
1164 */
11a2f1b7 1165 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1166 mdelay(10);
146ad66e
PO		 1167}
1168
d129bceb
PO		 1169/*****************************************************************************\
1170 * *
1171 * MMC callbacks *
1172 * *
1173\*****************************************************************************/
1174
1175static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1176{
1177 struct sdhci_host *host;
68d1fb7e 1178 bool present;
d129bceb
PO		 1179 unsigned long flags;
1180
1181 host = mmc_priv(mmc);
1182
1183 spin_lock_irqsave(&host->lock, flags);
1184
1185 WARN_ON(host->mrq != NULL);
1186
f9134319 1187#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1188 sdhci_activate_led(host);
2f730fec 1189#endif
c4512f79
JH		 1190 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) {
1191 if (mrq->stop) {
1192 mrq->data->stop = NULL;
1193 mrq->stop = NULL;
1194 }
1195 }
d129bceb
PO		 1196
1197 host->mrq = mrq;
1198
68d1fb7e
AV		 1199 /* If polling, assume that the card is always present. */
1200 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1201 present = true;
1202 else
1203 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1204 SDHCI_CARD_PRESENT;
1205
1206 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1207 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1208 tasklet_schedule(&host->finish_tasklet);
1209 } else
1210 sdhci_send_command(host, mrq->cmd);
1211
5f25a66f 1212 mmiowb();
d129bceb
PO		 1213 spin_unlock_irqrestore(&host->lock, flags);
1214}
1215
1216static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1217{
1218 struct sdhci_host *host;
1219 unsigned long flags;
1220 u8 ctrl;
1221
1222 host = mmc_priv(mmc);
1223
1224 spin_lock_irqsave(&host->lock, flags);
1225
1e72859e
PO		 1226 if (host->flags & SDHCI_DEVICE_DEAD)
1227 goto out;
1228
d129bceb
PO		 1229 /*
1230 * Reset the chip on each power off.
1231 * Should clear out any weird states.
1232 */
1233 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1234 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1235 sdhci_reinit(host);
d129bceb
PO		 1236 }
1237
1238 sdhci_set_clock(host, ios->clock);
1239
1240 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 1241 sdhci_set_power(host, -1);
d129bceb 1242 else
146ad66e 1243 sdhci_set_power(host, ios->vdd);
d129bceb 1244
643a81ff
PR		 1245 if (host->ops->platform_send_init_74_clocks)
1246 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1247
15ec4461
PR		 1248 /*
1249 * If your platform has 8-bit width support but is not a v3 controller,
1250 * or if it requires special setup code, you should implement that in
1251 * platform_8bit_width().
1252 */
1253 if (host->ops->platform_8bit_width)
1254 host->ops->platform_8bit_width(host, ios->bus_width);
1255 else {
1256 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1257 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1258 ctrl &= ~SDHCI_CTRL_4BITBUS;
1259 if (host->version >= SDHCI_SPEC_300)
1260 ctrl |= SDHCI_CTRL_8BITBUS;
1261 } else {
1262 if (host->version >= SDHCI_SPEC_300)
1263 ctrl &= ~SDHCI_CTRL_8BITBUS;
1264 if (ios->bus_width == MMC_BUS_WIDTH_4)
1265 ctrl |= SDHCI_CTRL_4BITBUS;
1266 else
1267 ctrl &= ~SDHCI_CTRL_4BITBUS;
1268 }
1269 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1270 }
ae6d6c92 1271
15ec4461 1272 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1273
3ab9c8da
PR		 1274 if ((ios->timing == MMC_TIMING_SD_HS ||
1275 ios->timing == MMC_TIMING_MMC_HS)
1276 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1277 ctrl |= SDHCI_CTRL_HISPD;
1278 else
1279 ctrl &= ~SDHCI_CTRL_HISPD;
1280
d6d50a15 1281 if (host->version >= SDHCI_SPEC_300) {
49c468fc
AN		 1282 u16 clk, ctrl_2;
1283 unsigned int clock;
1284
1285 /* In case of UHS-I modes, set High Speed Enable */
1286 if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
1287 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1288 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1289 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1290 (ios->timing == MMC_TIMING_UHS_SDR12))
1291 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1292
1293 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1294 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1295 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1296 /*
1297 * We only need to set Driver Strength if the
1298 * preset value enable is not set.
1299 */
1300 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1301 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1302 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1303 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1304 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1305
1306 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1307 } else {
1308 /*
1309 * According to SDHC Spec v3.00, if the Preset Value
1310 * Enable in the Host Control 2 register is set, we
1311 * need to reset SD Clock Enable before changing High
1312 * Speed Enable to avoid generating clock gliches.
1313 */
758535c4
AN		 1314
1315 /* Reset SD Clock Enable */
1316 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1317 clk &= ~SDHCI_CLOCK_CARD_EN;
1318 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1319
1320 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1321
1322 /* Re-enable SD Clock */
1323 clock = host->clock;
1324 host->clock = 0;
1325 sdhci_set_clock(host, clock);
d6d50a15 1326 }
49c468fc
AN		 1327
1328 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1329
1330 /* Select Bus Speed Mode for host */
1331 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1332 if (ios->timing == MMC_TIMING_UHS_SDR12)
1333 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1334 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1335 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1336 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1337 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1338 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1339 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1340 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1341 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1342
1343 /* Reset SD Clock Enable */
1344 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1345 clk &= ~SDHCI_CLOCK_CARD_EN;
1346 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1347
1348 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1349
1350 /* Re-enable SD Clock */
1351 clock = host->clock;
1352 host->clock = 0;
1353 sdhci_set_clock(host, clock);
758535c4
AN		 1354 } else
1355 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1356
b8352260
LD		 1357 /*
1358 * Some (ENE) controllers go apeshit on some ios operation,
1359 * signalling timeout and CRC errors even on CMD0. Resetting
1360 * it on each ios seems to solve the problem.
1361 */
b8c86fc5 1362 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1363 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1364
1e72859e 1365out:
5f25a66f 1366 mmiowb();
d129bceb
PO		 1367 spin_unlock_irqrestore(&host->lock, flags);
1368}
1369
82b0e23a 1370static int check_ro(struct sdhci_host *host)
d129bceb 1371{
d129bceb 1372 unsigned long flags;
2dfb579c 1373 int is_readonly;
d129bceb 1374
d129bceb
PO		 1375 spin_lock_irqsave(&host->lock, flags);
1376
1e72859e 1377 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1378 is_readonly = 0;
1379 else if (host->ops->get_ro)
1380 is_readonly = host->ops->get_ro(host);
1e72859e 1381 else
2dfb579c
WS		 1382 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1383 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1384
1385 spin_unlock_irqrestore(&host->lock, flags);
1386
2dfb579c
WS		 1387 /* This quirk needs to be replaced by a callback-function later */
1388 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1389 !is_readonly : is_readonly;
d129bceb
PO		 1390}
1391
82b0e23a
TI		 1392#define SAMPLE_COUNT 5
1393
1394static int sdhci_get_ro(struct mmc_host *mmc)
1395{
1396 struct sdhci_host *host;
1397 int i, ro_count;
1398
1399 host = mmc_priv(mmc);
1400
1401 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1402 return check_ro(host);
1403
1404 ro_count = 0;
1405 for (i = 0; i < SAMPLE_COUNT; i++) {
1406 if (check_ro(host)) {
1407 if (++ro_count > SAMPLE_COUNT / 2)
1408 return 1;
1409 }
1410 msleep(30);
1411 }
1412 return 0;
1413}
1414
f75979b7
PO		 1415static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1416{
1417 struct sdhci_host *host;
1418 unsigned long flags;
f75979b7
PO		 1419
1420 host = mmc_priv(mmc);
1421
1422 spin_lock_irqsave(&host->lock, flags);
1423
1e72859e
PO		 1424 if (host->flags & SDHCI_DEVICE_DEAD)
1425 goto out;
1426
f75979b7 1427 if (enable)
7260cf5e
AV		 1428 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1429 else
1430 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1431out:
f75979b7
PO		 1432 mmiowb();
1433
1434 spin_unlock_irqrestore(&host->lock, flags);
1435}
1436
f2119df6
AN		 1437static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1438 struct mmc_ios *ios)
1439{
1440 struct sdhci_host *host;
1441 u8 pwr;
1442 u16 clk, ctrl;
1443 u32 present_state;
1444
1445 host = mmc_priv(mmc);
1446
1447 /*
1448 * Signal Voltage Switching is only applicable for Host Controllers
1449 * v3.00 and above.
1450 */
1451 if (host->version < SDHCI_SPEC_300)
1452 return 0;
1453
1454 /*
1455 * We first check whether the request is to set signalling voltage
1456 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1457 */
1458 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1459 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1460 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1461 ctrl &= ~SDHCI_CTRL_VDD_180;
1462 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1463
1464 /* Wait for 5ms */
1465 usleep_range(5000, 5500);
1466
1467 /* 3.3V regulator output should be stable within 5 ms */
1468 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1469 if (!(ctrl & SDHCI_CTRL_VDD_180))
1470 return 0;
1471 else {
1472 printk(KERN_INFO DRIVER_NAME ": Switching to 3.3V "
1473 "signalling voltage failed\n");
1474 return -EIO;
1475 }
1476 } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1477 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1478 /* Stop SDCLK */
1479 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1480 clk &= ~SDHCI_CLOCK_CARD_EN;
1481 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1482
1483 /* Check whether DAT[3:0] is 0000 */
1484 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1485 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1486 SDHCI_DATA_LVL_SHIFT)) {
1487 /*
1488 * Enable 1.8V Signal Enable in the Host Control2
1489 * register
1490 */
1491 ctrl |= SDHCI_CTRL_VDD_180;
1492 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1493
1494 /* Wait for 5ms */
1495 usleep_range(5000, 5500);
1496
1497 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1498 if (ctrl & SDHCI_CTRL_VDD_180) {
1499 /* Provide SDCLK again and wait for 1ms*/
1500 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1501 clk |= SDHCI_CLOCK_CARD_EN;
1502 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1503 usleep_range(1000, 1500);
1504
1505 /*
1506 * If DAT[3:0] level is 1111b, then the card
1507 * was successfully switched to 1.8V signaling.
1508 */
1509 present_state = sdhci_readl(host,
1510 SDHCI_PRESENT_STATE);
1511 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1512 SDHCI_DATA_LVL_MASK)
1513 return 0;
1514 }
1515 }
1516
1517 /*
1518 * If we are here, that means the switch to 1.8V signaling
1519 * failed. We power cycle the card, and retry initialization
1520 * sequence by setting S18R to 0.
1521 */
1522 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1523 pwr &= ~SDHCI_POWER_ON;
1524 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1525
1526 /* Wait for 1ms as per the spec */
1527 usleep_range(1000, 1500);
1528 pwr |= SDHCI_POWER_ON;
1529 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1530
1531 printk(KERN_INFO DRIVER_NAME ": Switching to 1.8V signalling "
1532 "voltage failed, retrying with S18R set to 0\n");
1533 return -EAGAIN;
1534 } else
1535 /* No signal voltage switch required */
1536 return 0;
1537}
1538
b513ea25
AN		 1539static int sdhci_execute_tuning(struct mmc_host *mmc)
1540{
1541 struct sdhci_host *host;
1542 u16 ctrl;
1543 u32 ier;
1544 int tuning_loop_counter = MAX_TUNING_LOOP;
1545 unsigned long timeout;
1546 int err = 0;
1547
1548 host = mmc_priv(mmc);
1549
1550 disable_irq(host->irq);
1551 spin_lock(&host->lock);
1552
1553 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1554
1555 /*
1556 * Host Controller needs tuning only in case of SDR104 mode
1557 * and for SDR50 mode when Use Tuning for SDR50 is set in
1558 * Capabilities register.
1559 */
1560 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1561 (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1562 (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
1563 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1564 else {
1565 spin_unlock(&host->lock);
1566 enable_irq(host->irq);
1567 return 0;
1568 }
1569
1570 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1571
1572 /*
1573 * As per the Host Controller spec v3.00, tuning command
1574 * generates Buffer Read Ready interrupt, so enable that.
1575 *
1576 * Note: The spec clearly says that when tuning sequence
1577 * is being performed, the controller does not generate
1578 * interrupts other than Buffer Read Ready interrupt. But
1579 * to make sure we don't hit a controller bug, we _only_
1580 * enable Buffer Read Ready interrupt here.
1581 */
1582 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1583 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1584
1585 /*
1586 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1587 * of loops reaches 40 times or a timeout of 150ms occurs.
1588 */
1589 timeout = 150;
1590 do {
1591 struct mmc_command cmd = {0};
1592 struct mmc_request mrq = {0};
1593
1594 if (!tuning_loop_counter && !timeout)
1595 break;
1596
1597 cmd.opcode = MMC_SEND_TUNING_BLOCK;
1598 cmd.arg = 0;
1599 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1600 cmd.retries = 0;
1601 cmd.data = NULL;
1602 cmd.error = 0;
1603
1604 mrq.cmd = &cmd;
1605 host->mrq = &mrq;
1606
1607 /*
1608 * In response to CMD19, the card sends 64 bytes of tuning
1609 * block to the Host Controller. So we set the block size
1610 * to 64 here.
1611 */
1612 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
1613
1614 /*
1615 * The tuning block is sent by the card to the host controller.
1616 * So we set the TRNS_READ bit in the Transfer Mode register.
1617 * This also takes care of setting DMA Enable and Multi Block
1618 * Select in the same register to 0.
1619 */
1620 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1621
1622 sdhci_send_command(host, &cmd);
1623
1624 host->cmd = NULL;
1625 host->mrq = NULL;
1626
1627 spin_unlock(&host->lock);
1628 enable_irq(host->irq);
1629
1630 /* Wait for Buffer Read Ready interrupt */
1631 wait_event_interruptible_timeout(host->buf_ready_int,
1632 (host->tuning_done == 1),
1633 msecs_to_jiffies(50));
1634 disable_irq(host->irq);
1635 spin_lock(&host->lock);
1636
1637 if (!host->tuning_done) {
1638 printk(KERN_INFO DRIVER_NAME ": Timeout waiting for "
1639 "Buffer Read Ready interrupt during tuning "
1640 "procedure, falling back to fixed sampling "
1641 "clock\n");
1642 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1643 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1644 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1645 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1646
1647 err = -EIO;
1648 goto out;
1649 }
1650
1651 host->tuning_done = 0;
1652
1653 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1654 tuning_loop_counter--;
1655 timeout--;
1656 mdelay(1);
1657 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1658
1659 /*
1660 * The Host Driver has exhausted the maximum number of loops allowed,
1661 * so use fixed sampling frequency.
1662 */
1663 if (!tuning_loop_counter || !timeout) {
1664 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1665 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1666 } else {
1667 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1668 printk(KERN_INFO DRIVER_NAME ": Tuning procedure"
1669 " failed, falling back to fixed sampling"
1670 " clock\n");
1671 err = -EIO;
1672 }
1673 }
1674
1675out:
1676 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1677 spin_unlock(&host->lock);
1678 enable_irq(host->irq);
1679
1680 return err;
1681}
1682
4d55c5a1
AN		 1683static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1684{
1685 struct sdhci_host *host;
1686 u16 ctrl;
1687 unsigned long flags;
1688
1689 host = mmc_priv(mmc);
1690
1691 /* Host Controller v3.00 defines preset value registers */
1692 if (host->version < SDHCI_SPEC_300)
1693 return;
1694
1695 spin_lock_irqsave(&host->lock, flags);
1696
1697 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1698
1699 /*
1700 * We only enable or disable Preset Value if they are not already
1701 * enabled or disabled respectively. Otherwise, we bail out.
1702 */
1703 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1704 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1705 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1706 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1707 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1708 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1709 }
1710
1711 spin_unlock_irqrestore(&host->lock, flags);
1712}
1713
ab7aefd0 1714static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 1715 .request = sdhci_request,
1716 .set_ios = sdhci_set_ios,
1717 .get_ro = sdhci_get_ro,
f75979b7 1718 .enable_sdio_irq = sdhci_enable_sdio_irq,
f2119df6 1719 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b513ea25 1720 .execute_tuning = sdhci_execute_tuning,
4d55c5a1 1721 .enable_preset_value = sdhci_enable_preset_value,
d129bceb
PO		 1722};
1723
1724/*****************************************************************************\
1725 * *
1726 * Tasklets *
1727 * *
1728\*****************************************************************************/
1729
1730static void sdhci_tasklet_card(unsigned long param)
1731{
1732 struct sdhci_host *host;
1733 unsigned long flags;
1734
1735 host = (struct sdhci_host*)param;
1736
1737 spin_lock_irqsave(&host->lock, flags);
1738
4e4141a5 1739 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
d129bceb
PO		 1740 if (host->mrq) {
1741 printk(KERN_ERR "%s: Card removed during transfer!\n",
1742 mmc_hostname(host->mmc));
1743 printk(KERN_ERR "%s: Resetting controller.\n",
1744 mmc_hostname(host->mmc));
1745
1746 sdhci_reset(host, SDHCI_RESET_CMD);
1747 sdhci_reset(host, SDHCI_RESET_DATA);
1748
17b0429d 1749 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1750 tasklet_schedule(&host->finish_tasklet);
1751 }
1752 }
1753
1754 spin_unlock_irqrestore(&host->lock, flags);
1755
04cf585d 1756 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 1757}
1758
1759static void sdhci_tasklet_finish(unsigned long param)
1760{
1761 struct sdhci_host *host;
1762 unsigned long flags;
1763 struct mmc_request *mrq;
1764
1765 host = (struct sdhci_host*)param;
1766
0c9c99a7
CB		 1767 /*
1768 * If this tasklet gets rescheduled while running, it will
1769 * be run again afterwards but without any active request.
1770 */
1771 if (!host->mrq)
1772 return;
1773
d129bceb
PO		 1774 spin_lock_irqsave(&host->lock, flags);
1775
1776 del_timer(&host->timer);
1777
1778 mrq = host->mrq;
1779
d129bceb
PO		 1780 /*
1781 * The controller needs a reset of internal state machines
1782 * upon error conditions.
1783 */
1e72859e 1784 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 1785 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 1786 (mrq->data && (mrq->data->error ||
1787 (mrq->data->stop && mrq->data->stop->error))) ||
1788 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 1789
1790 /* Some controllers need this kick or reset won't work here */
b8c86fc5 1791 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
645289dc
PO		 1792 unsigned int clock;
1793
1794 /* This is to force an update */
1795 clock = host->clock;
1796 host->clock = 0;
1797 sdhci_set_clock(host, clock);
1798 }
1799
1800 /* Spec says we should do both at the same time, but Ricoh
1801 controllers do not like that. */
d129bceb
PO		 1802 sdhci_reset(host, SDHCI_RESET_CMD);
1803 sdhci_reset(host, SDHCI_RESET_DATA);
1804 }
1805
1806 host->mrq = NULL;
1807 host->cmd = NULL;
1808 host->data = NULL;
1809
f9134319 1810#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1811 sdhci_deactivate_led(host);
2f730fec 1812#endif
d129bceb 1813
5f25a66f 1814 mmiowb();
d129bceb
PO		 1815 spin_unlock_irqrestore(&host->lock, flags);
1816
1817 mmc_request_done(host->mmc, mrq);
1818}
1819
1820static void sdhci_timeout_timer(unsigned long data)
1821{
1822 struct sdhci_host *host;
1823 unsigned long flags;
1824
1825 host = (struct sdhci_host*)data;
1826
1827 spin_lock_irqsave(&host->lock, flags);
1828
1829 if (host->mrq) {
acf1da45
PO		 1830 printk(KERN_ERR "%s: Timeout waiting for hardware "
1831 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1832 sdhci_dumpregs(host);
1833
1834 if (host->data) {
17b0429d 1835 host->data->error = -ETIMEDOUT;
d129bceb
PO		 1836 sdhci_finish_data(host);
1837 } else {
1838 if (host->cmd)
17b0429d 1839 host->cmd->error = -ETIMEDOUT;
d129bceb 1840 else
17b0429d 1841 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 1842
1843 tasklet_schedule(&host->finish_tasklet);
1844 }
1845 }
1846
5f25a66f 1847 mmiowb();
d129bceb
PO		 1848 spin_unlock_irqrestore(&host->lock, flags);
1849}
1850
1851/*****************************************************************************\
1852 * *
1853 * Interrupt handling *
1854 * *
1855\*****************************************************************************/
1856
1857static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1858{
1859 BUG_ON(intmask == 0);
1860
1861 if (!host->cmd) {
b67ac3f3
PO		 1862 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1863 "though no command operation was in progress.\n",
1864 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1865 sdhci_dumpregs(host);
1866 return;
1867 }
1868
43b58b36 1869 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 1870 host->cmd->error = -ETIMEDOUT;
1871 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1872 SDHCI_INT_INDEX))
1873 host->cmd->error = -EILSEQ;
43b58b36 1874
e809517f 1875 if (host->cmd->error) {
d129bceb 1876 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 1877 return;
1878 }
1879
1880 /*
1881 * The host can send and interrupt when the busy state has
1882 * ended, allowing us to wait without wasting CPU cycles.
1883 * Unfortunately this is overloaded on the "data complete"
1884 * interrupt, so we need to take some care when handling
1885 * it.
1886 *
1887 * Note: The 1.0 specification is a bit ambiguous about this
1888 * feature so there might be some problems with older
1889 * controllers.
1890 */
1891 if (host->cmd->flags & MMC_RSP_BUSY) {
1892 if (host->cmd->data)
1893 DBG("Cannot wait for busy signal when also "
1894 "doing a data transfer");
f945405c 1895 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 1896 return;
f945405c
BD		 1897
1898 /* The controller does not support the end-of-busy IRQ,
1899 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 1900 }
1901
1902 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 1903 sdhci_finish_command(host);
d129bceb
PO		 1904}
1905
0957c333 1906#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 1907static void sdhci_show_adma_error(struct sdhci_host *host)
1908{
1909 const char *name = mmc_hostname(host->mmc);
1910 u8 *desc = host->adma_desc;
1911 __le32 *dma;
1912 __le16 *len;
1913 u8 attr;
1914
1915 sdhci_dumpregs(host);
1916
1917 while (true) {
1918 dma = (__le32 *)(desc + 4);
1919 len = (__le16 *)(desc + 2);
1920 attr = *desc;
1921
1922 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
1923 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
1924
1925 desc += 8;
1926
1927 if (attr & 2)
1928 break;
1929 }
1930}
1931#else
1932static void sdhci_show_adma_error(struct sdhci_host *host) { }
1933#endif
1934
d129bceb
PO		 1935static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1936{
1937 BUG_ON(intmask == 0);
1938
b513ea25
AN		 1939 /* CMD19 generates _only_ Buffer Read Ready interrupt */
1940 if (intmask & SDHCI_INT_DATA_AVAIL) {
1941 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
1942 MMC_SEND_TUNING_BLOCK) {
1943 host->tuning_done = 1;
1944 wake_up(&host->buf_ready_int);
1945 return;
1946 }
1947 }
1948
d129bceb
PO		 1949 if (!host->data) {
1950 /*
e809517f
PO		 1951 * The "data complete" interrupt is also used to
1952 * indicate that a busy state has ended. See comment
1953 * above in sdhci_cmd_irq().
d129bceb 1954 */
e809517f
PO		 1955 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1956 if (intmask & SDHCI_INT_DATA_END) {
1957 sdhci_finish_command(host);
1958 return;
1959 }
1960 }
d129bceb 1961
b67ac3f3
PO		 1962 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1963 "though no data operation was in progress.\n",
1964 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1965 sdhci_dumpregs(host);
1966
1967 return;
1968 }
1969
1970 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 1971 host->data->error = -ETIMEDOUT;
22113efd
AL		 1972 else if (intmask & SDHCI_INT_DATA_END_BIT)
1973 host->data->error = -EILSEQ;
1974 else if ((intmask & SDHCI_INT_DATA_CRC) &&
1975 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
1976 != MMC_BUS_TEST_R)
17b0429d 1977 host->data->error = -EILSEQ;
6882a8c0
BD		 1978 else if (intmask & SDHCI_INT_ADMA_ERROR) {
1979 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
1980 sdhci_show_adma_error(host);
2134a922 1981 host->data->error = -EIO;
6882a8c0 1982 }
d129bceb 1983
17b0429d 1984 if (host->data->error)
d129bceb
PO		 1985 sdhci_finish_data(host);
1986 else {
a406f5a3 1987 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 1988 sdhci_transfer_pio(host);
1989
6ba736a1
PO		 1990 /*
1991 * We currently don't do anything fancy with DMA
1992 * boundaries, but as we can't disable the feature
1993 * we need to at least restart the transfer.
f6a03cbf
MV		 1994 *
1995 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
1996 * should return a valid address to continue from, but as
1997 * some controllers are faulty, don't trust them.
6ba736a1 1998 */
f6a03cbf
MV		 1999 if (intmask & SDHCI_INT_DMA_END) {
2000 u32 dmastart, dmanow;
2001 dmastart = sg_dma_address(host->data->sg);
2002 dmanow = dmastart + host->data->bytes_xfered;
2003 /*
2004 * Force update to the next DMA block boundary.
2005 */
2006 dmanow = (dmanow &
2007 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2008 SDHCI_DEFAULT_BOUNDARY_SIZE;
2009 host->data->bytes_xfered = dmanow - dmastart;
2010 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2011 " next 0x%08x\n",
2012 mmc_hostname(host->mmc), dmastart,
2013 host->data->bytes_xfered, dmanow);
2014 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2015 }
6ba736a1 2016
e538fbe8
PO		 2017 if (intmask & SDHCI_INT_DATA_END) {
2018 if (host->cmd) {
2019 /*
2020 * Data managed to finish before the
2021 * command completed. Make sure we do
2022 * things in the proper order.
2023 */
2024 host->data_early = 1;
2025 } else {
2026 sdhci_finish_data(host);
2027 }
2028 }
d129bceb
PO		 2029 }
2030}
2031
7d12e780 2032static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 2033{
2034 irqreturn_t result;
2035 struct sdhci_host* host = dev_id;
2036 u32 intmask;
f75979b7 2037 int cardint = 0;
d129bceb
PO		 2038
2039 spin_lock(&host->lock);
2040
4e4141a5 2041 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 2042
62df67a5 2043 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2044 result = IRQ_NONE;
2045 goto out;
2046 }
2047
b69c9058
PO		 2048 DBG("*** %s got interrupt: 0x%08x\n",
2049 mmc_hostname(host->mmc), intmask);
d129bceb 2050
3192a28f 2051 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
4e4141a5
AV		 2052 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2053 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
d129bceb 2054 tasklet_schedule(&host->card_tasklet);
3192a28f 2055 }
d129bceb 2056
3192a28f 2057 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 2058
3192a28f 2059 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 2060 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2061 SDHCI_INT_STATUS);
3192a28f 2062 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 2063 }
2064
2065 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 2066 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2067 SDHCI_INT_STATUS);
3192a28f 2068 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 2069 }
2070
2071 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2072
964f9ce2
PO		 2073 intmask &= ~SDHCI_INT_ERROR;
2074
d129bceb 2075 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 2076 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 2077 mmc_hostname(host->mmc));
4e4141a5 2078 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 2079 }
2080
9d26a5d3 2081 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 2082
f75979b7
PO		 2083 if (intmask & SDHCI_INT_CARD_INT)
2084 cardint = 1;
2085
2086 intmask &= ~SDHCI_INT_CARD_INT;
2087
3192a28f 2088 if (intmask) {
acf1da45 2089 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
3192a28f 2090 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 2091 sdhci_dumpregs(host);
2092
4e4141a5 2093 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 2094 }
d129bceb
PO		 2095
2096 result = IRQ_HANDLED;
2097
5f25a66f 2098 mmiowb();
d129bceb
PO		 2099out:
2100 spin_unlock(&host->lock);
2101
f75979b7
PO		 2102 /*
2103 * We have to delay this as it calls back into the driver.
2104 */
2105 if (cardint)
2106 mmc_signal_sdio_irq(host->mmc);
2107
d129bceb
PO		 2108 return result;
2109}
2110
2111/*****************************************************************************\
2112 * *
2113 * Suspend/resume *
2114 * *
2115\*****************************************************************************/
2116
2117#ifdef CONFIG_PM
2118
b8c86fc5 2119int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
d129bceb 2120{
b8c86fc5 2121 int ret;
a715dfc7 2122
7260cf5e
AV		 2123 sdhci_disable_card_detection(host);
2124
1a13f8fa 2125 ret = mmc_suspend_host(host->mmc);
b8c86fc5
PO		 2126 if (ret)
2127 return ret;
a715dfc7 2128
b8c86fc5 2129 free_irq(host->irq, host);
d129bceb 2130
9bea3c85
MS		 2131 if (host->vmmc)
2132 ret = regulator_disable(host->vmmc);
2133
2134 return ret;
d129bceb
PO		 2135}
2136
b8c86fc5 2137EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2138
b8c86fc5
PO		 2139int sdhci_resume_host(struct sdhci_host *host)
2140{
2141 int ret;
d129bceb 2142
9bea3c85
MS		 2143 if (host->vmmc) {
2144 int ret = regulator_enable(host->vmmc);
2145 if (ret)
2146 return ret;
2147 }
2148
2149
a13abc7b 2150 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2151 if (host->ops->enable_dma)
2152 host->ops->enable_dma(host);
2153 }
d129bceb 2154
b8c86fc5
PO		 2155 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2156 mmc_hostname(host->mmc), host);
df1c4b7b
PO		 2157 if (ret)
2158 return ret;
d129bceb 2159
2f4cbb3d 2160 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
b8c86fc5
PO		 2161 mmiowb();
2162
2163 ret = mmc_resume_host(host->mmc);
7260cf5e
AV		 2164 sdhci_enable_card_detection(host);
2165
2f4cbb3d 2166 return ret;
d129bceb
PO		 2167}
2168
b8c86fc5 2169EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb 2170
5f619704
DD		 2171void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2172{
2173 u8 val;
2174 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2175 val |= SDHCI_WAKE_ON_INT;
2176 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2177}
2178
2179EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2180
d129bceb
PO		 2181#endif /* CONFIG_PM */
2182
2183/*****************************************************************************\
2184 * *
b8c86fc5 2185 * Device allocation/registration *
d129bceb
PO		 2186 * *
2187\*****************************************************************************/
2188
b8c86fc5
PO		 2189struct sdhci_host *sdhci_alloc_host(struct device *dev,
2190 size_t priv_size)
d129bceb 2191{
d129bceb
PO		 2192 struct mmc_host *mmc;
2193 struct sdhci_host *host;
2194
b8c86fc5 2195 WARN_ON(dev == NULL);
d129bceb 2196
b8c86fc5 2197 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2198 if (!mmc)
b8c86fc5 2199 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2200
2201 host = mmc_priv(mmc);
2202 host->mmc = mmc;
2203
b8c86fc5
PO		 2204 return host;
2205}
8a4da143 2206
b8c86fc5 2207EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2208
b8c86fc5
PO		 2209int sdhci_add_host(struct sdhci_host *host)
2210{
2211 struct mmc_host *mmc;
f2119df6
AN		 2212 u32 caps[2];
2213 u32 max_current_caps;
2214 unsigned int ocr_avail;
b8c86fc5 2215 int ret;
d129bceb 2216
b8c86fc5
PO		 2217 WARN_ON(host == NULL);
2218 if (host == NULL)
2219 return -EINVAL;
d129bceb 2220
b8c86fc5 2221 mmc = host->mmc;
d129bceb 2222
b8c86fc5
PO		 2223 if (debug_quirks)
2224 host->quirks = debug_quirks;
d129bceb 2225
d96649ed
PO		 2226 sdhci_reset(host, SDHCI_RESET_ALL);
2227
4e4141a5 2228 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2229 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2230 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2231 if (host->version > SDHCI_SPEC_300) {
4a965505 2232 printk(KERN_ERR "%s: Unknown controller version (%d). "
b69c9058 2233 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2234 host->version);
4a965505
PO		 2235 }
2236
f2119df6 2237 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2238 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2239
f2119df6
AN		 2240 caps[1] = (host->version >= SDHCI_SPEC_300) ?
2241 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2242
b8c86fc5 2243 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2244 host->flags |= SDHCI_USE_SDMA;
f2119df6 2245 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2246 DBG("Controller doesn't have SDMA capability\n");
67435274 2247 else
a13abc7b 2248 host->flags |= SDHCI_USE_SDMA;
d129bceb 2249
b8c86fc5 2250 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2251 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2252 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2253 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2254 }
2255
f2119df6
AN		 2256 if ((host->version >= SDHCI_SPEC_200) &&
2257 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2258 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2259
2260 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2261 (host->flags & SDHCI_USE_ADMA)) {
2262 DBG("Disabling ADMA as it is marked broken\n");
2263 host->flags &= ~SDHCI_USE_ADMA;
2264 }
2265
a13abc7b 2266 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2267 if (host->ops->enable_dma) {
2268 if (host->ops->enable_dma(host)) {
2269 printk(KERN_WARNING "%s: No suitable DMA "
2270 "available. Falling back to PIO.\n",
2271 mmc_hostname(mmc));
a13abc7b
RR		 2272 host->flags &=
2273 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2274 }
d129bceb
PO		 2275 }
2276 }
2277
2134a922
PO		 2278 if (host->flags & SDHCI_USE_ADMA) {
2279 /*
2280 * We need to allocate descriptors for all sg entries
2281 * (128) and potentially one alignment transfer for
2282 * each of those entries.
2283 */
2284 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2285 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2286 if (!host->adma_desc || !host->align_buffer) {
2287 kfree(host->adma_desc);
2288 kfree(host->align_buffer);
2289 printk(KERN_WARNING "%s: Unable to allocate ADMA "
2290 "buffers. Falling back to standard DMA.\n",
2291 mmc_hostname(mmc));
2292 host->flags &= ~SDHCI_USE_ADMA;
2293 }
2294 }
2295
7659150c
PO		 2296 /*
2297 * If we use DMA, then it's up to the caller to set the DMA
2298 * mask, but PIO does not need the hw shim so we set a new
2299 * mask here in that case.
2300 */
a13abc7b 2301 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2302 host->dma_mask = DMA_BIT_MASK(64);
2303 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2304 }
d129bceb 2305
c4687d5f 2306 if (host->version >= SDHCI_SPEC_300)
f2119df6 2307 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2308 >> SDHCI_CLOCK_BASE_SHIFT;
2309 else
f2119df6 2310 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2311 >> SDHCI_CLOCK_BASE_SHIFT;
2312
4240ff0a 2313 host->max_clk *= 1000000;
f27f47ef
AV		 2314 if (host->max_clk == 0 || host->quirks &
2315 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a
BD		 2316 if (!host->ops->get_max_clock) {
2317 printk(KERN_ERR
2318 "%s: Hardware doesn't specify base clock "
2319 "frequency.\n", mmc_hostname(mmc));
2320 return -ENODEV;
2321 }
2322 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2323 }
d129bceb 2324
1c8cde92 2325 host->timeout_clk =
f2119df6 2326 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1c8cde92 2327 if (host->timeout_clk == 0) {
81b39802
AV		 2328 if (host->ops->get_timeout_clock) {
2329 host->timeout_clk = host->ops->get_timeout_clock(host);
2330 } else if (!(host->quirks &
2331 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4240ff0a
BD		 2332 printk(KERN_ERR
2333 "%s: Hardware doesn't specify timeout clock "
2334 "frequency.\n", mmc_hostname(mmc));
2335 return -ENODEV;
2336 }
1c8cde92 2337 }
f2119df6 2338 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
1c8cde92 2339 host->timeout_clk *= 1000;
d129bceb 2340
c3ed3877
AN		 2341 /*
2342 * In case of Host Controller v3.00, find out whether clock
2343 * multiplier is supported.
2344 */
2345 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2346 SDHCI_CLOCK_MUL_SHIFT;
2347
2348 /*
2349 * In case the value in Clock Multiplier is 0, then programmable
2350 * clock mode is not supported, otherwise the actual clock
2351 * multiplier is one more than the value of Clock Multiplier
2352 * in the Capabilities Register.
2353 */
2354 if (host->clk_mul)
2355 host->clk_mul += 1;
2356
d129bceb
PO		 2357 /*
2358 * Set host parameters.
2359 */
2360 mmc->ops = &sdhci_ops;
c3ed3877 2361 mmc->f_max = host->max_clk;
ce5f036b 2362 if (host->ops->get_min_clock)
a9e58f25 2363 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2364 else if (host->version >= SDHCI_SPEC_300) {
2365 if (host->clk_mul) {
2366 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2367 mmc->f_max = host->max_clk * host->clk_mul;
2368 } else
2369 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2370 } else
0397526d 2371 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2372
a3c7778f 2373 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE;
5fe23c7f 2374
15ec4461
PR		 2375 /*
2376 * A controller may support 8-bit width, but the board itself
2377 * might not have the pins brought out. Boards that support
2378 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2379 * their platform code before calling sdhci_add_host(), and we
2380 * won't assume 8-bit width for hosts without that CAP.
2381 */
5fe23c7f 2382 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2383 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2384
f2119df6 2385 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2386 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2387
176d1ed4
JC		 2388 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2389 mmc_card_is_removable(mmc))
68d1fb7e
AV		 2390 mmc->caps |= MMC_CAP_NEEDS_POLL;
2391
f2119df6
AN		 2392 /* UHS-I mode(s) supported by the host controller. */
2393 if (host->version >= SDHCI_SPEC_300)
2394 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2395
2396 /* SDR104 supports also implies SDR50 support */
2397 if (caps[1] & SDHCI_SUPPORT_SDR104)
2398 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2399 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2400 mmc->caps |= MMC_CAP_UHS_SDR50;
2401
2402 if (caps[1] & SDHCI_SUPPORT_DDR50)
2403 mmc->caps |= MMC_CAP_UHS_DDR50;
2404
b513ea25
AN		 2405 /* Does the host needs tuning for SDR50? */
2406 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2407 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2408
d6d50a15
AN		 2409 /* Driver Type(s) (A, C, D) supported by the host */
2410 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2411 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2412 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2413 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2414 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2415 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2416
8f230f45 2417 ocr_avail = 0;
f2119df6
AN		 2418 /*
2419 * According to SD Host Controller spec v3.00, if the Host System
2420 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2421 * the value is meaningful only if Voltage Support in the Capabilities
2422 * register is set. The actual current value is 4 times the register
2423 * value.
2424 */
2425 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2426
2427 if (caps[0] & SDHCI_CAN_VDD_330) {
2428 int max_current_330;
2429
8f230f45 2430 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6
AN		 2431
2432 max_current_330 = ((max_current_caps &
2433 SDHCI_MAX_CURRENT_330_MASK) >>
2434 SDHCI_MAX_CURRENT_330_SHIFT) *
2435 SDHCI_MAX_CURRENT_MULTIPLIER;
2436
2437 if (max_current_330 > 150)
2438 mmc->caps |= MMC_CAP_SET_XPC_330;
2439 }
2440 if (caps[0] & SDHCI_CAN_VDD_300) {
2441 int max_current_300;
2442
8f230f45 2443 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6
AN		 2444
2445 max_current_300 = ((max_current_caps &
2446 SDHCI_MAX_CURRENT_300_MASK) >>
2447 SDHCI_MAX_CURRENT_300_SHIFT) *
2448 SDHCI_MAX_CURRENT_MULTIPLIER;
2449
2450 if (max_current_300 > 150)
2451 mmc->caps |= MMC_CAP_SET_XPC_300;
2452 }
2453 if (caps[0] & SDHCI_CAN_VDD_180) {
2454 int max_current_180;
2455
8f230f45
TI		 2456 ocr_avail |= MMC_VDD_165_195;
2457
f2119df6
AN		 2458 max_current_180 = ((max_current_caps &
2459 SDHCI_MAX_CURRENT_180_MASK) >>
2460 SDHCI_MAX_CURRENT_180_SHIFT) *
2461 SDHCI_MAX_CURRENT_MULTIPLIER;
2462
2463 if (max_current_180 > 150)
2464 mmc->caps |= MMC_CAP_SET_XPC_180;
5371c927
AN		 2465
2466 /* Maximum current capabilities of the host at 1.8V */
2467 if (max_current_180 >= 800)
2468 mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2469 else if (max_current_180 >= 600)
2470 mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2471 else if (max_current_180 >= 400)
2472 mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2473 else
2474 mmc->caps |= MMC_CAP_MAX_CURRENT_200;
f2119df6
AN		 2475 }
2476
8f230f45
TI		 2477 mmc->ocr_avail = ocr_avail;
2478 mmc->ocr_avail_sdio = ocr_avail;
2479 if (host->ocr_avail_sdio)
2480 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2481 mmc->ocr_avail_sd = ocr_avail;
2482 if (host->ocr_avail_sd)
2483 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2484 else /* normal SD controllers don't support 1.8V */
2485 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2486 mmc->ocr_avail_mmc = ocr_avail;
2487 if (host->ocr_avail_mmc)
2488 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 2489
2490 if (mmc->ocr_avail == 0) {
2491 printk(KERN_ERR "%s: Hardware doesn't report any "
b69c9058 2492 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 2493 return -ENODEV;
146ad66e
PO		 2494 }
2495
d129bceb
PO		 2496 spin_lock_init(&host->lock);
2497
2498 /*
2134a922
PO		 2499 * Maximum number of segments. Depends on if the hardware
2500 * can do scatter/gather or not.
d129bceb 2501 */
2134a922 2502 if (host->flags & SDHCI_USE_ADMA)
a36274e0 2503 mmc->max_segs = 128;
a13abc7b 2504 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 2505 mmc->max_segs = 1;
2134a922 2506 else /* PIO */
a36274e0 2507 mmc->max_segs = 128;
d129bceb
PO		 2508
2509 /*
bab76961 2510 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 2511 * size (512KiB).
d129bceb 2512 */
55db890a 2513 mmc->max_req_size = 524288;
d129bceb
PO		 2514
2515 /*
2516 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 2517 * of bytes. When doing hardware scatter/gather, each entry cannot
2518 * be larger than 64 KiB though.
d129bceb 2519 */
30652aa3
OJ		 2520 if (host->flags & SDHCI_USE_ADMA) {
2521 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2522 mmc->max_seg_size = 65535;
2523 else
2524 mmc->max_seg_size = 65536;
2525 } else {
2134a922 2526 mmc->max_seg_size = mmc->max_req_size;
30652aa3 2527 }
d129bceb 2528
fe4a3c7a
PO		 2529 /*
2530 * Maximum block size. This varies from controller to controller and
2531 * is specified in the capabilities register.
2532 */
0633f654
AV		 2533 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2534 mmc->max_blk_size = 2;
2535 } else {
f2119df6 2536 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 2537 SDHCI_MAX_BLOCK_SHIFT;
2538 if (mmc->max_blk_size >= 3) {
2539 printk(KERN_WARNING "%s: Invalid maximum block size, "
2540 "assuming 512 bytes\n", mmc_hostname(mmc));
2541 mmc->max_blk_size = 0;
2542 }
2543 }
2544
2545 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 2546
55db890a
PO		 2547 /*
2548 * Maximum block count.
2549 */
1388eefd 2550 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 2551
d129bceb
PO		 2552 /*
2553 * Init tasklets.
2554 */
2555 tasklet_init(&host->card_tasklet,
2556 sdhci_tasklet_card, (unsigned long)host);
2557 tasklet_init(&host->finish_tasklet,
2558 sdhci_tasklet_finish, (unsigned long)host);
2559
e4cad1b5 2560 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 2561
b513ea25
AN		 2562 if (host->version >= SDHCI_SPEC_300)
2563 init_waitqueue_head(&host->buf_ready_int);
2564
dace1453 2565 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 2566 mmc_hostname(mmc), host);
d129bceb 2567 if (ret)
8ef1a143 2568 goto untasklet;
d129bceb 2569
9bea3c85
MS		 2570 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2571 if (IS_ERR(host->vmmc)) {
2572 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
2573 host->vmmc = NULL;
2574 } else {
2575 regulator_enable(host->vmmc);
2576 }
2577
2f4cbb3d 2578 sdhci_init(host, 0);
d129bceb
PO		 2579
2580#ifdef CONFIG_MMC_DEBUG
2581 sdhci_dumpregs(host);
2582#endif
2583
f9134319 2584#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 2585 snprintf(host->led_name, sizeof(host->led_name),
2586 "%s::", mmc_hostname(mmc));
2587 host->led.name = host->led_name;
2f730fec
PO		 2588 host->led.brightness = LED_OFF;
2589 host->led.default_trigger = mmc_hostname(mmc);
2590 host->led.brightness_set = sdhci_led_control;
2591
b8c86fc5 2592 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2f730fec
PO		 2593 if (ret)
2594 goto reset;
2595#endif
2596
5f25a66f
PO		 2597 mmiowb();
2598
d129bceb
PO		 2599 mmc_add_host(mmc);
2600
a13abc7b 2601 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 2602 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 2603 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2604 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 2605
7260cf5e
AV		 2606 sdhci_enable_card_detection(host);
2607
d129bceb
PO		 2608 return 0;
2609
f9134319 2610#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 2611reset:
2612 sdhci_reset(host, SDHCI_RESET_ALL);
2613 free_irq(host->irq, host);
2614#endif
8ef1a143 2615untasklet:
d129bceb
PO		 2616 tasklet_kill(&host->card_tasklet);
2617 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 2618
2619 return ret;
2620}
2621
b8c86fc5 2622EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 2623
1e72859e 2624void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 2625{
1e72859e
PO		 2626 unsigned long flags;
2627
2628 if (dead) {
2629 spin_lock_irqsave(&host->lock, flags);
2630
2631 host->flags |= SDHCI_DEVICE_DEAD;
2632
2633 if (host->mrq) {
2634 printk(KERN_ERR "%s: Controller removed during "
2635 " transfer!\n", mmc_hostname(host->mmc));
2636
2637 host->mrq->cmd->error = -ENOMEDIUM;
2638 tasklet_schedule(&host->finish_tasklet);
2639 }
2640
2641 spin_unlock_irqrestore(&host->lock, flags);
2642 }
2643
7260cf5e
AV		 2644 sdhci_disable_card_detection(host);
2645
b8c86fc5 2646 mmc_remove_host(host->mmc);
d129bceb 2647
f9134319 2648#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 2649 led_classdev_unregister(&host->led);
2650#endif
2651
1e72859e
PO		 2652 if (!dead)
2653 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb
PO		 2654
2655 free_irq(host->irq, host);
2656
2657 del_timer_sync(&host->timer);
2658
2659 tasklet_kill(&host->card_tasklet);
2660 tasklet_kill(&host->finish_tasklet);
2134a922 2661
9bea3c85
MS		 2662 if (host->vmmc) {
2663 regulator_disable(host->vmmc);
2664 regulator_put(host->vmmc);
2665 }
2666
2134a922
PO		 2667 kfree(host->adma_desc);
2668 kfree(host->align_buffer);
2669
2670 host->adma_desc = NULL;
2671 host->align_buffer = NULL;
d129bceb
PO		 2672}
2673
b8c86fc5 2674EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 2675
b8c86fc5 2676void sdhci_free_host(struct sdhci_host *host)
d129bceb 2677{
b8c86fc5 2678 mmc_free_host(host->mmc);
d129bceb
PO		 2679}
2680
b8c86fc5 2681EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 2682
2683/*****************************************************************************\
2684 * *
2685 * Driver init/exit *
2686 * *
2687\*****************************************************************************/
2688
2689static int __init sdhci_drv_init(void)
2690{
2691 printk(KERN_INFO DRIVER_NAME
52fbf9c9 2692 ": Secure Digital Host Controller Interface driver\n");
d129bceb
PO		 2693 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2694
b8c86fc5 2695 return 0;
d129bceb
PO		 2696}
2697
2698static void __exit sdhci_drv_exit(void)
2699{
d129bceb
PO		 2700}
2701
2702module_init(sdhci_drv_init);
2703module_exit(sdhci_drv_exit);
2704
df673b22 2705module_param(debug_quirks, uint, 0444);
67435274 2706
32710e8f 2707MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 2708MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 2709MODULE_LICENSE("GPL");
67435274 2710
df673b22 2711MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
kernel source for telekom puls (alcatel/mediatek)