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V4L/DVB: ngene: Make checkpatch.pl happy
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / dvb / ngene / ngene-core.c
CommitLineData
dae52d00
MB		 1/*
2 * ngene.c: nGene PCIe bridge driver
3 *
4 * Copyright (C) 2005-2007 Micronas
5 *
6 * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
7 * Modifications for new nGene firmware,
8 * support for EEPROM-copying,
9 * support for new dual DVB-S2 card prototype
10 *
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * version 2 only, as published by the Free Software Foundation.
15 *
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
26 * 02110-1301, USA
27 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
28 */
29
30#include <linux/module.h>
31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
34#include <linux/poll.h>
684688d8 35#include <linux/io.h>
dae52d00
MB		 36#include <asm/div64.h>
37#include <linux/pci.h>
38#include <linux/pci_ids.h>
39#include <linux/smp_lock.h>
40#include <linux/timer.h>
41#include <linux/version.h>
42#include <linux/byteorder/generic.h>
43#include <linux/firmware.h>
44
45#include "ngene.h"
46
8bba2607
MB		 47#include "stv6110x.h"
48#include "stv090x.h"
49#include "lnbh24.h"
50
cf1b12f2
MB		 51static int one_adapter = 1;
52module_param(one_adapter, int, 0444);
53MODULE_PARM_DESC(one_adapter, "Use only one adapter.");
54
dae52d00 55
dae52d00
MB		 56static int debug;
57module_param(debug, int, 0444);
58MODULE_PARM_DESC(debug, "Print debugging information.");
59
83f3c715
OE		 60DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
61
b1ec9532
OE		 62#define COMMAND_TIMEOUT_WORKAROUND
63
dae52d00
MB		 64#define dprintk if (debug) printk
65
66#define DEVICE_NAME "ngene"
67
68#define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr)))
69#define ngwritel(dat, adr) writel((dat), (char *)(dev->iomem + (adr)))
70#define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr)))
71#define ngreadl(adr) readl(dev->iomem + (adr))
72#define ngreadb(adr) readb(dev->iomem + (adr))
73#define ngcpyto(adr, src, count) memcpy_toio((char *) \
74 (dev->iomem + (adr)), (src), (count))
75#define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), (char *) \
76 (dev->iomem + (adr)), (count))
77
dae52d00
MB		 78/****************************************************************************/
79/* nGene interrupt handler **************************************************/
80/****************************************************************************/
81
82static void event_tasklet(unsigned long data)
83{
84 struct ngene *dev = (struct ngene *)data;
85
86 while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) {
87 struct EVENT_BUFFER Event =
88 dev->EventQueue[dev->EventQueueReadIndex];
89 dev->EventQueueReadIndex =
90 (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1);
91
92 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify))
93 dev->TxEventNotify(dev, Event.TimeStamp);
94 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify))
95 dev->RxEventNotify(dev, Event.TimeStamp,
96 Event.RXCharacter);
97 }
98}
99
100static void demux_tasklet(unsigned long data)
101{
102 struct ngene_channel *chan = (struct ngene_channel *)data;
103 struct SBufferHeader *Cur = chan->nextBuffer;
104
105 spin_lock_irq(&chan->state_lock);
106
107 while (Cur->ngeneBuffer.SR.Flags & 0x80) {
108 if (chan->mode & NGENE_IO_TSOUT) {
109 u32 Flags = chan->DataFormatFlags;
110 if (Cur->ngeneBuffer.SR.Flags & 0x20)
111 Flags |= BEF_OVERFLOW;
112 if (chan->pBufferExchange) {
113 if (!chan->pBufferExchange(chan,
114 Cur->Buffer1,
115 chan->Capture1Length,
116 Cur->ngeneBuffer.SR.
117 Clock, Flags)) {
118 /*
119 We didn't get data
120 Clear in service flag to make sure we
121 get called on next interrupt again.
122 leave fill/empty (0x80) flag alone
123 to avoid hardware running out of
124 buffers during startup, we hold only
125 in run state ( the source may be late
126 delivering data )
127 */
128
129 if (chan->HWState == HWSTATE_RUN) {
130 Cur->ngeneBuffer.SR.Flags &=
131 ~0x40;
132 break;
133 /* Stop proccessing stream */
134 }
135 } else {
136 /* We got a valid buffer,
137 so switch to run state */
138 chan->HWState = HWSTATE_RUN;
139 }
140 } else {
141 printk(KERN_ERR DEVICE_NAME ": OOPS\n");
142 if (chan->HWState == HWSTATE_RUN) {
143 Cur->ngeneBuffer.SR.Flags &= ~0x40;
144 break; /* Stop proccessing stream */
145 }
146 }
147 if (chan->AudioDTOUpdated) {
148 printk(KERN_INFO DEVICE_NAME
149 ": Update AudioDTO = %d\n",
150 chan->AudioDTOValue);
151 Cur->ngeneBuffer.SR.DTOUpdate =
152 chan->AudioDTOValue;
153 chan->AudioDTOUpdated = 0;
154 }
155 } else {
156 if (chan->HWState == HWSTATE_RUN) {
157 u32 Flags = 0;
158 if (Cur->ngeneBuffer.SR.Flags & 0x01)
159 Flags |= BEF_EVEN_FIELD;
160 if (Cur->ngeneBuffer.SR.Flags & 0x20)
161 Flags |= BEF_OVERFLOW;
162 if (chan->pBufferExchange)
163 chan->pBufferExchange(chan,
164 Cur->Buffer1,
165 chan->
166 Capture1Length,
167 Cur->ngeneBuffer.
168 SR.Clock, Flags);
169 if (chan->pBufferExchange2)
170 chan->pBufferExchange2(chan,
171 Cur->Buffer2,
172 chan->
173 Capture2Length,
174 Cur->ngeneBuffer.
175 SR.Clock, Flags);
176 } else if (chan->HWState != HWSTATE_STOP)
177 chan->HWState = HWSTATE_RUN;
178 }
179 Cur->ngeneBuffer.SR.Flags = 0x00;
180 Cur = Cur->Next;
181 }
182 chan->nextBuffer = Cur;
183
184 spin_unlock_irq(&chan->state_lock);
185}
186
187static irqreturn_t irq_handler(int irq, void *dev_id)
188{
189 struct ngene *dev = (struct ngene *)dev_id;
190 u32 icounts = 0;
191 irqreturn_t rc = IRQ_NONE;
192 u32 i = MAX_STREAM;
193 u8 *tmpCmdDoneByte;
194
195 if (dev->BootFirmware) {
196 icounts = ngreadl(NGENE_INT_COUNTS);
197 if (icounts != dev->icounts) {
198 ngwritel(0, FORCE_NMI);
199 dev->cmd_done = 1;
200 wake_up(&dev->cmd_wq);
201 dev->icounts = icounts;
202 rc = IRQ_HANDLED;
203 }
204 return rc;
205 }
206
207 ngwritel(0, FORCE_NMI);
208
209 spin_lock(&dev->cmd_lock);
210 tmpCmdDoneByte = dev->CmdDoneByte;
211 if (tmpCmdDoneByte &&
212 (*tmpCmdDoneByte ||
213 (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) {
214 dev->CmdDoneByte = NULL;
215 dev->cmd_done = 1;
216 wake_up(&dev->cmd_wq);
217 rc = IRQ_HANDLED;
218 }
219 spin_unlock(&dev->cmd_lock);
220
221 if (dev->EventBuffer->EventStatus & 0x80) {
222 u8 nextWriteIndex =
223 (dev->EventQueueWriteIndex + 1) &
224 (EVENT_QUEUE_SIZE - 1);
225 if (nextWriteIndex != dev->EventQueueReadIndex) {
226 dev->EventQueue[dev->EventQueueWriteIndex] =
227 *(dev->EventBuffer);
228 dev->EventQueueWriteIndex = nextWriteIndex;
229 } else {
230 printk(KERN_ERR DEVICE_NAME ": event overflow\n");
231 dev->EventQueueOverflowCount += 1;
232 dev->EventQueueOverflowFlag = 1;
233 }
234 dev->EventBuffer->EventStatus &= ~0x80;
235 tasklet_schedule(&dev->event_tasklet);
236 rc = IRQ_HANDLED;
237 }
238
239 while (i > 0) {
240 i--;
241 spin_lock(&dev->channel[i].state_lock);
242 /* if (dev->channel[i].State>=KSSTATE_RUN) { */
243 if (dev->channel[i].nextBuffer) {
244 if ((dev->channel[i].nextBuffer->
245 ngeneBuffer.SR.Flags & 0xC0) == 0x80) {
246 dev->channel[i].nextBuffer->
247 ngeneBuffer.SR.Flags |= 0x40;
248 tasklet_schedule(
249 &dev->channel[i].demux_tasklet);
250 rc = IRQ_HANDLED;
251 }
252 }
253 spin_unlock(&dev->channel[i].state_lock);
254 }
255
ace30f74
OE		 256 /* Request might have been processed by a previous call. */
257 return IRQ_HANDLED;
dae52d00
MB		 258}
259
260/****************************************************************************/
261/* nGene command interface **************************************************/
262/****************************************************************************/
263
b1ec9532
OE		 264static void dump_command_io(struct ngene *dev)
265{
266 u8 buf[8], *b;
267
268 ngcpyfrom(buf, HOST_TO_NGENE, 8);
269 printk(KERN_ERR "host_to_ngene (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n",
684688d8
OE		 270 HOST_TO_NGENE, buf[0], buf[1], buf[2], buf[3],
271 buf[4], buf[5], buf[6], buf[7]);
b1ec9532
OE		 272
273 ngcpyfrom(buf, NGENE_TO_HOST, 8);
274 printk(KERN_ERR "ngene_to_host (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n",
684688d8
OE		 275 NGENE_TO_HOST, buf[0], buf[1], buf[2], buf[3],
276 buf[4], buf[5], buf[6], buf[7]);
b1ec9532
OE		 277
278 b = dev->hosttongene;
279 printk(KERN_ERR "dev->hosttongene (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n",
280 b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
281
282 b = dev->ngenetohost;
283 printk(KERN_ERR "dev->ngenetohost (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n",
284 b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
285}
286
dae52d00
MB		 287static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com)
288{
289 int ret;
290 u8 *tmpCmdDoneByte;
291
292 dev->cmd_done = 0;
293
294 if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) {
295 dev->BootFirmware = 1;
296 dev->icounts = ngreadl(NGENE_INT_COUNTS);
297 ngwritel(0, NGENE_COMMAND);
298 ngwritel(0, NGENE_COMMAND_HI);
299 ngwritel(0, NGENE_STATUS);
300 ngwritel(0, NGENE_STATUS_HI);
301 ngwritel(0, NGENE_EVENT);
302 ngwritel(0, NGENE_EVENT_HI);
303 } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) {
304 u64 fwio = dev->PAFWInterfaceBuffer;
305
306 ngwritel(fwio & 0xffffffff, NGENE_COMMAND);
307 ngwritel(fwio >> 32, NGENE_COMMAND_HI);
308 ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS);
309 ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI);
310 ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT);
311 ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI);
312 }
313
314 memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2);
315
316 if (dev->BootFirmware)
317 ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2);
318
319 spin_lock_irq(&dev->cmd_lock);
320 tmpCmdDoneByte = dev->ngenetohost + com->out_len;
321 if (!com->out_len)
322 tmpCmdDoneByte++;
323 *tmpCmdDoneByte = 0;
324 dev->ngenetohost[0] = 0;
325 dev->ngenetohost[1] = 0;
326 dev->CmdDoneByte = tmpCmdDoneByte;
327 spin_unlock_irq(&dev->cmd_lock);
328
329 /* Notify 8051. */
330 ngwritel(1, FORCE_INT);
331
332 ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ);
333 if (!ret) {
334 /*ngwritel(0, FORCE_NMI);*/
335
336 printk(KERN_ERR DEVICE_NAME
337 ": Command timeout cmd=%02x prev=%02x\n",
338 com->cmd.hdr.Opcode, dev->prev_cmd);
b1ec9532 339 dump_command_io(dev);
dae52d00
MB		 340 return -1;
341 }
342 if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH)
343 dev->BootFirmware = 0;
344
345 dev->prev_cmd = com->cmd.hdr.Opcode;
dae52d00
MB		 346
347 if (!com->out_len)
348 return 0;
349
350 memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len);
351
352 return 0;
353}
354
355static int ngene_command(struct ngene *dev, struct ngene_command *com)
356{
357 int result;
358
359 down(&dev->cmd_mutex);
360 result = ngene_command_mutex(dev, com);
361 up(&dev->cmd_mutex);
362 return result;
363}
364
dae52d00 365
9fdd7976 366static int ngene_command_i2c_read(struct ngene *dev, u8 adr,
dae52d00
MB		 367 u8 *out, u8 outlen, u8 *in, u8 inlen, int flag)
368{
369 struct ngene_command com;
370
371 com.cmd.hdr.Opcode = CMD_I2C_READ;
372 com.cmd.hdr.Length = outlen + 3;
373 com.cmd.I2CRead.Device = adr << 1;
374 memcpy(com.cmd.I2CRead.Data, out, outlen);
375 com.cmd.I2CRead.Data[outlen] = inlen;
376 com.cmd.I2CRead.Data[outlen + 1] = 0;
377 com.in_len = outlen + 3;
378 com.out_len = inlen + 1;
379
380 if (ngene_command(dev, &com) < 0)
381 return -EIO;
382
383 if ((com.cmd.raw8[0] >> 1) != adr)
384 return -EIO;
385
386 if (flag)
387 memcpy(in, com.cmd.raw8, inlen + 1);
388 else
389 memcpy(in, com.cmd.raw8 + 1, inlen);
390 return 0;
391}
392
9fdd7976
OE		 393static int ngene_command_i2c_write(struct ngene *dev, u8 adr,
394 u8 *out, u8 outlen)
dae52d00
MB		 395{
396 struct ngene_command com;
397
398
399 com.cmd.hdr.Opcode = CMD_I2C_WRITE;
400 com.cmd.hdr.Length = outlen + 1;
401 com.cmd.I2CRead.Device = adr << 1;
402 memcpy(com.cmd.I2CRead.Data, out, outlen);
403 com.in_len = outlen + 1;
404 com.out_len = 1;
405
406 if (ngene_command(dev, &com) < 0)
407 return -EIO;
408
409 if (com.cmd.raw8[0] == 1)
410 return -EIO;
411
412 return 0;
413}
414
415static int ngene_command_load_firmware(struct ngene *dev,
416 u8 *ngene_fw, u32 size)
417{
418#define FIRSTCHUNK (1024)
419 u32 cleft;
420 struct ngene_command com;
421
422 com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE;
423 com.cmd.hdr.Length = 0;
424 com.in_len = 0;
425 com.out_len = 0;
426
427 ngene_command(dev, &com);
428
429 cleft = (size + 3) & ~3;
430 if (cleft > FIRSTCHUNK) {
431 ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK,
432 cleft - FIRSTCHUNK);
433 cleft = FIRSTCHUNK;
434 }
dae52d00
MB		 435 ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft);
436
437 memset(&com, 0, sizeof(struct ngene_command));
438 com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH;
439 com.cmd.hdr.Length = 4;
440 com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA;
441 com.cmd.FWLoadFinish.Length = (unsigned short)cleft;
442 com.in_len = 4;
443 com.out_len = 0;
444
445 return ngene_command(dev, &com);
446}
447
dae52d00
MB		 448
449static int ngene_command_config_buf(struct ngene *dev, u8 config)
450{
451 struct ngene_command com;
452
453 com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER;
454 com.cmd.hdr.Length = 1;
455 com.cmd.ConfigureBuffers.config = config;
456 com.in_len = 1;
457 com.out_len = 0;
458
459 if (ngene_command(dev, &com) < 0)
460 return -EIO;
461 return 0;
462}
463
464static int ngene_command_config_free_buf(struct ngene *dev, u8 *config)
465{
466 struct ngene_command com;
467
468 com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER;
469 com.cmd.hdr.Length = 6;
470 memcpy(&com.cmd.ConfigureBuffers.config, config, 6);
471 com.in_len = 6;
472 com.out_len = 0;
473
474 if (ngene_command(dev, &com) < 0)
475 return -EIO;
476
477 return 0;
478}
479
480static int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level)
481{
482 struct ngene_command com;
483
484 com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN;
485 com.cmd.hdr.Length = 1;
486 com.cmd.SetGpioPin.select = select | (level << 7);
487 com.in_len = 1;
488 com.out_len = 0;
489
490 return ngene_command(dev, &com);
491}
492
dae52d00
MB		 493
494/*
495 02000640 is sample on rising edge.
496 02000740 is sample on falling edge.
497 02000040 is ignore "valid" signal
498
499 0: FD_CTL1 Bit 7,6 must be 0,1
500 7 disable(fw controlled)
501 6 0-AUX,1-TS
502 5 0-par,1-ser
503 4 0-lsb/1-msb
504 3,2 reserved
505 1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both
506 1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge
507 2: FD_STA is read-only. 0-sync
508 3: FD_INSYNC is number of 47s to trigger "in sync".
509 4: FD_OUTSYNC is number of 47s to trigger "out of sync".
510 5: FD_MAXBYTE1 is low-order of bytes per packet.
511 6: FD_MAXBYTE2 is high-order of bytes per packet.
512 7: Top byte is unused.
513*/
514
515/****************************************************************************/
516
517static u8 TSFeatureDecoderSetup[8 * 4] = {
518 0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00,
519 0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */
520 0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */
521 0x72, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */
522};
523
524/* Set NGENE I2S Config to 16 bit packed */
525static u8 I2SConfiguration[] = {
526 0x00, 0x10, 0x00, 0x00,
527 0x80, 0x10, 0x00, 0x00,
528};
529
530static u8 SPDIFConfiguration[10] = {
531 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
532};
533
534/* Set NGENE I2S Config to transport stream compatible mode */
535
536static u8 TS_I2SConfiguration[4] = { 0x3E, 0x1A, 0x00, 0x00 }; /*3e 18 00 00 ?*/
537
538static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x20, 0x00, 0x00 };
539
540static u8 ITUDecoderSetup[4][16] = {
541 {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20, /* SDTV */
542 0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00},
543 {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,
544 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
545 {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00, /* HDTV 1080i50 */
546 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
547 {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00, /* HDTV 1080i60 */
548 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
549};
550
551/*
552 * 50 48 60 gleich
553 * 27p50 9f 00 22 80 42 69 18 ...
554 * 27p60 93 00 22 80 82 69 1c ...
555 */
556
557/* Maxbyte to 1144 (for raw data) */
558static u8 ITUFeatureDecoderSetup[8] = {
559 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00
560};
561
562static void FillTSBuffer(void *Buffer, int Length, u32 Flags)
563{
564 u32 *ptr = Buffer;
565
566 memset(Buffer, Length, 0xff);
567 while (Length > 0) {
568 if (Flags & DF_SWAP32)
569 *ptr = 0x471FFF10;
570 else
571 *ptr = 0x10FF1F47;
572 ptr += (188 / 4);
573 Length -= 188;
574 }
575}
576
dae52d00
MB		 577
578static void flush_buffers(struct ngene_channel *chan)
579{
580 u8 val;
581
582 do {
583 msleep(1);
584 spin_lock_irq(&chan->state_lock);
585 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80;
586 spin_unlock_irq(&chan->state_lock);
587 } while (val);
588}
589
590static void clear_buffers(struct ngene_channel *chan)
591{
592 struct SBufferHeader *Cur = chan->nextBuffer;
593
594 do {
595 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR));
596 if (chan->mode & NGENE_IO_TSOUT)
597 FillTSBuffer(Cur->Buffer1,
598 chan->Capture1Length,
599 chan->DataFormatFlags);
600 Cur = Cur->Next;
601 } while (Cur != chan->nextBuffer);
602
603 if (chan->mode & NGENE_IO_TSOUT) {
604 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate =
605 chan->AudioDTOValue;
606 chan->AudioDTOUpdated = 0;
607
608 Cur = chan->TSIdleBuffer.Head;
609
610 do {
611 memset(&Cur->ngeneBuffer.SR, 0,
612 sizeof(Cur->ngeneBuffer.SR));
613 FillTSBuffer(Cur->Buffer1,
614 chan->Capture1Length,
615 chan->DataFormatFlags);
616 Cur = Cur->Next;
617 } while (Cur != chan->TSIdleBuffer.Head);
618 }
619}
620
9fdd7976
OE		 621static int ngene_command_stream_control(struct ngene *dev, u8 stream,
622 u8 control, u8 mode, u8 flags)
dae52d00
MB		 623{
624 struct ngene_channel *chan = &dev->channel[stream];
625 struct ngene_command com;
626 u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300);
627 u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500);
628 u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700);
629 u16 BsSDO = 0x9B00;
630
631 /* down(&dev->stream_mutex); */
632 while (down_trylock(&dev->stream_mutex)) {
633 printk(KERN_INFO DEVICE_NAME ": SC locked\n");
634 msleep(1);
635 }
636 memset(&com, 0, sizeof(com));
637 com.cmd.hdr.Opcode = CMD_CONTROL;
638 com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2;
639 com.cmd.StreamControl.Stream = stream | (control ? 8 : 0);
640 if (chan->mode & NGENE_IO_TSOUT)
641 com.cmd.StreamControl.Stream |= 0x07;
642 com.cmd.StreamControl.Control = control |
643 (flags & SFLAG_ORDER_LUMA_CHROMA);
644 com.cmd.StreamControl.Mode = mode;
645 com.in_len = sizeof(struct FW_STREAM_CONTROL);
646 com.out_len = 0;
647
44cdd064
OE		 648 dprintk(KERN_INFO DEVICE_NAME
649 ": Stream=%02x, Control=%02x, Mode=%02x\n",
650 com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control,
651 com.cmd.StreamControl.Mode);
652
dae52d00
MB		 653 chan->Mode = mode;
654
655 if (!(control & 0x80)) {
656 spin_lock_irq(&chan->state_lock);
657 if (chan->State == KSSTATE_RUN) {
658 chan->State = KSSTATE_ACQUIRE;
659 chan->HWState = HWSTATE_STOP;
660 spin_unlock_irq(&chan->state_lock);
661 if (ngene_command(dev, &com) < 0) {
662 up(&dev->stream_mutex);
663 return -1;
664 }
665 /* clear_buffers(chan); */
666 flush_buffers(chan);
667 up(&dev->stream_mutex);
668 return 0;
669 }
670 spin_unlock_irq(&chan->state_lock);
671 up(&dev->stream_mutex);
672 return 0;
673 }
674
675 if (mode & SMODE_AUDIO_CAPTURE) {
676 com.cmd.StreamControl.CaptureBlockCount =
677 chan->Capture1Length / AUDIO_BLOCK_SIZE;
678 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
679 } else if (mode & SMODE_TRANSPORT_STREAM) {
680 com.cmd.StreamControl.CaptureBlockCount =
681 chan->Capture1Length / TS_BLOCK_SIZE;
682 com.cmd.StreamControl.MaxLinesPerField =
683 chan->Capture1Length / TS_BLOCK_SIZE;
684 com.cmd.StreamControl.Buffer_Address =
685 chan->TSRingBuffer.PAHead;
686 if (chan->mode & NGENE_IO_TSOUT) {
687 com.cmd.StreamControl.BytesPerVBILine =
688 chan->Capture1Length / TS_BLOCK_SIZE;
689 com.cmd.StreamControl.Stream |= 0x07;
690 }
691 } else {
692 com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine;
693 com.cmd.StreamControl.MaxLinesPerField = chan->nLines;
694 com.cmd.StreamControl.MinLinesPerField = 100;
695 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
696
697 if (mode & SMODE_VBI_CAPTURE) {
698 com.cmd.StreamControl.MaxVBILinesPerField =
699 chan->nVBILines;
700 com.cmd.StreamControl.MinVBILinesPerField = 0;
701 com.cmd.StreamControl.BytesPerVBILine =
702 chan->nBytesPerVBILine;
703 }
704 if (flags & SFLAG_COLORBAR)
705 com.cmd.StreamControl.Stream |= 0x04;
706 }
707
708 spin_lock_irq(&chan->state_lock);
709 if (mode & SMODE_AUDIO_CAPTURE) {
710 chan->nextBuffer = chan->RingBuffer.Head;
711 if (mode & SMODE_AUDIO_SPDIF) {
712 com.cmd.StreamControl.SetupDataLen =
713 sizeof(SPDIFConfiguration);
714 com.cmd.StreamControl.SetupDataAddr = BsSPI;
715 memcpy(com.cmd.StreamControl.SetupData,
716 SPDIFConfiguration, sizeof(SPDIFConfiguration));
717 } else {
718 com.cmd.StreamControl.SetupDataLen = 4;
719 com.cmd.StreamControl.SetupDataAddr = BsSDI;
720 memcpy(com.cmd.StreamControl.SetupData,
721 I2SConfiguration +
722 4 * dev->card_info->i2s[stream], 4);
723 }
724 } else if (mode & SMODE_TRANSPORT_STREAM) {
725 chan->nextBuffer = chan->TSRingBuffer.Head;
726 if (stream >= STREAM_AUDIOIN1) {
727 if (chan->mode & NGENE_IO_TSOUT) {
728 com.cmd.StreamControl.SetupDataLen =
729 sizeof(TS_I2SOutConfiguration);
730 com.cmd.StreamControl.SetupDataAddr = BsSDO;
731 memcpy(com.cmd.StreamControl.SetupData,
732 TS_I2SOutConfiguration,
733 sizeof(TS_I2SOutConfiguration));
734 } else {
735 com.cmd.StreamControl.SetupDataLen =
736 sizeof(TS_I2SConfiguration);
737 com.cmd.StreamControl.SetupDataAddr = BsSDI;
738 memcpy(com.cmd.StreamControl.SetupData,
739 TS_I2SConfiguration,
740 sizeof(TS_I2SConfiguration));
741 }
742 } else {
743 com.cmd.StreamControl.SetupDataLen = 8;
744 com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10;
745 memcpy(com.cmd.StreamControl.SetupData,
746 TSFeatureDecoderSetup +
747 8 * dev->card_info->tsf[stream], 8);
748 }
749 } else {
750 chan->nextBuffer = chan->RingBuffer.Head;
751 com.cmd.StreamControl.SetupDataLen =
752 16 + sizeof(ITUFeatureDecoderSetup);
753 com.cmd.StreamControl.SetupDataAddr = BsUVI;
754 memcpy(com.cmd.StreamControl.SetupData,
755 ITUDecoderSetup[chan->itumode], 16);
756 memcpy(com.cmd.StreamControl.SetupData + 16,
757 ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup));
758 }
759 clear_buffers(chan);
760 chan->State = KSSTATE_RUN;
761 if (mode & SMODE_TRANSPORT_STREAM)
762 chan->HWState = HWSTATE_RUN;
763 else
764 chan->HWState = HWSTATE_STARTUP;
765 spin_unlock_irq(&chan->state_lock);
766
767 if (ngene_command(dev, &com) < 0) {
768 up(&dev->stream_mutex);
769 return -1;
770 }
771 up(&dev->stream_mutex);
772 return 0;
773}
774
dae52d00
MB		 775
776/****************************************************************************/
777/* I2C **********************************************************************/
778/****************************************************************************/
779
780static void ngene_i2c_set_bus(struct ngene *dev, int bus)
781{
782 if (!(dev->card_info->i2c_access & 2))
783 return;
784 if (dev->i2c_current_bus == bus)
785 return;
786
787 switch (bus) {
788 case 0:
789 ngene_command_gpio_set(dev, 3, 0);
790 ngene_command_gpio_set(dev, 2, 1);
791 break;
792
793 case 1:
794 ngene_command_gpio_set(dev, 2, 0);
795 ngene_command_gpio_set(dev, 3, 1);
796 break;
797 }
798 dev->i2c_current_bus = bus;
799}
800
801static int ngene_i2c_master_xfer(struct i2c_adapter *adapter,
802 struct i2c_msg msg[], int num)
803{
804 struct ngene_channel *chan =
805 (struct ngene_channel *)i2c_get_adapdata(adapter);
806 struct ngene *dev = chan->dev;
807
808 down(&dev->i2c_switch_mutex);
809 ngene_i2c_set_bus(dev, chan->number);
810
811 if (num == 2 && msg[1].flags & I2C_M_RD && !(msg[0].flags & I2C_M_RD))
812 if (!ngene_command_i2c_read(dev, msg[0].addr,
813 msg[0].buf, msg[0].len,
814 msg[1].buf, msg[1].len, 0))
815 goto done;
816
817 if (num == 1 && !(msg[0].flags & I2C_M_RD))
818 if (!ngene_command_i2c_write(dev, msg[0].addr,
819 msg[0].buf, msg[0].len))
820 goto done;
821 if (num == 1 && (msg[0].flags & I2C_M_RD))
822 if (!ngene_command_i2c_read(dev, msg[0].addr, 0, 0,
823 msg[0].buf, msg[0].len, 0))
824 goto done;
825
826 up(&dev->i2c_switch_mutex);
827 return -EIO;
828
829done:
830 up(&dev->i2c_switch_mutex);
831 return num;
832}
833
834
dae52d00
MB		 835static u32 ngene_i2c_functionality(struct i2c_adapter *adap)
836{
837 return I2C_FUNC_SMBUS_EMUL;
838}
839
9fdd7976 840static struct i2c_algorithm ngene_i2c_algo = {
dae52d00
MB		 841 .master_xfer = ngene_i2c_master_xfer,
842 .functionality = ngene_i2c_functionality,
843};
844
dae52d00
MB		 845static int ngene_i2c_init(struct ngene *dev, int dev_nr)
846{
847 struct i2c_adapter *adap = &(dev->channel[dev_nr].i2c_adapter);
848
849 i2c_set_adapdata(adap, &(dev->channel[dev_nr]));
850#ifdef I2C_ADAP_CLASS_TV_DIGITAL
851 adap->class = I2C_ADAP_CLASS_TV_DIGITAL | I2C_CLASS_TV_ANALOG;
852#else
853 adap->class = I2C_CLASS_TV_ANALOG;
854#endif
855
856 strcpy(adap->name, "nGene");
857
dae52d00
MB		 858 adap->algo = &ngene_i2c_algo;
859 adap->algo_data = (void *)&(dev->channel[dev_nr]);
c58b5ecd 860 adap->dev.parent = &dev->pci_dev->dev;
dae52d00
MB		 861
862 mutex_init(&adap->bus_lock);
863 return i2c_add_adapter(adap);
864}
865
dae52d00
MB		 866
867/****************************************************************************/
868/* DVB functions and API interface ******************************************/
869/****************************************************************************/
870
871static void swap_buffer(u32 *p, u32 len)
872{
873 while (len) {
874 *p = swab32(*p);
875 p++;
876 len -= 4;
877 }
878}
879
dae52d00
MB		 880
881static void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags)
882{
883 struct ngene_channel *chan = priv;
884
885
b1ec9532
OE		 886#ifdef COMMAND_TIMEOUT_WORKAROUND
887 if (chan->users > 0)
888#endif
889 dvb_dmx_swfilter(&chan->demux, buf, len);
dae52d00
MB		 890 return 0;
891}
892
893u8 fill_ts[188] = { 0x47, 0x1f, 0xff, 0x10 };
894
895static void *tsout_exchange(void *priv, void *buf, u32 len,
896 u32 clock, u32 flags)
897{
898 struct ngene_channel *chan = priv;
899 struct ngene *dev = chan->dev;
900 u32 alen;
901
902 alen = dvb_ringbuffer_avail(&dev->tsout_rbuf);
903 alen -= alen % 188;
904
905 if (alen < len)
906 FillTSBuffer(buf + alen, len - alen, flags);
907 else
908 alen = len;
909 dvb_ringbuffer_read(&dev->tsout_rbuf, buf, alen);
910 if (flags & DF_SWAP32)
911 swap_buffer((u32 *)buf, alen);
912 wake_up_interruptible(&dev->tsout_rbuf.queue);
913 return buf;
914}
915
dae52d00
MB		 916
917static void set_transfer(struct ngene_channel *chan, int state)
918{
919 u8 control = 0, mode = 0, flags = 0;
920 struct ngene *dev = chan->dev;
921 int ret;
922
dae52d00
MB		 923 /*
924 printk(KERN_INFO DEVICE_NAME ": st %d\n", state);
925 msleep(100);
926 */
927
928 if (state) {
929 if (chan->running) {
930 printk(KERN_INFO DEVICE_NAME ": already running\n");
931 return;
932 }
933 } else {
934 if (!chan->running) {
935 printk(KERN_INFO DEVICE_NAME ": already stopped\n");
936 return;
937 }
938 }
939
940 if (dev->card_info->switch_ctrl)
941 dev->card_info->switch_ctrl(chan, 1, state ^ 1);
942
943 if (state) {
944 spin_lock_irq(&chan->state_lock);
945
946 /* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
947 ngreadl(0x9310)); */
126cd4bc 948 dvb_ringbuffer_flush(&dev->tsout_rbuf);
dae52d00
MB		 949 control = 0x80;
950 if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
951 chan->Capture1Length = 512 * 188;
952 mode = SMODE_TRANSPORT_STREAM;
953 }
954 if (chan->mode & NGENE_IO_TSOUT) {
955 chan->pBufferExchange = tsout_exchange;
956 /* 0x66666666 = 50MHz *2^33 /250MHz */
957 chan->AudioDTOValue = 0x66666666;
958 /* set_dto(chan, 38810700+1000); */
959 /* set_dto(chan, 19392658); */
960 }
961 if (chan->mode & NGENE_IO_TSIN)
962 chan->pBufferExchange = tsin_exchange;
963 /* ngwritel(0, 0x9310); */
964 spin_unlock_irq(&chan->state_lock);
965 } else
966 ;/* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
967 ngreadl(0x9310)); */
968
969 ret = ngene_command_stream_control(dev, chan->number,
970 control, mode, flags);
971 if (!ret)
972 chan->running = state;
973 else
974 printk(KERN_ERR DEVICE_NAME ": set_transfer %d failed\n",
975 state);
976 if (!state) {
977 spin_lock_irq(&chan->state_lock);
978 chan->pBufferExchange = 0;
126cd4bc 979 dvb_ringbuffer_flush(&dev->tsout_rbuf);
dae52d00
MB		 980 spin_unlock_irq(&chan->state_lock);
981 }
982}
983
984static int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed)
985{
986 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
987 struct ngene_channel *chan = dvbdmx->priv;
dae52d00
MB		 988
989 if (chan->users == 0) {
b1ec9532
OE		 990#ifdef COMMAND_TIMEOUT_WORKAROUND
991 if (!chan->running)
992#endif
993 set_transfer(chan, 1);
dae52d00
MB		 994 /* msleep(10); */
995 }
996
997 return ++chan->users;
998}
999
1000static int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
1001{
1002 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
1003 struct ngene_channel *chan = dvbdmx->priv;
dae52d00
MB		 1004
1005 if (--chan->users)
1006 return chan->users;
1007
b1ec9532 1008#ifndef COMMAND_TIMEOUT_WORKAROUND
dae52d00 1009 set_transfer(chan, 0);
b1ec9532 1010#endif
dae52d00
MB		 1011
1012 return 0;
1013}
1014
dae52d00 1015
dae52d00 1016
dae52d00
MB		 1017static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
1018 int (*start_feed)(struct dvb_demux_feed *),
1019 int (*stop_feed)(struct dvb_demux_feed *),
1020 void *priv)
1021{
1022 dvbdemux->priv = priv;
1023
1024 dvbdemux->filternum = 256;
1025 dvbdemux->feednum = 256;
1026 dvbdemux->start_feed = start_feed;
1027 dvbdemux->stop_feed = stop_feed;
1028 dvbdemux->write_to_decoder = 0;
1029 dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
1030 DMX_SECTION_FILTERING |
1031 DMX_MEMORY_BASED_FILTERING);
1032 return dvb_dmx_init(dvbdemux);
1033}
1034
1035static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
1036 struct dvb_demux *dvbdemux,
1037 struct dmx_frontend *hw_frontend,
1038 struct dmx_frontend *mem_frontend,
1039 struct dvb_adapter *dvb_adapter)
1040{
1041 int ret;
1042
1043 dmxdev->filternum = 256;
1044 dmxdev->demux = &dvbdemux->dmx;
1045 dmxdev->capabilities = 0;
1046 ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
1047 if (ret < 0)
1048 return ret;
1049
1050 hw_frontend->source = DMX_FRONTEND_0;
1051 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
1052 mem_frontend->source = DMX_MEMORY_FE;
1053 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
1054 return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
1055}
1056
dae52d00
MB		 1057
1058/****************************************************************************/
1059/* nGene hardware init and release functions ********************************/
1060/****************************************************************************/
1061
9fdd7976 1062static void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb)
dae52d00
MB		 1063{
1064 struct SBufferHeader *Cur = rb->Head;
1065 u32 j;
1066
1067 if (!Cur)
1068 return;
1069
1070 for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) {
1071 if (Cur->Buffer1)
1072 pci_free_consistent(dev->pci_dev,
1073 rb->Buffer1Length,
1074 Cur->Buffer1,
1075 Cur->scList1->Address);
1076
1077 if (Cur->Buffer2)
1078 pci_free_consistent(dev->pci_dev,
1079 rb->Buffer2Length,
1080 Cur->Buffer2,
1081 Cur->scList2->Address);
1082 }
1083
1084 if (rb->SCListMem)
1085 pci_free_consistent(dev->pci_dev, rb->SCListMemSize,
1086 rb->SCListMem, rb->PASCListMem);
1087
1088 pci_free_consistent(dev->pci_dev, rb->MemSize, rb->Head, rb->PAHead);
1089}
1090
9fdd7976 1091static void free_idlebuffer(struct ngene *dev,
dae52d00
MB		 1092 struct SRingBufferDescriptor *rb,
1093 struct SRingBufferDescriptor *tb)
1094{
1095 int j;
1096 struct SBufferHeader *Cur = tb->Head;
1097
1098 if (!rb->Head)
1099 return;
1100 free_ringbuffer(dev, rb);
1101 for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) {
1102 Cur->Buffer2 = 0;
1103 Cur->scList2 = 0;
1104 Cur->ngeneBuffer.Address_of_first_entry_2 = 0;
1105 Cur->ngeneBuffer.Number_of_entries_2 = 0;
1106 }
1107}
1108
9fdd7976 1109static void free_common_buffers(struct ngene *dev)
dae52d00
MB		 1110{
1111 u32 i;
1112 struct ngene_channel *chan;
1113
1114 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1115 chan = &dev->channel[i];
1116 free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer);
1117 free_ringbuffer(dev, &chan->RingBuffer);
1118 free_ringbuffer(dev, &chan->TSRingBuffer);
1119 }
1120
1121 if (dev->OverflowBuffer)
1122 pci_free_consistent(dev->pci_dev,
1123 OVERFLOW_BUFFER_SIZE,
1124 dev->OverflowBuffer, dev->PAOverflowBuffer);
1125
1126 if (dev->FWInterfaceBuffer)
1127 pci_free_consistent(dev->pci_dev,
1128 4096,
1129 dev->FWInterfaceBuffer,
1130 dev->PAFWInterfaceBuffer);
1131}
1132
1133/****************************************************************************/
1134/* Ring buffer handling *****************************************************/
1135/****************************************************************************/
1136
9fdd7976 1137static int create_ring_buffer(struct pci_dev *pci_dev,
dae52d00
MB		 1138 struct SRingBufferDescriptor *descr, u32 NumBuffers)
1139{
1140 dma_addr_t tmp;
1141 struct SBufferHeader *Head;
1142 u32 i;
1143 u32 MemSize = SIZEOF_SBufferHeader * NumBuffers;
1144 u64 PARingBufferHead;
1145 u64 PARingBufferCur;
1146 u64 PARingBufferNext;
1147 struct SBufferHeader *Cur, *Next;
1148
1149 descr->Head = 0;
1150 descr->MemSize = 0;
1151 descr->PAHead = 0;
1152 descr->NumBuffers = 0;
1153
1154 if (MemSize < 4096)
1155 MemSize = 4096;
1156
1157 Head = pci_alloc_consistent(pci_dev, MemSize, &tmp);
1158 PARingBufferHead = tmp;
1159
1160 if (!Head)
1161 return -ENOMEM;
1162
1163 memset(Head, 0, MemSize);
1164
1165 PARingBufferCur = PARingBufferHead;
1166 Cur = Head;
1167
1168 for (i = 0; i < NumBuffers - 1; i++) {
1169 Next = (struct SBufferHeader *)
1170 (((u8 *) Cur) + SIZEOF_SBufferHeader);
1171 PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader;
1172 Cur->Next = Next;
1173 Cur->ngeneBuffer.Next = PARingBufferNext;
1174 Cur = Next;
1175 PARingBufferCur = PARingBufferNext;
1176 }
1177 /* Last Buffer points back to first one */
1178 Cur->Next = Head;
1179 Cur->ngeneBuffer.Next = PARingBufferHead;
1180
1181 descr->Head = Head;
1182 descr->MemSize = MemSize;
1183 descr->PAHead = PARingBufferHead;
1184 descr->NumBuffers = NumBuffers;
1185
1186 return 0;
1187}
1188
1189static int AllocateRingBuffers(struct pci_dev *pci_dev,
1190 dma_addr_t of,
1191 struct SRingBufferDescriptor *pRingBuffer,
1192 u32 Buffer1Length, u32 Buffer2Length)
1193{
1194 dma_addr_t tmp;
1195 u32 i, j;
1196 int status = 0;
1197 u32 SCListMemSize = pRingBuffer->NumBuffers
1198 * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) :
1199 NUM_SCATTER_GATHER_ENTRIES)
1200 * sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1201
1202 u64 PASCListMem;
684688d8 1203 struct HW_SCATTER_GATHER_ELEMENT *SCListEntry;
dae52d00
MB		 1204 u64 PASCListEntry;
1205 struct SBufferHeader *Cur;
1206 void *SCListMem;
1207
1208 if (SCListMemSize < 4096)
1209 SCListMemSize = 4096;
1210
1211 SCListMem = pci_alloc_consistent(pci_dev, SCListMemSize, &tmp);
1212
1213 PASCListMem = tmp;
1214 if (SCListMem == NULL)
1215 return -ENOMEM;
1216
1217 memset(SCListMem, 0, SCListMemSize);
1218
1219 pRingBuffer->SCListMem = SCListMem;
1220 pRingBuffer->PASCListMem = PASCListMem;
1221 pRingBuffer->SCListMemSize = SCListMemSize;
1222 pRingBuffer->Buffer1Length = Buffer1Length;
1223 pRingBuffer->Buffer2Length = Buffer2Length;
1224
684688d8 1225 SCListEntry = SCListMem;
dae52d00
MB		 1226 PASCListEntry = PASCListMem;
1227 Cur = pRingBuffer->Head;
1228
1229 for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) {
1230 u64 PABuffer;
1231
1232 void *Buffer = pci_alloc_consistent(pci_dev, Buffer1Length,
1233 &tmp);
1234 PABuffer = tmp;
1235
1236 if (Buffer == NULL)
1237 return -ENOMEM;
1238
1239 Cur->Buffer1 = Buffer;
1240
1241 SCListEntry->Address = PABuffer;
1242 SCListEntry->Length = Buffer1Length;
1243
1244 Cur->scList1 = SCListEntry;
1245 Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry;
1246 Cur->ngeneBuffer.Number_of_entries_1 =
1247 NUM_SCATTER_GATHER_ENTRIES;
1248
1249 SCListEntry += 1;
1250 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1251
1252#if NUM_SCATTER_GATHER_ENTRIES > 1
1253 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) {
1254 SCListEntry->Address = of;
1255 SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1256 SCListEntry += 1;
1257 PASCListEntry +=
1258 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1259 }
1260#endif
1261
1262 if (!Buffer2Length)
1263 continue;
1264
1265 Buffer = pci_alloc_consistent(pci_dev, Buffer2Length, &tmp);
1266 PABuffer = tmp;
1267
1268 if (Buffer == NULL)
1269 return -ENOMEM;
1270
1271 Cur->Buffer2 = Buffer;
1272
1273 SCListEntry->Address = PABuffer;
1274 SCListEntry->Length = Buffer2Length;
1275
1276 Cur->scList2 = SCListEntry;
1277 Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry;
1278 Cur->ngeneBuffer.Number_of_entries_2 =
1279 NUM_SCATTER_GATHER_ENTRIES;
1280
1281 SCListEntry += 1;
1282 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1283
1284#if NUM_SCATTER_GATHER_ENTRIES > 1
1285 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) {
1286 SCListEntry->Address = of;
1287 SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1288 SCListEntry += 1;
1289 PASCListEntry +=
1290 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1291 }
1292#endif
1293
1294 }
1295
1296 return status;
1297}
1298
1299static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer,
1300 struct SRingBufferDescriptor *pRingBuffer)
1301{
1302 int status = 0;
1303
1304 /* Copy pointer to scatter gather list in TSRingbuffer
1305 structure for buffer 2
1306 Load number of buffer
1307 */
1308 u32 n = pRingBuffer->NumBuffers;
1309
1310 /* Point to first buffer entry */
1311 struct SBufferHeader *Cur = pRingBuffer->Head;
1312 int i;
1313 /* Loop thru all buffer and set Buffer 2 pointers to TSIdlebuffer */
1314 for (i = 0; i < n; i++) {
1315 Cur->Buffer2 = pIdleBuffer->Head->Buffer1;
1316 Cur->scList2 = pIdleBuffer->Head->scList1;
1317 Cur->ngeneBuffer.Address_of_first_entry_2 =
1318 pIdleBuffer->Head->ngeneBuffer.
1319 Address_of_first_entry_1;
1320 Cur->ngeneBuffer.Number_of_entries_2 =
1321 pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1;
1322 Cur = Cur->Next;
1323 }
1324 return status;
1325}
1326
1327static u32 RingBufferSizes[MAX_STREAM] = {
1328 RING_SIZE_VIDEO,
1329 RING_SIZE_VIDEO,
1330 RING_SIZE_AUDIO,
1331 RING_SIZE_AUDIO,
1332 RING_SIZE_AUDIO,
1333};
1334
1335static u32 Buffer1Sizes[MAX_STREAM] = {
1336 MAX_VIDEO_BUFFER_SIZE,
1337 MAX_VIDEO_BUFFER_SIZE,
1338 MAX_AUDIO_BUFFER_SIZE,
1339 MAX_AUDIO_BUFFER_SIZE,
1340 MAX_AUDIO_BUFFER_SIZE
1341};
1342
1343static u32 Buffer2Sizes[MAX_STREAM] = {
1344 MAX_VBI_BUFFER_SIZE,
1345 MAX_VBI_BUFFER_SIZE,
1346 0,
1347 0,
1348 0
1349};
1350
dae52d00
MB		 1351
1352static int AllocCommonBuffers(struct ngene *dev)
1353{
1354 int status = 0, i;
1355
1356 dev->FWInterfaceBuffer = pci_alloc_consistent(dev->pci_dev, 4096,
1357 &dev->PAFWInterfaceBuffer);
1358 if (!dev->FWInterfaceBuffer)
1359 return -ENOMEM;
1360 dev->hosttongene = dev->FWInterfaceBuffer;
1361 dev->ngenetohost = dev->FWInterfaceBuffer + 256;
1362 dev->EventBuffer = dev->FWInterfaceBuffer + 512;
1363
1364 dev->OverflowBuffer = pci_alloc_consistent(dev->pci_dev,
1365 OVERFLOW_BUFFER_SIZE,
1366 &dev->PAOverflowBuffer);
1367 if (!dev->OverflowBuffer)
1368 return -ENOMEM;
1369 memset(dev->OverflowBuffer, 0, OVERFLOW_BUFFER_SIZE);
1370
1371 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1372 int type = dev->card_info->io_type[i];
1373
1374 dev->channel[i].State = KSSTATE_STOP;
1375
1376 if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) {
1377 status = create_ring_buffer(dev->pci_dev,
1378 &dev->channel[i].RingBuffer,
1379 RingBufferSizes[i]);
1380 if (status < 0)
1381 break;
1382
1383 if (type & (NGENE_IO_TV | NGENE_IO_AIN)) {
1384 status = AllocateRingBuffers(dev->pci_dev,
1385 dev->
1386 PAOverflowBuffer,
1387 &dev->channel[i].
1388 RingBuffer,
1389 Buffer1Sizes[i],
1390 Buffer2Sizes[i]);
1391 if (status < 0)
1392 break;
1393 } else if (type & NGENE_IO_HDTV) {
1394 status = AllocateRingBuffers(dev->pci_dev,
1395 dev->
1396 PAOverflowBuffer,
1397 &dev->channel[i].
1398 RingBuffer,
1399 MAX_HDTV_BUFFER_SIZE,
1400 0);
1401 if (status < 0)
1402 break;
1403 }
1404 }
1405
1406 if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1407
1408 status = create_ring_buffer(dev->pci_dev,
1409 &dev->channel[i].
1410 TSRingBuffer, RING_SIZE_TS);
1411 if (status < 0)
1412 break;
1413
1414 status = AllocateRingBuffers(dev->pci_dev,
1415 dev->PAOverflowBuffer,
1416 &dev->channel[i].
1417 TSRingBuffer,
1418 MAX_TS_BUFFER_SIZE, 0);
1419 if (status)
1420 break;
1421 }
1422
1423 if (type & NGENE_IO_TSOUT) {
1424 status = create_ring_buffer(dev->pci_dev,
1425 &dev->channel[i].
1426 TSIdleBuffer, 1);
1427 if (status < 0)
1428 break;
1429 status = AllocateRingBuffers(dev->pci_dev,
1430 dev->PAOverflowBuffer,
1431 &dev->channel[i].
1432 TSIdleBuffer,
1433 MAX_TS_BUFFER_SIZE, 0);
1434 if (status)
1435 break;
1436 FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer,
1437 &dev->channel[i].TSRingBuffer);
1438 }
1439 }
1440 return status;
1441}
1442
1443static void ngene_release_buffers(struct ngene *dev)
1444{
1445 if (dev->iomem)
1446 iounmap(dev->iomem);
1447 free_common_buffers(dev);
1448 vfree(dev->tsout_buf);
1449 vfree(dev->ain_buf);
1450 vfree(dev->vin_buf);
1451 vfree(dev);
1452}
1453
1454static int ngene_get_buffers(struct ngene *dev)
1455{
1456 if (AllocCommonBuffers(dev))
1457 return -ENOMEM;
1458 if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) {
1459 dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE);
1460 if (!dev->tsout_buf)
1461 return -ENOMEM;
1462 dvb_ringbuffer_init(&dev->tsout_rbuf,
1463 dev->tsout_buf, TSOUT_BUF_SIZE);
1464 }
1465 if (dev->card_info->io_type[2] & NGENE_IO_AIN) {
1466 dev->ain_buf = vmalloc(AIN_BUF_SIZE);
1467 if (!dev->ain_buf)
1468 return -ENOMEM;
1469 dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE);
1470 }
1471 if (dev->card_info->io_type[0] & NGENE_IO_HDTV) {
1472 dev->vin_buf = vmalloc(VIN_BUF_SIZE);
1473 if (!dev->vin_buf)
1474 return -ENOMEM;
1475 dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE);
1476 }
1477 dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0),
1478 pci_resource_len(dev->pci_dev, 0));
1479 if (!dev->iomem)
1480 return -ENOMEM;
1481
1482 return 0;
1483}
1484
1485static void ngene_init(struct ngene *dev)
1486{
1487 int i;
1488
1489 tasklet_init(&dev->event_tasklet, event_tasklet, (unsigned long)dev);
1490
1491 memset_io(dev->iomem + 0xc000, 0x00, 0x220);
1492 memset_io(dev->iomem + 0xc400, 0x00, 0x100);
1493
1494 for (i = 0; i < MAX_STREAM; i++) {
1495 dev->channel[i].dev = dev;
1496 dev->channel[i].number = i;
1497 }
1498
1499 dev->fw_interface_version = 0;
1500
1501 ngwritel(0, NGENE_INT_ENABLE);
1502
1503 dev->icounts = ngreadl(NGENE_INT_COUNTS);
1504
1505 dev->device_version = ngreadl(DEV_VER) & 0x0f;
1506 printk(KERN_INFO DEVICE_NAME ": Device version %d\n",
1507 dev->device_version);
1508}
1509
1510static int ngene_load_firm(struct ngene *dev)
1511{
1512 u32 size;
1513 const struct firmware *fw = NULL;
1514 u8 *ngene_fw;
1515 char *fw_name;
1516 int err, version;
1517
1518 version = dev->card_info->fw_version;
1519
1520 switch (version) {
1521 default:
1522 case 15:
1523 version = 15;
0027ebb7 1524 size = 23466;
dae52d00
MB		 1525 fw_name = "ngene_15.fw";
1526 break;
1527 case 16:
0027ebb7 1528 size = 23498;
dae52d00
MB		 1529 fw_name = "ngene_16.fw";
1530 break;
1531 case 17:
0027ebb7 1532 size = 24446;
dae52d00
MB		 1533 fw_name = "ngene_17.fw";
1534 break;
1535 }
dae52d00 1536
dae52d00
MB		 1537 if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) {
1538 printk(KERN_ERR DEVICE_NAME
0027ebb7 1539 ": Could not load firmware file %s.\n", fw_name);
dae52d00
MB		 1540 printk(KERN_INFO DEVICE_NAME
1541 ": Copy %s to your hotplug directory!\n", fw_name);
1542 return -1;
1543 }
0027ebb7
OE		 1544 if (size != fw->size) {
1545 printk(KERN_ERR DEVICE_NAME
1546 ": Firmware %s has invalid size!", fw_name);
1547 err = -1;
1548 } else {
1549 printk(KERN_INFO DEVICE_NAME
1550 ": Loading firmware file %s.\n", fw_name);
1551 ngene_fw = (u8 *) fw->data;
1552 err = ngene_command_load_firmware(dev, ngene_fw, size);
1553 }
1554
dae52d00 1555 release_firmware(fw);
0027ebb7 1556
dae52d00
MB		 1557 return err;
1558}
1559
1560static void ngene_stop(struct ngene *dev)
1561{
1562 down(&dev->cmd_mutex);
1563 i2c_del_adapter(&(dev->channel[0].i2c_adapter));
1564 i2c_del_adapter(&(dev->channel[1].i2c_adapter));
1565 ngwritel(0, NGENE_INT_ENABLE);
1566 ngwritel(0, NGENE_COMMAND);
1567 ngwritel(0, NGENE_COMMAND_HI);
1568 ngwritel(0, NGENE_STATUS);
1569 ngwritel(0, NGENE_STATUS_HI);
1570 ngwritel(0, NGENE_EVENT);
1571 ngwritel(0, NGENE_EVENT_HI);
1572 free_irq(dev->pci_dev->irq, dev);
1573}
1574
1575static int ngene_start(struct ngene *dev)
1576{
1577 int stat;
1578 int i;
1579
1580 pci_set_master(dev->pci_dev);
1581 ngene_init(dev);
1582
1583 stat = request_irq(dev->pci_dev->irq, irq_handler,
1584 IRQF_SHARED, "nGene",
1585 (void *)dev);
1586 if (stat < 0)
1587 return stat;
1588
1589 init_waitqueue_head(&dev->cmd_wq);
1590 init_waitqueue_head(&dev->tx_wq);
1591 init_waitqueue_head(&dev->rx_wq);
1592 sema_init(&dev->cmd_mutex, 1);
1593 sema_init(&dev->stream_mutex, 1);
1594 sema_init(&dev->pll_mutex, 1);
1595 sema_init(&dev->i2c_switch_mutex, 1);
1596 spin_lock_init(&dev->cmd_lock);
1597 for (i = 0; i < MAX_STREAM; i++)
1598 spin_lock_init(&dev->channel[i].state_lock);
1599 ngwritel(1, TIMESTAMPS);
1600
1601 ngwritel(1, NGENE_INT_ENABLE);
1602
1603 stat = ngene_load_firm(dev);
1604 if (stat < 0)
1605 goto fail;
1606
1607 stat = ngene_i2c_init(dev, 0);
1608 if (stat < 0)
1609 goto fail;
1610
1611 stat = ngene_i2c_init(dev, 1);
1612 if (stat < 0)
1613 goto fail;
1614
1615 if (dev->card_info->fw_version == 17) {
684688d8
OE		 1616 u8 tsin4_config[6] = {
1617 3072 / 64, 3072 / 64, 0, 3072 / 64, 3072 / 64, 0};
1618 u8 default_config[6] = {
1619 4096 / 64, 4096 / 64, 0, 2048 / 64, 2048 / 64, 0};
dae52d00
MB		 1620 u8 *bconf = default_config;
1621
1622 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1623 bconf = tsin4_config;
44cdd064 1624 dprintk(KERN_DEBUG DEVICE_NAME ": FW 17 buffer config\n");
dae52d00
MB		 1625 stat = ngene_command_config_free_buf(dev, bconf);
1626 } else {
1627 int bconf = BUFFER_CONFIG_4422;
dae52d00
MB		 1628 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1629 bconf = BUFFER_CONFIG_3333;
1630 stat = ngene_command_config_buf(dev, bconf);
1631 }
dae52d00
MB		 1632 return stat;
1633fail:
1634 ngwritel(0, NGENE_INT_ENABLE);
1635 free_irq(dev->pci_dev->irq, dev);
1636 return stat;
1637}
1638
83f3c715
OE		 1639
1640
dae52d00 1641/****************************************************************************/
83f3c715 1642/* Switch control (I2C gates, etc.) *****************************************/
dae52d00
MB		 1643/****************************************************************************/
1644
dae52d00 1645
83f3c715
OE		 1646/****************************************************************************/
1647/* Demod/tuner attachment ***************************************************/
1648/****************************************************************************/
dae52d00 1649
8bba2607
MB		 1650static int tuner_attach_stv6110(struct ngene_channel *chan)
1651{
1652 struct stv090x_config *feconf = (struct stv090x_config *)
1653 chan->dev->card_info->fe_config[chan->number];
1654 struct stv6110x_config *tunerconf = (struct stv6110x_config *)
1655 chan->dev->card_info->tuner_config[chan->number];
1656 struct stv6110x_devctl *ctl;
1657
1658 ctl = dvb_attach(stv6110x_attach, chan->fe, tunerconf,
1659 &chan->i2c_adapter);
1660 if (ctl == NULL) {
1661 printk(KERN_ERR DEVICE_NAME ": No STV6110X found!\n");
1662 return -ENODEV;
1663 }
1664
1665 feconf->tuner_init = ctl->tuner_init;
1666 feconf->tuner_set_mode = ctl->tuner_set_mode;
1667 feconf->tuner_set_frequency = ctl->tuner_set_frequency;
1668 feconf->tuner_get_frequency = ctl->tuner_get_frequency;
1669 feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth;
1670 feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth;
1671 feconf->tuner_set_bbgain = ctl->tuner_set_bbgain;
1672 feconf->tuner_get_bbgain = ctl->tuner_get_bbgain;
1673 feconf->tuner_set_refclk = ctl->tuner_set_refclk;
1674 feconf->tuner_get_status = ctl->tuner_get_status;
1675
1676 return 0;
1677}
1678
1679
1680static int demod_attach_stv0900(struct ngene_channel *chan)
1681{
1682 struct stv090x_config *feconf = (struct stv090x_config *)
1683 chan->dev->card_info->fe_config[chan->number];
1684
1685 chan->fe = dvb_attach(stv090x_attach,
1686 feconf,
1687 &chan->i2c_adapter,
1688 chan->number == 0 ? STV090x_DEMODULATOR_0 :
1689 STV090x_DEMODULATOR_1);
1690 if (chan->fe == NULL) {
1691 printk(KERN_ERR DEVICE_NAME ": No STV0900 found!\n");
1692 return -ENODEV;
1693 }
1694
1695 if (!dvb_attach(lnbh24_attach, chan->fe, &chan->i2c_adapter, 0,
1696 0, chan->dev->card_info->lnb[chan->number])) {
1697 printk(KERN_ERR DEVICE_NAME ": No LNBH24 found!\n");
1698 dvb_frontend_detach(chan->fe);
1699 return -ENODEV;
1700 }
1701
1702 return 0;
1703}
dae52d00 1704
83f3c715
OE		 1705/****************************************************************************/
1706/****************************************************************************/
1707/****************************************************************************/
1708
1709static void release_channel(struct ngene_channel *chan)
dae52d00
MB		 1710{
1711 struct dvb_demux *dvbdemux = &chan->demux;
1712 struct ngene *dev = chan->dev;
1713 struct ngene_info *ni = dev->card_info;
1714 int io = ni->io_type[chan->number];
1715
b1ec9532
OE		 1716#ifdef COMMAND_TIMEOUT_WORKAROUND
1717 if (chan->running)
1718 set_transfer(chan, 0);
1719#endif
1720
dae52d00
MB		 1721 tasklet_kill(&chan->demux_tasklet);
1722
1723 if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
dae52d00
MB		 1724 if (chan->fe) {
1725 dvb_unregister_frontend(chan->fe);
dc35c9ae 1726 dvb_frontend_detach(chan->fe);
dae52d00
MB		 1727 chan->fe = 0;
1728 }
1729 dvbdemux->dmx.close(&dvbdemux->dmx);
1730 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1731 &chan->hw_frontend);
1732 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1733 &chan->mem_frontend);
1734 dvb_dmxdev_release(&chan->dmxdev);
1735 dvb_dmx_release(&chan->demux);
cf1b12f2
MB		 1736
1737 if (chan->number == 0 || !one_adapter)
1738 dvb_unregister_adapter(&dev->adapter[chan->number]);
dae52d00 1739 }
dae52d00
MB		 1740}
1741
1742static int init_channel(struct ngene_channel *chan)
1743{
1744 int ret = 0, nr = chan->number;
948a1195 1745 struct dvb_adapter *adapter = NULL;
dae52d00
MB		 1746 struct dvb_demux *dvbdemux = &chan->demux;
1747 struct ngene *dev = chan->dev;
1748 struct ngene_info *ni = dev->card_info;
1749 int io = ni->io_type[nr];
1750
1751 tasklet_init(&chan->demux_tasklet, demux_tasklet, (unsigned long)chan);
1752 chan->users = 0;
1753 chan->type = io;
1754 chan->mode = chan->type; /* for now only one mode */
1755
1756 if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1757 if (nr >= STREAM_AUDIOIN1)
1758 chan->DataFormatFlags = DF_SWAP32;
cf1b12f2
MB		 1759 if (nr == 0 || !one_adapter) {
1760 adapter = &dev->adapter[nr];
1761 ret = dvb_register_adapter(adapter, "nGene",
1762 THIS_MODULE,
1763 &chan->dev->pci_dev->dev,
1764 adapter_nr);
1765 if (ret < 0)
1766 return ret;
1767 } else {
1768 adapter = &dev->adapter[0];
1769 }
1770
dae52d00
MB		 1771 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
1772 ngene_start_feed,
1773 ngene_stop_feed, chan);
1774 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux,
1775 &chan->hw_frontend,
1776 &chan->mem_frontend, adapter);
dae52d00
MB		 1777 }
1778
1779 if (io & NGENE_IO_TSIN) {
1780 chan->fe = NULL;
1781 if (ni->demod_attach[nr])
1782 ni->demod_attach[nr](chan);
1783 if (chan->fe) {
1784 if (dvb_register_frontend(adapter, chan->fe) < 0) {
1785 if (chan->fe->ops.release)
1786 chan->fe->ops.release(chan->fe);
1787 chan->fe = NULL;
1788 }
1789 }
1790 if (chan->fe && ni->tuner_attach[nr])
1791 if (ni->tuner_attach[nr] (chan) < 0) {
1792 printk(KERN_ERR DEVICE_NAME
1793 ": Tuner attach failed on channel %d!\n",
1794 nr);
1795 }
1796 }
dae52d00
MB		 1797 return ret;
1798}
1799
1800static int init_channels(struct ngene *dev)
1801{
1802 int i, j;
1803
1804 for (i = 0; i < MAX_STREAM; i++) {
1805 if (init_channel(&dev->channel[i]) < 0) {
cf1b12f2 1806 for (j = i - 1; j >= 0; j--)
dae52d00
MB		 1807 release_channel(&dev->channel[j]);
1808 return -1;
1809 }
1810 }
1811 return 0;
1812}
1813
1814/****************************************************************************/
1815/* device probe/remove calls ************************************************/
1816/****************************************************************************/
1817
1818static void __devexit ngene_remove(struct pci_dev *pdev)
1819{
1820 struct ngene *dev = (struct ngene *)pci_get_drvdata(pdev);
1821 int i;
1822
1823 tasklet_kill(&dev->event_tasklet);
cf1b12f2 1824 for (i = MAX_STREAM - 1; i >= 0; i--)
dae52d00 1825 release_channel(&dev->channel[i]);
dae52d00
MB		 1826 ngene_stop(dev);
1827 ngene_release_buffers(dev);
1828 pci_set_drvdata(pdev, 0);
1829 pci_disable_device(pdev);
1830}
1831
1832static int __devinit ngene_probe(struct pci_dev *pci_dev,
1833 const struct pci_device_id *id)
1834{
1835 struct ngene *dev;
1836 int stat = 0;
1837
1838 if (pci_enable_device(pci_dev) < 0)
1839 return -ENODEV;
1840
1841 dev = vmalloc(sizeof(struct ngene));
dc35c9ae
RP		 1842 if (dev == NULL) {
1843 stat = -ENOMEM;
1844 goto fail0;
1845 }
dae52d00
MB		 1846 memset(dev, 0, sizeof(struct ngene));
1847
1848 dev->pci_dev = pci_dev;
1849 dev->card_info = (struct ngene_info *)id->driver_data;
1850 printk(KERN_INFO DEVICE_NAME ": Found %s\n", dev->card_info->name);
1851
1852 pci_set_drvdata(pci_dev, dev);
1853
1854 /* Alloc buffers and start nGene */
1855 stat = ngene_get_buffers(dev);
1856 if (stat < 0)
1857 goto fail1;
1858 stat = ngene_start(dev);
1859 if (stat < 0)
1860 goto fail1;
1861
1862 dev->i2c_current_bus = -1;
dae52d00
MB		 1863
1864 /* Register DVB adapters and devices for both channels */
dae52d00
MB		 1865 if (init_channels(dev) < 0)
1866 goto fail2;
1867
1868 return 0;
1869
1870fail2:
1871 ngene_stop(dev);
1872fail1:
1873 ngene_release_buffers(dev);
dc35c9ae
RP		 1874fail0:
1875 pci_disable_device(pci_dev);
dae52d00
MB		 1876 pci_set_drvdata(pci_dev, 0);
1877 return stat;
1878}
1879
1880/****************************************************************************/
1881/* Card configs *************************************************************/
1882/****************************************************************************/
1883
e890e7c0 1884static struct stv090x_config fe_cineS2 = {
8bba2607
MB		 1885 .device = STV0900,
1886 .demod_mode = STV090x_DUAL,
1887 .clk_mode = STV090x_CLK_EXT,
1888
1889 .xtal = 27000000,
1890 .address = 0x68,
8bba2607
MB		 1891
1892 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
1893 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
1894
1895 .repeater_level = STV090x_RPTLEVEL_16,
1896
589816c6
OE		 1897 .adc1_range = STV090x_ADC_1Vpp,
1898 .adc2_range = STV090x_ADC_1Vpp,
1899
8bba2607 1900 .diseqc_envelope_mode = true,
8bba2607
MB		 1901};
1902
e890e7c0 1903static struct stv6110x_config tuner_cineS2_0 = {
8bba2607
MB		 1904 .addr = 0x60,
1905 .refclk = 27000000,
83e74554 1906 .clk_div = 1,
8bba2607
MB		 1907};
1908
e890e7c0 1909static struct stv6110x_config tuner_cineS2_1 = {
8bba2607
MB		 1910 .addr = 0x63,
1911 .refclk = 27000000,
83e74554 1912 .clk_div = 1,
8bba2607
MB		 1913};
1914
e890e7c0 1915static struct ngene_info ngene_info_cineS2 = {
8bba2607 1916 .type = NGENE_SIDEWINDER,
e890e7c0 1917 .name = "Linux4Media cineS2 DVB-S2 Twin Tuner",
8bba2607
MB		 1918 .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN},
1919 .demod_attach = {demod_attach_stv0900, demod_attach_stv0900},
1920 .tuner_attach = {tuner_attach_stv6110, tuner_attach_stv6110},
e890e7c0
OE		 1921 .fe_config = {&fe_cineS2, &fe_cineS2},
1922 .tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1},
8bba2607
MB		 1923 .lnb = {0x0b, 0x08},
1924 .tsf = {3, 3},
b1ec9532 1925 .fw_version = 15,
8bba2607
MB		 1926};
1927
edad22a7
MB		 1928static struct ngene_info ngene_info_satixs2 = {
1929 .type = NGENE_SIDEWINDER,
1930 .name = "Mystique SaTiX-S2 Dual",
1931 .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN},
1932 .demod_attach = {demod_attach_stv0900, demod_attach_stv0900},
1933 .tuner_attach = {tuner_attach_stv6110, tuner_attach_stv6110},
e890e7c0
OE		 1934 .fe_config = {&fe_cineS2, &fe_cineS2},
1935 .tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1},
edad22a7
MB		 1936 .lnb = {0x0b, 0x08},
1937 .tsf = {3, 3},
b1ec9532 1938 .fw_version = 15,
edad22a7
MB		 1939};
1940
8bba2607
MB		 1941/****************************************************************************/
1942
dae52d00
MB		 1943
1944
1945/****************************************************************************/
edad22a7 1946/* PCI Subsystem ID *********************************************************/
dae52d00
MB		 1947/****************************************************************************/
1948
1949#define NGENE_ID(_subvend, _subdev, _driverdata) { \
1950 .vendor = NGENE_VID, .device = NGENE_PID, \
1951 .subvendor = _subvend, .subdevice = _subdev, \
1952 .driver_data = (unsigned long) &_driverdata }
1953
1954/****************************************************************************/
1955
1956static const struct pci_device_id ngene_id_tbl[] __devinitdata = {
e890e7c0
OE		 1957 NGENE_ID(0x18c3, 0xabc3, ngene_info_cineS2),
1958 NGENE_ID(0x18c3, 0xabc4, ngene_info_cineS2),
edad22a7 1959 NGENE_ID(0x18c3, 0xdb01, ngene_info_satixs2),
dae52d00
MB		 1960 {0}
1961};
8bba2607 1962MODULE_DEVICE_TABLE(pci, ngene_id_tbl);
dae52d00
MB		 1963
1964/****************************************************************************/
1965/* Init/Exit ****************************************************************/
1966/****************************************************************************/
1967
1968static pci_ers_result_t ngene_error_detected(struct pci_dev *dev,
1969 enum pci_channel_state state)
1970{
1971 printk(KERN_ERR DEVICE_NAME ": PCI error\n");
1972 if (state == pci_channel_io_perm_failure)
1973 return PCI_ERS_RESULT_DISCONNECT;
1974 if (state == pci_channel_io_frozen)
1975 return PCI_ERS_RESULT_NEED_RESET;
1976 return PCI_ERS_RESULT_CAN_RECOVER;
1977}
1978
1979static pci_ers_result_t ngene_link_reset(struct pci_dev *dev)
1980{
1981 printk(KERN_INFO DEVICE_NAME ": link reset\n");
1982 return 0;
1983}
1984
1985static pci_ers_result_t ngene_slot_reset(struct pci_dev *dev)
1986{
1987 printk(KERN_INFO DEVICE_NAME ": slot reset\n");
1988 return 0;
1989}
1990
1991static void ngene_resume(struct pci_dev *dev)
1992{
1993 printk(KERN_INFO DEVICE_NAME ": resume\n");
1994}
1995
1996static struct pci_error_handlers ngene_errors = {
1997 .error_detected = ngene_error_detected,
1998 .link_reset = ngene_link_reset,
1999 .slot_reset = ngene_slot_reset,
2000 .resume = ngene_resume,
2001};
2002
2003static struct pci_driver ngene_pci_driver = {
2004 .name = "ngene",
2005 .id_table = ngene_id_tbl,
2006 .probe = ngene_probe,
dc35c9ae 2007 .remove = __devexit_p(ngene_remove),
dae52d00
MB		 2008 .err_handler = &ngene_errors,
2009};
2010
2011static __init int module_init_ngene(void)
2012{
2013 printk(KERN_INFO
2014 "nGene PCIE bridge driver, Copyright (C) 2005-2007 Micronas\n");
2015 return pci_register_driver(&ngene_pci_driver);
2016}
2017
2018static __exit void module_exit_ngene(void)
2019{
2020 pci_unregister_driver(&ngene_pci_driver);
2021}
2022
2023module_init(module_init_ngene);
2024module_exit(module_exit_ngene);
2025
2026MODULE_DESCRIPTION("nGene");
2027MODULE_AUTHOR("Micronas, Ralph Metzler, Manfred Voelkel");
2028MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)