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swarm: use ide_find_port()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / ppc / pmac.c
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1da177e4 1/*
1da177e4 2 * Support for IDE interfaces on PowerMacs.
58f189fc 3 *
1da177e4
LT		 4 * These IDE interfaces are memory-mapped and have a DBDMA channel
5 * for doing DMA.
6 *
7 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
c15d5d43 8 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
1da177e4
LT		 9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 * Some code taken from drivers/ide/ide-dma.c:
16 *
17 * Copyright (c) 1995-1998 Mark Lord
18 *
19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
20 * get rid of the "rounded" tables used previously, so we have the
21 * same table format for all controllers and can then just have one
22 * big table
23 *
24 */
1da177e4
LT		 25#include <linux/types.h>
26#include <linux/kernel.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/ide.h>
30#include <linux/notifier.h>
31#include <linux/reboot.h>
32#include <linux/pci.h>
33#include <linux/adb.h>
34#include <linux/pmu.h>
35#include <linux/scatterlist.h>
36
37#include <asm/prom.h>
38#include <asm/io.h>
39#include <asm/dbdma.h>
40#include <asm/ide.h>
41#include <asm/pci-bridge.h>
42#include <asm/machdep.h>
43#include <asm/pmac_feature.h>
44#include <asm/sections.h>
45#include <asm/irq.h>
46
47#ifndef CONFIG_PPC64
48#include <asm/mediabay.h>
49#endif
50
9e5755bc 51#include "../ide-timing.h"
1da177e4
LT		 52
53#undef IDE_PMAC_DEBUG
54
55#define DMA_WAIT_TIMEOUT 50
56
57typedef struct pmac_ide_hwif {
58 unsigned long regbase;
59 int irq;
60 int kind;
61 int aapl_bus_id;
62 unsigned cable_80 : 1;
63 unsigned mediabay : 1;
64 unsigned broken_dma : 1;
65 unsigned broken_dma_warn : 1;
66 struct device_node* node;
67 struct macio_dev *mdev;
68 u32 timings[4];
69 volatile u32 __iomem * *kauai_fcr;
70#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
71 /* Those fields are duplicating what is in hwif. We currently
72 * can't use the hwif ones because of some assumptions that are
73 * beeing done by the generic code about the kind of dma controller
74 * and format of the dma table. This will have to be fixed though.
75 */
76 volatile struct dbdma_regs __iomem * dma_regs;
77 struct dbdma_cmd* dma_table_cpu;
78#endif
79
80} pmac_ide_hwif_t;
81
aacaf9bd 82static pmac_ide_hwif_t pmac_ide[MAX_HWIFS];
1da177e4
LT		 83
84enum {
85 controller_ohare, /* OHare based */
86 controller_heathrow, /* Heathrow/Paddington */
87 controller_kl_ata3, /* KeyLargo ATA-3 */
88 controller_kl_ata4, /* KeyLargo ATA-4 */
89 controller_un_ata6, /* UniNorth2 ATA-6 */
90 controller_k2_ata6, /* K2 ATA-6 */
91 controller_sh_ata6, /* Shasta ATA-6 */
92};
93
94static const char* model_name[] = {
95 "OHare ATA", /* OHare based */
96 "Heathrow ATA", /* Heathrow/Paddington */
97 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
98 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
99 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
100 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
101 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
102};
103
104/*
105 * Extra registers, both 32-bit little-endian
106 */
107#define IDE_TIMING_CONFIG 0x200
108#define IDE_INTERRUPT 0x300
109
110/* Kauai (U2) ATA has different register setup */
111#define IDE_KAUAI_PIO_CONFIG 0x200
112#define IDE_KAUAI_ULTRA_CONFIG 0x210
113#define IDE_KAUAI_POLL_CONFIG 0x220
114
115/*
116 * Timing configuration register definitions
117 */
118
119/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
120#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
121#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
122#define IDE_SYSCLK_NS 30 /* 33Mhz cell */
123#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
124
125/* 133Mhz cell, found in shasta.
126 * See comments about 100 Mhz Uninorth 2...
127 * Note that PIO_MASK and MDMA_MASK seem to overlap
128 */
129#define TR_133_PIOREG_PIO_MASK 0xff000fff
130#define TR_133_PIOREG_MDMA_MASK 0x00fff800
131#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
132#define TR_133_UDMAREG_UDMA_EN 0x00000001
133
134/* 100Mhz cell, found in Uninorth 2. I don't have much infos about
135 * this one yet, it appears as a pci device (106b/0033) on uninorth
136 * internal PCI bus and it's clock is controlled like gem or fw. It
137 * appears to be an evolution of keylargo ATA4 with a timing register
138 * extended to 2 32bits registers and a similar DBDMA channel. Other
139 * registers seem to exist but I can't tell much about them.
140 *
141 * So far, I'm using pre-calculated tables for this extracted from
142 * the values used by the MacOS X driver.
143 *
144 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
145 * register controls the UDMA timings. At least, it seems bit 0
146 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
147 * cycle time in units of 10ns. Bits 8..15 are used by I don't
148 * know their meaning yet
149 */
150#define TR_100_PIOREG_PIO_MASK 0xff000fff
151#define TR_100_PIOREG_MDMA_MASK 0x00fff000
152#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
153#define TR_100_UDMAREG_UDMA_EN 0x00000001
154
155
156/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
157 * 40 connector cable and to 4 on 80 connector one.
158 * Clock unit is 15ns (66Mhz)
159 *
160 * 3 Values can be programmed:
161 * - Write data setup, which appears to match the cycle time. They
162 * also call it DIOW setup.
163 * - Ready to pause time (from spec)
164 * - Address setup. That one is weird. I don't see where exactly
165 * it fits in UDMA cycles, I got it's name from an obscure piece
166 * of commented out code in Darwin. They leave it to 0, we do as
167 * well, despite a comment that would lead to think it has a
168 * min value of 45ns.
169 * Apple also add 60ns to the write data setup (or cycle time ?) on
170 * reads.
171 */
172#define TR_66_UDMA_MASK 0xfff00000
173#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
174#define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
175#define TR_66_UDMA_ADDRSETUP_SHIFT 29
176#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
177#define TR_66_UDMA_RDY2PAUS_SHIFT 25
178#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
179#define TR_66_UDMA_WRDATASETUP_SHIFT 21
180#define TR_66_MDMA_MASK 0x000ffc00
181#define TR_66_MDMA_RECOVERY_MASK 0x000f8000
182#define TR_66_MDMA_RECOVERY_SHIFT 15
183#define TR_66_MDMA_ACCESS_MASK 0x00007c00
184#define TR_66_MDMA_ACCESS_SHIFT 10
185#define TR_66_PIO_MASK 0x000003ff
186#define TR_66_PIO_RECOVERY_MASK 0x000003e0
187#define TR_66_PIO_RECOVERY_SHIFT 5
188#define TR_66_PIO_ACCESS_MASK 0x0000001f
189#define TR_66_PIO_ACCESS_SHIFT 0
190
191/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
192 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
193 *
194 * The access time and recovery time can be programmed. Some older
195 * Darwin code base limit OHare to 150ns cycle time. I decided to do
196 * the same here fore safety against broken old hardware ;)
197 * The HalfTick bit, when set, adds half a clock (15ns) to the access
198 * time and removes one from recovery. It's not supported on KeyLargo
199 * implementation afaik. The E bit appears to be set for PIO mode 0 and
200 * is used to reach long timings used in this mode.
201 */
202#define TR_33_MDMA_MASK 0x003ff800
203#define TR_33_MDMA_RECOVERY_MASK 0x001f0000
204#define TR_33_MDMA_RECOVERY_SHIFT 16
205#define TR_33_MDMA_ACCESS_MASK 0x0000f800
206#define TR_33_MDMA_ACCESS_SHIFT 11
207#define TR_33_MDMA_HALFTICK 0x00200000
208#define TR_33_PIO_MASK 0x000007ff
209#define TR_33_PIO_E 0x00000400
210#define TR_33_PIO_RECOVERY_MASK 0x000003e0
211#define TR_33_PIO_RECOVERY_SHIFT 5
212#define TR_33_PIO_ACCESS_MASK 0x0000001f
213#define TR_33_PIO_ACCESS_SHIFT 0
214
215/*
216 * Interrupt register definitions
217 */
218#define IDE_INTR_DMA 0x80000000
219#define IDE_INTR_DEVICE 0x40000000
220
221/*
222 * FCR Register on Kauai. Not sure what bit 0x4 is ...
223 */
224#define KAUAI_FCR_UATA_MAGIC 0x00000004
225#define KAUAI_FCR_UATA_RESET_N 0x00000002
226#define KAUAI_FCR_UATA_ENABLE 0x00000001
227
228#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
229
230/* Rounded Multiword DMA timings
231 *
232 * I gave up finding a generic formula for all controller
233 * types and instead, built tables based on timing values
234 * used by Apple in Darwin's implementation.
235 */
236struct mdma_timings_t {
237 int accessTime;
238 int recoveryTime;
239 int cycleTime;
240};
241
aacaf9bd 242struct mdma_timings_t mdma_timings_33[] =
1da177e4
LT		 243{
244 { 240, 240, 480 },
245 { 180, 180, 360 },
246 { 135, 135, 270 },
247 { 120, 120, 240 },
248 { 105, 105, 210 },
249 { 90, 90, 180 },
250 { 75, 75, 150 },
251 { 75, 45, 120 },
252 { 0, 0, 0 }
253};
254
aacaf9bd 255struct mdma_timings_t mdma_timings_33k[] =
1da177e4
LT		 256{
257 { 240, 240, 480 },
258 { 180, 180, 360 },
259 { 150, 150, 300 },
260 { 120, 120, 240 },
261 { 90, 120, 210 },
262 { 90, 90, 180 },
263 { 90, 60, 150 },
264 { 90, 30, 120 },
265 { 0, 0, 0 }
266};
267
aacaf9bd 268struct mdma_timings_t mdma_timings_66[] =
1da177e4
LT		 269{
270 { 240, 240, 480 },
271 { 180, 180, 360 },
272 { 135, 135, 270 },
273 { 120, 120, 240 },
274 { 105, 105, 210 },
275 { 90, 90, 180 },
276 { 90, 75, 165 },
277 { 75, 45, 120 },
278 { 0, 0, 0 }
279};
280
281/* KeyLargo ATA-4 Ultra DMA timings (rounded) */
282struct {
283 int addrSetup; /* ??? */
284 int rdy2pause;
285 int wrDataSetup;
aacaf9bd 286} kl66_udma_timings[] =
1da177e4
LT		 287{
288 { 0, 180, 120 }, /* Mode 0 */
289 { 0, 150, 90 }, /* 1 */
290 { 0, 120, 60 }, /* 2 */
291 { 0, 90, 45 }, /* 3 */
292 { 0, 90, 30 } /* 4 */
293};
294
295/* UniNorth 2 ATA/100 timings */
296struct kauai_timing {
297 int cycle_time;
298 u32 timing_reg;
299};
300
aacaf9bd 301static struct kauai_timing kauai_pio_timings[] =
1da177e4
LT		 302{
303 { 930 , 0x08000fff },
304 { 600 , 0x08000a92 },
305 { 383 , 0x0800060f },
306 { 360 , 0x08000492 },
307 { 330 , 0x0800048f },
308 { 300 , 0x080003cf },
309 { 270 , 0x080003cc },
310 { 240 , 0x0800038b },
311 { 239 , 0x0800030c },
312 { 180 , 0x05000249 },
c15d5d43
BZ		 313 { 120 , 0x04000148 },
314 { 0 , 0 },
1da177e4
LT		 315};
316
aacaf9bd 317static struct kauai_timing kauai_mdma_timings[] =
1da177e4
LT		 318{
319 { 1260 , 0x00fff000 },
320 { 480 , 0x00618000 },
321 { 360 , 0x00492000 },
322 { 270 , 0x0038e000 },
323 { 240 , 0x0030c000 },
324 { 210 , 0x002cb000 },
325 { 180 , 0x00249000 },
326 { 150 , 0x00209000 },
327 { 120 , 0x00148000 },
328 { 0 , 0 },
329};
330
aacaf9bd 331static struct kauai_timing kauai_udma_timings[] =
1da177e4
LT		 332{
333 { 120 , 0x000070c0 },
334 { 90 , 0x00005d80 },
335 { 60 , 0x00004a60 },
336 { 45 , 0x00003a50 },
337 { 30 , 0x00002a30 },
338 { 20 , 0x00002921 },
339 { 0 , 0 },
340};
341
aacaf9bd 342static struct kauai_timing shasta_pio_timings[] =
1da177e4
LT		 343{
344 { 930 , 0x08000fff },
345 { 600 , 0x0A000c97 },
346 { 383 , 0x07000712 },
347 { 360 , 0x040003cd },
348 { 330 , 0x040003cd },
349 { 300 , 0x040003cd },
350 { 270 , 0x040003cd },
351 { 240 , 0x040003cd },
352 { 239 , 0x040003cd },
353 { 180 , 0x0400028b },
c15d5d43
BZ		 354 { 120 , 0x0400010a },
355 { 0 , 0 },
1da177e4
LT		 356};
357
aacaf9bd 358static struct kauai_timing shasta_mdma_timings[] =
1da177e4
LT		 359{
360 { 1260 , 0x00fff000 },
361 { 480 , 0x00820800 },
362 { 360 , 0x00820800 },
363 { 270 , 0x00820800 },
364 { 240 , 0x00820800 },
365 { 210 , 0x00820800 },
366 { 180 , 0x00820800 },
367 { 150 , 0x0028b000 },
368 { 120 , 0x001ca000 },
369 { 0 , 0 },
370};
371
aacaf9bd 372static struct kauai_timing shasta_udma133_timings[] =
1da177e4
LT		 373{
374 { 120 , 0x00035901, },
375 { 90 , 0x000348b1, },
376 { 60 , 0x00033881, },
377 { 45 , 0x00033861, },
378 { 30 , 0x00033841, },
379 { 20 , 0x00033031, },
380 { 15 , 0x00033021, },
381 { 0 , 0 },
382};
383
384
385static inline u32
386kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
387{
388 int i;
389
390 for (i=0; table[i].cycle_time; i++)
391 if (cycle_time > table[i+1].cycle_time)
392 return table[i].timing_reg;
90a87ea4 393 BUG();
1da177e4
LT		 394 return 0;
395}
396
397/* allow up to 256 DBDMA commands per xfer */
398#define MAX_DCMDS 256
399
400/*
401 * Wait 1s for disk to answer on IDE bus after a hard reset
402 * of the device (via GPIO/FCR).
403 *
404 * Some devices seem to "pollute" the bus even after dropping
405 * the BSY bit (typically some combo drives slave on the UDMA
406 * bus) after a hard reset. Since we hard reset all drives on
407 * KeyLargo ATA66, we have to keep that delay around. I may end
408 * up not hard resetting anymore on these and keep the delay only
409 * for older interfaces instead (we have to reset when coming
410 * from MacOS...) --BenH.
411 */
412#define IDE_WAKEUP_DELAY (1*HZ)
413
c413b9b9 414static int pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif);
1da177e4 415static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq);
1da177e4
LT		 416static void pmac_ide_selectproc(ide_drive_t *drive);
417static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
418
419#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
420
23579a2a
BZ		 421#define PMAC_IDE_REG(x) \
422 ((void __iomem *)((drive)->hwif->io_ports[IDE_DATA_OFFSET] + (x)))
1da177e4
LT		 423
424/*
425 * Apply the timings of the proper unit (master/slave) to the shared
426 * timing register when selecting that unit. This version is for
427 * ASICs with a single timing register
428 */
aacaf9bd 429static void
1da177e4
LT		 430pmac_ide_selectproc(ide_drive_t *drive)
431{
432 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
433
434 if (pmif == NULL)
435 return;
436
437 if (drive->select.b.unit & 0x01)
438 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
439 else
440 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
441 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
442}
443
444/*
445 * Apply the timings of the proper unit (master/slave) to the shared
446 * timing register when selecting that unit. This version is for
447 * ASICs with a dual timing register (Kauai)
448 */
aacaf9bd 449static void
1da177e4
LT		 450pmac_ide_kauai_selectproc(ide_drive_t *drive)
451{
452 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
453
454 if (pmif == NULL)
455 return;
456
457 if (drive->select.b.unit & 0x01) {
458 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
459 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
460 } else {
461 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
462 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
463 }
464 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
465}
466
467/*
468 * Force an update of controller timing values for a given drive
469 */
aacaf9bd 470static void
1da177e4
LT		 471pmac_ide_do_update_timings(ide_drive_t *drive)
472{
473 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
474
475 if (pmif == NULL)
476 return;
477
478 if (pmif->kind == controller_sh_ata6 ||
479 pmif->kind == controller_un_ata6 ||
480 pmif->kind == controller_k2_ata6)
481 pmac_ide_kauai_selectproc(drive);
482 else
483 pmac_ide_selectproc(drive);
484}
485
486static void
487pmac_outbsync(ide_drive_t *drive, u8 value, unsigned long port)
488{
489 u32 tmp;
490
491 writeb(value, (void __iomem *) port);
492 tmp = readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
493}
494
1da177e4
LT		 495/*
496 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
497 */
aacaf9bd 498static void
26bcb879 499pmac_ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4 500{
0b46ff2e 501 u32 *timings, t;
1da177e4
LT		 502 unsigned accessTicks, recTicks;
503 unsigned accessTime, recTime;
504 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
7dd00083
BZ		 505 unsigned int cycle_time;
506
1da177e4
LT		 507 if (pmif == NULL)
508 return;
509
510 /* which drive is it ? */
511 timings = &pmif->timings[drive->select.b.unit & 0x01];
0b46ff2e 512 t = *timings;
1da177e4 513
7dd00083 514 cycle_time = ide_pio_cycle_time(drive, pio);
1da177e4
LT		 515
516 switch (pmif->kind) {
517 case controller_sh_ata6: {
518 /* 133Mhz cell */
7dd00083 519 u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time);
0b46ff2e 520 t = (t & ~TR_133_PIOREG_PIO_MASK) | tr;
1da177e4
LT		 521 break;
522 }
523 case controller_un_ata6:
524 case controller_k2_ata6: {
525 /* 100Mhz cell */
7dd00083 526 u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time);
0b46ff2e 527 t = (t & ~TR_100_PIOREG_PIO_MASK) | tr;
1da177e4
LT		 528 break;
529 }
530 case controller_kl_ata4:
531 /* 66Mhz cell */
7dd00083 532 recTime = cycle_time - ide_pio_timings[pio].active_time
1da177e4
LT		 533 - ide_pio_timings[pio].setup_time;
534 recTime = max(recTime, 150U);
535 accessTime = ide_pio_timings[pio].active_time;
536 accessTime = max(accessTime, 150U);
537 accessTicks = SYSCLK_TICKS_66(accessTime);
538 accessTicks = min(accessTicks, 0x1fU);
539 recTicks = SYSCLK_TICKS_66(recTime);
540 recTicks = min(recTicks, 0x1fU);
0b46ff2e
BH		 541 t = (t & ~TR_66_PIO_MASK) |
542 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
543 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
1da177e4
LT		 544 break;
545 default: {
546 /* 33Mhz cell */
547 int ebit = 0;
7dd00083 548 recTime = cycle_time - ide_pio_timings[pio].active_time
1da177e4
LT		 549 - ide_pio_timings[pio].setup_time;
550 recTime = max(recTime, 150U);
551 accessTime = ide_pio_timings[pio].active_time;
552 accessTime = max(accessTime, 150U);
553 accessTicks = SYSCLK_TICKS(accessTime);
554 accessTicks = min(accessTicks, 0x1fU);
555 accessTicks = max(accessTicks, 4U);
556 recTicks = SYSCLK_TICKS(recTime);
557 recTicks = min(recTicks, 0x1fU);
558 recTicks = max(recTicks, 5U) - 4;
559 if (recTicks > 9) {
560 recTicks--; /* guess, but it's only for PIO0, so... */
561 ebit = 1;
562 }
0b46ff2e 563 t = (t & ~TR_33_PIO_MASK) |
1da177e4
LT		 564 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
565 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
566 if (ebit)
0b46ff2e 567 t |= TR_33_PIO_E;
1da177e4
LT		 568 break;
569 }
570 }
571
572#ifdef IDE_PMAC_DEBUG
573 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
574 drive->name, pio, *timings);
575#endif
576
0b46ff2e 577 *timings = t;
c15d5d43 578 pmac_ide_do_update_timings(drive);
1da177e4
LT		 579}
580
581#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
582
583/*
584 * Calculate KeyLargo ATA/66 UDMA timings
585 */
aacaf9bd 586static int
1da177e4
LT		 587set_timings_udma_ata4(u32 *timings, u8 speed)
588{
589 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
590
591 if (speed > XFER_UDMA_4)
592 return 1;
593
594 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
595 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
596 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
597
598 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
599 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
600 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
601 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
602 TR_66_UDMA_EN;
603#ifdef IDE_PMAC_DEBUG
604 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
605 speed & 0xf, *timings);
606#endif
607
608 return 0;
609}
610
611/*
612 * Calculate Kauai ATA/100 UDMA timings
613 */
aacaf9bd 614static int
1da177e4
LT		 615set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
616{
617 struct ide_timing *t = ide_timing_find_mode(speed);
618 u32 tr;
619
620 if (speed > XFER_UDMA_5 || t == NULL)
621 return 1;
622 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
1da177e4
LT		 623 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
624 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
625
626 return 0;
627}
628
629/*
630 * Calculate Shasta ATA/133 UDMA timings
631 */
aacaf9bd 632static int
1da177e4
LT		 633set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
634{
635 struct ide_timing *t = ide_timing_find_mode(speed);
636 u32 tr;
637
638 if (speed > XFER_UDMA_6 || t == NULL)
639 return 1;
640 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
1da177e4
LT		 641 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
642 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
643
644 return 0;
645}
646
647/*
648 * Calculate MDMA timings for all cells
649 */
90f72eca 650static void
1da177e4 651set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
90f72eca 652 u8 speed)
1da177e4
LT		 653{
654 int cycleTime, accessTime = 0, recTime = 0;
655 unsigned accessTicks, recTicks;
90f72eca 656 struct hd_driveid *id = drive->id;
1da177e4
LT		 657 struct mdma_timings_t* tm = NULL;
658 int i;
659
660 /* Get default cycle time for mode */
661 switch(speed & 0xf) {
662 case 0: cycleTime = 480; break;
663 case 1: cycleTime = 150; break;
664 case 2: cycleTime = 120; break;
665 default:
90f72eca
BZ		 666 BUG();
667 break;
1da177e4 668 }
90f72eca
BZ		 669
670 /* Check if drive provides explicit DMA cycle time */
671 if ((id->field_valid & 2) && id->eide_dma_time)
672 cycleTime = max_t(int, id->eide_dma_time, cycleTime);
673
1da177e4
LT		 674 /* OHare limits according to some old Apple sources */
675 if ((intf_type == controller_ohare) && (cycleTime < 150))
676 cycleTime = 150;
677 /* Get the proper timing array for this controller */
678 switch(intf_type) {
679 case controller_sh_ata6:
680 case controller_un_ata6:
681 case controller_k2_ata6:
682 break;
683 case controller_kl_ata4:
684 tm = mdma_timings_66;
685 break;
686 case controller_kl_ata3:
687 tm = mdma_timings_33k;
688 break;
689 default:
690 tm = mdma_timings_33;
691 break;
692 }
693 if (tm != NULL) {
694 /* Lookup matching access & recovery times */
695 i = -1;
696 for (;;) {
697 if (tm[i+1].cycleTime < cycleTime)
698 break;
699 i++;
700 }
1da177e4
LT		 701 cycleTime = tm[i].cycleTime;
702 accessTime = tm[i].accessTime;
703 recTime = tm[i].recoveryTime;
704
705#ifdef IDE_PMAC_DEBUG
706 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
707 drive->name, cycleTime, accessTime, recTime);
708#endif
709 }
710 switch(intf_type) {
711 case controller_sh_ata6: {
712 /* 133Mhz cell */
713 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
1da177e4
LT		 714 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
715 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
716 }
717 case controller_un_ata6:
718 case controller_k2_ata6: {
719 /* 100Mhz cell */
720 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
1da177e4
LT		 721 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
722 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
723 }
724 break;
725 case controller_kl_ata4:
726 /* 66Mhz cell */
727 accessTicks = SYSCLK_TICKS_66(accessTime);
728 accessTicks = min(accessTicks, 0x1fU);
729 accessTicks = max(accessTicks, 0x1U);
730 recTicks = SYSCLK_TICKS_66(recTime);
731 recTicks = min(recTicks, 0x1fU);
732 recTicks = max(recTicks, 0x3U);
733 /* Clear out mdma bits and disable udma */
734 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
735 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
736 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
737 break;
738 case controller_kl_ata3:
739 /* 33Mhz cell on KeyLargo */
740 accessTicks = SYSCLK_TICKS(accessTime);
741 accessTicks = max(accessTicks, 1U);
742 accessTicks = min(accessTicks, 0x1fU);
743 accessTime = accessTicks * IDE_SYSCLK_NS;
744 recTicks = SYSCLK_TICKS(recTime);
745 recTicks = max(recTicks, 1U);
746 recTicks = min(recTicks, 0x1fU);
747 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
748 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
749 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
750 break;
751 default: {
752 /* 33Mhz cell on others */
753 int halfTick = 0;
754 int origAccessTime = accessTime;
755 int origRecTime = recTime;
756
757 accessTicks = SYSCLK_TICKS(accessTime);
758 accessTicks = max(accessTicks, 1U);
759 accessTicks = min(accessTicks, 0x1fU);
760 accessTime = accessTicks * IDE_SYSCLK_NS;
761 recTicks = SYSCLK_TICKS(recTime);
762 recTicks = max(recTicks, 2U) - 1;
763 recTicks = min(recTicks, 0x1fU);
764 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
765 if ((accessTicks > 1) &&
766 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
767 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
768 halfTick = 1;
769 accessTicks--;
770 }
771 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
772 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
773 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
774 if (halfTick)
775 *timings |= TR_33_MDMA_HALFTICK;
776 }
777 }
778#ifdef IDE_PMAC_DEBUG
779 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
780 drive->name, speed & 0xf, *timings);
781#endif
1da177e4
LT		 782}
783#endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
784
88b2b32b 785static void pmac_ide_set_dma_mode(ide_drive_t *drive, const u8 speed)
1da177e4
LT		 786{
787 int unit = (drive->select.b.unit & 0x01);
788 int ret = 0;
789 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
085798b1 790 u32 *timings, *timings2, tl[2];
1da177e4 791
1da177e4
LT		 792 timings = &pmif->timings[unit];
793 timings2 = &pmif->timings[unit+2];
085798b1
BZ		 794
795 /* Copy timings to local image */
796 tl[0] = *timings;
797 tl[1] = *timings2;
798
1da177e4 799#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
4db90a14
BZ		 800 if (speed >= XFER_UDMA_0) {
801 if (pmif->kind == controller_kl_ata4)
802 ret = set_timings_udma_ata4(&tl[0], speed);
803 else if (pmif->kind == controller_un_ata6
804 || pmif->kind == controller_k2_ata6)
805 ret = set_timings_udma_ata6(&tl[0], &tl[1], speed);
806 else if (pmif->kind == controller_sh_ata6)
807 ret = set_timings_udma_shasta(&tl[0], &tl[1], speed);
808 else
809 ret = -1;
810 } else
811 set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed);
1da177e4 812#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1da177e4 813 if (ret)
88b2b32b 814 return;
085798b1
BZ		 815
816 /* Apply timings to controller */
817 *timings = tl[0];
818 *timings2 = tl[1];
819
1da177e4 820 pmac_ide_do_update_timings(drive);
1da177e4
LT		 821}
822
823/*
824 * Blast some well known "safe" values to the timing registers at init or
825 * wakeup from sleep time, before we do real calculation
826 */
aacaf9bd 827static void
1da177e4
LT		 828sanitize_timings(pmac_ide_hwif_t *pmif)
829{
830 unsigned int value, value2 = 0;
831
832 switch(pmif->kind) {
833 case controller_sh_ata6:
834 value = 0x0a820c97;
835 value2 = 0x00033031;
836 break;
837 case controller_un_ata6:
838 case controller_k2_ata6:
839 value = 0x08618a92;
840 value2 = 0x00002921;
841 break;
842 case controller_kl_ata4:
843 value = 0x0008438c;
844 break;
845 case controller_kl_ata3:
846 value = 0x00084526;
847 break;
848 case controller_heathrow:
849 case controller_ohare:
850 default:
851 value = 0x00074526;
852 break;
853 }
854 pmif->timings[0] = pmif->timings[1] = value;
855 pmif->timings[2] = pmif->timings[3] = value2;
856}
857
1da177e4
LT		 858/* Suspend call back, should be called after the child devices
859 * have actually been suspended
860 */
861static int
862pmac_ide_do_suspend(ide_hwif_t *hwif)
863{
864 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
865
866 /* We clear the timings */
867 pmif->timings[0] = 0;
868 pmif->timings[1] = 0;
869
616299af
BH		 870 disable_irq(pmif->irq);
871
1da177e4
LT		 872 /* The media bay will handle itself just fine */
873 if (pmif->mediabay)
874 return 0;
875
876 /* Kauai has bus control FCRs directly here */
877 if (pmif->kauai_fcr) {
878 u32 fcr = readl(pmif->kauai_fcr);
879 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
880 writel(fcr, pmif->kauai_fcr);
881 }
882
883 /* Disable the bus on older machines and the cell on kauai */
884 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
885 0);
886
887 return 0;
888}
889
890/* Resume call back, should be called before the child devices
891 * are resumed
892 */
893static int
894pmac_ide_do_resume(ide_hwif_t *hwif)
895{
896 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
897
898 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
899 if (!pmif->mediabay) {
900 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
901 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
902 msleep(10);
903 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
1da177e4
LT		 904
905 /* Kauai has it different */
906 if (pmif->kauai_fcr) {
907 u32 fcr = readl(pmif->kauai_fcr);
908 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
909 writel(fcr, pmif->kauai_fcr);
910 }
616299af
BH		 911
912 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1da177e4
LT		 913 }
914
915 /* Sanitize drive timings */
916 sanitize_timings(pmif);
917
616299af
BH		 918 enable_irq(pmif->irq);
919
1da177e4
LT		 920 return 0;
921}
922
c413b9b9
BZ		 923static const struct ide_port_info pmac_port_info = {
924 .chipset = ide_pmac,
925 .host_flags = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA |
926 IDE_HFLAG_PIO_NO_DOWNGRADE |
927 IDE_HFLAG_POST_SET_MODE |
928 IDE_HFLAG_NO_DMA | /* no SFF-style DMA */
929 IDE_HFLAG_UNMASK_IRQS,
930 .pio_mask = ATA_PIO4,
931 .mwdma_mask = ATA_MWDMA2,
932};
933
1da177e4
LT		 934/*
935 * Setup, register & probe an IDE channel driven by this driver, this is
936 * called by one of the 2 probe functions (macio or PCI). Note that a channel
937 * that ends up beeing free of any device is not kept around by this driver
938 * (it is kept in 2.4). This introduce an interface numbering change on some
939 * rare machines unfortunately, but it's better this way.
940 */
468e4681 941static int __devinit
57c802e8 942pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw)
1da177e4
LT		 943{
944 struct device_node *np = pmif->node;
018a3d1d 945 const int *bidp;
8447d9d5 946 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
c413b9b9 947 struct ide_port_info d = pmac_port_info;
1da177e4
LT		 948
949 pmif->cable_80 = 0;
950 pmif->broken_dma = pmif->broken_dma_warn = 0;
c413b9b9 951 if (of_device_is_compatible(np, "shasta-ata")) {
1da177e4 952 pmif->kind = controller_sh_ata6;
c413b9b9
BZ		 953 d.udma_mask = ATA_UDMA6;
954 } else if (of_device_is_compatible(np, "kauai-ata")) {
1da177e4 955 pmif->kind = controller_un_ata6;
c413b9b9
BZ		 956 d.udma_mask = ATA_UDMA5;
957 } else if (of_device_is_compatible(np, "K2-UATA")) {
1da177e4 958 pmif->kind = controller_k2_ata6;
c413b9b9
BZ		 959 d.udma_mask = ATA_UDMA5;
960 } else if (of_device_is_compatible(np, "keylargo-ata")) {
961 if (strcmp(np->name, "ata-4") == 0) {
1da177e4 962 pmif->kind = controller_kl_ata4;
c413b9b9
BZ		 963 d.udma_mask = ATA_UDMA4;
964 } else
1da177e4 965 pmif->kind = controller_kl_ata3;
c413b9b9 966 } else if (of_device_is_compatible(np, "heathrow-ata")) {
1da177e4 967 pmif->kind = controller_heathrow;
c413b9b9 968 } else {
1da177e4
LT		 969 pmif->kind = controller_ohare;
970 pmif->broken_dma = 1;
971 }
972
40cd3a45 973 bidp = of_get_property(np, "AAPL,bus-id", NULL);
1da177e4
LT		 974 pmif->aapl_bus_id = bidp ? *bidp : 0;
975
976 /* Get cable type from device-tree */
977 if (pmif->kind == controller_kl_ata4 || pmif->kind == controller_un_ata6
978 || pmif->kind == controller_k2_ata6
979 || pmif->kind == controller_sh_ata6) {
40cd3a45 980 const char* cable = of_get_property(np, "cable-type", NULL);
1da177e4
LT		 981 if (cable && !strncmp(cable, "80-", 3))
982 pmif->cable_80 = 1;
983 }
984 /* G5's seem to have incorrect cable type in device-tree. Let's assume
985 * they have a 80 conductor cable, this seem to be always the case unless
986 * the user mucked around
987 */
55b61fec
SR		 988 if (of_device_is_compatible(np, "K2-UATA") ||
989 of_device_is_compatible(np, "shasta-ata"))
1da177e4
LT		 990 pmif->cable_80 = 1;
991
992 /* On Kauai-type controllers, we make sure the FCR is correct */
993 if (pmif->kauai_fcr)
994 writel(KAUAI_FCR_UATA_MAGIC |
995 KAUAI_FCR_UATA_RESET_N |
996 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
997
998 pmif->mediabay = 0;
999
1000 /* Make sure we have sane timings */
1001 sanitize_timings(pmif);
1002
1003#ifndef CONFIG_PPC64
1004 /* XXX FIXME: Media bay stuff need re-organizing */
1005 if (np->parent && np->parent->name
1006 && strcasecmp(np->parent->name, "media-bay") == 0) {
8c870933 1007#ifdef CONFIG_PMAC_MEDIABAY
2dde7861
BZ		 1008 media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq,
1009 hwif);
8c870933 1010#endif /* CONFIG_PMAC_MEDIABAY */
1da177e4
LT		 1011 pmif->mediabay = 1;
1012 if (!bidp)
1013 pmif->aapl_bus_id = 1;
1014 } else if (pmif->kind == controller_ohare) {
1015 /* The code below is having trouble on some ohare machines
1016 * (timing related ?). Until I can put my hand on one of these
1017 * units, I keep the old way
1018 */
1019 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1020 } else
1021#endif
1022 {
1023 /* This is necessary to enable IDE when net-booting */
1024 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1025 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1026 msleep(10);
1027 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1028 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1029 }
1030
1031 /* Setup MMIO ops */
1032 default_hwif_mmiops(hwif);
1033 hwif->OUTBSYNC = pmac_outbsync;
1034
1035 /* Tell common code _not_ to mess with resources */
2ad1e558 1036 hwif->mmio = 1;
1da177e4 1037 hwif->hwif_data = pmif;
57c802e8
BZ		 1038 ide_init_port_hw(hwif, hw);
1039 hwif->noprobe = pmif->mediabay;
49521f97 1040 hwif->cbl = pmif->cable_80 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
26bcb879 1041 hwif->set_pio_mode = pmac_ide_set_pio_mode;
1da177e4
LT		 1042 if (pmif->kind == controller_un_ata6
1043 || pmif->kind == controller_k2_ata6
1044 || pmif->kind == controller_sh_ata6)
1045 hwif->selectproc = pmac_ide_kauai_selectproc;
1046 else
1047 hwif->selectproc = pmac_ide_selectproc;
88b2b32b 1048 hwif->set_dma_mode = pmac_ide_set_dma_mode;
1da177e4 1049
1da177e4
LT		 1050 printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1051 hwif->index, model_name[pmif->kind], pmif->aapl_bus_id,
1052 pmif->mediabay ? " (mediabay)" : "", hwif->irq);
1053
8c870933 1054#ifdef CONFIG_PMAC_MEDIABAY
1da177e4
LT		 1055 if (pmif->mediabay && check_media_bay_by_base(pmif->regbase, MB_CD) == 0)
1056 hwif->noprobe = 0;
8c870933 1057#endif /* CONFIG_PMAC_MEDIABAY */
1da177e4 1058
1da177e4 1059#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
c413b9b9
BZ		 1060 if (pmif->cable_80 == 0)
1061 d.udma_mask &= ATA_UDMA2;
1da177e4 1062 /* has a DBDMA controller channel */
c413b9b9
BZ		 1063 if (pmif->dma_regs == 0 || pmac_ide_setup_dma(pmif, hwif) < 0)
1064#endif
1065 d.udma_mask = d.mwdma_mask = 0;
1da177e4 1066
8447d9d5 1067 idx[0] = hwif->index;
1da177e4 1068
c413b9b9 1069 ide_device_add(idx, &d);
5cbf79cd 1070
1da177e4
LT		 1071 return 0;
1072}
1073
5c58666f
BZ		 1074static void __devinit pmac_ide_init_ports(hw_regs_t *hw, unsigned long base)
1075{
1076 int i;
1077
1078 for (i = 0; i < 8; ++i)
1079 hw->io_ports[i] = base + i * 0x10;
1080 hw->io_ports[8] = base + 0x160;
1081}
1082
1da177e4
LT		 1083/*
1084 * Attach to a macio probed interface
1085 */
1086static int __devinit
5e655772 1087pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match)
1da177e4
LT		 1088{
1089 void __iomem *base;
1090 unsigned long regbase;
1091 int irq;
1092 ide_hwif_t *hwif;
1093 pmac_ide_hwif_t *pmif;
1094 int i, rc;
57c802e8 1095 hw_regs_t hw;
1da177e4
LT		 1096
1097 i = 0;
1098 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1099 || pmac_ide[i].node != NULL))
1100 ++i;
1101 if (i >= MAX_HWIFS) {
1102 printk(KERN_ERR "ide-pmac: MacIO interface attach with no slot\n");
1103 printk(KERN_ERR " %s\n", mdev->ofdev.node->full_name);
1104 return -ENODEV;
1105 }
1106
1107 pmif = &pmac_ide[i];
1108 hwif = &ide_hwifs[i];
1109
cc5d0189 1110 if (macio_resource_count(mdev) == 0) {
1da177e4
LT		 1111 printk(KERN_WARNING "ide%d: no address for %s\n",
1112 i, mdev->ofdev.node->full_name);
1113 return -ENXIO;
1114 }
1115
1116 /* Request memory resource for IO ports */
1117 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1118 printk(KERN_ERR "ide%d: can't request mmio resource !\n", i);
1119 return -EBUSY;
1120 }
1121
1122 /* XXX This is bogus. Should be fixed in the registry by checking
1123 * the kind of host interrupt controller, a bit like gatwick
1124 * fixes in irq.c. That works well enough for the single case
1125 * where that happens though...
1126 */
1127 if (macio_irq_count(mdev) == 0) {
1128 printk(KERN_WARNING "ide%d: no intrs for device %s, using 13\n",
1129 i, mdev->ofdev.node->full_name);
69917c26 1130 irq = irq_create_mapping(NULL, 13);
1da177e4
LT		 1131 } else
1132 irq = macio_irq(mdev, 0);
1133
1134 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1135 regbase = (unsigned long) base;
1136
36501650 1137 hwif->dev = &mdev->bus->pdev->dev;
1da177e4
LT		 1138
1139 pmif->mdev = mdev;
1140 pmif->node = mdev->ofdev.node;
1141 pmif->regbase = regbase;
1142 pmif->irq = irq;
1143 pmif->kauai_fcr = NULL;
1144#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1145 if (macio_resource_count(mdev) >= 2) {
1146 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1147 printk(KERN_WARNING "ide%d: can't request DMA resource !\n", i);
1148 else
1149 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1150 } else
1151 pmif->dma_regs = NULL;
1152#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1153 dev_set_drvdata(&mdev->ofdev.dev, hwif);
1154
57c802e8 1155 memset(&hw, 0, sizeof(hw));
5c58666f 1156 pmac_ide_init_ports(&hw, pmif->regbase);
57c802e8
BZ		 1157 hw.irq = irq;
1158 hw.dev = &mdev->ofdev.dev;
1159
1160 rc = pmac_ide_setup_device(pmif, hwif, &hw);
1da177e4
LT		 1161 if (rc != 0) {
1162 /* The inteface is released to the common IDE layer */
1163 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1164 iounmap(base);
ed908fa1 1165 if (pmif->dma_regs) {
1da177e4 1166 iounmap(pmif->dma_regs);
ed908fa1
BZ		 1167 macio_release_resource(mdev, 1);
1168 }
1da177e4
LT		 1169 memset(pmif, 0, sizeof(*pmif));
1170 macio_release_resource(mdev, 0);
1da177e4
LT		 1171 }
1172
1173 return rc;
1174}
1175
1176static int
8b4b8a24 1177pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
1da177e4
LT		 1178{
1179 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1180 int rc = 0;
1181
8b4b8a24 1182 if (mesg.event != mdev->ofdev.dev.power.power_state.event
3a2d5b70 1183 && (mesg.event & PM_EVENT_SLEEP)) {
1da177e4
LT		 1184 rc = pmac_ide_do_suspend(hwif);
1185 if (rc == 0)
8b4b8a24 1186 mdev->ofdev.dev.power.power_state = mesg;
1da177e4
LT		 1187 }
1188
1189 return rc;
1190}
1191
1192static int
1193pmac_ide_macio_resume(struct macio_dev *mdev)
1194{
1195 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1196 int rc = 0;
1197
ca078bae 1198 if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
1da177e4
LT		 1199 rc = pmac_ide_do_resume(hwif);
1200 if (rc == 0)
829ca9a3 1201 mdev->ofdev.dev.power.power_state = PMSG_ON;
1da177e4
LT		 1202 }
1203
1204 return rc;
1205}
1206
1207/*
1208 * Attach to a PCI probed interface
1209 */
1210static int __devinit
1211pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1212{
1213 ide_hwif_t *hwif;
1214 struct device_node *np;
1215 pmac_ide_hwif_t *pmif;
1216 void __iomem *base;
1217 unsigned long rbase, rlen;
1218 int i, rc;
57c802e8 1219 hw_regs_t hw;
1da177e4
LT		 1220
1221 np = pci_device_to_OF_node(pdev);
1222 if (np == NULL) {
1223 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1224 return -ENODEV;
1225 }
1226 i = 0;
1227 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1228 || pmac_ide[i].node != NULL))
1229 ++i;
1230 if (i >= MAX_HWIFS) {
1231 printk(KERN_ERR "ide-pmac: PCI interface attach with no slot\n");
1232 printk(KERN_ERR " %s\n", np->full_name);
1233 return -ENODEV;
1234 }
1235
1236 pmif = &pmac_ide[i];
1237 hwif = &ide_hwifs[i];
1238
1239 if (pci_enable_device(pdev)) {
1240 printk(KERN_WARNING "ide%i: Can't enable PCI device for %s\n",
1241 i, np->full_name);
1242 return -ENXIO;
1243 }
1244 pci_set_master(pdev);
1245
1246 if (pci_request_regions(pdev, "Kauai ATA")) {
1247 printk(KERN_ERR "ide%d: Cannot obtain PCI resources for %s\n",
1248 i, np->full_name);
1249 return -ENXIO;
1250 }
1251
36501650 1252 hwif->dev = &pdev->dev;
1da177e4
LT		 1253 pmif->mdev = NULL;
1254 pmif->node = np;
1255
1256 rbase = pci_resource_start(pdev, 0);
1257 rlen = pci_resource_len(pdev, 0);
1258
1259 base = ioremap(rbase, rlen);
1260 pmif->regbase = (unsigned long) base + 0x2000;
1261#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1262 pmif->dma_regs = base + 0x1000;
1263#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1264 pmif->kauai_fcr = base;
1265 pmif->irq = pdev->irq;
1266
1267 pci_set_drvdata(pdev, hwif);
1268
57c802e8 1269 memset(&hw, 0, sizeof(hw));
5c58666f 1270 pmac_ide_init_ports(&hw, pmif->regbase);
57c802e8
BZ		 1271 hw.irq = pdev->irq;
1272 hw.dev = &pdev->dev;
1273
1274 rc = pmac_ide_setup_device(pmif, hwif, &hw);
1da177e4
LT		 1275 if (rc != 0) {
1276 /* The inteface is released to the common IDE layer */
1277 pci_set_drvdata(pdev, NULL);
1278 iounmap(base);
1279 memset(pmif, 0, sizeof(*pmif));
1280 pci_release_regions(pdev);
1281 }
1282
1283 return rc;
1284}
1285
1286static int
8b4b8a24 1287pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
1da177e4
LT		 1288{
1289 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1290 int rc = 0;
1291
8b4b8a24 1292 if (mesg.event != pdev->dev.power.power_state.event
3a2d5b70 1293 && (mesg.event & PM_EVENT_SLEEP)) {
1da177e4
LT		 1294 rc = pmac_ide_do_suspend(hwif);
1295 if (rc == 0)
8b4b8a24 1296 pdev->dev.power.power_state = mesg;
1da177e4
LT		 1297 }
1298
1299 return rc;
1300}
1301
1302static int
1303pmac_ide_pci_resume(struct pci_dev *pdev)
1304{
1305 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1306 int rc = 0;
1307
ca078bae 1308 if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
1da177e4
LT		 1309 rc = pmac_ide_do_resume(hwif);
1310 if (rc == 0)
829ca9a3 1311 pdev->dev.power.power_state = PMSG_ON;
1da177e4
LT		 1312 }
1313
1314 return rc;
1315}
1316
5e655772 1317static struct of_device_id pmac_ide_macio_match[] =
1da177e4
LT		 1318{
1319 {
1320 .name = "IDE",
1da177e4
LT		 1321 },
1322 {
1323 .name = "ATA",
1da177e4
LT		 1324 },
1325 {
1da177e4 1326 .type = "ide",
1da177e4
LT		 1327 },
1328 {
1da177e4 1329 .type = "ata",
1da177e4
LT		 1330 },
1331 {},
1332};
1333
1334static struct macio_driver pmac_ide_macio_driver =
1335{
1336 .name = "ide-pmac",
1337 .match_table = pmac_ide_macio_match,
1338 .probe = pmac_ide_macio_attach,
1339 .suspend = pmac_ide_macio_suspend,
1340 .resume = pmac_ide_macio_resume,
1341};
1342
9cbcc5e3
BZ		 1343static const struct pci_device_id pmac_ide_pci_match[] = {
1344 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 },
1345 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 },
1346 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 },
1347 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 },
1348 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 },
71e4eda8 1349 {},
1da177e4
LT		 1350};
1351
1352static struct pci_driver pmac_ide_pci_driver = {
1353 .name = "ide-pmac",
1354 .id_table = pmac_ide_pci_match,
1355 .probe = pmac_ide_pci_attach,
1356 .suspend = pmac_ide_pci_suspend,
1357 .resume = pmac_ide_pci_resume,
1358};
1359MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1360
9e5755bc 1361int __init pmac_ide_probe(void)
1da177e4 1362{
9e5755bc
AM		 1363 int error;
1364
e8222502 1365 if (!machine_is(powermac))
9e5755bc 1366 return -ENODEV;
1da177e4
LT		 1367
1368#ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
9e5755bc
AM		 1369 error = pci_register_driver(&pmac_ide_pci_driver);
1370 if (error)
1371 goto out;
1372 error = macio_register_driver(&pmac_ide_macio_driver);
1373 if (error) {
1374 pci_unregister_driver(&pmac_ide_pci_driver);
1375 goto out;
1376 }
1da177e4 1377#else
9e5755bc
AM		 1378 error = macio_register_driver(&pmac_ide_macio_driver);
1379 if (error)
1380 goto out;
1381 error = pci_register_driver(&pmac_ide_pci_driver);
1382 if (error) {
1383 macio_unregister_driver(&pmac_ide_macio_driver);
1384 goto out;
1385 }
1beb6a7d 1386#endif
9e5755bc
AM		 1387out:
1388 return error;
1da177e4
LT		 1389}
1390
1391#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1392
1393/*
1394 * pmac_ide_build_dmatable builds the DBDMA command list
1395 * for a transfer and sets the DBDMA channel to point to it.
1396 */
aacaf9bd 1397static int
1da177e4
LT		 1398pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq)
1399{
1400 struct dbdma_cmd *table;
1401 int i, count = 0;
1402 ide_hwif_t *hwif = HWIF(drive);
1403 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1404 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1405 struct scatterlist *sg;
1406 int wr = (rq_data_dir(rq) == WRITE);
1407
1408 /* DMA table is already aligned */
1409 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1410
1411 /* Make sure DMA controller is stopped (necessary ?) */
1412 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1413 while (readl(&dma->status) & RUN)
1414 udelay(1);
1415
1416 hwif->sg_nents = i = ide_build_sglist(drive, rq);
1417
1418 if (!i)
1419 return 0;
1420
1421 /* Build DBDMA commands list */
1422 sg = hwif->sg_table;
1423 while (i && sg_dma_len(sg)) {
1424 u32 cur_addr;
1425 u32 cur_len;
1426
1427 cur_addr = sg_dma_address(sg);
1428 cur_len = sg_dma_len(sg);
1429
1430 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1431 if (pmif->broken_dma_warn == 0) {
aca38a51 1432 printk(KERN_WARNING "%s: DMA on non aligned address, "
1da177e4
LT		 1433 "switching to PIO on Ohare chipset\n", drive->name);
1434 pmif->broken_dma_warn = 1;
1435 }
1436 goto use_pio_instead;
1437 }
1438 while (cur_len) {
1439 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1440
1441 if (count++ >= MAX_DCMDS) {
1442 printk(KERN_WARNING "%s: DMA table too small\n",
1443 drive->name);
1444 goto use_pio_instead;
1445 }
1446 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1447 st_le16(&table->req_count, tc);
1448 st_le32(&table->phy_addr, cur_addr);
1449 table->cmd_dep = 0;
1450 table->xfer_status = 0;
1451 table->res_count = 0;
1452 cur_addr += tc;
1453 cur_len -= tc;
1454 ++table;
1455 }
55c16a70 1456 sg = sg_next(sg);
1da177e4
LT		 1457 i--;
1458 }
1459
1460 /* convert the last command to an input/output last command */
1461 if (count) {
1462 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1463 /* add the stop command to the end of the list */
1464 memset(table, 0, sizeof(struct dbdma_cmd));
1465 st_le16(&table->command, DBDMA_STOP);
1466 mb();
1467 writel(hwif->dmatable_dma, &dma->cmdptr);
1468 return 1;
1469 }
1470
1471 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
f6fb786d
BZ		 1472
1473use_pio_instead:
1474 ide_destroy_dmatable(drive);
1475
1da177e4
LT		 1476 return 0; /* revert to PIO for this request */
1477}
1478
1479/* Teardown mappings after DMA has completed. */
aacaf9bd 1480static void
1da177e4
LT		 1481pmac_ide_destroy_dmatable (ide_drive_t *drive)
1482{
1483 ide_hwif_t *hwif = drive->hwif;
1da177e4 1484
f6fb786d
BZ		 1485 if (hwif->sg_nents) {
1486 ide_destroy_dmatable(drive);
1da177e4
LT		 1487 hwif->sg_nents = 0;
1488 }
1489}
1490
1da177e4
LT		 1491/*
1492 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1493 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1494 */
aacaf9bd 1495static int
1da177e4
LT		 1496pmac_ide_dma_setup(ide_drive_t *drive)
1497{
1498 ide_hwif_t *hwif = HWIF(drive);
1499 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1500 struct request *rq = HWGROUP(drive)->rq;
1501 u8 unit = (drive->select.b.unit & 0x01);
1502 u8 ata4;
1503
1504 if (pmif == NULL)
1505 return 1;
1506 ata4 = (pmif->kind == controller_kl_ata4);
1507
1508 if (!pmac_ide_build_dmatable(drive, rq)) {
1509 ide_map_sg(drive, rq);
1510 return 1;
1511 }
1512
1513 /* Apple adds 60ns to wrDataSetup on reads */
1514 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1515 writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0),
1516 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1517 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1518 }
1519
1520 drive->waiting_for_dma = 1;
1521
1522 return 0;
1523}
1524
aacaf9bd 1525static void
1da177e4
LT		 1526pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
1527{
1528 /* issue cmd to drive */
1529 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL);
1530}
1531
1532/*
1533 * Kick the DMA controller into life after the DMA command has been issued
1534 * to the drive.
1535 */
aacaf9bd 1536static void
1da177e4
LT		 1537pmac_ide_dma_start(ide_drive_t *drive)
1538{
1539 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1540 volatile struct dbdma_regs __iomem *dma;
1541
1542 dma = pmif->dma_regs;
1543
1544 writel((RUN << 16) | RUN, &dma->control);
1545 /* Make sure it gets to the controller right now */
1546 (void)readl(&dma->control);
1547}
1548
1549/*
1550 * After a DMA transfer, make sure the controller is stopped
1551 */
aacaf9bd 1552static int
1da177e4
LT		 1553pmac_ide_dma_end (ide_drive_t *drive)
1554{
1555 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1556 volatile struct dbdma_regs __iomem *dma;
1557 u32 dstat;
1558
1559 if (pmif == NULL)
1560 return 0;
1561 dma = pmif->dma_regs;
1562
1563 drive->waiting_for_dma = 0;
1564 dstat = readl(&dma->status);
1565 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
1566 pmac_ide_destroy_dmatable(drive);
1567 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1568 * in theory, but with ATAPI decices doing buffer underruns, that would
1569 * cause us to disable DMA, which isn't what we want
1570 */
1571 return (dstat & (RUN|DEAD)) != RUN;
1572}
1573
1574/*
1575 * Check out that the interrupt we got was for us. We can't always know this
1576 * for sure with those Apple interfaces (well, we could on the recent ones but
1577 * that's not implemented yet), on the other hand, we don't have shared interrupts
1578 * so it's not really a problem
1579 */
aacaf9bd 1580static int
1da177e4
LT		 1581pmac_ide_dma_test_irq (ide_drive_t *drive)
1582{
1583 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1584 volatile struct dbdma_regs __iomem *dma;
1585 unsigned long status, timeout;
1586
1587 if (pmif == NULL)
1588 return 0;
1589 dma = pmif->dma_regs;
1590
1591 /* We have to things to deal with here:
1592 *
1593 * - The dbdma won't stop if the command was started
1594 * but completed with an error without transferring all
1595 * datas. This happens when bad blocks are met during
1596 * a multi-block transfer.
1597 *
1598 * - The dbdma fifo hasn't yet finished flushing to
1599 * to system memory when the disk interrupt occurs.
1600 *
1601 */
1602
1603 /* If ACTIVE is cleared, the STOP command have passed and
1604 * transfer is complete.
1605 */
1606 status = readl(&dma->status);
1607 if (!(status & ACTIVE))
1608 return 1;
1609 if (!drive->waiting_for_dma)
1610 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1611 called while not waiting\n", HWIF(drive)->index);
1612
1613 /* If dbdma didn't execute the STOP command yet, the
1614 * active bit is still set. We consider that we aren't
1615 * sharing interrupts (which is hopefully the case with
1616 * those controllers) and so we just try to flush the
1617 * channel for pending data in the fifo
1618 */
1619 udelay(1);
1620 writel((FLUSH << 16) | FLUSH, &dma->control);
1621 timeout = 0;
1622 for (;;) {
1623 udelay(1);
1624 status = readl(&dma->status);
1625 if ((status & FLUSH) == 0)
1626 break;
1627 if (++timeout > 100) {
1628 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1629 timeout flushing channel\n", HWIF(drive)->index);
1630 break;
1631 }
1632 }
1633 return 1;
1634}
1635
15ce926a 1636static void pmac_ide_dma_host_set(ide_drive_t *drive, int on)
1da177e4 1637{
1da177e4
LT		 1638}
1639
841d2a9b
SS		 1640static void
1641pmac_ide_dma_lost_irq (ide_drive_t *drive)
1da177e4
LT		 1642{
1643 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1644 volatile struct dbdma_regs __iomem *dma;
1645 unsigned long status;
1646
1647 if (pmif == NULL)
841d2a9b 1648 return;
1da177e4
LT		 1649 dma = pmif->dma_regs;
1650
1651 status = readl(&dma->status);
1652 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
1da177e4
LT		 1653}
1654
1655/*
1656 * Allocate the data structures needed for using DMA with an interface
1657 * and fill the proper list of functions pointers
1658 */
c413b9b9 1659static int __devinit pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1da177e4 1660{
36501650
BZ		 1661 struct pci_dev *dev = to_pci_dev(hwif->dev);
1662
1da177e4
LT		 1663 /* We won't need pci_dev if we switch to generic consistent
1664 * DMA routines ...
1665 */
36501650 1666 if (dev == NULL)
c413b9b9 1667 return -ENODEV;
1da177e4
LT		 1668 /*
1669 * Allocate space for the DBDMA commands.
1670 * The +2 is +1 for the stop command and +1 to allow for
1671 * aligning the start address to a multiple of 16 bytes.
1672 */
1673 pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent(
36501650 1674 dev,
1da177e4
LT		 1675 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
1676 &hwif->dmatable_dma);
1677 if (pmif->dma_table_cpu == NULL) {
1678 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
1679 hwif->name);
c413b9b9 1680 return -ENOMEM;
1da177e4
LT		 1681 }
1682
4f52a329
BZ		 1683 hwif->sg_max_nents = MAX_DCMDS;
1684
15ce926a 1685 hwif->dma_host_set = &pmac_ide_dma_host_set;
1da177e4
LT		 1686 hwif->dma_setup = &pmac_ide_dma_setup;
1687 hwif->dma_exec_cmd = &pmac_ide_dma_exec_cmd;
1688 hwif->dma_start = &pmac_ide_dma_start;
1689 hwif->ide_dma_end = &pmac_ide_dma_end;
1690 hwif->ide_dma_test_irq = &pmac_ide_dma_test_irq;
c283f5db 1691 hwif->dma_timeout = &ide_dma_timeout;
841d2a9b 1692 hwif->dma_lost_irq = &pmac_ide_dma_lost_irq;
1da177e4 1693
c413b9b9 1694 return 0;
1da177e4
LT		 1695}
1696
1697#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
ade2daf9
BZ		 1698
1699module_init(pmac_ide_probe);
de9facbf
AB		 1700
1701MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)