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[PATCH] powerpc: Fix platinumfb for some modes
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / ppc / pmac.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/ide/ide-pmac.c
3 *
4 * Support for IDE interfaces on PowerMacs.
5 * These IDE interfaces are memory-mapped and have a DBDMA channel
6 * for doing DMA.
7 *
8 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 * Some code taken from drivers/ide/ide-dma.c:
16 *
17 * Copyright (c) 1995-1998 Mark Lord
18 *
19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
20 * get rid of the "rounded" tables used previously, so we have the
21 * same table format for all controllers and can then just have one
22 * big table
23 *
24 */
25#include <linux/config.h>
26#include <linux/types.h>
27#include <linux/kernel.h>
28#include <linux/sched.h>
29#include <linux/init.h>
30#include <linux/delay.h>
31#include <linux/ide.h>
32#include <linux/notifier.h>
33#include <linux/reboot.h>
34#include <linux/pci.h>
35#include <linux/adb.h>
36#include <linux/pmu.h>
37#include <linux/scatterlist.h>
38
39#include <asm/prom.h>
40#include <asm/io.h>
41#include <asm/dbdma.h>
42#include <asm/ide.h>
43#include <asm/pci-bridge.h>
44#include <asm/machdep.h>
45#include <asm/pmac_feature.h>
46#include <asm/sections.h>
47#include <asm/irq.h>
48
49#ifndef CONFIG_PPC64
50#include <asm/mediabay.h>
51#endif
52
53#include "ide-timing.h"
54
55#undef IDE_PMAC_DEBUG
56
57#define DMA_WAIT_TIMEOUT 50
58
59typedef struct pmac_ide_hwif {
60 unsigned long regbase;
61 int irq;
62 int kind;
63 int aapl_bus_id;
64 unsigned cable_80 : 1;
65 unsigned mediabay : 1;
66 unsigned broken_dma : 1;
67 unsigned broken_dma_warn : 1;
68 struct device_node* node;
69 struct macio_dev *mdev;
70 u32 timings[4];
71 volatile u32 __iomem * *kauai_fcr;
72#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
73 /* Those fields are duplicating what is in hwif. We currently
74 * can't use the hwif ones because of some assumptions that are
75 * beeing done by the generic code about the kind of dma controller
76 * and format of the dma table. This will have to be fixed though.
77 */
78 volatile struct dbdma_regs __iomem * dma_regs;
79 struct dbdma_cmd* dma_table_cpu;
80#endif
81
82} pmac_ide_hwif_t;
83
aacaf9bd 84static pmac_ide_hwif_t pmac_ide[MAX_HWIFS];
1da177e4
LT		 85static int pmac_ide_count;
86
87enum {
88 controller_ohare, /* OHare based */
89 controller_heathrow, /* Heathrow/Paddington */
90 controller_kl_ata3, /* KeyLargo ATA-3 */
91 controller_kl_ata4, /* KeyLargo ATA-4 */
92 controller_un_ata6, /* UniNorth2 ATA-6 */
93 controller_k2_ata6, /* K2 ATA-6 */
94 controller_sh_ata6, /* Shasta ATA-6 */
95};
96
97static const char* model_name[] = {
98 "OHare ATA", /* OHare based */
99 "Heathrow ATA", /* Heathrow/Paddington */
100 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
101 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
102 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
103 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
104 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
105};
106
107/*
108 * Extra registers, both 32-bit little-endian
109 */
110#define IDE_TIMING_CONFIG 0x200
111#define IDE_INTERRUPT 0x300
112
113/* Kauai (U2) ATA has different register setup */
114#define IDE_KAUAI_PIO_CONFIG 0x200
115#define IDE_KAUAI_ULTRA_CONFIG 0x210
116#define IDE_KAUAI_POLL_CONFIG 0x220
117
118/*
119 * Timing configuration register definitions
120 */
121
122/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
123#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
124#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
125#define IDE_SYSCLK_NS 30 /* 33Mhz cell */
126#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
127
128/* 133Mhz cell, found in shasta.
129 * See comments about 100 Mhz Uninorth 2...
130 * Note that PIO_MASK and MDMA_MASK seem to overlap
131 */
132#define TR_133_PIOREG_PIO_MASK 0xff000fff
133#define TR_133_PIOREG_MDMA_MASK 0x00fff800
134#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
135#define TR_133_UDMAREG_UDMA_EN 0x00000001
136
137/* 100Mhz cell, found in Uninorth 2. I don't have much infos about
138 * this one yet, it appears as a pci device (106b/0033) on uninorth
139 * internal PCI bus and it's clock is controlled like gem or fw. It
140 * appears to be an evolution of keylargo ATA4 with a timing register
141 * extended to 2 32bits registers and a similar DBDMA channel. Other
142 * registers seem to exist but I can't tell much about them.
143 *
144 * So far, I'm using pre-calculated tables for this extracted from
145 * the values used by the MacOS X driver.
146 *
147 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
148 * register controls the UDMA timings. At least, it seems bit 0
149 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
150 * cycle time in units of 10ns. Bits 8..15 are used by I don't
151 * know their meaning yet
152 */
153#define TR_100_PIOREG_PIO_MASK 0xff000fff
154#define TR_100_PIOREG_MDMA_MASK 0x00fff000
155#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
156#define TR_100_UDMAREG_UDMA_EN 0x00000001
157
158
159/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
160 * 40 connector cable and to 4 on 80 connector one.
161 * Clock unit is 15ns (66Mhz)
162 *
163 * 3 Values can be programmed:
164 * - Write data setup, which appears to match the cycle time. They
165 * also call it DIOW setup.
166 * - Ready to pause time (from spec)
167 * - Address setup. That one is weird. I don't see where exactly
168 * it fits in UDMA cycles, I got it's name from an obscure piece
169 * of commented out code in Darwin. They leave it to 0, we do as
170 * well, despite a comment that would lead to think it has a
171 * min value of 45ns.
172 * Apple also add 60ns to the write data setup (or cycle time ?) on
173 * reads.
174 */
175#define TR_66_UDMA_MASK 0xfff00000
176#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
177#define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
178#define TR_66_UDMA_ADDRSETUP_SHIFT 29
179#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
180#define TR_66_UDMA_RDY2PAUS_SHIFT 25
181#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
182#define TR_66_UDMA_WRDATASETUP_SHIFT 21
183#define TR_66_MDMA_MASK 0x000ffc00
184#define TR_66_MDMA_RECOVERY_MASK 0x000f8000
185#define TR_66_MDMA_RECOVERY_SHIFT 15
186#define TR_66_MDMA_ACCESS_MASK 0x00007c00
187#define TR_66_MDMA_ACCESS_SHIFT 10
188#define TR_66_PIO_MASK 0x000003ff
189#define TR_66_PIO_RECOVERY_MASK 0x000003e0
190#define TR_66_PIO_RECOVERY_SHIFT 5
191#define TR_66_PIO_ACCESS_MASK 0x0000001f
192#define TR_66_PIO_ACCESS_SHIFT 0
193
194/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
195 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
196 *
197 * The access time and recovery time can be programmed. Some older
198 * Darwin code base limit OHare to 150ns cycle time. I decided to do
199 * the same here fore safety against broken old hardware ;)
200 * The HalfTick bit, when set, adds half a clock (15ns) to the access
201 * time and removes one from recovery. It's not supported on KeyLargo
202 * implementation afaik. The E bit appears to be set for PIO mode 0 and
203 * is used to reach long timings used in this mode.
204 */
205#define TR_33_MDMA_MASK 0x003ff800
206#define TR_33_MDMA_RECOVERY_MASK 0x001f0000
207#define TR_33_MDMA_RECOVERY_SHIFT 16
208#define TR_33_MDMA_ACCESS_MASK 0x0000f800
209#define TR_33_MDMA_ACCESS_SHIFT 11
210#define TR_33_MDMA_HALFTICK 0x00200000
211#define TR_33_PIO_MASK 0x000007ff
212#define TR_33_PIO_E 0x00000400
213#define TR_33_PIO_RECOVERY_MASK 0x000003e0
214#define TR_33_PIO_RECOVERY_SHIFT 5
215#define TR_33_PIO_ACCESS_MASK 0x0000001f
216#define TR_33_PIO_ACCESS_SHIFT 0
217
218/*
219 * Interrupt register definitions
220 */
221#define IDE_INTR_DMA 0x80000000
222#define IDE_INTR_DEVICE 0x40000000
223
224/*
225 * FCR Register on Kauai. Not sure what bit 0x4 is ...
226 */
227#define KAUAI_FCR_UATA_MAGIC 0x00000004
228#define KAUAI_FCR_UATA_RESET_N 0x00000002
229#define KAUAI_FCR_UATA_ENABLE 0x00000001
230
231#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
232
233/* Rounded Multiword DMA timings
234 *
235 * I gave up finding a generic formula for all controller
236 * types and instead, built tables based on timing values
237 * used by Apple in Darwin's implementation.
238 */
239struct mdma_timings_t {
240 int accessTime;
241 int recoveryTime;
242 int cycleTime;
243};
244
aacaf9bd 245struct mdma_timings_t mdma_timings_33[] =
1da177e4
LT		 246{
247 { 240, 240, 480 },
248 { 180, 180, 360 },
249 { 135, 135, 270 },
250 { 120, 120, 240 },
251 { 105, 105, 210 },
252 { 90, 90, 180 },
253 { 75, 75, 150 },
254 { 75, 45, 120 },
255 { 0, 0, 0 }
256};
257
aacaf9bd 258struct mdma_timings_t mdma_timings_33k[] =
1da177e4
LT		 259{
260 { 240, 240, 480 },
261 { 180, 180, 360 },
262 { 150, 150, 300 },
263 { 120, 120, 240 },
264 { 90, 120, 210 },
265 { 90, 90, 180 },
266 { 90, 60, 150 },
267 { 90, 30, 120 },
268 { 0, 0, 0 }
269};
270
aacaf9bd 271struct mdma_timings_t mdma_timings_66[] =
1da177e4
LT		 272{
273 { 240, 240, 480 },
274 { 180, 180, 360 },
275 { 135, 135, 270 },
276 { 120, 120, 240 },
277 { 105, 105, 210 },
278 { 90, 90, 180 },
279 { 90, 75, 165 },
280 { 75, 45, 120 },
281 { 0, 0, 0 }
282};
283
284/* KeyLargo ATA-4 Ultra DMA timings (rounded) */
285struct {
286 int addrSetup; /* ??? */
287 int rdy2pause;
288 int wrDataSetup;
aacaf9bd 289} kl66_udma_timings[] =
1da177e4
LT		 290{
291 { 0, 180, 120 }, /* Mode 0 */
292 { 0, 150, 90 }, /* 1 */
293 { 0, 120, 60 }, /* 2 */
294 { 0, 90, 45 }, /* 3 */
295 { 0, 90, 30 } /* 4 */
296};
297
298/* UniNorth 2 ATA/100 timings */
299struct kauai_timing {
300 int cycle_time;
301 u32 timing_reg;
302};
303
aacaf9bd 304static struct kauai_timing kauai_pio_timings[] =
1da177e4
LT		 305{
306 { 930 , 0x08000fff },
307 { 600 , 0x08000a92 },
308 { 383 , 0x0800060f },
309 { 360 , 0x08000492 },
310 { 330 , 0x0800048f },
311 { 300 , 0x080003cf },
312 { 270 , 0x080003cc },
313 { 240 , 0x0800038b },
314 { 239 , 0x0800030c },
315 { 180 , 0x05000249 },
316 { 120 , 0x04000148 }
317};
318
aacaf9bd 319static struct kauai_timing kauai_mdma_timings[] =
1da177e4
LT		 320{
321 { 1260 , 0x00fff000 },
322 { 480 , 0x00618000 },
323 { 360 , 0x00492000 },
324 { 270 , 0x0038e000 },
325 { 240 , 0x0030c000 },
326 { 210 , 0x002cb000 },
327 { 180 , 0x00249000 },
328 { 150 , 0x00209000 },
329 { 120 , 0x00148000 },
330 { 0 , 0 },
331};
332
aacaf9bd 333static struct kauai_timing kauai_udma_timings[] =
1da177e4
LT		 334{
335 { 120 , 0x000070c0 },
336 { 90 , 0x00005d80 },
337 { 60 , 0x00004a60 },
338 { 45 , 0x00003a50 },
339 { 30 , 0x00002a30 },
340 { 20 , 0x00002921 },
341 { 0 , 0 },
342};
343
aacaf9bd 344static struct kauai_timing shasta_pio_timings[] =
1da177e4
LT		 345{
346 { 930 , 0x08000fff },
347 { 600 , 0x0A000c97 },
348 { 383 , 0x07000712 },
349 { 360 , 0x040003cd },
350 { 330 , 0x040003cd },
351 { 300 , 0x040003cd },
352 { 270 , 0x040003cd },
353 { 240 , 0x040003cd },
354 { 239 , 0x040003cd },
355 { 180 , 0x0400028b },
356 { 120 , 0x0400010a }
357};
358
aacaf9bd 359static struct kauai_timing shasta_mdma_timings[] =
1da177e4
LT		 360{
361 { 1260 , 0x00fff000 },
362 { 480 , 0x00820800 },
363 { 360 , 0x00820800 },
364 { 270 , 0x00820800 },
365 { 240 , 0x00820800 },
366 { 210 , 0x00820800 },
367 { 180 , 0x00820800 },
368 { 150 , 0x0028b000 },
369 { 120 , 0x001ca000 },
370 { 0 , 0 },
371};
372
aacaf9bd 373static struct kauai_timing shasta_udma133_timings[] =
1da177e4
LT		 374{
375 { 120 , 0x00035901, },
376 { 90 , 0x000348b1, },
377 { 60 , 0x00033881, },
378 { 45 , 0x00033861, },
379 { 30 , 0x00033841, },
380 { 20 , 0x00033031, },
381 { 15 , 0x00033021, },
382 { 0 , 0 },
383};
384
385
386static inline u32
387kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
388{
389 int i;
390
391 for (i=0; table[i].cycle_time; i++)
392 if (cycle_time > table[i+1].cycle_time)
393 return table[i].timing_reg;
394 return 0;
395}
396
397/* allow up to 256 DBDMA commands per xfer */
398#define MAX_DCMDS 256
399
400/*
401 * Wait 1s for disk to answer on IDE bus after a hard reset
402 * of the device (via GPIO/FCR).
403 *
404 * Some devices seem to "pollute" the bus even after dropping
405 * the BSY bit (typically some combo drives slave on the UDMA
406 * bus) after a hard reset. Since we hard reset all drives on
407 * KeyLargo ATA66, we have to keep that delay around. I may end
408 * up not hard resetting anymore on these and keep the delay only
409 * for older interfaces instead (we have to reset when coming
410 * from MacOS...) --BenH.
411 */
412#define IDE_WAKEUP_DELAY (1*HZ)
413
414static void pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif);
415static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq);
416static int pmac_ide_tune_chipset(ide_drive_t *drive, u8 speed);
417static void pmac_ide_tuneproc(ide_drive_t *drive, u8 pio);
418static void pmac_ide_selectproc(ide_drive_t *drive);
419static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
420
421#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
422
423/*
424 * Below is the code for blinking the laptop LED along with hard
425 * disk activity.
426 */
427
428#ifdef CONFIG_BLK_DEV_IDE_PMAC_BLINK
429
430/* Set to 50ms minimum led-on time (also used to limit frequency
431 * of requests sent to the PMU
432 */
433#define PMU_HD_BLINK_TIME (HZ/50)
434
435static struct adb_request pmu_blink_on, pmu_blink_off;
436static spinlock_t pmu_blink_lock;
437static unsigned long pmu_blink_stoptime;
438static int pmu_blink_ledstate;
439static struct timer_list pmu_blink_timer;
440static int pmu_ide_blink_enabled;
441
442
443static void
444pmu_hd_blink_timeout(unsigned long data)
445{
446 unsigned long flags;
447
448 spin_lock_irqsave(&pmu_blink_lock, flags);
449
450 /* We may have been triggered again in a racy way, check
451 * that we really want to switch it off
452 */
453 if (time_after(pmu_blink_stoptime, jiffies))
454 goto done;
455
456 /* Previous req. not complete, try 100ms more */
457 if (pmu_blink_off.complete == 0)
458 mod_timer(&pmu_blink_timer, jiffies + PMU_HD_BLINK_TIME);
459 else if (pmu_blink_ledstate) {
460 pmu_request(&pmu_blink_off, NULL, 4, 0xee, 4, 0, 0);
461 pmu_blink_ledstate = 0;
462 }
463done:
464 spin_unlock_irqrestore(&pmu_blink_lock, flags);
465}
466
467static void
468pmu_hd_kick_blink(void *data, int rw)
469{
470 unsigned long flags;
471
472 pmu_blink_stoptime = jiffies + PMU_HD_BLINK_TIME;
473 wmb();
474 mod_timer(&pmu_blink_timer, pmu_blink_stoptime);
475 /* Fast path when LED is already ON */
476 if (pmu_blink_ledstate == 1)
477 return;
478 spin_lock_irqsave(&pmu_blink_lock, flags);
479 if (pmu_blink_on.complete && !pmu_blink_ledstate) {
480 pmu_request(&pmu_blink_on, NULL, 4, 0xee, 4, 0, 1);
481 pmu_blink_ledstate = 1;
482 }
483 spin_unlock_irqrestore(&pmu_blink_lock, flags);
484}
485
486static int
487pmu_hd_blink_init(void)
488{
489 struct device_node *dt;
490 const char *model;
491
492 /* Currently, I only enable this feature on KeyLargo based laptops,
493 * older laptops may support it (at least heathrow/paddington) but
494 * I don't feel like loading those venerable old machines with so
495 * much additional interrupt & PMU activity...
496 */
497 if (pmu_get_model() != PMU_KEYLARGO_BASED)
498 return 0;
499
42596ec5 500 dt = of_find_node_by_path("/");
1da177e4
LT		 501 if (dt == NULL)
502 return 0;
503 model = (const char *)get_property(dt, "model", NULL);
504 if (model == NULL)
505 return 0;
506 if (strncmp(model, "PowerBook", strlen("PowerBook")) != 0 &&
42596ec5
BH		 507 strncmp(model, "iBook", strlen("iBook")) != 0) {
508 of_node_put(dt);
1da177e4 509 return 0;
42596ec5
BH		 510 }
511 of_node_put(dt);
512
1da177e4
LT		 513 pmu_blink_on.complete = 1;
514 pmu_blink_off.complete = 1;
515 spin_lock_init(&pmu_blink_lock);
516 init_timer(&pmu_blink_timer);
517 pmu_blink_timer.function = pmu_hd_blink_timeout;
518
519 return 1;
520}
521
522#endif /* CONFIG_BLK_DEV_IDE_PMAC_BLINK */
523
524/*
525 * N.B. this can't be an initfunc, because the media-bay task can
526 * call ide_[un]register at any time.
527 */
aacaf9bd 528void
1da177e4
LT		 529pmac_ide_init_hwif_ports(hw_regs_t *hw,
530 unsigned long data_port, unsigned long ctrl_port,
531 int *irq)
532{
533 int i, ix;
534
535 if (data_port == 0)
536 return;
537
538 for (ix = 0; ix < MAX_HWIFS; ++ix)
539 if (data_port == pmac_ide[ix].regbase)
540 break;
541
542 if (ix >= MAX_HWIFS) {
543 /* Probably a PCI interface... */
544 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; ++i)
545 hw->io_ports[i] = data_port + i - IDE_DATA_OFFSET;
546 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
547 return;
548 }
549
550 for (i = 0; i < 8; ++i)
551 hw->io_ports[i] = data_port + i * 0x10;
552 hw->io_ports[8] = data_port + 0x160;
553
554 if (irq != NULL)
555 *irq = pmac_ide[ix].irq;
556}
557
558#define PMAC_IDE_REG(x) ((void __iomem *)(IDE_DATA_REG+(x)))
559
560/*
561 * Apply the timings of the proper unit (master/slave) to the shared
562 * timing register when selecting that unit. This version is for
563 * ASICs with a single timing register
564 */
aacaf9bd 565static void
1da177e4
LT		 566pmac_ide_selectproc(ide_drive_t *drive)
567{
568 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
569
570 if (pmif == NULL)
571 return;
572
573 if (drive->select.b.unit & 0x01)
574 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
575 else
576 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
577 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
578}
579
580/*
581 * Apply the timings of the proper unit (master/slave) to the shared
582 * timing register when selecting that unit. This version is for
583 * ASICs with a dual timing register (Kauai)
584 */
aacaf9bd 585static void
1da177e4
LT		 586pmac_ide_kauai_selectproc(ide_drive_t *drive)
587{
588 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
589
590 if (pmif == NULL)
591 return;
592
593 if (drive->select.b.unit & 0x01) {
594 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
595 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
596 } else {
597 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
598 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
599 }
600 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
601}
602
603/*
604 * Force an update of controller timing values for a given drive
605 */
aacaf9bd 606static void
1da177e4
LT		 607pmac_ide_do_update_timings(ide_drive_t *drive)
608{
609 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
610
611 if (pmif == NULL)
612 return;
613
614 if (pmif->kind == controller_sh_ata6 ||
615 pmif->kind == controller_un_ata6 ||
616 pmif->kind == controller_k2_ata6)
617 pmac_ide_kauai_selectproc(drive);
618 else
619 pmac_ide_selectproc(drive);
620}
621
622static void
623pmac_outbsync(ide_drive_t *drive, u8 value, unsigned long port)
624{
625 u32 tmp;
626
627 writeb(value, (void __iomem *) port);
628 tmp = readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
629}
630
631/*
632 * Send the SET_FEATURE IDE command to the drive and update drive->id with
633 * the new state. We currently don't use the generic routine as it used to
634 * cause various trouble, especially with older mediabays.
635 * This code is sometimes triggering a spurrious interrupt though, I need
636 * to sort that out sooner or later and see if I can finally get the
637 * common version to work properly in all cases
638 */
aacaf9bd 639static int
1da177e4
LT		 640pmac_ide_do_setfeature(ide_drive_t *drive, u8 command)
641{
642 ide_hwif_t *hwif = HWIF(drive);
643 int result = 1;
644
645 disable_irq_nosync(hwif->irq);
646 udelay(1);
647 SELECT_DRIVE(drive);
648 SELECT_MASK(drive, 0);
649 udelay(1);
650 /* Get rid of pending error state */
651 (void) hwif->INB(IDE_STATUS_REG);
652 /* Timeout bumped for some powerbooks */
653 if (wait_for_ready(drive, 2000)) {
654 /* Timeout bumped for some powerbooks */
655 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
656 "before SET_FEATURE!\n", drive->name);
657 goto out;
658 }
659 udelay(10);
660 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
661 hwif->OUTB(command, IDE_NSECTOR_REG);
662 hwif->OUTB(SETFEATURES_XFER, IDE_FEATURE_REG);
663 hwif->OUTBSYNC(drive, WIN_SETFEATURES, IDE_COMMAND_REG);
664 udelay(1);
665 /* Timeout bumped for some powerbooks */
666 result = wait_for_ready(drive, 2000);
667 hwif->OUTB(drive->ctl, IDE_CONTROL_REG);
668 if (result)
669 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
670 "after SET_FEATURE !\n", drive->name);
671out:
672 SELECT_MASK(drive, 0);
673 if (result == 0) {
674 drive->id->dma_ultra &= ~0xFF00;
675 drive->id->dma_mword &= ~0x0F00;
676 drive->id->dma_1word &= ~0x0F00;
677 switch(command) {
678 case XFER_UDMA_7:
679 drive->id->dma_ultra |= 0x8080; break;
680 case XFER_UDMA_6:
681 drive->id->dma_ultra |= 0x4040; break;
682 case XFER_UDMA_5:
683 drive->id->dma_ultra |= 0x2020; break;
684 case XFER_UDMA_4:
685 drive->id->dma_ultra |= 0x1010; break;
686 case XFER_UDMA_3:
687 drive->id->dma_ultra |= 0x0808; break;
688 case XFER_UDMA_2:
689 drive->id->dma_ultra |= 0x0404; break;
690 case XFER_UDMA_1:
691 drive->id->dma_ultra |= 0x0202; break;
692 case XFER_UDMA_0:
693 drive->id->dma_ultra |= 0x0101; break;
694 case XFER_MW_DMA_2:
695 drive->id->dma_mword |= 0x0404; break;
696 case XFER_MW_DMA_1:
697 drive->id->dma_mword |= 0x0202; break;
698 case XFER_MW_DMA_0:
699 drive->id->dma_mword |= 0x0101; break;
700 case XFER_SW_DMA_2:
701 drive->id->dma_1word |= 0x0404; break;
702 case XFER_SW_DMA_1:
703 drive->id->dma_1word |= 0x0202; break;
704 case XFER_SW_DMA_0:
705 drive->id->dma_1word |= 0x0101; break;
706 default: break;
707 }
708 }
709 enable_irq(hwif->irq);
710 return result;
711}
712
713/*
714 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
715 */
aacaf9bd 716static void
1da177e4
LT		 717pmac_ide_tuneproc(ide_drive_t *drive, u8 pio)
718{
719 ide_pio_data_t d;
720 u32 *timings;
721 unsigned accessTicks, recTicks;
722 unsigned accessTime, recTime;
723 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
724
725 if (pmif == NULL)
726 return;
727
728 /* which drive is it ? */
729 timings = &pmif->timings[drive->select.b.unit & 0x01];
730
731 pio = ide_get_best_pio_mode(drive, pio, 4, &d);
732
733 switch (pmif->kind) {
734 case controller_sh_ata6: {
735 /* 133Mhz cell */
736 u32 tr = kauai_lookup_timing(shasta_pio_timings, d.cycle_time);
737 if (tr == 0)
738 return;
739 *timings = ((*timings) & ~TR_133_PIOREG_PIO_MASK) | tr;
740 break;
741 }
742 case controller_un_ata6:
743 case controller_k2_ata6: {
744 /* 100Mhz cell */
745 u32 tr = kauai_lookup_timing(kauai_pio_timings, d.cycle_time);
746 if (tr == 0)
747 return;
748 *timings = ((*timings) & ~TR_100_PIOREG_PIO_MASK) | tr;
749 break;
750 }
751 case controller_kl_ata4:
752 /* 66Mhz cell */
753 recTime = d.cycle_time - ide_pio_timings[pio].active_time
754 - ide_pio_timings[pio].setup_time;
755 recTime = max(recTime, 150U);
756 accessTime = ide_pio_timings[pio].active_time;
757 accessTime = max(accessTime, 150U);
758 accessTicks = SYSCLK_TICKS_66(accessTime);
759 accessTicks = min(accessTicks, 0x1fU);
760 recTicks = SYSCLK_TICKS_66(recTime);
761 recTicks = min(recTicks, 0x1fU);
762 *timings = ((*timings) & ~TR_66_PIO_MASK) |
763 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
764 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
765 break;
766 default: {
767 /* 33Mhz cell */
768 int ebit = 0;
769 recTime = d.cycle_time - ide_pio_timings[pio].active_time
770 - ide_pio_timings[pio].setup_time;
771 recTime = max(recTime, 150U);
772 accessTime = ide_pio_timings[pio].active_time;
773 accessTime = max(accessTime, 150U);
774 accessTicks = SYSCLK_TICKS(accessTime);
775 accessTicks = min(accessTicks, 0x1fU);
776 accessTicks = max(accessTicks, 4U);
777 recTicks = SYSCLK_TICKS(recTime);
778 recTicks = min(recTicks, 0x1fU);
779 recTicks = max(recTicks, 5U) - 4;
780 if (recTicks > 9) {
781 recTicks--; /* guess, but it's only for PIO0, so... */
782 ebit = 1;
783 }
784 *timings = ((*timings) & ~TR_33_PIO_MASK) |
785 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
786 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
787 if (ebit)
788 *timings |= TR_33_PIO_E;
789 break;
790 }
791 }
792
793#ifdef IDE_PMAC_DEBUG
794 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
795 drive->name, pio, *timings);
796#endif
797
798 if (drive->select.all == HWIF(drive)->INB(IDE_SELECT_REG))
799 pmac_ide_do_update_timings(drive);
800}
801
802#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
803
804/*
805 * Calculate KeyLargo ATA/66 UDMA timings
806 */
aacaf9bd 807static int
1da177e4
LT		 808set_timings_udma_ata4(u32 *timings, u8 speed)
809{
810 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
811
812 if (speed > XFER_UDMA_4)
813 return 1;
814
815 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
816 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
817 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
818
819 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
820 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
821 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
822 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
823 TR_66_UDMA_EN;
824#ifdef IDE_PMAC_DEBUG
825 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
826 speed & 0xf, *timings);
827#endif
828
829 return 0;
830}
831
832/*
833 * Calculate Kauai ATA/100 UDMA timings
834 */
aacaf9bd 835static int
1da177e4
LT		 836set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
837{
838 struct ide_timing *t = ide_timing_find_mode(speed);
839 u32 tr;
840
841 if (speed > XFER_UDMA_5 || t == NULL)
842 return 1;
843 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
844 if (tr == 0)
845 return 1;
846 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
847 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
848
849 return 0;
850}
851
852/*
853 * Calculate Shasta ATA/133 UDMA timings
854 */
aacaf9bd 855static int
1da177e4
LT		 856set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
857{
858 struct ide_timing *t = ide_timing_find_mode(speed);
859 u32 tr;
860
861 if (speed > XFER_UDMA_6 || t == NULL)
862 return 1;
863 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
864 if (tr == 0)
865 return 1;
866 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
867 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
868
869 return 0;
870}
871
872/*
873 * Calculate MDMA timings for all cells
874 */
aacaf9bd 875static int
1da177e4
LT		 876set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
877 u8 speed, int drive_cycle_time)
878{
879 int cycleTime, accessTime = 0, recTime = 0;
880 unsigned accessTicks, recTicks;
881 struct mdma_timings_t* tm = NULL;
882 int i;
883
884 /* Get default cycle time for mode */
885 switch(speed & 0xf) {
886 case 0: cycleTime = 480; break;
887 case 1: cycleTime = 150; break;
888 case 2: cycleTime = 120; break;
889 default:
890 return 1;
891 }
892 /* Adjust for drive */
893 if (drive_cycle_time && drive_cycle_time > cycleTime)
894 cycleTime = drive_cycle_time;
895 /* OHare limits according to some old Apple sources */
896 if ((intf_type == controller_ohare) && (cycleTime < 150))
897 cycleTime = 150;
898 /* Get the proper timing array for this controller */
899 switch(intf_type) {
900 case controller_sh_ata6:
901 case controller_un_ata6:
902 case controller_k2_ata6:
903 break;
904 case controller_kl_ata4:
905 tm = mdma_timings_66;
906 break;
907 case controller_kl_ata3:
908 tm = mdma_timings_33k;
909 break;
910 default:
911 tm = mdma_timings_33;
912 break;
913 }
914 if (tm != NULL) {
915 /* Lookup matching access & recovery times */
916 i = -1;
917 for (;;) {
918 if (tm[i+1].cycleTime < cycleTime)
919 break;
920 i++;
921 }
922 if (i < 0)
923 return 1;
924 cycleTime = tm[i].cycleTime;
925 accessTime = tm[i].accessTime;
926 recTime = tm[i].recoveryTime;
927
928#ifdef IDE_PMAC_DEBUG
929 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
930 drive->name, cycleTime, accessTime, recTime);
931#endif
932 }
933 switch(intf_type) {
934 case controller_sh_ata6: {
935 /* 133Mhz cell */
936 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
937 if (tr == 0)
938 return 1;
939 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
940 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
941 }
942 case controller_un_ata6:
943 case controller_k2_ata6: {
944 /* 100Mhz cell */
945 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
946 if (tr == 0)
947 return 1;
948 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
949 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
950 }
951 break;
952 case controller_kl_ata4:
953 /* 66Mhz cell */
954 accessTicks = SYSCLK_TICKS_66(accessTime);
955 accessTicks = min(accessTicks, 0x1fU);
956 accessTicks = max(accessTicks, 0x1U);
957 recTicks = SYSCLK_TICKS_66(recTime);
958 recTicks = min(recTicks, 0x1fU);
959 recTicks = max(recTicks, 0x3U);
960 /* Clear out mdma bits and disable udma */
961 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
962 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
963 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
964 break;
965 case controller_kl_ata3:
966 /* 33Mhz cell on KeyLargo */
967 accessTicks = SYSCLK_TICKS(accessTime);
968 accessTicks = max(accessTicks, 1U);
969 accessTicks = min(accessTicks, 0x1fU);
970 accessTime = accessTicks * IDE_SYSCLK_NS;
971 recTicks = SYSCLK_TICKS(recTime);
972 recTicks = max(recTicks, 1U);
973 recTicks = min(recTicks, 0x1fU);
974 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
975 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
976 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
977 break;
978 default: {
979 /* 33Mhz cell on others */
980 int halfTick = 0;
981 int origAccessTime = accessTime;
982 int origRecTime = recTime;
983
984 accessTicks = SYSCLK_TICKS(accessTime);
985 accessTicks = max(accessTicks, 1U);
986 accessTicks = min(accessTicks, 0x1fU);
987 accessTime = accessTicks * IDE_SYSCLK_NS;
988 recTicks = SYSCLK_TICKS(recTime);
989 recTicks = max(recTicks, 2U) - 1;
990 recTicks = min(recTicks, 0x1fU);
991 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
992 if ((accessTicks > 1) &&
993 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
994 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
995 halfTick = 1;
996 accessTicks--;
997 }
998 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
999 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
1000 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
1001 if (halfTick)
1002 *timings |= TR_33_MDMA_HALFTICK;
1003 }
1004 }
1005#ifdef IDE_PMAC_DEBUG
1006 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
1007 drive->name, speed & 0xf, *timings);
1008#endif
1009 return 0;
1010}
1011#endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
1012
1013/*
1014 * Speedproc. This function is called by the core to set any of the standard
1015 * timing (PIO, MDMA or UDMA) to both the drive and the controller.
1016 * You may notice we don't use this function on normal "dma check" operation,
1017 * our dedicated function is more precise as it uses the drive provided
1018 * cycle time value. We should probably fix this one to deal with that too...
1019 */
aacaf9bd 1020static int
1da177e4
LT		 1021pmac_ide_tune_chipset (ide_drive_t *drive, byte speed)
1022{
1023 int unit = (drive->select.b.unit & 0x01);
1024 int ret = 0;
1025 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1026 u32 *timings, *timings2;
1027
1028 if (pmif == NULL)
1029 return 1;
1030
1031 timings = &pmif->timings[unit];
1032 timings2 = &pmif->timings[unit+2];
1033
1034 switch(speed) {
1035#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1036 case XFER_UDMA_6:
1037 if (pmif->kind != controller_sh_ata6)
1038 return 1;
1039 case XFER_UDMA_5:
1040 if (pmif->kind != controller_un_ata6 &&
1041 pmif->kind != controller_k2_ata6 &&
1042 pmif->kind != controller_sh_ata6)
1043 return 1;
1044 case XFER_UDMA_4:
1045 case XFER_UDMA_3:
1046 if (HWIF(drive)->udma_four == 0)
1047 return 1;
1048 case XFER_UDMA_2:
1049 case XFER_UDMA_1:
1050 case XFER_UDMA_0:
1051 if (pmif->kind == controller_kl_ata4)
1052 ret = set_timings_udma_ata4(timings, speed);
1053 else if (pmif->kind == controller_un_ata6
1054 || pmif->kind == controller_k2_ata6)
1055 ret = set_timings_udma_ata6(timings, timings2, speed);
1056 else if (pmif->kind == controller_sh_ata6)
1057 ret = set_timings_udma_shasta(timings, timings2, speed);
1058 else
1059 ret = 1;
1060 break;
1061 case XFER_MW_DMA_2:
1062 case XFER_MW_DMA_1:
1063 case XFER_MW_DMA_0:
1064 ret = set_timings_mdma(drive, pmif->kind, timings, timings2, speed, 0);
1065 break;
1066 case XFER_SW_DMA_2:
1067 case XFER_SW_DMA_1:
1068 case XFER_SW_DMA_0:
1069 return 1;
1070#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1071 case XFER_PIO_4:
1072 case XFER_PIO_3:
1073 case XFER_PIO_2:
1074 case XFER_PIO_1:
1075 case XFER_PIO_0:
1076 pmac_ide_tuneproc(drive, speed & 0x07);
1077 break;
1078 default:
1079 ret = 1;
1080 }
1081 if (ret)
1082 return ret;
1083
1084 ret = pmac_ide_do_setfeature(drive, speed);
1085 if (ret)
1086 return ret;
1087
1088 pmac_ide_do_update_timings(drive);
1089 drive->current_speed = speed;
1090
1091 return 0;
1092}
1093
1094/*
1095 * Blast some well known "safe" values to the timing registers at init or
1096 * wakeup from sleep time, before we do real calculation
1097 */
aacaf9bd 1098static void
1da177e4
LT		 1099sanitize_timings(pmac_ide_hwif_t *pmif)
1100{
1101 unsigned int value, value2 = 0;
1102
1103 switch(pmif->kind) {
1104 case controller_sh_ata6:
1105 value = 0x0a820c97;
1106 value2 = 0x00033031;
1107 break;
1108 case controller_un_ata6:
1109 case controller_k2_ata6:
1110 value = 0x08618a92;
1111 value2 = 0x00002921;
1112 break;
1113 case controller_kl_ata4:
1114 value = 0x0008438c;
1115 break;
1116 case controller_kl_ata3:
1117 value = 0x00084526;
1118 break;
1119 case controller_heathrow:
1120 case controller_ohare:
1121 default:
1122 value = 0x00074526;
1123 break;
1124 }
1125 pmif->timings[0] = pmif->timings[1] = value;
1126 pmif->timings[2] = pmif->timings[3] = value2;
1127}
1128
aacaf9bd 1129unsigned long
1da177e4
LT		 1130pmac_ide_get_base(int index)
1131{
1132 return pmac_ide[index].regbase;
1133}
1134
aacaf9bd 1135int
1da177e4
LT		 1136pmac_ide_check_base(unsigned long base)
1137{
1138 int ix;
1139
1140 for (ix = 0; ix < MAX_HWIFS; ++ix)
1141 if (base == pmac_ide[ix].regbase)
1142 return ix;
1143 return -1;
1144}
1145
aacaf9bd 1146int
1da177e4
LT		 1147pmac_ide_get_irq(unsigned long base)
1148{
1149 int ix;
1150
1151 for (ix = 0; ix < MAX_HWIFS; ++ix)
1152 if (base == pmac_ide[ix].regbase)
1153 return pmac_ide[ix].irq;
1154 return 0;
1155}
1156
aacaf9bd 1157static int ide_majors[] = { 3, 22, 33, 34, 56, 57 };
1da177e4
LT		 1158
1159dev_t __init
1160pmac_find_ide_boot(char *bootdevice, int n)
1161{
1162 int i;
1163
1164 /*
1165 * Look through the list of IDE interfaces for this one.
1166 */
1167 for (i = 0; i < pmac_ide_count; ++i) {
1168 char *name;
1169 if (!pmac_ide[i].node || !pmac_ide[i].node->full_name)
1170 continue;
1171 name = pmac_ide[i].node->full_name;
1172 if (memcmp(name, bootdevice, n) == 0 && name[n] == 0) {
1173 /* XXX should cope with the 2nd drive as well... */
1174 return MKDEV(ide_majors[i], 0);
1175 }
1176 }
1177
1178 return 0;
1179}
1180
1181/* Suspend call back, should be called after the child devices
1182 * have actually been suspended
1183 */
1184static int
1185pmac_ide_do_suspend(ide_hwif_t *hwif)
1186{
1187 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1188
1189 /* We clear the timings */
1190 pmif->timings[0] = 0;
1191 pmif->timings[1] = 0;
1192
1193#ifdef CONFIG_BLK_DEV_IDE_PMAC_BLINK
1194 /* Note: This code will be called for every hwif, thus we'll
1195 * try several time to stop the LED blinker timer, but that
1196 * should be harmless
1197 */
1198 if (pmu_ide_blink_enabled) {
1199 unsigned long flags;
1200
1201 /* Make sure we don't hit the PMU blink */
1202 spin_lock_irqsave(&pmu_blink_lock, flags);
1203 if (pmu_blink_ledstate)
1204 del_timer(&pmu_blink_timer);
1205 pmu_blink_ledstate = 0;
1206 spin_unlock_irqrestore(&pmu_blink_lock, flags);
1207 }
1208#endif /* CONFIG_BLK_DEV_IDE_PMAC_BLINK */
1209
616299af
BH		 1210 disable_irq(pmif->irq);
1211
1da177e4
LT		 1212 /* The media bay will handle itself just fine */
1213 if (pmif->mediabay)
1214 return 0;
1215
1216 /* Kauai has bus control FCRs directly here */
1217 if (pmif->kauai_fcr) {
1218 u32 fcr = readl(pmif->kauai_fcr);
1219 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
1220 writel(fcr, pmif->kauai_fcr);
1221 }
1222
1223 /* Disable the bus on older machines and the cell on kauai */
1224 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
1225 0);
1226
1227 return 0;
1228}
1229
1230/* Resume call back, should be called before the child devices
1231 * are resumed
1232 */
1233static int
1234pmac_ide_do_resume(ide_hwif_t *hwif)
1235{
1236 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1237
1238 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
1239 if (!pmif->mediabay) {
1240 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
1241 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
1242 msleep(10);
1243 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
1da177e4
LT		 1244
1245 /* Kauai has it different */
1246 if (pmif->kauai_fcr) {
1247 u32 fcr = readl(pmif->kauai_fcr);
1248 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
1249 writel(fcr, pmif->kauai_fcr);
1250 }
616299af
BH		 1251
1252 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1da177e4
LT		 1253 }
1254
1255 /* Sanitize drive timings */
1256 sanitize_timings(pmif);
1257
616299af
BH		 1258 enable_irq(pmif->irq);
1259
1da177e4
LT		 1260 return 0;
1261}
1262
1263/*
1264 * Setup, register & probe an IDE channel driven by this driver, this is
1265 * called by one of the 2 probe functions (macio or PCI). Note that a channel
1266 * that ends up beeing free of any device is not kept around by this driver
1267 * (it is kept in 2.4). This introduce an interface numbering change on some
1268 * rare machines unfortunately, but it's better this way.
1269 */
1270static int
1271pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1272{
1273 struct device_node *np = pmif->node;
1274 int *bidp, i;
1275
1276 pmif->cable_80 = 0;
1277 pmif->broken_dma = pmif->broken_dma_warn = 0;
1278 if (device_is_compatible(np, "shasta-ata"))
1279 pmif->kind = controller_sh_ata6;
1280 else if (device_is_compatible(np, "kauai-ata"))
1281 pmif->kind = controller_un_ata6;
1282 else if (device_is_compatible(np, "K2-UATA"))
1283 pmif->kind = controller_k2_ata6;
1284 else if (device_is_compatible(np, "keylargo-ata")) {
1285 if (strcmp(np->name, "ata-4") == 0)
1286 pmif->kind = controller_kl_ata4;
1287 else
1288 pmif->kind = controller_kl_ata3;
1289 } else if (device_is_compatible(np, "heathrow-ata"))
1290 pmif->kind = controller_heathrow;
1291 else {
1292 pmif->kind = controller_ohare;
1293 pmif->broken_dma = 1;
1294 }
1295
1296 bidp = (int *)get_property(np, "AAPL,bus-id", NULL);
1297 pmif->aapl_bus_id = bidp ? *bidp : 0;
1298
1299 /* Get cable type from device-tree */
1300 if (pmif->kind == controller_kl_ata4 || pmif->kind == controller_un_ata6
1301 || pmif->kind == controller_k2_ata6
1302 || pmif->kind == controller_sh_ata6) {
1303 char* cable = get_property(np, "cable-type", NULL);
1304 if (cable && !strncmp(cable, "80-", 3))
1305 pmif->cable_80 = 1;
1306 }
1307 /* G5's seem to have incorrect cable type in device-tree. Let's assume
1308 * they have a 80 conductor cable, this seem to be always the case unless
1309 * the user mucked around
1310 */
1311 if (device_is_compatible(np, "K2-UATA") ||
1312 device_is_compatible(np, "shasta-ata"))
1313 pmif->cable_80 = 1;
1314
1315 /* On Kauai-type controllers, we make sure the FCR is correct */
1316 if (pmif->kauai_fcr)
1317 writel(KAUAI_FCR_UATA_MAGIC |
1318 KAUAI_FCR_UATA_RESET_N |
1319 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1320
1321 pmif->mediabay = 0;
1322
1323 /* Make sure we have sane timings */
1324 sanitize_timings(pmif);
1325
1326#ifndef CONFIG_PPC64
1327 /* XXX FIXME: Media bay stuff need re-organizing */
1328 if (np->parent && np->parent->name
1329 && strcasecmp(np->parent->name, "media-bay") == 0) {
8c870933 1330#ifdef CONFIG_PMAC_MEDIABAY
1da177e4 1331 media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq, hwif->index);
8c870933 1332#endif /* CONFIG_PMAC_MEDIABAY */
1da177e4
LT		 1333 pmif->mediabay = 1;
1334 if (!bidp)
1335 pmif->aapl_bus_id = 1;
1336 } else if (pmif->kind == controller_ohare) {
1337 /* The code below is having trouble on some ohare machines
1338 * (timing related ?). Until I can put my hand on one of these
1339 * units, I keep the old way
1340 */
1341 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1342 } else
1343#endif
1344 {
1345 /* This is necessary to enable IDE when net-booting */
1346 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1347 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1348 msleep(10);
1349 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1350 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1351 }
1352
1353 /* Setup MMIO ops */
1354 default_hwif_mmiops(hwif);
1355 hwif->OUTBSYNC = pmac_outbsync;
1356
1357 /* Tell common code _not_ to mess with resources */
1358 hwif->mmio = 2;
1359 hwif->hwif_data = pmif;
1360 pmac_ide_init_hwif_ports(&hwif->hw, pmif->regbase, 0, &hwif->irq);
1361 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
1362 hwif->chipset = ide_pmac;
1363 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET] || pmif->mediabay;
1364 hwif->hold = pmif->mediabay;
1365 hwif->udma_four = pmif->cable_80;
1366 hwif->drives[0].unmask = 1;
1367 hwif->drives[1].unmask = 1;
1368 hwif->tuneproc = pmac_ide_tuneproc;
1369 if (pmif->kind == controller_un_ata6
1370 || pmif->kind == controller_k2_ata6
1371 || pmif->kind == controller_sh_ata6)
1372 hwif->selectproc = pmac_ide_kauai_selectproc;
1373 else
1374 hwif->selectproc = pmac_ide_selectproc;
1375 hwif->speedproc = pmac_ide_tune_chipset;
1376
1377#ifdef CONFIG_BLK_DEV_IDE_PMAC_BLINK
1378 pmu_ide_blink_enabled = pmu_hd_blink_init();
1379
1380 if (pmu_ide_blink_enabled)
1381 hwif->led_act = pmu_hd_kick_blink;
1382#endif
1383
1384 printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1385 hwif->index, model_name[pmif->kind], pmif->aapl_bus_id,
1386 pmif->mediabay ? " (mediabay)" : "", hwif->irq);
1387
8c870933 1388#ifdef CONFIG_PMAC_MEDIABAY
1da177e4
LT		 1389 if (pmif->mediabay && check_media_bay_by_base(pmif->regbase, MB_CD) == 0)
1390 hwif->noprobe = 0;
8c870933 1391#endif /* CONFIG_PMAC_MEDIABAY */
1da177e4
LT		 1392
1393 hwif->sg_max_nents = MAX_DCMDS;
1394
1395#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1396 /* has a DBDMA controller channel */
1397 if (pmif->dma_regs)
1398 pmac_ide_setup_dma(pmif, hwif);
1399#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1400
1401 /* We probe the hwif now */
1402 probe_hwif_init(hwif);
1403
1da177e4
LT		 1404 return 0;
1405}
1406
1407/*
1408 * Attach to a macio probed interface
1409 */
1410static int __devinit
5e655772 1411pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match)
1da177e4
LT		 1412{
1413 void __iomem *base;
1414 unsigned long regbase;
1415 int irq;
1416 ide_hwif_t *hwif;
1417 pmac_ide_hwif_t *pmif;
1418 int i, rc;
1419
1420 i = 0;
1421 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1422 || pmac_ide[i].node != NULL))
1423 ++i;
1424 if (i >= MAX_HWIFS) {
1425 printk(KERN_ERR "ide-pmac: MacIO interface attach with no slot\n");
1426 printk(KERN_ERR " %s\n", mdev->ofdev.node->full_name);
1427 return -ENODEV;
1428 }
1429
1430 pmif = &pmac_ide[i];
1431 hwif = &ide_hwifs[i];
1432
1433 if (mdev->ofdev.node->n_addrs == 0) {
1434 printk(KERN_WARNING "ide%d: no address for %s\n",
1435 i, mdev->ofdev.node->full_name);
1436 return -ENXIO;
1437 }
1438
1439 /* Request memory resource for IO ports */
1440 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1441 printk(KERN_ERR "ide%d: can't request mmio resource !\n", i);
1442 return -EBUSY;
1443 }
1444
1445 /* XXX This is bogus. Should be fixed in the registry by checking
1446 * the kind of host interrupt controller, a bit like gatwick
1447 * fixes in irq.c. That works well enough for the single case
1448 * where that happens though...
1449 */
1450 if (macio_irq_count(mdev) == 0) {
1451 printk(KERN_WARNING "ide%d: no intrs for device %s, using 13\n",
1452 i, mdev->ofdev.node->full_name);
1453 irq = 13;
1454 } else
1455 irq = macio_irq(mdev, 0);
1456
1457 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1458 regbase = (unsigned long) base;
1459
1460 hwif->pci_dev = mdev->bus->pdev;
1461 hwif->gendev.parent = &mdev->ofdev.dev;
1462
1463 pmif->mdev = mdev;
1464 pmif->node = mdev->ofdev.node;
1465 pmif->regbase = regbase;
1466 pmif->irq = irq;
1467 pmif->kauai_fcr = NULL;
1468#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1469 if (macio_resource_count(mdev) >= 2) {
1470 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1471 printk(KERN_WARNING "ide%d: can't request DMA resource !\n", i);
1472 else
1473 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1474 } else
1475 pmif->dma_regs = NULL;
1476#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1477 dev_set_drvdata(&mdev->ofdev.dev, hwif);
1478
1479 rc = pmac_ide_setup_device(pmif, hwif);
1480 if (rc != 0) {
1481 /* The inteface is released to the common IDE layer */
1482 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1483 iounmap(base);
1484 if (pmif->dma_regs)
1485 iounmap(pmif->dma_regs);
1486 memset(pmif, 0, sizeof(*pmif));
1487 macio_release_resource(mdev, 0);
1488 if (pmif->dma_regs)
1489 macio_release_resource(mdev, 1);
1490 }
1491
1492 return rc;
1493}
1494
1495static int
829ca9a3 1496pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t state)
1da177e4
LT		 1497{
1498 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1499 int rc = 0;
1500
ca078bae 1501 if (state.event != mdev->ofdev.dev.power.power_state.event && state.event >= PM_EVENT_SUSPEND) {
1da177e4
LT		 1502 rc = pmac_ide_do_suspend(hwif);
1503 if (rc == 0)
1504 mdev->ofdev.dev.power.power_state = state;
1505 }
1506
1507 return rc;
1508}
1509
1510static int
1511pmac_ide_macio_resume(struct macio_dev *mdev)
1512{
1513 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1514 int rc = 0;
1515
ca078bae 1516 if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
1da177e4
LT		 1517 rc = pmac_ide_do_resume(hwif);
1518 if (rc == 0)
829ca9a3 1519 mdev->ofdev.dev.power.power_state = PMSG_ON;
1da177e4
LT		 1520 }
1521
1522 return rc;
1523}
1524
1525/*
1526 * Attach to a PCI probed interface
1527 */
1528static int __devinit
1529pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1530{
1531 ide_hwif_t *hwif;
1532 struct device_node *np;
1533 pmac_ide_hwif_t *pmif;
1534 void __iomem *base;
1535 unsigned long rbase, rlen;
1536 int i, rc;
1537
1538 np = pci_device_to_OF_node(pdev);
1539 if (np == NULL) {
1540 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1541 return -ENODEV;
1542 }
1543 i = 0;
1544 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1545 || pmac_ide[i].node != NULL))
1546 ++i;
1547 if (i >= MAX_HWIFS) {
1548 printk(KERN_ERR "ide-pmac: PCI interface attach with no slot\n");
1549 printk(KERN_ERR " %s\n", np->full_name);
1550 return -ENODEV;
1551 }
1552
1553 pmif = &pmac_ide[i];
1554 hwif = &ide_hwifs[i];
1555
1556 if (pci_enable_device(pdev)) {
1557 printk(KERN_WARNING "ide%i: Can't enable PCI device for %s\n",
1558 i, np->full_name);
1559 return -ENXIO;
1560 }
1561 pci_set_master(pdev);
1562
1563 if (pci_request_regions(pdev, "Kauai ATA")) {
1564 printk(KERN_ERR "ide%d: Cannot obtain PCI resources for %s\n",
1565 i, np->full_name);
1566 return -ENXIO;
1567 }
1568
1569 hwif->pci_dev = pdev;
1570 hwif->gendev.parent = &pdev->dev;
1571 pmif->mdev = NULL;
1572 pmif->node = np;
1573
1574 rbase = pci_resource_start(pdev, 0);
1575 rlen = pci_resource_len(pdev, 0);
1576
1577 base = ioremap(rbase, rlen);
1578 pmif->regbase = (unsigned long) base + 0x2000;
1579#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1580 pmif->dma_regs = base + 0x1000;
1581#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1582 pmif->kauai_fcr = base;
1583 pmif->irq = pdev->irq;
1584
1585 pci_set_drvdata(pdev, hwif);
1586
1587 rc = pmac_ide_setup_device(pmif, hwif);
1588 if (rc != 0) {
1589 /* The inteface is released to the common IDE layer */
1590 pci_set_drvdata(pdev, NULL);
1591 iounmap(base);
1592 memset(pmif, 0, sizeof(*pmif));
1593 pci_release_regions(pdev);
1594 }
1595
1596 return rc;
1597}
1598
1599static int
829ca9a3 1600pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 1601{
1602 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1603 int rc = 0;
1604
ca078bae 1605 if (state.event != pdev->dev.power.power_state.event && state.event >= 2) {
1da177e4
LT		 1606 rc = pmac_ide_do_suspend(hwif);
1607 if (rc == 0)
1608 pdev->dev.power.power_state = state;
1609 }
1610
1611 return rc;
1612}
1613
1614static int
1615pmac_ide_pci_resume(struct pci_dev *pdev)
1616{
1617 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1618 int rc = 0;
1619
ca078bae 1620 if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
1da177e4
LT		 1621 rc = pmac_ide_do_resume(hwif);
1622 if (rc == 0)
829ca9a3 1623 pdev->dev.power.power_state = PMSG_ON;
1da177e4
LT		 1624 }
1625
1626 return rc;
1627}
1628
5e655772 1629static struct of_device_id pmac_ide_macio_match[] =
1da177e4
LT		 1630{
1631 {
1632 .name = "IDE",
1da177e4
LT		 1633 },
1634 {
1635 .name = "ATA",
1da177e4
LT		 1636 },
1637 {
1da177e4 1638 .type = "ide",
1da177e4
LT		 1639 },
1640 {
1da177e4 1641 .type = "ata",
1da177e4
LT		 1642 },
1643 {},
1644};
1645
1646static struct macio_driver pmac_ide_macio_driver =
1647{
1648 .name = "ide-pmac",
1649 .match_table = pmac_ide_macio_match,
1650 .probe = pmac_ide_macio_attach,
1651 .suspend = pmac_ide_macio_suspend,
1652 .resume = pmac_ide_macio_resume,
1653};
1654
1655static struct pci_device_id pmac_ide_pci_match[] = {
7fce260a
OJ		 1656 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA,
1657 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1658 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100,
1659 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1660 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100,
1661 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1da177e4
LT		 1662 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_ATA,
1663 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
7fce260a
OJ		 1664 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA,
1665 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1da177e4
LT		 1666};
1667
1668static struct pci_driver pmac_ide_pci_driver = {
1669 .name = "ide-pmac",
1670 .id_table = pmac_ide_pci_match,
1671 .probe = pmac_ide_pci_attach,
1672 .suspend = pmac_ide_pci_suspend,
1673 .resume = pmac_ide_pci_resume,
1674};
1675MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1676
1677void __init
1678pmac_ide_probe(void)
1679{
1680 if (_machine != _MACH_Pmac)
1681 return;
1682
1683#ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
1684 pci_register_driver(&pmac_ide_pci_driver);
1685 macio_register_driver(&pmac_ide_macio_driver);
1686#else
1687 macio_register_driver(&pmac_ide_macio_driver);
1688 pci_register_driver(&pmac_ide_pci_driver);
1689#endif
1690}
1691
1692#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1693
1694/*
1695 * pmac_ide_build_dmatable builds the DBDMA command list
1696 * for a transfer and sets the DBDMA channel to point to it.
1697 */
aacaf9bd 1698static int
1da177e4
LT		 1699pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq)
1700{
1701 struct dbdma_cmd *table;
1702 int i, count = 0;
1703 ide_hwif_t *hwif = HWIF(drive);
1704 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1705 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1706 struct scatterlist *sg;
1707 int wr = (rq_data_dir(rq) == WRITE);
1708
1709 /* DMA table is already aligned */
1710 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1711
1712 /* Make sure DMA controller is stopped (necessary ?) */
1713 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1714 while (readl(&dma->status) & RUN)
1715 udelay(1);
1716
1717 hwif->sg_nents = i = ide_build_sglist(drive, rq);
1718
1719 if (!i)
1720 return 0;
1721
1722 /* Build DBDMA commands list */
1723 sg = hwif->sg_table;
1724 while (i && sg_dma_len(sg)) {
1725 u32 cur_addr;
1726 u32 cur_len;
1727
1728 cur_addr = sg_dma_address(sg);
1729 cur_len = sg_dma_len(sg);
1730
1731 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1732 if (pmif->broken_dma_warn == 0) {
1733 printk(KERN_WARNING "%s: DMA on non aligned address,"
1734 "switching to PIO on Ohare chipset\n", drive->name);
1735 pmif->broken_dma_warn = 1;
1736 }
1737 goto use_pio_instead;
1738 }
1739 while (cur_len) {
1740 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1741
1742 if (count++ >= MAX_DCMDS) {
1743 printk(KERN_WARNING "%s: DMA table too small\n",
1744 drive->name);
1745 goto use_pio_instead;
1746 }
1747 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1748 st_le16(&table->req_count, tc);
1749 st_le32(&table->phy_addr, cur_addr);
1750 table->cmd_dep = 0;
1751 table->xfer_status = 0;
1752 table->res_count = 0;
1753 cur_addr += tc;
1754 cur_len -= tc;
1755 ++table;
1756 }
1757 sg++;
1758 i--;
1759 }
1760
1761 /* convert the last command to an input/output last command */
1762 if (count) {
1763 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1764 /* add the stop command to the end of the list */
1765 memset(table, 0, sizeof(struct dbdma_cmd));
1766 st_le16(&table->command, DBDMA_STOP);
1767 mb();
1768 writel(hwif->dmatable_dma, &dma->cmdptr);
1769 return 1;
1770 }
1771
1772 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
1773 use_pio_instead:
1774 pci_unmap_sg(hwif->pci_dev,
1775 hwif->sg_table,
1776 hwif->sg_nents,
1777 hwif->sg_dma_direction);
1778 return 0; /* revert to PIO for this request */
1779}
1780
1781/* Teardown mappings after DMA has completed. */
aacaf9bd 1782static void
1da177e4
LT		 1783pmac_ide_destroy_dmatable (ide_drive_t *drive)
1784{
1785 ide_hwif_t *hwif = drive->hwif;
1786 struct pci_dev *dev = HWIF(drive)->pci_dev;
1787 struct scatterlist *sg = hwif->sg_table;
1788 int nents = hwif->sg_nents;
1789
1790 if (nents) {
1791 pci_unmap_sg(dev, sg, nents, hwif->sg_dma_direction);
1792 hwif->sg_nents = 0;
1793 }
1794}
1795
1796/*
1797 * Pick up best MDMA timing for the drive and apply it
1798 */
aacaf9bd 1799static int
1da177e4
LT		 1800pmac_ide_mdma_enable(ide_drive_t *drive, u16 mode)
1801{
1802 ide_hwif_t *hwif = HWIF(drive);
1803 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1804 int drive_cycle_time;
1805 struct hd_driveid *id = drive->id;
1806 u32 *timings, *timings2;
1807 u32 timing_local[2];
1808 int ret;
1809
1810 /* which drive is it ? */
1811 timings = &pmif->timings[drive->select.b.unit & 0x01];
1812 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1813
1814 /* Check if drive provide explicit cycle time */
1815 if ((id->field_valid & 2) && (id->eide_dma_time))
1816 drive_cycle_time = id->eide_dma_time;
1817 else
1818 drive_cycle_time = 0;
1819
1820 /* Copy timings to local image */
1821 timing_local[0] = *timings;
1822 timing_local[1] = *timings2;
1823
1824 /* Calculate controller timings */
1825 ret = set_timings_mdma( drive, pmif->kind,
1826 &timing_local[0],
1827 &timing_local[1],
1828 mode,
1829 drive_cycle_time);
1830 if (ret)
1831 return 0;
1832
1833 /* Set feature on drive */
1834 printk(KERN_INFO "%s: Enabling MultiWord DMA %d\n", drive->name, mode & 0xf);
1835 ret = pmac_ide_do_setfeature(drive, mode);
1836 if (ret) {
1837 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1838 return 0;
1839 }
1840
1841 /* Apply timings to controller */
1842 *timings = timing_local[0];
1843 *timings2 = timing_local[1];
1844
1845 /* Set speed info in drive */
1846 drive->current_speed = mode;
1847 if (!drive->init_speed)
1848 drive->init_speed = mode;
1849
1850 return 1;
1851}
1852
1853/*
1854 * Pick up best UDMA timing for the drive and apply it
1855 */
aacaf9bd 1856static int
1da177e4
LT		 1857pmac_ide_udma_enable(ide_drive_t *drive, u16 mode)
1858{
1859 ide_hwif_t *hwif = HWIF(drive);
1860 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1861 u32 *timings, *timings2;
1862 u32 timing_local[2];
1863 int ret;
1864
1865 /* which drive is it ? */
1866 timings = &pmif->timings[drive->select.b.unit & 0x01];
1867 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1868
1869 /* Copy timings to local image */
1870 timing_local[0] = *timings;
1871 timing_local[1] = *timings2;
1872
1873 /* Calculate timings for interface */
1874 if (pmif->kind == controller_un_ata6
1875 || pmif->kind == controller_k2_ata6)
1876 ret = set_timings_udma_ata6( &timing_local[0],
1877 &timing_local[1],
1878 mode);
1879 else if (pmif->kind == controller_sh_ata6)
1880 ret = set_timings_udma_shasta( &timing_local[0],
1881 &timing_local[1],
1882 mode);
1883 else
1884 ret = set_timings_udma_ata4(&timing_local[0], mode);
1885 if (ret)
1886 return 0;
1887
1888 /* Set feature on drive */
1889 printk(KERN_INFO "%s: Enabling Ultra DMA %d\n", drive->name, mode & 0x0f);
1890 ret = pmac_ide_do_setfeature(drive, mode);
1891 if (ret) {
1892 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1893 return 0;
1894 }
1895
1896 /* Apply timings to controller */
1897 *timings = timing_local[0];
1898 *timings2 = timing_local[1];
1899
1900 /* Set speed info in drive */
1901 drive->current_speed = mode;
1902 if (!drive->init_speed)
1903 drive->init_speed = mode;
1904
1905 return 1;
1906}
1907
1908/*
1909 * Check what is the best DMA timing setting for the drive and
1910 * call appropriate functions to apply it.
1911 */
aacaf9bd 1912static int
1da177e4
LT		 1913pmac_ide_dma_check(ide_drive_t *drive)
1914{
1915 struct hd_driveid *id = drive->id;
1916 ide_hwif_t *hwif = HWIF(drive);
1917 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1918 int enable = 1;
1919 int map;
1920 drive->using_dma = 0;
1921
1922 if (drive->media == ide_floppy)
1923 enable = 0;
1924 if (((id->capability & 1) == 0) && !__ide_dma_good_drive(drive))
1925 enable = 0;
1926 if (__ide_dma_bad_drive(drive))
1927 enable = 0;
1928
1929 if (enable) {
1930 short mode;
1931
1932 map = XFER_MWDMA;
1933 if (pmif->kind == controller_kl_ata4
1934 || pmif->kind == controller_un_ata6
1935 || pmif->kind == controller_k2_ata6
1936 || pmif->kind == controller_sh_ata6) {
1937 map |= XFER_UDMA;
1938 if (pmif->cable_80) {
1939 map |= XFER_UDMA_66;
1940 if (pmif->kind == controller_un_ata6 ||
1941 pmif->kind == controller_k2_ata6 ||
1942 pmif->kind == controller_sh_ata6)
1943 map |= XFER_UDMA_100;
1944 if (pmif->kind == controller_sh_ata6)
1945 map |= XFER_UDMA_133;
1946 }
1947 }
1948 mode = ide_find_best_mode(drive, map);
1949 if (mode & XFER_UDMA)
1950 drive->using_dma = pmac_ide_udma_enable(drive, mode);
1951 else if (mode & XFER_MWDMA)
1952 drive->using_dma = pmac_ide_mdma_enable(drive, mode);
1953 hwif->OUTB(0, IDE_CONTROL_REG);
1954 /* Apply settings to controller */
1955 pmac_ide_do_update_timings(drive);
1956 }
1957 return 0;
1958}
1959
1960/*
1961 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1962 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1963 */
aacaf9bd 1964static int
1da177e4
LT		 1965pmac_ide_dma_setup(ide_drive_t *drive)
1966{
1967 ide_hwif_t *hwif = HWIF(drive);
1968 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1969 struct request *rq = HWGROUP(drive)->rq;
1970 u8 unit = (drive->select.b.unit & 0x01);
1971 u8 ata4;
1972
1973 if (pmif == NULL)
1974 return 1;
1975 ata4 = (pmif->kind == controller_kl_ata4);
1976
1977 if (!pmac_ide_build_dmatable(drive, rq)) {
1978 ide_map_sg(drive, rq);
1979 return 1;
1980 }
1981
1982 /* Apple adds 60ns to wrDataSetup on reads */
1983 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1984 writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0),
1985 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1986 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1987 }
1988
1989 drive->waiting_for_dma = 1;
1990
1991 return 0;
1992}
1993
aacaf9bd 1994static void
1da177e4
LT		 1995pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
1996{
1997 /* issue cmd to drive */
1998 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL);
1999}
2000
2001/*
2002 * Kick the DMA controller into life after the DMA command has been issued
2003 * to the drive.
2004 */
aacaf9bd 2005static void
1da177e4
LT		 2006pmac_ide_dma_start(ide_drive_t *drive)
2007{
2008 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
2009 volatile struct dbdma_regs __iomem *dma;
2010
2011 dma = pmif->dma_regs;
2012
2013 writel((RUN << 16) | RUN, &dma->control);
2014 /* Make sure it gets to the controller right now */
2015 (void)readl(&dma->control);
2016}
2017
2018/*
2019 * After a DMA transfer, make sure the controller is stopped
2020 */
aacaf9bd 2021static int
1da177e4
LT		 2022pmac_ide_dma_end (ide_drive_t *drive)
2023{
2024 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
2025 volatile struct dbdma_regs __iomem *dma;
2026 u32 dstat;
2027
2028 if (pmif == NULL)
2029 return 0;
2030 dma = pmif->dma_regs;
2031
2032 drive->waiting_for_dma = 0;
2033 dstat = readl(&dma->status);
2034 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
2035 pmac_ide_destroy_dmatable(drive);
2036 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
2037 * in theory, but with ATAPI decices doing buffer underruns, that would
2038 * cause us to disable DMA, which isn't what we want
2039 */
2040 return (dstat & (RUN|DEAD)) != RUN;
2041}
2042
2043/*
2044 * Check out that the interrupt we got was for us. We can't always know this
2045 * for sure with those Apple interfaces (well, we could on the recent ones but
2046 * that's not implemented yet), on the other hand, we don't have shared interrupts
2047 * so it's not really a problem
2048 */
aacaf9bd 2049static int
1da177e4
LT		 2050pmac_ide_dma_test_irq (ide_drive_t *drive)
2051{
2052 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
2053 volatile struct dbdma_regs __iomem *dma;
2054 unsigned long status, timeout;
2055
2056 if (pmif == NULL)
2057 return 0;
2058 dma = pmif->dma_regs;
2059
2060 /* We have to things to deal with here:
2061 *
2062 * - The dbdma won't stop if the command was started
2063 * but completed with an error without transferring all
2064 * datas. This happens when bad blocks are met during
2065 * a multi-block transfer.
2066 *
2067 * - The dbdma fifo hasn't yet finished flushing to
2068 * to system memory when the disk interrupt occurs.
2069 *
2070 */
2071
2072 /* If ACTIVE is cleared, the STOP command have passed and
2073 * transfer is complete.
2074 */
2075 status = readl(&dma->status);
2076 if (!(status & ACTIVE))
2077 return 1;
2078 if (!drive->waiting_for_dma)
2079 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
2080 called while not waiting\n", HWIF(drive)->index);
2081
2082 /* If dbdma didn't execute the STOP command yet, the
2083 * active bit is still set. We consider that we aren't
2084 * sharing interrupts (which is hopefully the case with
2085 * those controllers) and so we just try to flush the
2086 * channel for pending data in the fifo
2087 */
2088 udelay(1);
2089 writel((FLUSH << 16) | FLUSH, &dma->control);
2090 timeout = 0;
2091 for (;;) {
2092 udelay(1);
2093 status = readl(&dma->status);
2094 if ((status & FLUSH) == 0)
2095 break;
2096 if (++timeout > 100) {
2097 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
2098 timeout flushing channel\n", HWIF(drive)->index);
2099 break;
2100 }
2101 }
2102 return 1;
2103}
2104
aacaf9bd 2105static int
1da177e4
LT		 2106pmac_ide_dma_host_off (ide_drive_t *drive)
2107{
2108 return 0;
2109}
2110
aacaf9bd 2111static int
1da177e4
LT		 2112pmac_ide_dma_host_on (ide_drive_t *drive)
2113{
2114 return 0;
2115}
2116
aacaf9bd 2117static int
1da177e4
LT		 2118pmac_ide_dma_lostirq (ide_drive_t *drive)
2119{
2120 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
2121 volatile struct dbdma_regs __iomem *dma;
2122 unsigned long status;
2123
2124 if (pmif == NULL)
2125 return 0;
2126 dma = pmif->dma_regs;
2127
2128 status = readl(&dma->status);
2129 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
2130 return 0;
2131}
2132
2133/*
2134 * Allocate the data structures needed for using DMA with an interface
2135 * and fill the proper list of functions pointers
2136 */
2137static void __init
2138pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
2139{
2140 /* We won't need pci_dev if we switch to generic consistent
2141 * DMA routines ...
2142 */
2143 if (hwif->pci_dev == NULL)
2144 return;
2145 /*
2146 * Allocate space for the DBDMA commands.
2147 * The +2 is +1 for the stop command and +1 to allow for
2148 * aligning the start address to a multiple of 16 bytes.
2149 */
2150 pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent(
2151 hwif->pci_dev,
2152 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
2153 &hwif->dmatable_dma);
2154 if (pmif->dma_table_cpu == NULL) {
2155 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
2156 hwif->name);
2157 return;
2158 }
2159
2160 hwif->ide_dma_off_quietly = &__ide_dma_off_quietly;
2161 hwif->ide_dma_on = &__ide_dma_on;
2162 hwif->ide_dma_check = &pmac_ide_dma_check;
2163 hwif->dma_setup = &pmac_ide_dma_setup;
2164 hwif->dma_exec_cmd = &pmac_ide_dma_exec_cmd;
2165 hwif->dma_start = &pmac_ide_dma_start;
2166 hwif->ide_dma_end = &pmac_ide_dma_end;
2167 hwif->ide_dma_test_irq = &pmac_ide_dma_test_irq;
2168 hwif->ide_dma_host_off = &pmac_ide_dma_host_off;
2169 hwif->ide_dma_host_on = &pmac_ide_dma_host_on;
2170 hwif->ide_dma_timeout = &__ide_dma_timeout;
2171 hwif->ide_dma_lostirq = &pmac_ide_dma_lostirq;
2172
2173 hwif->atapi_dma = 1;
2174 switch(pmif->kind) {
2175 case controller_sh_ata6:
2176 hwif->ultra_mask = pmif->cable_80 ? 0x7f : 0x07;
2177 hwif->mwdma_mask = 0x07;
2178 hwif->swdma_mask = 0x00;
2179 break;
2180 case controller_un_ata6:
2181 case controller_k2_ata6:
2182 hwif->ultra_mask = pmif->cable_80 ? 0x3f : 0x07;
2183 hwif->mwdma_mask = 0x07;
2184 hwif->swdma_mask = 0x00;
2185 break;
2186 case controller_kl_ata4:
2187 hwif->ultra_mask = pmif->cable_80 ? 0x1f : 0x07;
2188 hwif->mwdma_mask = 0x07;
2189 hwif->swdma_mask = 0x00;
2190 break;
2191 default:
2192 hwif->ultra_mask = 0x00;
2193 hwif->mwdma_mask = 0x07;
2194 hwif->swdma_mask = 0x00;
2195 break;
2196 }
2197}
2198
2199#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
kernel source for telekom puls (alcatel/mediatek)