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ide-pmac: use ide_tune_dma() (take 2)
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / ppc / pmac.c
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1da177e4 1/*
f30c2269 2 * linux/drivers/ide/ppc/pmac.c
1da177e4
LT		 3 *
4 * Support for IDE interfaces on PowerMacs.
5 * These IDE interfaces are memory-mapped and have a DBDMA channel
6 * for doing DMA.
7 *
8 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
c15d5d43 9 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
1da177e4
LT		 10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 *
16 * Some code taken from drivers/ide/ide-dma.c:
17 *
18 * Copyright (c) 1995-1998 Mark Lord
19 *
20 * TODO: - Use pre-calculated (kauai) timing tables all the time and
21 * get rid of the "rounded" tables used previously, so we have the
22 * same table format for all controllers and can then just have one
23 * big table
24 *
25 */
1da177e4
LT		 26#include <linux/types.h>
27#include <linux/kernel.h>
1da177e4
LT		 28#include <linux/init.h>
29#include <linux/delay.h>
30#include <linux/ide.h>
31#include <linux/notifier.h>
32#include <linux/reboot.h>
33#include <linux/pci.h>
34#include <linux/adb.h>
35#include <linux/pmu.h>
36#include <linux/scatterlist.h>
37
38#include <asm/prom.h>
39#include <asm/io.h>
40#include <asm/dbdma.h>
41#include <asm/ide.h>
42#include <asm/pci-bridge.h>
43#include <asm/machdep.h>
44#include <asm/pmac_feature.h>
45#include <asm/sections.h>
46#include <asm/irq.h>
47
48#ifndef CONFIG_PPC64
49#include <asm/mediabay.h>
50#endif
51
9e5755bc 52#include "../ide-timing.h"
1da177e4
LT		 53
54#undef IDE_PMAC_DEBUG
55
56#define DMA_WAIT_TIMEOUT 50
57
58typedef struct pmac_ide_hwif {
59 unsigned long regbase;
60 int irq;
61 int kind;
62 int aapl_bus_id;
63 unsigned cable_80 : 1;
64 unsigned mediabay : 1;
65 unsigned broken_dma : 1;
66 unsigned broken_dma_warn : 1;
67 struct device_node* node;
68 struct macio_dev *mdev;
69 u32 timings[4];
70 volatile u32 __iomem * *kauai_fcr;
71#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
72 /* Those fields are duplicating what is in hwif. We currently
73 * can't use the hwif ones because of some assumptions that are
74 * beeing done by the generic code about the kind of dma controller
75 * and format of the dma table. This will have to be fixed though.
76 */
77 volatile struct dbdma_regs __iomem * dma_regs;
78 struct dbdma_cmd* dma_table_cpu;
79#endif
80
81} pmac_ide_hwif_t;
82
aacaf9bd 83static pmac_ide_hwif_t pmac_ide[MAX_HWIFS];
1da177e4
LT		 84static int pmac_ide_count;
85
86enum {
87 controller_ohare, /* OHare based */
88 controller_heathrow, /* Heathrow/Paddington */
89 controller_kl_ata3, /* KeyLargo ATA-3 */
90 controller_kl_ata4, /* KeyLargo ATA-4 */
91 controller_un_ata6, /* UniNorth2 ATA-6 */
92 controller_k2_ata6, /* K2 ATA-6 */
93 controller_sh_ata6, /* Shasta ATA-6 */
94};
95
96static const char* model_name[] = {
97 "OHare ATA", /* OHare based */
98 "Heathrow ATA", /* Heathrow/Paddington */
99 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
100 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
101 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
102 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
103 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
104};
105
106/*
107 * Extra registers, both 32-bit little-endian
108 */
109#define IDE_TIMING_CONFIG 0x200
110#define IDE_INTERRUPT 0x300
111
112/* Kauai (U2) ATA has different register setup */
113#define IDE_KAUAI_PIO_CONFIG 0x200
114#define IDE_KAUAI_ULTRA_CONFIG 0x210
115#define IDE_KAUAI_POLL_CONFIG 0x220
116
117/*
118 * Timing configuration register definitions
119 */
120
121/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
122#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
123#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
124#define IDE_SYSCLK_NS 30 /* 33Mhz cell */
125#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
126
127/* 133Mhz cell, found in shasta.
128 * See comments about 100 Mhz Uninorth 2...
129 * Note that PIO_MASK and MDMA_MASK seem to overlap
130 */
131#define TR_133_PIOREG_PIO_MASK 0xff000fff
132#define TR_133_PIOREG_MDMA_MASK 0x00fff800
133#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
134#define TR_133_UDMAREG_UDMA_EN 0x00000001
135
136/* 100Mhz cell, found in Uninorth 2. I don't have much infos about
137 * this one yet, it appears as a pci device (106b/0033) on uninorth
138 * internal PCI bus and it's clock is controlled like gem or fw. It
139 * appears to be an evolution of keylargo ATA4 with a timing register
140 * extended to 2 32bits registers and a similar DBDMA channel. Other
141 * registers seem to exist but I can't tell much about them.
142 *
143 * So far, I'm using pre-calculated tables for this extracted from
144 * the values used by the MacOS X driver.
145 *
146 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
147 * register controls the UDMA timings. At least, it seems bit 0
148 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
149 * cycle time in units of 10ns. Bits 8..15 are used by I don't
150 * know their meaning yet
151 */
152#define TR_100_PIOREG_PIO_MASK 0xff000fff
153#define TR_100_PIOREG_MDMA_MASK 0x00fff000
154#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
155#define TR_100_UDMAREG_UDMA_EN 0x00000001
156
157
158/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
159 * 40 connector cable and to 4 on 80 connector one.
160 * Clock unit is 15ns (66Mhz)
161 *
162 * 3 Values can be programmed:
163 * - Write data setup, which appears to match the cycle time. They
164 * also call it DIOW setup.
165 * - Ready to pause time (from spec)
166 * - Address setup. That one is weird. I don't see where exactly
167 * it fits in UDMA cycles, I got it's name from an obscure piece
168 * of commented out code in Darwin. They leave it to 0, we do as
169 * well, despite a comment that would lead to think it has a
170 * min value of 45ns.
171 * Apple also add 60ns to the write data setup (or cycle time ?) on
172 * reads.
173 */
174#define TR_66_UDMA_MASK 0xfff00000
175#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
176#define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
177#define TR_66_UDMA_ADDRSETUP_SHIFT 29
178#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
179#define TR_66_UDMA_RDY2PAUS_SHIFT 25
180#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
181#define TR_66_UDMA_WRDATASETUP_SHIFT 21
182#define TR_66_MDMA_MASK 0x000ffc00
183#define TR_66_MDMA_RECOVERY_MASK 0x000f8000
184#define TR_66_MDMA_RECOVERY_SHIFT 15
185#define TR_66_MDMA_ACCESS_MASK 0x00007c00
186#define TR_66_MDMA_ACCESS_SHIFT 10
187#define TR_66_PIO_MASK 0x000003ff
188#define TR_66_PIO_RECOVERY_MASK 0x000003e0
189#define TR_66_PIO_RECOVERY_SHIFT 5
190#define TR_66_PIO_ACCESS_MASK 0x0000001f
191#define TR_66_PIO_ACCESS_SHIFT 0
192
193/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
194 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
195 *
196 * The access time and recovery time can be programmed. Some older
197 * Darwin code base limit OHare to 150ns cycle time. I decided to do
198 * the same here fore safety against broken old hardware ;)
199 * The HalfTick bit, when set, adds half a clock (15ns) to the access
200 * time and removes one from recovery. It's not supported on KeyLargo
201 * implementation afaik. The E bit appears to be set for PIO mode 0 and
202 * is used to reach long timings used in this mode.
203 */
204#define TR_33_MDMA_MASK 0x003ff800
205#define TR_33_MDMA_RECOVERY_MASK 0x001f0000
206#define TR_33_MDMA_RECOVERY_SHIFT 16
207#define TR_33_MDMA_ACCESS_MASK 0x0000f800
208#define TR_33_MDMA_ACCESS_SHIFT 11
209#define TR_33_MDMA_HALFTICK 0x00200000
210#define TR_33_PIO_MASK 0x000007ff
211#define TR_33_PIO_E 0x00000400
212#define TR_33_PIO_RECOVERY_MASK 0x000003e0
213#define TR_33_PIO_RECOVERY_SHIFT 5
214#define TR_33_PIO_ACCESS_MASK 0x0000001f
215#define TR_33_PIO_ACCESS_SHIFT 0
216
217/*
218 * Interrupt register definitions
219 */
220#define IDE_INTR_DMA 0x80000000
221#define IDE_INTR_DEVICE 0x40000000
222
223/*
224 * FCR Register on Kauai. Not sure what bit 0x4 is ...
225 */
226#define KAUAI_FCR_UATA_MAGIC 0x00000004
227#define KAUAI_FCR_UATA_RESET_N 0x00000002
228#define KAUAI_FCR_UATA_ENABLE 0x00000001
229
230#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
231
232/* Rounded Multiword DMA timings
233 *
234 * I gave up finding a generic formula for all controller
235 * types and instead, built tables based on timing values
236 * used by Apple in Darwin's implementation.
237 */
238struct mdma_timings_t {
239 int accessTime;
240 int recoveryTime;
241 int cycleTime;
242};
243
aacaf9bd 244struct mdma_timings_t mdma_timings_33[] =
1da177e4
LT		 245{
246 { 240, 240, 480 },
247 { 180, 180, 360 },
248 { 135, 135, 270 },
249 { 120, 120, 240 },
250 { 105, 105, 210 },
251 { 90, 90, 180 },
252 { 75, 75, 150 },
253 { 75, 45, 120 },
254 { 0, 0, 0 }
255};
256
aacaf9bd 257struct mdma_timings_t mdma_timings_33k[] =
1da177e4
LT		 258{
259 { 240, 240, 480 },
260 { 180, 180, 360 },
261 { 150, 150, 300 },
262 { 120, 120, 240 },
263 { 90, 120, 210 },
264 { 90, 90, 180 },
265 { 90, 60, 150 },
266 { 90, 30, 120 },
267 { 0, 0, 0 }
268};
269
aacaf9bd 270struct mdma_timings_t mdma_timings_66[] =
1da177e4
LT		 271{
272 { 240, 240, 480 },
273 { 180, 180, 360 },
274 { 135, 135, 270 },
275 { 120, 120, 240 },
276 { 105, 105, 210 },
277 { 90, 90, 180 },
278 { 90, 75, 165 },
279 { 75, 45, 120 },
280 { 0, 0, 0 }
281};
282
283/* KeyLargo ATA-4 Ultra DMA timings (rounded) */
284struct {
285 int addrSetup; /* ??? */
286 int rdy2pause;
287 int wrDataSetup;
aacaf9bd 288} kl66_udma_timings[] =
1da177e4
LT		 289{
290 { 0, 180, 120 }, /* Mode 0 */
291 { 0, 150, 90 }, /* 1 */
292 { 0, 120, 60 }, /* 2 */
293 { 0, 90, 45 }, /* 3 */
294 { 0, 90, 30 } /* 4 */
295};
296
297/* UniNorth 2 ATA/100 timings */
298struct kauai_timing {
299 int cycle_time;
300 u32 timing_reg;
301};
302
aacaf9bd 303static struct kauai_timing kauai_pio_timings[] =
1da177e4
LT		 304{
305 { 930 , 0x08000fff },
306 { 600 , 0x08000a92 },
307 { 383 , 0x0800060f },
308 { 360 , 0x08000492 },
309 { 330 , 0x0800048f },
310 { 300 , 0x080003cf },
311 { 270 , 0x080003cc },
312 { 240 , 0x0800038b },
313 { 239 , 0x0800030c },
314 { 180 , 0x05000249 },
c15d5d43
BZ		 315 { 120 , 0x04000148 },
316 { 0 , 0 },
1da177e4
LT		 317};
318
aacaf9bd 319static struct kauai_timing kauai_mdma_timings[] =
1da177e4
LT		 320{
321 { 1260 , 0x00fff000 },
322 { 480 , 0x00618000 },
323 { 360 , 0x00492000 },
324 { 270 , 0x0038e000 },
325 { 240 , 0x0030c000 },
326 { 210 , 0x002cb000 },
327 { 180 , 0x00249000 },
328 { 150 , 0x00209000 },
329 { 120 , 0x00148000 },
330 { 0 , 0 },
331};
332
aacaf9bd 333static struct kauai_timing kauai_udma_timings[] =
1da177e4
LT		 334{
335 { 120 , 0x000070c0 },
336 { 90 , 0x00005d80 },
337 { 60 , 0x00004a60 },
338 { 45 , 0x00003a50 },
339 { 30 , 0x00002a30 },
340 { 20 , 0x00002921 },
341 { 0 , 0 },
342};
343
aacaf9bd 344static struct kauai_timing shasta_pio_timings[] =
1da177e4
LT		 345{
346 { 930 , 0x08000fff },
347 { 600 , 0x0A000c97 },
348 { 383 , 0x07000712 },
349 { 360 , 0x040003cd },
350 { 330 , 0x040003cd },
351 { 300 , 0x040003cd },
352 { 270 , 0x040003cd },
353 { 240 , 0x040003cd },
354 { 239 , 0x040003cd },
355 { 180 , 0x0400028b },
c15d5d43
BZ		 356 { 120 , 0x0400010a },
357 { 0 , 0 },
1da177e4
LT		 358};
359
aacaf9bd 360static struct kauai_timing shasta_mdma_timings[] =
1da177e4
LT		 361{
362 { 1260 , 0x00fff000 },
363 { 480 , 0x00820800 },
364 { 360 , 0x00820800 },
365 { 270 , 0x00820800 },
366 { 240 , 0x00820800 },
367 { 210 , 0x00820800 },
368 { 180 , 0x00820800 },
369 { 150 , 0x0028b000 },
370 { 120 , 0x001ca000 },
371 { 0 , 0 },
372};
373
aacaf9bd 374static struct kauai_timing shasta_udma133_timings[] =
1da177e4
LT		 375{
376 { 120 , 0x00035901, },
377 { 90 , 0x000348b1, },
378 { 60 , 0x00033881, },
379 { 45 , 0x00033861, },
380 { 30 , 0x00033841, },
381 { 20 , 0x00033031, },
382 { 15 , 0x00033021, },
383 { 0 , 0 },
384};
385
386
387static inline u32
388kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
389{
390 int i;
391
392 for (i=0; table[i].cycle_time; i++)
393 if (cycle_time > table[i+1].cycle_time)
394 return table[i].timing_reg;
90a87ea4 395 BUG();
1da177e4
LT		 396 return 0;
397}
398
399/* allow up to 256 DBDMA commands per xfer */
400#define MAX_DCMDS 256
401
402/*
403 * Wait 1s for disk to answer on IDE bus after a hard reset
404 * of the device (via GPIO/FCR).
405 *
406 * Some devices seem to "pollute" the bus even after dropping
407 * the BSY bit (typically some combo drives slave on the UDMA
408 * bus) after a hard reset. Since we hard reset all drives on
409 * KeyLargo ATA66, we have to keep that delay around. I may end
410 * up not hard resetting anymore on these and keep the delay only
411 * for older interfaces instead (we have to reset when coming
412 * from MacOS...) --BenH.
413 */
414#define IDE_WAKEUP_DELAY (1*HZ)
415
416static void pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif);
417static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq);
1da177e4
LT		 418static void pmac_ide_selectproc(ide_drive_t *drive);
419static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
420
421#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
422
1da177e4
LT		 423/*
424 * N.B. this can't be an initfunc, because the media-bay task can
425 * call ide_[un]register at any time.
426 */
aacaf9bd 427void
1da177e4
LT		 428pmac_ide_init_hwif_ports(hw_regs_t *hw,
429 unsigned long data_port, unsigned long ctrl_port,
430 int *irq)
431{
432 int i, ix;
433
434 if (data_port == 0)
435 return;
436
437 for (ix = 0; ix < MAX_HWIFS; ++ix)
438 if (data_port == pmac_ide[ix].regbase)
439 break;
440
441 if (ix >= MAX_HWIFS) {
442 /* Probably a PCI interface... */
443 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; ++i)
444 hw->io_ports[i] = data_port + i - IDE_DATA_OFFSET;
445 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
446 return;
447 }
448
449 for (i = 0; i < 8; ++i)
450 hw->io_ports[i] = data_port + i * 0x10;
451 hw->io_ports[8] = data_port + 0x160;
452
453 if (irq != NULL)
454 *irq = pmac_ide[ix].irq;
22192ccd
BH		 455
456 hw->dev = &pmac_ide[ix].mdev->ofdev.dev;
1da177e4
LT		 457}
458
459#define PMAC_IDE_REG(x) ((void __iomem *)(IDE_DATA_REG+(x)))
460
461/*
462 * Apply the timings of the proper unit (master/slave) to the shared
463 * timing register when selecting that unit. This version is for
464 * ASICs with a single timing register
465 */
aacaf9bd 466static void
1da177e4
LT		 467pmac_ide_selectproc(ide_drive_t *drive)
468{
469 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
470
471 if (pmif == NULL)
472 return;
473
474 if (drive->select.b.unit & 0x01)
475 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
476 else
477 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
478 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
479}
480
481/*
482 * Apply the timings of the proper unit (master/slave) to the shared
483 * timing register when selecting that unit. This version is for
484 * ASICs with a dual timing register (Kauai)
485 */
aacaf9bd 486static void
1da177e4
LT		 487pmac_ide_kauai_selectproc(ide_drive_t *drive)
488{
489 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
490
491 if (pmif == NULL)
492 return;
493
494 if (drive->select.b.unit & 0x01) {
495 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
496 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
497 } else {
498 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
499 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
500 }
501 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
502}
503
504/*
505 * Force an update of controller timing values for a given drive
506 */
aacaf9bd 507static void
1da177e4
LT		 508pmac_ide_do_update_timings(ide_drive_t *drive)
509{
510 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
511
512 if (pmif == NULL)
513 return;
514
515 if (pmif->kind == controller_sh_ata6 ||
516 pmif->kind == controller_un_ata6 ||
517 pmif->kind == controller_k2_ata6)
518 pmac_ide_kauai_selectproc(drive);
519 else
520 pmac_ide_selectproc(drive);
521}
522
523static void
524pmac_outbsync(ide_drive_t *drive, u8 value, unsigned long port)
525{
526 u32 tmp;
527
528 writeb(value, (void __iomem *) port);
529 tmp = readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
530}
531
1da177e4
LT		 532/*
533 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
534 */
aacaf9bd 535static void
26bcb879 536pmac_ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4 537{
1da177e4
LT		 538 u32 *timings;
539 unsigned accessTicks, recTicks;
540 unsigned accessTime, recTime;
541 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
7dd00083
BZ		 542 unsigned int cycle_time;
543
1da177e4
LT		 544 if (pmif == NULL)
545 return;
546
547 /* which drive is it ? */
548 timings = &pmif->timings[drive->select.b.unit & 0x01];
549
7dd00083 550 cycle_time = ide_pio_cycle_time(drive, pio);
1da177e4
LT		 551
552 switch (pmif->kind) {
553 case controller_sh_ata6: {
554 /* 133Mhz cell */
7dd00083 555 u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time);
1da177e4
LT		 556 *timings = ((*timings) & ~TR_133_PIOREG_PIO_MASK) | tr;
557 break;
558 }
559 case controller_un_ata6:
560 case controller_k2_ata6: {
561 /* 100Mhz cell */
7dd00083 562 u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time);
1da177e4
LT		 563 *timings = ((*timings) & ~TR_100_PIOREG_PIO_MASK) | tr;
564 break;
565 }
566 case controller_kl_ata4:
567 /* 66Mhz cell */
7dd00083 568 recTime = cycle_time - ide_pio_timings[pio].active_time
1da177e4
LT		 569 - ide_pio_timings[pio].setup_time;
570 recTime = max(recTime, 150U);
571 accessTime = ide_pio_timings[pio].active_time;
572 accessTime = max(accessTime, 150U);
573 accessTicks = SYSCLK_TICKS_66(accessTime);
574 accessTicks = min(accessTicks, 0x1fU);
575 recTicks = SYSCLK_TICKS_66(recTime);
576 recTicks = min(recTicks, 0x1fU);
577 *timings = ((*timings) & ~TR_66_PIO_MASK) |
578 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
579 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
580 break;
581 default: {
582 /* 33Mhz cell */
583 int ebit = 0;
7dd00083 584 recTime = cycle_time - ide_pio_timings[pio].active_time
1da177e4
LT		 585 - ide_pio_timings[pio].setup_time;
586 recTime = max(recTime, 150U);
587 accessTime = ide_pio_timings[pio].active_time;
588 accessTime = max(accessTime, 150U);
589 accessTicks = SYSCLK_TICKS(accessTime);
590 accessTicks = min(accessTicks, 0x1fU);
591 accessTicks = max(accessTicks, 4U);
592 recTicks = SYSCLK_TICKS(recTime);
593 recTicks = min(recTicks, 0x1fU);
594 recTicks = max(recTicks, 5U) - 4;
595 if (recTicks > 9) {
596 recTicks--; /* guess, but it's only for PIO0, so... */
597 ebit = 1;
598 }
599 *timings = ((*timings) & ~TR_33_PIO_MASK) |
600 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
601 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
602 if (ebit)
603 *timings |= TR_33_PIO_E;
604 break;
605 }
606 }
607
608#ifdef IDE_PMAC_DEBUG
609 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
610 drive->name, pio, *timings);
611#endif
612
aedea591 613 if (ide_config_drive_speed(drive, XFER_PIO_0 + pio))
c15d5d43
BZ		 614 return;
615
616 pmac_ide_do_update_timings(drive);
1da177e4
LT		 617}
618
619#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
620
621/*
622 * Calculate KeyLargo ATA/66 UDMA timings
623 */
aacaf9bd 624static int
1da177e4
LT		 625set_timings_udma_ata4(u32 *timings, u8 speed)
626{
627 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
628
629 if (speed > XFER_UDMA_4)
630 return 1;
631
632 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
633 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
634 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
635
636 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
637 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
638 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
639 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
640 TR_66_UDMA_EN;
641#ifdef IDE_PMAC_DEBUG
642 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
643 speed & 0xf, *timings);
644#endif
645
646 return 0;
647}
648
649/*
650 * Calculate Kauai ATA/100 UDMA timings
651 */
aacaf9bd 652static int
1da177e4
LT		 653set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
654{
655 struct ide_timing *t = ide_timing_find_mode(speed);
656 u32 tr;
657
658 if (speed > XFER_UDMA_5 || t == NULL)
659 return 1;
660 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
1da177e4
LT		 661 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
662 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
663
664 return 0;
665}
666
667/*
668 * Calculate Shasta ATA/133 UDMA timings
669 */
aacaf9bd 670static int
1da177e4
LT		 671set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
672{
673 struct ide_timing *t = ide_timing_find_mode(speed);
674 u32 tr;
675
676 if (speed > XFER_UDMA_6 || t == NULL)
677 return 1;
678 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
1da177e4
LT		 679 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
680 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
681
682 return 0;
683}
684
685/*
686 * Calculate MDMA timings for all cells
687 */
90f72eca 688static void
1da177e4 689set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
90f72eca 690 u8 speed)
1da177e4
LT		 691{
692 int cycleTime, accessTime = 0, recTime = 0;
693 unsigned accessTicks, recTicks;
90f72eca 694 struct hd_driveid *id = drive->id;
1da177e4
LT		 695 struct mdma_timings_t* tm = NULL;
696 int i;
697
698 /* Get default cycle time for mode */
699 switch(speed & 0xf) {
700 case 0: cycleTime = 480; break;
701 case 1: cycleTime = 150; break;
702 case 2: cycleTime = 120; break;
703 default:
90f72eca
BZ		 704 BUG();
705 break;
1da177e4 706 }
90f72eca
BZ		 707
708 /* Check if drive provides explicit DMA cycle time */
709 if ((id->field_valid & 2) && id->eide_dma_time)
710 cycleTime = max_t(int, id->eide_dma_time, cycleTime);
711
1da177e4
LT		 712 /* OHare limits according to some old Apple sources */
713 if ((intf_type == controller_ohare) && (cycleTime < 150))
714 cycleTime = 150;
715 /* Get the proper timing array for this controller */
716 switch(intf_type) {
717 case controller_sh_ata6:
718 case controller_un_ata6:
719 case controller_k2_ata6:
720 break;
721 case controller_kl_ata4:
722 tm = mdma_timings_66;
723 break;
724 case controller_kl_ata3:
725 tm = mdma_timings_33k;
726 break;
727 default:
728 tm = mdma_timings_33;
729 break;
730 }
731 if (tm != NULL) {
732 /* Lookup matching access & recovery times */
733 i = -1;
734 for (;;) {
735 if (tm[i+1].cycleTime < cycleTime)
736 break;
737 i++;
738 }
1da177e4
LT		 739 cycleTime = tm[i].cycleTime;
740 accessTime = tm[i].accessTime;
741 recTime = tm[i].recoveryTime;
742
743#ifdef IDE_PMAC_DEBUG
744 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
745 drive->name, cycleTime, accessTime, recTime);
746#endif
747 }
748 switch(intf_type) {
749 case controller_sh_ata6: {
750 /* 133Mhz cell */
751 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
1da177e4
LT		 752 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
753 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
754 }
755 case controller_un_ata6:
756 case controller_k2_ata6: {
757 /* 100Mhz cell */
758 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
1da177e4
LT		 759 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
760 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
761 }
762 break;
763 case controller_kl_ata4:
764 /* 66Mhz cell */
765 accessTicks = SYSCLK_TICKS_66(accessTime);
766 accessTicks = min(accessTicks, 0x1fU);
767 accessTicks = max(accessTicks, 0x1U);
768 recTicks = SYSCLK_TICKS_66(recTime);
769 recTicks = min(recTicks, 0x1fU);
770 recTicks = max(recTicks, 0x3U);
771 /* Clear out mdma bits and disable udma */
772 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
773 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
774 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
775 break;
776 case controller_kl_ata3:
777 /* 33Mhz cell on KeyLargo */
778 accessTicks = SYSCLK_TICKS(accessTime);
779 accessTicks = max(accessTicks, 1U);
780 accessTicks = min(accessTicks, 0x1fU);
781 accessTime = accessTicks * IDE_SYSCLK_NS;
782 recTicks = SYSCLK_TICKS(recTime);
783 recTicks = max(recTicks, 1U);
784 recTicks = min(recTicks, 0x1fU);
785 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
786 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
787 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
788 break;
789 default: {
790 /* 33Mhz cell on others */
791 int halfTick = 0;
792 int origAccessTime = accessTime;
793 int origRecTime = recTime;
794
795 accessTicks = SYSCLK_TICKS(accessTime);
796 accessTicks = max(accessTicks, 1U);
797 accessTicks = min(accessTicks, 0x1fU);
798 accessTime = accessTicks * IDE_SYSCLK_NS;
799 recTicks = SYSCLK_TICKS(recTime);
800 recTicks = max(recTicks, 2U) - 1;
801 recTicks = min(recTicks, 0x1fU);
802 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
803 if ((accessTicks > 1) &&
804 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
805 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
806 halfTick = 1;
807 accessTicks--;
808 }
809 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
810 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
811 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
812 if (halfTick)
813 *timings |= TR_33_MDMA_HALFTICK;
814 }
815 }
816#ifdef IDE_PMAC_DEBUG
817 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
818 drive->name, speed & 0xf, *timings);
819#endif
1da177e4
LT		 820}
821#endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
822
823/*
824 * Speedproc. This function is called by the core to set any of the standard
8f4dd2e4 825 * DMA timing (MDMA or UDMA) to both the drive and the controller.
1da177e4 826 */
f212ff28 827static int pmac_ide_tune_chipset(ide_drive_t *drive, const u8 speed)
1da177e4
LT		 828{
829 int unit = (drive->select.b.unit & 0x01);
830 int ret = 0;
831 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
085798b1 832 u32 *timings, *timings2, tl[2];
1da177e4 833
1da177e4
LT		 834 timings = &pmif->timings[unit];
835 timings2 = &pmif->timings[unit+2];
085798b1
BZ		 836
837 /* Copy timings to local image */
838 tl[0] = *timings;
839 tl[1] = *timings2;
840
1da177e4
LT		 841 switch(speed) {
842#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
843 case XFER_UDMA_6:
1da177e4 844 case XFER_UDMA_5:
1da177e4
LT		 845 case XFER_UDMA_4:
846 case XFER_UDMA_3:
1da177e4
LT		 847 case XFER_UDMA_2:
848 case XFER_UDMA_1:
849 case XFER_UDMA_0:
850 if (pmif->kind == controller_kl_ata4)
085798b1 851 ret = set_timings_udma_ata4(&tl[0], speed);
1da177e4
LT		 852 else if (pmif->kind == controller_un_ata6
853 || pmif->kind == controller_k2_ata6)
085798b1 854 ret = set_timings_udma_ata6(&tl[0], &tl[1], speed);
1da177e4 855 else if (pmif->kind == controller_sh_ata6)
085798b1 856 ret = set_timings_udma_shasta(&tl[0], &tl[1], speed);
1da177e4 857 else
085798b1 858 ret = 1;
1da177e4
LT		 859 break;
860 case XFER_MW_DMA_2:
861 case XFER_MW_DMA_1:
862 case XFER_MW_DMA_0:
90f72eca 863 set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed);
1da177e4
LT		 864 break;
865 case XFER_SW_DMA_2:
866 case XFER_SW_DMA_1:
867 case XFER_SW_DMA_0:
868 return 1;
869#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1da177e4
LT		 870 default:
871 ret = 1;
872 }
873 if (ret)
874 return ret;
875
aedea591 876 ret = ide_config_drive_speed(drive, speed);
1da177e4
LT		 877 if (ret)
878 return ret;
085798b1
BZ		 879
880 /* Apply timings to controller */
881 *timings = tl[0];
882 *timings2 = tl[1];
883
1da177e4 884 pmac_ide_do_update_timings(drive);
1da177e4
LT		 885
886 return 0;
887}
888
889/*
890 * Blast some well known "safe" values to the timing registers at init or
891 * wakeup from sleep time, before we do real calculation
892 */
aacaf9bd 893static void
1da177e4
LT		 894sanitize_timings(pmac_ide_hwif_t *pmif)
895{
896 unsigned int value, value2 = 0;
897
898 switch(pmif->kind) {
899 case controller_sh_ata6:
900 value = 0x0a820c97;
901 value2 = 0x00033031;
902 break;
903 case controller_un_ata6:
904 case controller_k2_ata6:
905 value = 0x08618a92;
906 value2 = 0x00002921;
907 break;
908 case controller_kl_ata4:
909 value = 0x0008438c;
910 break;
911 case controller_kl_ata3:
912 value = 0x00084526;
913 break;
914 case controller_heathrow:
915 case controller_ohare:
916 default:
917 value = 0x00074526;
918 break;
919 }
920 pmif->timings[0] = pmif->timings[1] = value;
921 pmif->timings[2] = pmif->timings[3] = value2;
922}
923
aacaf9bd 924unsigned long
1da177e4
LT		 925pmac_ide_get_base(int index)
926{
927 return pmac_ide[index].regbase;
928}
929
aacaf9bd 930int
1da177e4
LT		 931pmac_ide_check_base(unsigned long base)
932{
933 int ix;
934
935 for (ix = 0; ix < MAX_HWIFS; ++ix)
936 if (base == pmac_ide[ix].regbase)
937 return ix;
938 return -1;
939}
940
aacaf9bd 941int
1da177e4
LT		 942pmac_ide_get_irq(unsigned long base)
943{
944 int ix;
945
946 for (ix = 0; ix < MAX_HWIFS; ++ix)
947 if (base == pmac_ide[ix].regbase)
948 return pmac_ide[ix].irq;
949 return 0;
950}
951
aacaf9bd 952static int ide_majors[] = { 3, 22, 33, 34, 56, 57 };
1da177e4
LT		 953
954dev_t __init
955pmac_find_ide_boot(char *bootdevice, int n)
956{
957 int i;
958
959 /*
960 * Look through the list of IDE interfaces for this one.
961 */
962 for (i = 0; i < pmac_ide_count; ++i) {
963 char *name;
964 if (!pmac_ide[i].node || !pmac_ide[i].node->full_name)
965 continue;
966 name = pmac_ide[i].node->full_name;
967 if (memcmp(name, bootdevice, n) == 0 && name[n] == 0) {
968 /* XXX should cope with the 2nd drive as well... */
969 return MKDEV(ide_majors[i], 0);
970 }
971 }
972
973 return 0;
974}
975
976/* Suspend call back, should be called after the child devices
977 * have actually been suspended
978 */
979static int
980pmac_ide_do_suspend(ide_hwif_t *hwif)
981{
982 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
983
984 /* We clear the timings */
985 pmif->timings[0] = 0;
986 pmif->timings[1] = 0;
987
616299af
BH		 988 disable_irq(pmif->irq);
989
1da177e4
LT		 990 /* The media bay will handle itself just fine */
991 if (pmif->mediabay)
992 return 0;
993
994 /* Kauai has bus control FCRs directly here */
995 if (pmif->kauai_fcr) {
996 u32 fcr = readl(pmif->kauai_fcr);
997 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
998 writel(fcr, pmif->kauai_fcr);
999 }
1000
1001 /* Disable the bus on older machines and the cell on kauai */
1002 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
1003 0);
1004
1005 return 0;
1006}
1007
1008/* Resume call back, should be called before the child devices
1009 * are resumed
1010 */
1011static int
1012pmac_ide_do_resume(ide_hwif_t *hwif)
1013{
1014 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1015
1016 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
1017 if (!pmif->mediabay) {
1018 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
1019 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
1020 msleep(10);
1021 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
1da177e4
LT		 1022
1023 /* Kauai has it different */
1024 if (pmif->kauai_fcr) {
1025 u32 fcr = readl(pmif->kauai_fcr);
1026 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
1027 writel(fcr, pmif->kauai_fcr);
1028 }
616299af
BH		 1029
1030 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1da177e4
LT		 1031 }
1032
1033 /* Sanitize drive timings */
1034 sanitize_timings(pmif);
1035
616299af
BH		 1036 enable_irq(pmif->irq);
1037
1da177e4
LT		 1038 return 0;
1039}
1040
1041/*
1042 * Setup, register & probe an IDE channel driven by this driver, this is
1043 * called by one of the 2 probe functions (macio or PCI). Note that a channel
1044 * that ends up beeing free of any device is not kept around by this driver
1045 * (it is kept in 2.4). This introduce an interface numbering change on some
1046 * rare machines unfortunately, but it's better this way.
1047 */
1048static int
1049pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1050{
1051 struct device_node *np = pmif->node;
018a3d1d 1052 const int *bidp;
1da177e4
LT		 1053
1054 pmif->cable_80 = 0;
1055 pmif->broken_dma = pmif->broken_dma_warn = 0;
55b61fec 1056 if (of_device_is_compatible(np, "shasta-ata"))
1da177e4 1057 pmif->kind = controller_sh_ata6;
55b61fec 1058 else if (of_device_is_compatible(np, "kauai-ata"))
1da177e4 1059 pmif->kind = controller_un_ata6;
55b61fec 1060 else if (of_device_is_compatible(np, "K2-UATA"))
1da177e4 1061 pmif->kind = controller_k2_ata6;
55b61fec 1062 else if (of_device_is_compatible(np, "keylargo-ata")) {
1da177e4
LT		 1063 if (strcmp(np->name, "ata-4") == 0)
1064 pmif->kind = controller_kl_ata4;
1065 else
1066 pmif->kind = controller_kl_ata3;
55b61fec 1067 } else if (of_device_is_compatible(np, "heathrow-ata"))
1da177e4
LT		 1068 pmif->kind = controller_heathrow;
1069 else {
1070 pmif->kind = controller_ohare;
1071 pmif->broken_dma = 1;
1072 }
1073
40cd3a45 1074 bidp = of_get_property(np, "AAPL,bus-id", NULL);
1da177e4
LT		 1075 pmif->aapl_bus_id = bidp ? *bidp : 0;
1076
1077 /* Get cable type from device-tree */
1078 if (pmif->kind == controller_kl_ata4 || pmif->kind == controller_un_ata6
1079 || pmif->kind == controller_k2_ata6
1080 || pmif->kind == controller_sh_ata6) {
40cd3a45 1081 const char* cable = of_get_property(np, "cable-type", NULL);
1da177e4
LT		 1082 if (cable && !strncmp(cable, "80-", 3))
1083 pmif->cable_80 = 1;
1084 }
1085 /* G5's seem to have incorrect cable type in device-tree. Let's assume
1086 * they have a 80 conductor cable, this seem to be always the case unless
1087 * the user mucked around
1088 */
55b61fec
SR		 1089 if (of_device_is_compatible(np, "K2-UATA") ||
1090 of_device_is_compatible(np, "shasta-ata"))
1da177e4
LT		 1091 pmif->cable_80 = 1;
1092
1093 /* On Kauai-type controllers, we make sure the FCR is correct */
1094 if (pmif->kauai_fcr)
1095 writel(KAUAI_FCR_UATA_MAGIC |
1096 KAUAI_FCR_UATA_RESET_N |
1097 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1098
1099 pmif->mediabay = 0;
1100
1101 /* Make sure we have sane timings */
1102 sanitize_timings(pmif);
1103
1104#ifndef CONFIG_PPC64
1105 /* XXX FIXME: Media bay stuff need re-organizing */
1106 if (np->parent && np->parent->name
1107 && strcasecmp(np->parent->name, "media-bay") == 0) {
8c870933 1108#ifdef CONFIG_PMAC_MEDIABAY
1da177e4 1109 media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq, hwif->index);
8c870933 1110#endif /* CONFIG_PMAC_MEDIABAY */
1da177e4
LT		 1111 pmif->mediabay = 1;
1112 if (!bidp)
1113 pmif->aapl_bus_id = 1;
1114 } else if (pmif->kind == controller_ohare) {
1115 /* The code below is having trouble on some ohare machines
1116 * (timing related ?). Until I can put my hand on one of these
1117 * units, I keep the old way
1118 */
1119 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1120 } else
1121#endif
1122 {
1123 /* This is necessary to enable IDE when net-booting */
1124 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1125 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1126 msleep(10);
1127 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1128 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1129 }
1130
1131 /* Setup MMIO ops */
1132 default_hwif_mmiops(hwif);
1133 hwif->OUTBSYNC = pmac_outbsync;
1134
1135 /* Tell common code _not_ to mess with resources */
2ad1e558 1136 hwif->mmio = 1;
1da177e4
LT		 1137 hwif->hwif_data = pmif;
1138 pmac_ide_init_hwif_ports(&hwif->hw, pmif->regbase, 0, &hwif->irq);
1139 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
1140 hwif->chipset = ide_pmac;
1141 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET] || pmif->mediabay;
1142 hwif->hold = pmif->mediabay;
49521f97 1143 hwif->cbl = pmif->cable_80 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
1da177e4
LT		 1144 hwif->drives[0].unmask = 1;
1145 hwif->drives[1].unmask = 1;
aedea591 1146 hwif->host_flags = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA;
4099d143 1147 hwif->pio_mask = ATA_PIO4;
26bcb879 1148 hwif->set_pio_mode = pmac_ide_set_pio_mode;
1da177e4
LT		 1149 if (pmif->kind == controller_un_ata6
1150 || pmif->kind == controller_k2_ata6
1151 || pmif->kind == controller_sh_ata6)
1152 hwif->selectproc = pmac_ide_kauai_selectproc;
1153 else
1154 hwif->selectproc = pmac_ide_selectproc;
1155 hwif->speedproc = pmac_ide_tune_chipset;
1156
1da177e4
LT		 1157 printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1158 hwif->index, model_name[pmif->kind], pmif->aapl_bus_id,
1159 pmif->mediabay ? " (mediabay)" : "", hwif->irq);
1160
8c870933 1161#ifdef CONFIG_PMAC_MEDIABAY
1da177e4
LT		 1162 if (pmif->mediabay && check_media_bay_by_base(pmif->regbase, MB_CD) == 0)
1163 hwif->noprobe = 0;
8c870933 1164#endif /* CONFIG_PMAC_MEDIABAY */
1da177e4
LT		 1165
1166 hwif->sg_max_nents = MAX_DCMDS;
1167
1168#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1169 /* has a DBDMA controller channel */
1170 if (pmif->dma_regs)
1171 pmac_ide_setup_dma(pmif, hwif);
1172#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1173
1174 /* We probe the hwif now */
1175 probe_hwif_init(hwif);
1176
5cbf79cd
BZ		 1177 ide_proc_register_port(hwif);
1178
1da177e4
LT		 1179 return 0;
1180}
1181
1182/*
1183 * Attach to a macio probed interface
1184 */
1185static int __devinit
5e655772 1186pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match)
1da177e4
LT		 1187{
1188 void __iomem *base;
1189 unsigned long regbase;
1190 int irq;
1191 ide_hwif_t *hwif;
1192 pmac_ide_hwif_t *pmif;
1193 int i, rc;
1194
1195 i = 0;
1196 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1197 || pmac_ide[i].node != NULL))
1198 ++i;
1199 if (i >= MAX_HWIFS) {
1200 printk(KERN_ERR "ide-pmac: MacIO interface attach with no slot\n");
1201 printk(KERN_ERR " %s\n", mdev->ofdev.node->full_name);
1202 return -ENODEV;
1203 }
1204
1205 pmif = &pmac_ide[i];
1206 hwif = &ide_hwifs[i];
1207
cc5d0189 1208 if (macio_resource_count(mdev) == 0) {
1da177e4
LT		 1209 printk(KERN_WARNING "ide%d: no address for %s\n",
1210 i, mdev->ofdev.node->full_name);
1211 return -ENXIO;
1212 }
1213
1214 /* Request memory resource for IO ports */
1215 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1216 printk(KERN_ERR "ide%d: can't request mmio resource !\n", i);
1217 return -EBUSY;
1218 }
1219
1220 /* XXX This is bogus. Should be fixed in the registry by checking
1221 * the kind of host interrupt controller, a bit like gatwick
1222 * fixes in irq.c. That works well enough for the single case
1223 * where that happens though...
1224 */
1225 if (macio_irq_count(mdev) == 0) {
1226 printk(KERN_WARNING "ide%d: no intrs for device %s, using 13\n",
1227 i, mdev->ofdev.node->full_name);
69917c26 1228 irq = irq_create_mapping(NULL, 13);
1da177e4
LT		 1229 } else
1230 irq = macio_irq(mdev, 0);
1231
1232 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1233 regbase = (unsigned long) base;
1234
1235 hwif->pci_dev = mdev->bus->pdev;
1236 hwif->gendev.parent = &mdev->ofdev.dev;
1237
1238 pmif->mdev = mdev;
1239 pmif->node = mdev->ofdev.node;
1240 pmif->regbase = regbase;
1241 pmif->irq = irq;
1242 pmif->kauai_fcr = NULL;
1243#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1244 if (macio_resource_count(mdev) >= 2) {
1245 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1246 printk(KERN_WARNING "ide%d: can't request DMA resource !\n", i);
1247 else
1248 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1249 } else
1250 pmif->dma_regs = NULL;
1251#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1252 dev_set_drvdata(&mdev->ofdev.dev, hwif);
1253
1254 rc = pmac_ide_setup_device(pmif, hwif);
1255 if (rc != 0) {
1256 /* The inteface is released to the common IDE layer */
1257 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1258 iounmap(base);
1259 if (pmif->dma_regs)
1260 iounmap(pmif->dma_regs);
1261 memset(pmif, 0, sizeof(*pmif));
1262 macio_release_resource(mdev, 0);
1263 if (pmif->dma_regs)
1264 macio_release_resource(mdev, 1);
1265 }
1266
1267 return rc;
1268}
1269
1270static int
8b4b8a24 1271pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
1da177e4
LT		 1272{
1273 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1274 int rc = 0;
1275
8b4b8a24
DB		 1276 if (mesg.event != mdev->ofdev.dev.power.power_state.event
1277 && mesg.event == PM_EVENT_SUSPEND) {
1da177e4
LT		 1278 rc = pmac_ide_do_suspend(hwif);
1279 if (rc == 0)
8b4b8a24 1280 mdev->ofdev.dev.power.power_state = mesg;
1da177e4
LT		 1281 }
1282
1283 return rc;
1284}
1285
1286static int
1287pmac_ide_macio_resume(struct macio_dev *mdev)
1288{
1289 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1290 int rc = 0;
1291
ca078bae 1292 if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
1da177e4
LT		 1293 rc = pmac_ide_do_resume(hwif);
1294 if (rc == 0)
829ca9a3 1295 mdev->ofdev.dev.power.power_state = PMSG_ON;
1da177e4
LT		 1296 }
1297
1298 return rc;
1299}
1300
1301/*
1302 * Attach to a PCI probed interface
1303 */
1304static int __devinit
1305pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1306{
1307 ide_hwif_t *hwif;
1308 struct device_node *np;
1309 pmac_ide_hwif_t *pmif;
1310 void __iomem *base;
1311 unsigned long rbase, rlen;
1312 int i, rc;
1313
1314 np = pci_device_to_OF_node(pdev);
1315 if (np == NULL) {
1316 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1317 return -ENODEV;
1318 }
1319 i = 0;
1320 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1321 || pmac_ide[i].node != NULL))
1322 ++i;
1323 if (i >= MAX_HWIFS) {
1324 printk(KERN_ERR "ide-pmac: PCI interface attach with no slot\n");
1325 printk(KERN_ERR " %s\n", np->full_name);
1326 return -ENODEV;
1327 }
1328
1329 pmif = &pmac_ide[i];
1330 hwif = &ide_hwifs[i];
1331
1332 if (pci_enable_device(pdev)) {
1333 printk(KERN_WARNING "ide%i: Can't enable PCI device for %s\n",
1334 i, np->full_name);
1335 return -ENXIO;
1336 }
1337 pci_set_master(pdev);
1338
1339 if (pci_request_regions(pdev, "Kauai ATA")) {
1340 printk(KERN_ERR "ide%d: Cannot obtain PCI resources for %s\n",
1341 i, np->full_name);
1342 return -ENXIO;
1343 }
1344
1345 hwif->pci_dev = pdev;
1346 hwif->gendev.parent = &pdev->dev;
1347 pmif->mdev = NULL;
1348 pmif->node = np;
1349
1350 rbase = pci_resource_start(pdev, 0);
1351 rlen = pci_resource_len(pdev, 0);
1352
1353 base = ioremap(rbase, rlen);
1354 pmif->regbase = (unsigned long) base + 0x2000;
1355#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1356 pmif->dma_regs = base + 0x1000;
1357#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1358 pmif->kauai_fcr = base;
1359 pmif->irq = pdev->irq;
1360
1361 pci_set_drvdata(pdev, hwif);
1362
1363 rc = pmac_ide_setup_device(pmif, hwif);
1364 if (rc != 0) {
1365 /* The inteface is released to the common IDE layer */
1366 pci_set_drvdata(pdev, NULL);
1367 iounmap(base);
1368 memset(pmif, 0, sizeof(*pmif));
1369 pci_release_regions(pdev);
1370 }
1371
1372 return rc;
1373}
1374
1375static int
8b4b8a24 1376pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
1da177e4
LT		 1377{
1378 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1379 int rc = 0;
1380
8b4b8a24
DB		 1381 if (mesg.event != pdev->dev.power.power_state.event
1382 && mesg.event == PM_EVENT_SUSPEND) {
1da177e4
LT		 1383 rc = pmac_ide_do_suspend(hwif);
1384 if (rc == 0)
8b4b8a24 1385 pdev->dev.power.power_state = mesg;
1da177e4
LT		 1386 }
1387
1388 return rc;
1389}
1390
1391static int
1392pmac_ide_pci_resume(struct pci_dev *pdev)
1393{
1394 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1395 int rc = 0;
1396
ca078bae 1397 if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
1da177e4
LT		 1398 rc = pmac_ide_do_resume(hwif);
1399 if (rc == 0)
829ca9a3 1400 pdev->dev.power.power_state = PMSG_ON;
1da177e4
LT		 1401 }
1402
1403 return rc;
1404}
1405
5e655772 1406static struct of_device_id pmac_ide_macio_match[] =
1da177e4
LT		 1407{
1408 {
1409 .name = "IDE",
1da177e4
LT		 1410 },
1411 {
1412 .name = "ATA",
1da177e4
LT		 1413 },
1414 {
1da177e4 1415 .type = "ide",
1da177e4
LT		 1416 },
1417 {
1da177e4 1418 .type = "ata",
1da177e4
LT		 1419 },
1420 {},
1421};
1422
1423static struct macio_driver pmac_ide_macio_driver =
1424{
1425 .name = "ide-pmac",
1426 .match_table = pmac_ide_macio_match,
1427 .probe = pmac_ide_macio_attach,
1428 .suspend = pmac_ide_macio_suspend,
1429 .resume = pmac_ide_macio_resume,
1430};
1431
1432static struct pci_device_id pmac_ide_pci_match[] = {
7fce260a
OJ		 1433 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA,
1434 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1435 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100,
1436 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1437 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100,
1438 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1da177e4
LT		 1439 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_ATA,
1440 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
7fce260a
OJ		 1441 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA,
1442 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
71e4eda8 1443 {},
1da177e4
LT		 1444};
1445
1446static struct pci_driver pmac_ide_pci_driver = {
1447 .name = "ide-pmac",
1448 .id_table = pmac_ide_pci_match,
1449 .probe = pmac_ide_pci_attach,
1450 .suspend = pmac_ide_pci_suspend,
1451 .resume = pmac_ide_pci_resume,
1452};
1453MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1454
9e5755bc 1455int __init pmac_ide_probe(void)
1da177e4 1456{
9e5755bc
AM		 1457 int error;
1458
e8222502 1459 if (!machine_is(powermac))
9e5755bc 1460 return -ENODEV;
1da177e4
LT		 1461
1462#ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
9e5755bc
AM		 1463 error = pci_register_driver(&pmac_ide_pci_driver);
1464 if (error)
1465 goto out;
1466 error = macio_register_driver(&pmac_ide_macio_driver);
1467 if (error) {
1468 pci_unregister_driver(&pmac_ide_pci_driver);
1469 goto out;
1470 }
1da177e4 1471#else
9e5755bc
AM		 1472 error = macio_register_driver(&pmac_ide_macio_driver);
1473 if (error)
1474 goto out;
1475 error = pci_register_driver(&pmac_ide_pci_driver);
1476 if (error) {
1477 macio_unregister_driver(&pmac_ide_macio_driver);
1478 goto out;
1479 }
1beb6a7d 1480#endif
9e5755bc
AM		 1481out:
1482 return error;
1da177e4
LT		 1483}
1484
1485#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1486
1487/*
1488 * pmac_ide_build_dmatable builds the DBDMA command list
1489 * for a transfer and sets the DBDMA channel to point to it.
1490 */
aacaf9bd 1491static int
1da177e4
LT		 1492pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq)
1493{
1494 struct dbdma_cmd *table;
1495 int i, count = 0;
1496 ide_hwif_t *hwif = HWIF(drive);
1497 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1498 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1499 struct scatterlist *sg;
1500 int wr = (rq_data_dir(rq) == WRITE);
1501
1502 /* DMA table is already aligned */
1503 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1504
1505 /* Make sure DMA controller is stopped (necessary ?) */
1506 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1507 while (readl(&dma->status) & RUN)
1508 udelay(1);
1509
1510 hwif->sg_nents = i = ide_build_sglist(drive, rq);
1511
1512 if (!i)
1513 return 0;
1514
1515 /* Build DBDMA commands list */
1516 sg = hwif->sg_table;
1517 while (i && sg_dma_len(sg)) {
1518 u32 cur_addr;
1519 u32 cur_len;
1520
1521 cur_addr = sg_dma_address(sg);
1522 cur_len = sg_dma_len(sg);
1523
1524 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1525 if (pmif->broken_dma_warn == 0) {
1526 printk(KERN_WARNING "%s: DMA on non aligned address,"
1527 "switching to PIO on Ohare chipset\n", drive->name);
1528 pmif->broken_dma_warn = 1;
1529 }
1530 goto use_pio_instead;
1531 }
1532 while (cur_len) {
1533 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1534
1535 if (count++ >= MAX_DCMDS) {
1536 printk(KERN_WARNING "%s: DMA table too small\n",
1537 drive->name);
1538 goto use_pio_instead;
1539 }
1540 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1541 st_le16(&table->req_count, tc);
1542 st_le32(&table->phy_addr, cur_addr);
1543 table->cmd_dep = 0;
1544 table->xfer_status = 0;
1545 table->res_count = 0;
1546 cur_addr += tc;
1547 cur_len -= tc;
1548 ++table;
1549 }
1550 sg++;
1551 i--;
1552 }
1553
1554 /* convert the last command to an input/output last command */
1555 if (count) {
1556 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1557 /* add the stop command to the end of the list */
1558 memset(table, 0, sizeof(struct dbdma_cmd));
1559 st_le16(&table->command, DBDMA_STOP);
1560 mb();
1561 writel(hwif->dmatable_dma, &dma->cmdptr);
1562 return 1;
1563 }
1564
1565 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
1566 use_pio_instead:
1567 pci_unmap_sg(hwif->pci_dev,
1568 hwif->sg_table,
1569 hwif->sg_nents,
1570 hwif->sg_dma_direction);
1571 return 0; /* revert to PIO for this request */
1572}
1573
1574/* Teardown mappings after DMA has completed. */
aacaf9bd 1575static void
1da177e4
LT		 1576pmac_ide_destroy_dmatable (ide_drive_t *drive)
1577{
1578 ide_hwif_t *hwif = drive->hwif;
1579 struct pci_dev *dev = HWIF(drive)->pci_dev;
1580 struct scatterlist *sg = hwif->sg_table;
1581 int nents = hwif->sg_nents;
1582
1583 if (nents) {
1584 pci_unmap_sg(dev, sg, nents, hwif->sg_dma_direction);
1585 hwif->sg_nents = 0;
1586 }
1587}
1588
1da177e4
LT		 1589/*
1590 * Check what is the best DMA timing setting for the drive and
1591 * call appropriate functions to apply it.
1592 */
aacaf9bd 1593static int
1da177e4
LT		 1594pmac_ide_dma_check(ide_drive_t *drive)
1595{
254bb550
BZ		 1596 if (ide_tune_dma(drive))
1597 return 0;
fd553ce8 1598
254bb550 1599 return -1;
1da177e4
LT		 1600}
1601
1602/*
1603 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1604 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1605 */
aacaf9bd 1606static int
1da177e4
LT		 1607pmac_ide_dma_setup(ide_drive_t *drive)
1608{
1609 ide_hwif_t *hwif = HWIF(drive);
1610 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1611 struct request *rq = HWGROUP(drive)->rq;
1612 u8 unit = (drive->select.b.unit & 0x01);
1613 u8 ata4;
1614
1615 if (pmif == NULL)
1616 return 1;
1617 ata4 = (pmif->kind == controller_kl_ata4);
1618
1619 if (!pmac_ide_build_dmatable(drive, rq)) {
1620 ide_map_sg(drive, rq);
1621 return 1;
1622 }
1623
1624 /* Apple adds 60ns to wrDataSetup on reads */
1625 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1626 writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0),
1627 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1628 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1629 }
1630
1631 drive->waiting_for_dma = 1;
1632
1633 return 0;
1634}
1635
aacaf9bd 1636static void
1da177e4
LT		 1637pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
1638{
1639 /* issue cmd to drive */
1640 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL);
1641}
1642
1643/*
1644 * Kick the DMA controller into life after the DMA command has been issued
1645 * to the drive.
1646 */
aacaf9bd 1647static void
1da177e4
LT		 1648pmac_ide_dma_start(ide_drive_t *drive)
1649{
1650 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1651 volatile struct dbdma_regs __iomem *dma;
1652
1653 dma = pmif->dma_regs;
1654
1655 writel((RUN << 16) | RUN, &dma->control);
1656 /* Make sure it gets to the controller right now */
1657 (void)readl(&dma->control);
1658}
1659
1660/*
1661 * After a DMA transfer, make sure the controller is stopped
1662 */
aacaf9bd 1663static int
1da177e4
LT		 1664pmac_ide_dma_end (ide_drive_t *drive)
1665{
1666 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1667 volatile struct dbdma_regs __iomem *dma;
1668 u32 dstat;
1669
1670 if (pmif == NULL)
1671 return 0;
1672 dma = pmif->dma_regs;
1673
1674 drive->waiting_for_dma = 0;
1675 dstat = readl(&dma->status);
1676 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
1677 pmac_ide_destroy_dmatable(drive);
1678 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1679 * in theory, but with ATAPI decices doing buffer underruns, that would
1680 * cause us to disable DMA, which isn't what we want
1681 */
1682 return (dstat & (RUN|DEAD)) != RUN;
1683}
1684
1685/*
1686 * Check out that the interrupt we got was for us. We can't always know this
1687 * for sure with those Apple interfaces (well, we could on the recent ones but
1688 * that's not implemented yet), on the other hand, we don't have shared interrupts
1689 * so it's not really a problem
1690 */
aacaf9bd 1691static int
1da177e4
LT		 1692pmac_ide_dma_test_irq (ide_drive_t *drive)
1693{
1694 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1695 volatile struct dbdma_regs __iomem *dma;
1696 unsigned long status, timeout;
1697
1698 if (pmif == NULL)
1699 return 0;
1700 dma = pmif->dma_regs;
1701
1702 /* We have to things to deal with here:
1703 *
1704 * - The dbdma won't stop if the command was started
1705 * but completed with an error without transferring all
1706 * datas. This happens when bad blocks are met during
1707 * a multi-block transfer.
1708 *
1709 * - The dbdma fifo hasn't yet finished flushing to
1710 * to system memory when the disk interrupt occurs.
1711 *
1712 */
1713
1714 /* If ACTIVE is cleared, the STOP command have passed and
1715 * transfer is complete.
1716 */
1717 status = readl(&dma->status);
1718 if (!(status & ACTIVE))
1719 return 1;
1720 if (!drive->waiting_for_dma)
1721 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1722 called while not waiting\n", HWIF(drive)->index);
1723
1724 /* If dbdma didn't execute the STOP command yet, the
1725 * active bit is still set. We consider that we aren't
1726 * sharing interrupts (which is hopefully the case with
1727 * those controllers) and so we just try to flush the
1728 * channel for pending data in the fifo
1729 */
1730 udelay(1);
1731 writel((FLUSH << 16) | FLUSH, &dma->control);
1732 timeout = 0;
1733 for (;;) {
1734 udelay(1);
1735 status = readl(&dma->status);
1736 if ((status & FLUSH) == 0)
1737 break;
1738 if (++timeout > 100) {
1739 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1740 timeout flushing channel\n", HWIF(drive)->index);
1741 break;
1742 }
1743 }
1744 return 1;
1745}
1746
7469aaf6 1747static void pmac_ide_dma_host_off(ide_drive_t *drive)
1da177e4 1748{
1da177e4
LT		 1749}
1750
9e5755bc 1751static void pmac_ide_dma_host_on(ide_drive_t *drive)
1da177e4 1752{
1da177e4
LT		 1753}
1754
841d2a9b
SS		 1755static void
1756pmac_ide_dma_lost_irq (ide_drive_t *drive)
1da177e4
LT		 1757{
1758 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1759 volatile struct dbdma_regs __iomem *dma;
1760 unsigned long status;
1761
1762 if (pmif == NULL)
841d2a9b 1763 return;
1da177e4
LT		 1764 dma = pmif->dma_regs;
1765
1766 status = readl(&dma->status);
1767 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
1da177e4
LT		 1768}
1769
1770/*
1771 * Allocate the data structures needed for using DMA with an interface
1772 * and fill the proper list of functions pointers
1773 */
1774static void __init
1775pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1776{
1777 /* We won't need pci_dev if we switch to generic consistent
1778 * DMA routines ...
1779 */
1780 if (hwif->pci_dev == NULL)
1781 return;
1782 /*
1783 * Allocate space for the DBDMA commands.
1784 * The +2 is +1 for the stop command and +1 to allow for
1785 * aligning the start address to a multiple of 16 bytes.
1786 */
1787 pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent(
1788 hwif->pci_dev,
1789 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
1790 &hwif->dmatable_dma);
1791 if (pmif->dma_table_cpu == NULL) {
1792 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
1793 hwif->name);
1794 return;
1795 }
1796
7469aaf6 1797 hwif->dma_off_quietly = &ide_dma_off_quietly;
1da177e4
LT		 1798 hwif->ide_dma_on = &__ide_dma_on;
1799 hwif->ide_dma_check = &pmac_ide_dma_check;
1800 hwif->dma_setup = &pmac_ide_dma_setup;
1801 hwif->dma_exec_cmd = &pmac_ide_dma_exec_cmd;
1802 hwif->dma_start = &pmac_ide_dma_start;
1803 hwif->ide_dma_end = &pmac_ide_dma_end;
1804 hwif->ide_dma_test_irq = &pmac_ide_dma_test_irq;
7469aaf6 1805 hwif->dma_host_off = &pmac_ide_dma_host_off;
ccf35289 1806 hwif->dma_host_on = &pmac_ide_dma_host_on;
c283f5db 1807 hwif->dma_timeout = &ide_dma_timeout;
841d2a9b 1808 hwif->dma_lost_irq = &pmac_ide_dma_lost_irq;
1da177e4
LT		 1809
1810 hwif->atapi_dma = 1;
1811 switch(pmif->kind) {
1812 case controller_sh_ata6:
1813 hwif->ultra_mask = pmif->cable_80 ? 0x7f : 0x07;
1814 hwif->mwdma_mask = 0x07;
1815 hwif->swdma_mask = 0x00;
1816 break;
1817 case controller_un_ata6:
1818 case controller_k2_ata6:
1819 hwif->ultra_mask = pmif->cable_80 ? 0x3f : 0x07;
1820 hwif->mwdma_mask = 0x07;
1821 hwif->swdma_mask = 0x00;
1822 break;
1823 case controller_kl_ata4:
1824 hwif->ultra_mask = pmif->cable_80 ? 0x1f : 0x07;
1825 hwif->mwdma_mask = 0x07;
1826 hwif->swdma_mask = 0x00;
1827 break;
1828 default:
1829 hwif->ultra_mask = 0x00;
1830 hwif->mwdma_mask = 0x07;
1831 hwif->swdma_mask = 0x00;
1832 break;
254bb550
BZ		 1833 }
1834
1835 hwif->autodma = 1;
1836 hwif->drives[1].autodma = hwif->drives[0].autodma = hwif->autodma;
1da177e4
LT		 1837}
1838
1839#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
kernel source for telekom puls (alcatel/mediatek)