[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / serverworks.c

/*
 * Copyright (C) 1998-2000 Michel Aubry
 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
 * Copyright (C)      2007 Bartlomiej Zolnierkiewicz
 * Portions copyright (c) 2001 Sun Microsystems
 *
 *
 * RCC/ServerWorks IDE driver for Linux
 *
 *   OSB4: `Open South Bridge' IDE Interface (fn 1)
 *         supports UDMA mode 2 (33 MB/s)
 *
 *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
 *         all revisions support UDMA mode 4 (66 MB/s)
 *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
 *
 *         *** The CSB5 does not provide ANY register ***
 *         *** to detect 80-conductor cable presence. ***
 *
 *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
 *
 *   HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
 *   controller same as the CSB6. Single channel ATA100 only.
 *
 * Documentation:
 *	Available under NDA only. Errata info very hard to get.
 *
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

#define SVWKS_CSB5_REVISION_NEW	0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
#define SVWKS_CSB6_REVISION	0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */

/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
 * can overrun their FIFOs when used with the CSB5 */
static const char *svwks_bad_ata100[] = {
	"ST320011A",
	"ST340016A",
	"ST360021A",
	"ST380021A",
	NULL
};

static struct pci_dev *isa_dev;

static int check_in_drive_lists (ide_drive_t *drive, const char **list)
{
	while (*list)
		if (!strcmp(*list++, drive->id->model))
			return 1;
	return 0;
}

static u8 svwks_udma_filter(ide_drive_t *drive)
{
	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
	u8 mask = 0;

	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
		return 0x1f;
	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
		u32 reg = 0;
		if (isa_dev)
			pci_read_config_dword(isa_dev, 0x64, &reg);
			
		/*
		 *	Don't enable UDMA on disk devices for the moment
		 */
		if(drive->media == ide_disk)
			return 0;
		/* Check the OSB4 DMA33 enable bit */
		return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0;
	} else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
		return 0x07;
	} else if (dev->revision >= SVWKS_CSB5_REVISION_NEW) {
		u8 btr = 0, mode;
		pci_read_config_byte(dev, 0x5A, &btr);
		mode = btr & 0x3;

		/* If someone decides to do UDMA133 on CSB5 the same
		   issue will bite so be inclusive */
		if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
			mode = 2;

		switch(mode) {
		case 3:	 mask = 0x3f; break;
		case 2:	 mask = 0x1f; break;
		case 1:	 mask = 0x07; break;
		default: mask = 0x00; break;
		}
	}
	if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
	     (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
	    (!(PCI_FUNC(dev->devfn) & 1)))
		mask = 0x1f;

	return mask;
}

static u8 svwks_csb_check (struct pci_dev *dev)
{
	switch (dev->device) {
		case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
		case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
			return 1;
		default:
			break;
	}
	return 0;
}

static void svwks_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
	static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };

	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);

	pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);

	if (svwks_csb_check(dev)) {
		u16 csb_pio = 0;

		pci_read_config_word(dev, 0x4a, &csb_pio);

		csb_pio &= ~(0x0f << (4 * drive->dn));
		csb_pio |= (pio << (4 * drive->dn));

		pci_write_config_word(dev, 0x4a, csb_pio);
	}
}

static void svwks_set_dma_mode(ide_drive_t *drive, const u8 speed)
{
	static const u8 udma_modes[]		= { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
	static const u8 dma_modes[]		= { 0x77, 0x21, 0x20 };
	static const u8 drive_pci2[]		= { 0x45, 0x44, 0x47, 0x46 };

	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	u8 unit			= (drive->select.b.unit & 0x01);

	u8 ultra_enable	 = 0, ultra_timing = 0, dma_timing = 0;

	pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
	pci_read_config_byte(dev, 0x54, &ultra_enable);

	ultra_timing	&= ~(0x0F << (4*unit));
	ultra_enable	&= ~(0x01 << drive->dn);

	if (speed >= XFER_UDMA_0) {
		dma_timing   |= dma_modes[2];
		ultra_timing |= (udma_modes[speed - XFER_UDMA_0] << (4 * unit));
		ultra_enable |= (0x01 << drive->dn);
	} else if (speed >= XFER_MW_DMA_0)
		dma_timing   |= dma_modes[speed - XFER_MW_DMA_0];

	pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
	pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
	pci_write_config_byte(dev, 0x54, ultra_enable);
}

static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name)
{
	unsigned int reg;
	u8 btr;

	/* force Master Latency Timer value to 64 PCICLKs */
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);

	/* OSB4 : South Bridge and IDE */
	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
		isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
			  PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
		if (isa_dev) {
			pci_read_config_dword(isa_dev, 0x64, &reg);
			reg &= ~0x00002000; /* disable 600ns interrupt mask */
			if(!(reg & 0x00004000))
				printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
			reg |=  0x00004000; /* enable UDMA/33 support */
			pci_write_config_dword(isa_dev, 0x64, reg);
		}
	}

	/* setup CSB5/CSB6 : South Bridge and IDE option RAID */
	else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
		 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
		 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {

		/* Third Channel Test */
		if (!(PCI_FUNC(dev->devfn) & 1)) {
			struct pci_dev * findev = NULL;
			u32 reg4c = 0;
			findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
				PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
			if (findev) {
				pci_read_config_dword(findev, 0x4C, &reg4c);
				reg4c &= ~0x000007FF;
				reg4c |=  0x00000040;
				reg4c |=  0x00000020;
				pci_write_config_dword(findev, 0x4C, reg4c);
				pci_dev_put(findev);
			}
			outb_p(0x06, 0x0c00);
			dev->irq = inb_p(0x0c01);
		} else {
			struct pci_dev * findev = NULL;
			u8 reg41 = 0;

			findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
					PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
			if (findev) {
				pci_read_config_byte(findev, 0x41, &reg41);
				reg41 &= ~0x40;
				pci_write_config_byte(findev, 0x41, reg41);
				pci_dev_put(findev);
			}
			/*
			 * This is a device pin issue on CSB6.
			 * Since there will be a future raid mode,
			 * early versions of the chipset require the
			 * interrupt pin to be set, and it is a compatibility
			 * mode issue.
			 */
			if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
				dev->irq = 0;
		}
//		pci_read_config_dword(dev, 0x40, &pioreg)
//		pci_write_config_dword(dev, 0x40, 0x99999999);
//		pci_read_config_dword(dev, 0x44, &dmareg);
//		pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
		/* setup the UDMA Control register
		 *
		 * 1. clear bit 6 to enable DMA
		 * 2. enable DMA modes with bits 0-1
		 * 	00 : legacy
		 * 	01 : udma2
		 * 	10 : udma2/udma4
		 * 	11 : udma2/udma4/udma5
		 */
		pci_read_config_byte(dev, 0x5A, &btr);
		btr &= ~0x40;
		if (!(PCI_FUNC(dev->devfn) & 1))
			btr |= 0x2;
		else
			btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
		pci_write_config_byte(dev, 0x5A, btr);
	}
	/* Setup HT1000 SouthBridge Controller - Single Channel Only */
	else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
		pci_read_config_byte(dev, 0x5A, &btr);
		btr &= ~0x40;
		btr |= 0x3;
		pci_write_config_byte(dev, 0x5A, btr);
	}

	return dev->irq;
}

static u8 __devinit ata66_svwks_svwks(ide_hwif_t *hwif)
{
	return ATA_CBL_PATA80;
}

/* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
 * of the subsystem device ID indicate presence of an 80-pin cable.
 * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
 * Bit 15 set   = secondary IDE channel has 80-pin cable.
 * Bit 14 clear = primary IDE channel does not have 80-pin cable.
 * Bit 14 set   = primary IDE channel has 80-pin cable.
 */
static u8 __devinit ata66_svwks_dell(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);

	if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
	    dev->vendor	== PCI_VENDOR_ID_SERVERWORKS &&
	    (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
	     dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
		return ((1 << (hwif->channel + 14)) &
			dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
	return ATA_CBL_PATA40;
}

/* Sun Cobalt Alpine hardware avoids the 80-pin cable
 * detect issue by attaching the drives directly to the board.
 * This check follows the Dell precedent (how scary is that?!)
 *
 * WARNING: this only works on Alpine hardware!
 */
static u8 __devinit ata66_svwks_cobalt(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);

	if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
	    dev->vendor	== PCI_VENDOR_ID_SERVERWORKS &&
	    dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
		return ((1 << (hwif->channel + 14)) &
			dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
	return ATA_CBL_PATA40;
}

static u8 __devinit ata66_svwks(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);

	/* Server Works */
	if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
		return ata66_svwks_svwks (hwif);
	
	/* Dell PowerEdge */
	if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
		return ata66_svwks_dell (hwif);

	/* Cobalt Alpine */
	if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
		return ata66_svwks_cobalt (hwif);

	/* Per Specified Design by OEM, and ASIC Architect */
	if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
	    (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
		return ATA_CBL_PATA80;

	return ATA_CBL_PATA40;
}

static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);

	hwif->set_pio_mode = &svwks_set_pio_mode;
	hwif->set_dma_mode = &svwks_set_dma_mode;
	hwif->udma_filter = &svwks_udma_filter;

	if (dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
		hwif->cable_detect = ata66_svwks;
}

#define IDE_HFLAGS_SVWKS \
	(IDE_HFLAG_LEGACY_IRQS | \
	 IDE_HFLAG_ABUSE_SET_DMA_MODE)

static const struct ide_port_info serverworks_chipsets[] __devinitdata = {
	{	/* 0 */
		.name		= "SvrWks OSB4",
		.init_chipset	= init_chipset_svwks,
		.init_hwif	= init_hwif_svwks,
		.host_flags	= IDE_HFLAGS_SVWKS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= 0x00, /* UDMA is problematic on OSB4 */
	},{	/* 1 */
		.name		= "SvrWks CSB5",
		.init_chipset	= init_chipset_svwks,
		.init_hwif	= init_hwif_svwks,
		.host_flags	= IDE_HFLAGS_SVWKS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	},{	/* 2 */
		.name		= "SvrWks CSB6",
		.init_chipset	= init_chipset_svwks,
		.init_hwif	= init_hwif_svwks,
		.host_flags	= IDE_HFLAGS_SVWKS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	},{	/* 3 */
		.name		= "SvrWks CSB6",
		.init_chipset	= init_chipset_svwks,
		.init_hwif	= init_hwif_svwks,
		.host_flags	= IDE_HFLAGS_SVWKS | IDE_HFLAG_SINGLE,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	},{	/* 4 */
		.name		= "SvrWks HT1000",
		.init_chipset	= init_chipset_svwks,
		.init_hwif	= init_hwif_svwks,
		.host_flags	= IDE_HFLAGS_SVWKS | IDE_HFLAG_SINGLE,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	}
};

/**
 *	svwks_init_one	-	called when a OSB/CSB is found
 *	@dev: the svwks device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct ide_port_info d;
	u8 idx = id->driver_data;

	d = serverworks_chipsets[idx];

	if (idx == 1)
		d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
	else if (idx == 2 || idx == 3) {
		if ((PCI_FUNC(dev->devfn) & 1) == 0) {
			if (pci_resource_start(dev, 0) != 0x01f1)
				d.host_flags |= IDE_HFLAG_NON_BOOTABLE;
			d.host_flags |= IDE_HFLAG_SINGLE;
		} else
			d.host_flags &= ~IDE_HFLAG_SINGLE;
	}

	return ide_setup_pci_device(dev, &d);
}

static const struct pci_device_id svwks_pci_tbl[] = {
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE),   0 },
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE),   1 },
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE),   2 },
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2),  3 },
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);

static struct pci_driver driver = {
	.name		= "Serverworks_IDE",
	.id_table	= svwks_pci_tbl,
	.probe		= svwks_init_one,
};

static int __init svwks_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(svwks_ide_init);

MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1998-2000 Michel Aubry
	3	* Copyright (C) 1998-2000 Andrzej Krzysztofowicz
	4	* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
9445de76	5	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
1da177e4 LT	6	* Portions copyright (c) 2001 Sun Microsystems
	7	*
	8	*
	9	* RCC/ServerWorks IDE driver for Linux
	10	*
	11	* OSB4: `Open South Bridge' IDE Interface (fn 1)
	12	* supports UDMA mode 2 (33 MB/s)
	13	*
	14	* CSB5: `Champion South Bridge' IDE Interface (fn 1)
	15	* all revisions support UDMA mode 4 (66 MB/s)
	16	* revision A2.0 and up support UDMA mode 5 (100 MB/s)
	17	*
	18	* * The CSB5 does not provide ANY register *
	19	* * to detect 80-conductor cable presence. *
	20	*
	21	* CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
	22	*
84f57fbc NS	23	* HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
	24	* controller same as the CSB6. Single channel ATA100 only.
	25	*
1da177e4 LT	26	* Documentation:
	27	* Available under NDA only. Errata info very hard to get.
	28	*
	29	*/
	30
1da177e4 LT	31	#include <linux/types.h>
	32	#include <linux/module.h>
	33	#include <linux/kernel.h>
1da177e4 LT	34	#include <linux/pci.h>
	35	#include <linux/hdreg.h>
	36	#include <linux/ide.h>
	37	#include <linux/init.h>
1da177e4 LT	38
	39	#include <asm/io.h>
	40
	41	#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
	42	#define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
	43
	44	/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
	45	* can overrun their FIFOs when used with the CSB5 */
	46	static const char *svwks_bad_ata100[] = {
	47	"ST320011A",
	48	"ST340016A",
	49	"ST360021A",
	50	"ST380021A",
	51	NULL
	52	};
	53
1da177e4 LT	54	static struct pci_dev *isa_dev;
	55
	56	static int check_in_drive_lists (ide_drive_t drive, const char *list)
	57	{
	58	while (*list)
	59	if (!strcmp(*list++, drive->id->model))
	60	return 1;
	61	return 0;
	62	}
	63
2d5eaa6d	64	static u8 svwks_udma_filter(ide_drive_t *drive)
1da177e4	65	{
36501650	66	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
2d5eaa6d	67	u8 mask = 0;
1da177e4	68
84f57fbc	69	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
2d5eaa6d	70	return 0x1f;
1da177e4 LT	71	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
	72	u32 reg = 0;
	73	if (isa_dev)
	74	pci_read_config_dword(isa_dev, 0x64, &reg);
	75
	76	/*
	77	* Don't enable UDMA on disk devices for the moment
	78	*/
	79	if(drive->media == ide_disk)
	80	return 0;
	81	/* Check the OSB4 DMA33 enable bit */
2d5eaa6d	82	return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0;
44c10138	83	} else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
2d5eaa6d	84	return 0x07;
44c10138	85	} else if (dev->revision >= SVWKS_CSB5_REVISION_NEW) {
2d5eaa6d	86	u8 btr = 0, mode;
1da177e4 LT	87	pci_read_config_byte(dev, 0x5A, &btr);
1da177e4 LT	88	mode = btr & 0x3;
2d5eaa6d	89
1da177e4 LT	90	/* If someone decides to do UDMA133 on CSB5 the same
	91	issue will bite so be inclusive */
	92	if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
	93	mode = 2;
2d5eaa6d BZ	94
2d5eaa6d BZ	95	switch(mode) {
0c824b51	96	case 3: mask = 0x3f; break;
2d5eaa6d BZ	97	case 2: mask = 0x1f; break;
	98	case 1: mask = 0x07; break;
	99	default: mask = 0x00; break;
	100	}
1da177e4 LT	101	}
	102	if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) \|\|
	103	(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
	104	(!(PCI_FUNC(dev->devfn) & 1)))
2d5eaa6d BZ	105	mask = 0x1f;
	106
	107	return mask;
1da177e4 LT	108	}
	109
	110	static u8 svwks_csb_check (struct pci_dev *dev)
	111	{
	112	switch (dev->device) {
	113	case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
	114	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
	115	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
84f57fbc	116	case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
1da177e4 LT	117	return 1;
	118	default:
	119	break;
	120	}
	121	return 0;
	122	}
1880a8d7	123
88b2b32b	124	static void svwks_set_pio_mode(ide_drive_t *drive, const u8 pio)
1880a8d7 BZ	125	{
	126	static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
	127	static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
	128
36501650	129	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
1880a8d7 BZ	130
	131	pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);
	132
	133	if (svwks_csb_check(dev)) {
	134	u16 csb_pio = 0;
	135
	136	pci_read_config_word(dev, 0x4a, &csb_pio);
	137
	138	csb_pio &= ~(0x0f << (4 * drive->dn));
	139	csb_pio \|= (pio << (4 * drive->dn));
	140
	141	pci_write_config_word(dev, 0x4a, csb_pio);
	142	}
	143	}
	144
88b2b32b	145	static void svwks_set_dma_mode(ide_drive_t *drive, const u8 speed)
1da177e4	146	{
f201f504 AC	147	static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
f201f504 AC	148	static const u8 dma_modes[] = { 0x77, 0x21, 0x20 };
f201f504	149	static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 };
1da177e4 LT	150
1da177e4 LT	151	ide_hwif_t *hwif = HWIF(drive);
36501650	152	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	153	u8 unit = (drive->select.b.unit & 0x01);
1880a8d7 BZ	154
	155	u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0;
	156
1da177e4	157	pci_read_config_byte(dev, (0x56\|hwif->channel), &ultra_timing);
1da177e4 LT	158	pci_read_config_byte(dev, 0x54, &ultra_enable);
1da177e4 LT	159
1da177e4 LT	160	ultra_timing &= ~(0x0F << (4*unit));
1da177e4 LT	161	ultra_enable &= ~(0x01 << drive->dn);
1da177e4	162
7b971df1 BZ	163	if (speed >= XFER_UDMA_0) {
	164	dma_timing \|= dma_modes[2];
	165	ultra_timing \|= (udma_modes[speed - XFER_UDMA_0] << (4 * unit));
	166	ultra_enable \|= (0x01 << drive->dn);
	167	} else if (speed >= XFER_MW_DMA_0)
	168	dma_timing \|= dma_modes[speed - XFER_MW_DMA_0];
1da177e4	169
1da177e4 LT	170	pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
	171	pci_write_config_byte(dev, (0x56\|hwif->channel), ultra_timing);
	172	pci_write_config_byte(dev, 0x54, ultra_enable);
1da177e4 LT	173	}
1da177e4 LT	174
1da177e4 LT	175	static unsigned int __devinit init_chipset_svwks (struct pci_dev dev, const char name)
	176	{
	177	unsigned int reg;
	178	u8 btr;
	179
1da177e4 LT	180	/* force Master Latency Timer value to 64 PCICLKs */
	181	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
	182
	183	/* OSB4 : South Bridge and IDE */
	184	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
970a6136	185	isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
1da177e4 LT	186	PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
	187	if (isa_dev) {
	188	pci_read_config_dword(isa_dev, 0x64, &reg);
	189	reg &= ~0x00002000; /* disable 600ns interrupt mask */
	190	if(!(reg & 0x00004000))
	191	printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
	192	reg \|= 0x00004000; /* enable UDMA/33 support */
	193	pci_write_config_dword(isa_dev, 0x64, reg);
	194	}
	195	}
	196
	197	/* setup CSB5/CSB6 : South Bridge and IDE option RAID */
	198	else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) \|\|
	199	(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) \|\|
	200	(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
	201
	202	/* Third Channel Test */
	203	if (!(PCI_FUNC(dev->devfn) & 1)) {
	204	struct pci_dev * findev = NULL;
	205	u32 reg4c = 0;
970a6136	206	findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
1da177e4 LT	207	PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
	208	if (findev) {
	209	pci_read_config_dword(findev, 0x4C, &reg4c);
	210	reg4c &= ~0x000007FF;
	211	reg4c \|= 0x00000040;
	212	reg4c \|= 0x00000020;
	213	pci_write_config_dword(findev, 0x4C, reg4c);
970a6136	214	pci_dev_put(findev);
1da177e4 LT	215	}
	216	outb_p(0x06, 0x0c00);
	217	dev->irq = inb_p(0x0c01);
1da177e4 LT	218	} else {
	219	struct pci_dev * findev = NULL;
	220	u8 reg41 = 0;
	221
970a6136	222	findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
1da177e4 LT	223	PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
	224	if (findev) {
	225	pci_read_config_byte(findev, 0x41, &reg41);
	226	reg41 &= ~0x40;
	227	pci_write_config_byte(findev, 0x41, reg41);
970a6136	228	pci_dev_put(findev);
1da177e4 LT	229	}
	230	/*
	231	* This is a device pin issue on CSB6.
	232	* Since there will be a future raid mode,
	233	* early versions of the chipset require the
	234	* interrupt pin to be set, and it is a compatibility
	235	* mode issue.
	236	*/
	237	if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
	238	dev->irq = 0;
	239	}
	240	// pci_read_config_dword(dev, 0x40, &pioreg)
	241	// pci_write_config_dword(dev, 0x40, 0x99999999);
	242	// pci_read_config_dword(dev, 0x44, &dmareg);
	243	// pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
	244	/* setup the UDMA Control register
	245	*
	246	* 1. clear bit 6 to enable DMA
	247	* 2. enable DMA modes with bits 0-1
	248	* 00 : legacy
	249	* 01 : udma2
	250	* 10 : udma2/udma4
	251	* 11 : udma2/udma4/udma5
	252	*/
	253	pci_read_config_byte(dev, 0x5A, &btr);
	254	btr &= ~0x40;
	255	if (!(PCI_FUNC(dev->devfn) & 1))
	256	btr \|= 0x2;
	257	else
44c10138	258	btr \|= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
1da177e4 LT	259	pci_write_config_byte(dev, 0x5A, btr);
1da177e4 LT	260	}
84f57fbc NS	261	/* Setup HT1000 SouthBridge Controller - Single Channel Only */
	262	else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
	263	pci_read_config_byte(dev, 0x5A, &btr);
	264	btr &= ~0x40;
	265	btr \|= 0x3;
	266	pci_write_config_byte(dev, 0x5A, btr);
	267	}
1da177e4	268
f201f504	269	return dev->irq;
1da177e4 LT	270	}
1da177e4 LT	271
49521f97	272	static u8 __devinit ata66_svwks_svwks(ide_hwif_t *hwif)
1da177e4	273	{
49521f97	274	return ATA_CBL_PATA80;
1da177e4 LT	275	}
	276
	277	/* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
	278	* of the subsystem device ID indicate presence of an 80-pin cable.
	279	* Bit 15 clear = secondary IDE channel does not have 80-pin cable.
	280	* Bit 15 set = secondary IDE channel has 80-pin cable.
	281	* Bit 14 clear = primary IDE channel does not have 80-pin cable.
	282	* Bit 14 set = primary IDE channel has 80-pin cable.
	283	*/
49521f97	284	static u8 __devinit ata66_svwks_dell(ide_hwif_t *hwif)
1da177e4	285	{
36501650 BZ	286	struct pci_dev *dev = to_pci_dev(hwif->dev);
36501650 BZ	287
1da177e4 LT	288	if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
	289	dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
	290	(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE \|\|
	291	dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
	292	return ((1 << (hwif->channel + 14)) &
49521f97 BZ	293	dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
49521f97 BZ	294	return ATA_CBL_PATA40;
1da177e4 LT	295	}
	296
	297	/* Sun Cobalt Alpine hardware avoids the 80-pin cable
	298	* detect issue by attaching the drives directly to the board.
	299	* This check follows the Dell precedent (how scary is that?!)
	300	*
	301	* WARNING: this only works on Alpine hardware!
	302	*/
49521f97	303	static u8 __devinit ata66_svwks_cobalt(ide_hwif_t *hwif)
1da177e4	304	{
36501650 BZ	305	struct pci_dev *dev = to_pci_dev(hwif->dev);
36501650 BZ	306
1da177e4 LT	307	if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
	308	dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
	309	dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
	310	return ((1 << (hwif->channel + 14)) &
49521f97 BZ	311	dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
49521f97 BZ	312	return ATA_CBL_PATA40;
1da177e4 LT	313	}
1da177e4 LT	314
49521f97	315	static u8 __devinit ata66_svwks(ide_hwif_t *hwif)
1da177e4	316	{
36501650	317	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	318
1da177e4 LT	319	/* Server Works */
	320	if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
	321	return ata66_svwks_svwks (hwif);
	322
	323	/* Dell PowerEdge */
	324	if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
	325	return ata66_svwks_dell (hwif);
	326
	327	/* Cobalt Alpine */
	328	if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
	329	return ata66_svwks_cobalt (hwif);
	330
f201f504 AC	331	/* Per Specified Design by OEM, and ASIC Architect */
	332	if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) \|\|
	333	(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
49521f97	334	return ATA_CBL_PATA80;
f201f504	335
49521f97	336	return ATA_CBL_PATA40;
1da177e4 LT	337	}
1da177e4 LT	338
1da177e4 LT	339	static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
1da177e4 LT	340	{
36501650 BZ	341	struct pci_dev *dev = to_pci_dev(hwif->dev);
36501650 BZ	342
26bcb879	343	hwif->set_pio_mode = &svwks_set_pio_mode;
88b2b32b	344	hwif->set_dma_mode = &svwks_set_dma_mode;
2d5eaa6d	345	hwif->udma_filter = &svwks_udma_filter;
1da177e4	346
bfa14b42 BZ	347	if (dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
bfa14b42 BZ	348	hwif->cable_detect = ata66_svwks;
1da177e4 LT	349	}
1da177e4 LT	350
4db90a14 BZ	351	#define IDE_HFLAGS_SVWKS \
4db90a14 BZ	352	(IDE_HFLAG_LEGACY_IRQS \| \
5e71d9c5	353	IDE_HFLAG_ABUSE_SET_DMA_MODE)
4db90a14	354
85620436	355	static const struct ide_port_info serverworks_chipsets[] __devinitdata = {
1da177e4 LT	356	{ /* 0 */
1da177e4 LT	357	.name = "SvrWks OSB4",
1da177e4 LT	358	.init_chipset = init_chipset_svwks,
1da177e4 LT	359	.init_hwif = init_hwif_svwks,
4db90a14	360	.host_flags = IDE_HFLAGS_SVWKS,
4099d143	361	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	362	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	363	.udma_mask = 0x00, /* UDMA is problematic on OSB4 */
1da177e4 LT	364	},{ /* 1 */
1da177e4 LT	365	.name = "SvrWks CSB5",
1da177e4 LT	366	.init_chipset = init_chipset_svwks,
1da177e4 LT	367	.init_hwif = init_hwif_svwks,
4db90a14	368	.host_flags = IDE_HFLAGS_SVWKS,
4099d143	369	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	370	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	371	.udma_mask = ATA_UDMA5,
1da177e4 LT	372	},{ /* 2 */
1da177e4 LT	373	.name = "SvrWks CSB6",
1da177e4 LT	374	.init_chipset = init_chipset_svwks,
1da177e4 LT	375	.init_hwif = init_hwif_svwks,
4db90a14	376	.host_flags = IDE_HFLAGS_SVWKS,
4099d143	377	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	378	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	379	.udma_mask = ATA_UDMA5,
1da177e4 LT	380	},{ /* 3 */
1da177e4 LT	381	.name = "SvrWks CSB6",
1da177e4 LT	382	.init_chipset = init_chipset_svwks,
1da177e4 LT	383	.init_hwif = init_hwif_svwks,
4db90a14	384	.host_flags = IDE_HFLAGS_SVWKS \| IDE_HFLAG_SINGLE,
4099d143	385	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	386	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	387	.udma_mask = ATA_UDMA5,
84f57fbc NS	388	},{ /* 4 */
84f57fbc NS	389	.name = "SvrWks HT1000",
84f57fbc NS	390	.init_chipset = init_chipset_svwks,
84f57fbc NS	391	.init_hwif = init_hwif_svwks,
4db90a14	392	.host_flags = IDE_HFLAGS_SVWKS \| IDE_HFLAG_SINGLE,
4099d143	393	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	394	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	395	.udma_mask = ATA_UDMA5,
1da177e4 LT	396	}
	397	};
	398
	399	/**
	400	* svwks_init_one - called when a OSB/CSB is found
	401	* @dev: the svwks device
	402	* @id: the matching pci id
	403	*
	404	* Called when the PCI registration layer (or the IDE initialization)
	405	* finds a device matching our IDE device tables.
	406	*/
	407
	408	static int __devinit svwks_init_one(struct pci_dev dev, const struct pci_device_id id)
	409	{
039788e1	410	struct ide_port_info d;
7ed58297 BZ	411	u8 idx = id->driver_data;
	412
	413	d = serverworks_chipsets[idx];
	414
8ac2b42a BZ	415	if (idx == 1)
	416	d.host_flags \|= IDE_HFLAG_CLEAR_SIMPLEX;
	417	else if (idx == 2 \|\| idx == 3) {
7ed58297 BZ	418	if ((PCI_FUNC(dev->devfn) & 1) == 0) {
7ed58297 BZ	419	if (pci_resource_start(dev, 0) != 0x01f1)
5e71d9c5	420	d.host_flags \|= IDE_HFLAG_NON_BOOTABLE;
7ed58297 BZ	421	d.host_flags \|= IDE_HFLAG_SINGLE;
	422	} else
	423	d.host_flags &= ~IDE_HFLAG_SINGLE;
	424	}
1da177e4	425
7ed58297	426	return ide_setup_pci_device(dev, &d);
1da177e4 LT	427	}
1da177e4 LT	428
9cbcc5e3 BZ	429	static const struct pci_device_id svwks_pci_tbl[] = {
	430	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0 },
	431	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 1 },
	432	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2 },
	433	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 3 },
	434	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 },
1da177e4 LT	435	{ 0, },
	436	};
	437	MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
	438
	439	static struct pci_driver driver = {
	440	.name = "Serverworks_IDE",
	441	.id_table = svwks_pci_tbl,
	442	.probe = svwks_init_one,
	443	};
	444
82ab1eec	445	static int __init svwks_ide_init(void)
1da177e4 LT	446	{
	447	return ide_pci_register_driver(&driver);
	448	}
	449
	450	module_init(svwks_ide_init);
	451
	452	MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
	453	MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
	454	MODULE_LICENSE("GPL");