Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1998-2000 Michel Aubry |
3 | * Copyright (C) 1998-2000 Andrzej Krzysztofowicz | |
4 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
9445de76 | 5 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
6 | * Portions copyright (c) 2001 Sun Microsystems |
7 | * | |
8 | * | |
9 | * RCC/ServerWorks IDE driver for Linux | |
10 | * | |
11 | * OSB4: `Open South Bridge' IDE Interface (fn 1) | |
12 | * supports UDMA mode 2 (33 MB/s) | |
13 | * | |
14 | * CSB5: `Champion South Bridge' IDE Interface (fn 1) | |
15 | * all revisions support UDMA mode 4 (66 MB/s) | |
16 | * revision A2.0 and up support UDMA mode 5 (100 MB/s) | |
17 | * | |
18 | * *** The CSB5 does not provide ANY register *** | |
19 | * *** to detect 80-conductor cable presence. *** | |
20 | * | |
21 | * CSB6: `Champion South Bridge' IDE Interface (optional: third channel) | |
22 | * | |
84f57fbc NS |
23 | * HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE |
24 | * controller same as the CSB6. Single channel ATA100 only. | |
25 | * | |
1da177e4 LT |
26 | * Documentation: |
27 | * Available under NDA only. Errata info very hard to get. | |
28 | * | |
29 | */ | |
30 | ||
1da177e4 LT |
31 | #include <linux/types.h> |
32 | #include <linux/module.h> | |
33 | #include <linux/kernel.h> | |
34 | #include <linux/ioport.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/hdreg.h> | |
37 | #include <linux/ide.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/delay.h> | |
40 | ||
41 | #include <asm/io.h> | |
42 | ||
43 | #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */ | |
44 | #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */ | |
45 | ||
46 | /* Seagate Barracuda ATA IV Family drives in UDMA mode 5 | |
47 | * can overrun their FIFOs when used with the CSB5 */ | |
48 | static const char *svwks_bad_ata100[] = { | |
49 | "ST320011A", | |
50 | "ST340016A", | |
51 | "ST360021A", | |
52 | "ST380021A", | |
53 | NULL | |
54 | }; | |
55 | ||
1da177e4 LT |
56 | static struct pci_dev *isa_dev; |
57 | ||
58 | static int check_in_drive_lists (ide_drive_t *drive, const char **list) | |
59 | { | |
60 | while (*list) | |
61 | if (!strcmp(*list++, drive->id->model)) | |
62 | return 1; | |
63 | return 0; | |
64 | } | |
65 | ||
2d5eaa6d | 66 | static u8 svwks_udma_filter(ide_drive_t *drive) |
1da177e4 | 67 | { |
36501650 | 68 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
2d5eaa6d | 69 | u8 mask = 0; |
1da177e4 | 70 | |
84f57fbc | 71 | if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) |
2d5eaa6d | 72 | return 0x1f; |
1da177e4 LT |
73 | if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { |
74 | u32 reg = 0; | |
75 | if (isa_dev) | |
76 | pci_read_config_dword(isa_dev, 0x64, ®); | |
77 | ||
78 | /* | |
79 | * Don't enable UDMA on disk devices for the moment | |
80 | */ | |
81 | if(drive->media == ide_disk) | |
82 | return 0; | |
83 | /* Check the OSB4 DMA33 enable bit */ | |
2d5eaa6d | 84 | return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0; |
44c10138 | 85 | } else if (dev->revision < SVWKS_CSB5_REVISION_NEW) { |
2d5eaa6d | 86 | return 0x07; |
44c10138 | 87 | } else if (dev->revision >= SVWKS_CSB5_REVISION_NEW) { |
2d5eaa6d | 88 | u8 btr = 0, mode; |
1da177e4 LT |
89 | pci_read_config_byte(dev, 0x5A, &btr); |
90 | mode = btr & 0x3; | |
2d5eaa6d | 91 | |
1da177e4 LT |
92 | /* If someone decides to do UDMA133 on CSB5 the same |
93 | issue will bite so be inclusive */ | |
94 | if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100)) | |
95 | mode = 2; | |
2d5eaa6d BZ |
96 | |
97 | switch(mode) { | |
0c824b51 | 98 | case 3: mask = 0x3f; break; |
2d5eaa6d BZ |
99 | case 2: mask = 0x1f; break; |
100 | case 1: mask = 0x07; break; | |
101 | default: mask = 0x00; break; | |
102 | } | |
1da177e4 LT |
103 | } |
104 | if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || | |
105 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) && | |
106 | (!(PCI_FUNC(dev->devfn) & 1))) | |
2d5eaa6d BZ |
107 | mask = 0x1f; |
108 | ||
109 | return mask; | |
1da177e4 LT |
110 | } |
111 | ||
112 | static u8 svwks_csb_check (struct pci_dev *dev) | |
113 | { | |
114 | switch (dev->device) { | |
115 | case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: | |
116 | case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE: | |
117 | case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2: | |
84f57fbc | 118 | case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE: |
1da177e4 LT |
119 | return 1; |
120 | default: | |
121 | break; | |
122 | } | |
123 | return 0; | |
124 | } | |
1880a8d7 | 125 | |
88b2b32b | 126 | static void svwks_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1880a8d7 BZ |
127 | { |
128 | static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; | |
129 | static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 }; | |
130 | ||
36501650 | 131 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
1880a8d7 BZ |
132 | |
133 | pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]); | |
134 | ||
135 | if (svwks_csb_check(dev)) { | |
136 | u16 csb_pio = 0; | |
137 | ||
138 | pci_read_config_word(dev, 0x4a, &csb_pio); | |
139 | ||
140 | csb_pio &= ~(0x0f << (4 * drive->dn)); | |
141 | csb_pio |= (pio << (4 * drive->dn)); | |
142 | ||
143 | pci_write_config_word(dev, 0x4a, csb_pio); | |
144 | } | |
145 | } | |
146 | ||
88b2b32b | 147 | static void svwks_set_dma_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 | 148 | { |
f201f504 AC |
149 | static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 }; |
150 | static const u8 dma_modes[] = { 0x77, 0x21, 0x20 }; | |
f201f504 | 151 | static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 }; |
1da177e4 LT |
152 | |
153 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 154 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 155 | u8 unit = (drive->select.b.unit & 0x01); |
1880a8d7 BZ |
156 | |
157 | u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0; | |
158 | ||
1da177e4 | 159 | pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing); |
1da177e4 LT |
160 | pci_read_config_byte(dev, 0x54, &ultra_enable); |
161 | ||
1da177e4 LT |
162 | ultra_timing &= ~(0x0F << (4*unit)); |
163 | ultra_enable &= ~(0x01 << drive->dn); | |
1da177e4 | 164 | |
7b971df1 BZ |
165 | if (speed >= XFER_UDMA_0) { |
166 | dma_timing |= dma_modes[2]; | |
167 | ultra_timing |= (udma_modes[speed - XFER_UDMA_0] << (4 * unit)); | |
168 | ultra_enable |= (0x01 << drive->dn); | |
169 | } else if (speed >= XFER_MW_DMA_0) | |
170 | dma_timing |= dma_modes[speed - XFER_MW_DMA_0]; | |
1da177e4 | 171 | |
1da177e4 LT |
172 | pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing); |
173 | pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing); | |
174 | pci_write_config_byte(dev, 0x54, ultra_enable); | |
1da177e4 LT |
175 | } |
176 | ||
1da177e4 LT |
177 | static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name) |
178 | { | |
179 | unsigned int reg; | |
180 | u8 btr; | |
181 | ||
1da177e4 LT |
182 | /* force Master Latency Timer value to 64 PCICLKs */ |
183 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40); | |
184 | ||
185 | /* OSB4 : South Bridge and IDE */ | |
186 | if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { | |
970a6136 | 187 | isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, |
1da177e4 LT |
188 | PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL); |
189 | if (isa_dev) { | |
190 | pci_read_config_dword(isa_dev, 0x64, ®); | |
191 | reg &= ~0x00002000; /* disable 600ns interrupt mask */ | |
192 | if(!(reg & 0x00004000)) | |
193 | printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name); | |
194 | reg |= 0x00004000; /* enable UDMA/33 support */ | |
195 | pci_write_config_dword(isa_dev, 0x64, reg); | |
196 | } | |
197 | } | |
198 | ||
199 | /* setup CSB5/CSB6 : South Bridge and IDE option RAID */ | |
200 | else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) || | |
201 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || | |
202 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) { | |
203 | ||
204 | /* Third Channel Test */ | |
205 | if (!(PCI_FUNC(dev->devfn) & 1)) { | |
206 | struct pci_dev * findev = NULL; | |
207 | u32 reg4c = 0; | |
970a6136 | 208 | findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, |
1da177e4 LT |
209 | PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL); |
210 | if (findev) { | |
211 | pci_read_config_dword(findev, 0x4C, ®4c); | |
212 | reg4c &= ~0x000007FF; | |
213 | reg4c |= 0x00000040; | |
214 | reg4c |= 0x00000020; | |
215 | pci_write_config_dword(findev, 0x4C, reg4c); | |
970a6136 | 216 | pci_dev_put(findev); |
1da177e4 LT |
217 | } |
218 | outb_p(0x06, 0x0c00); | |
219 | dev->irq = inb_p(0x0c01); | |
1da177e4 LT |
220 | } else { |
221 | struct pci_dev * findev = NULL; | |
222 | u8 reg41 = 0; | |
223 | ||
970a6136 | 224 | findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, |
1da177e4 LT |
225 | PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL); |
226 | if (findev) { | |
227 | pci_read_config_byte(findev, 0x41, ®41); | |
228 | reg41 &= ~0x40; | |
229 | pci_write_config_byte(findev, 0x41, reg41); | |
970a6136 | 230 | pci_dev_put(findev); |
1da177e4 LT |
231 | } |
232 | /* | |
233 | * This is a device pin issue on CSB6. | |
234 | * Since there will be a future raid mode, | |
235 | * early versions of the chipset require the | |
236 | * interrupt pin to be set, and it is a compatibility | |
237 | * mode issue. | |
238 | */ | |
239 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) | |
240 | dev->irq = 0; | |
241 | } | |
242 | // pci_read_config_dword(dev, 0x40, &pioreg) | |
243 | // pci_write_config_dword(dev, 0x40, 0x99999999); | |
244 | // pci_read_config_dword(dev, 0x44, &dmareg); | |
245 | // pci_write_config_dword(dev, 0x44, 0xFFFFFFFF); | |
246 | /* setup the UDMA Control register | |
247 | * | |
248 | * 1. clear bit 6 to enable DMA | |
249 | * 2. enable DMA modes with bits 0-1 | |
250 | * 00 : legacy | |
251 | * 01 : udma2 | |
252 | * 10 : udma2/udma4 | |
253 | * 11 : udma2/udma4/udma5 | |
254 | */ | |
255 | pci_read_config_byte(dev, 0x5A, &btr); | |
256 | btr &= ~0x40; | |
257 | if (!(PCI_FUNC(dev->devfn) & 1)) | |
258 | btr |= 0x2; | |
259 | else | |
44c10138 | 260 | btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2; |
1da177e4 LT |
261 | pci_write_config_byte(dev, 0x5A, btr); |
262 | } | |
84f57fbc NS |
263 | /* Setup HT1000 SouthBridge Controller - Single Channel Only */ |
264 | else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) { | |
265 | pci_read_config_byte(dev, 0x5A, &btr); | |
266 | btr &= ~0x40; | |
267 | btr |= 0x3; | |
268 | pci_write_config_byte(dev, 0x5A, btr); | |
269 | } | |
1da177e4 | 270 | |
f201f504 | 271 | return dev->irq; |
1da177e4 LT |
272 | } |
273 | ||
49521f97 | 274 | static u8 __devinit ata66_svwks_svwks(ide_hwif_t *hwif) |
1da177e4 | 275 | { |
49521f97 | 276 | return ATA_CBL_PATA80; |
1da177e4 LT |
277 | } |
278 | ||
279 | /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits | |
280 | * of the subsystem device ID indicate presence of an 80-pin cable. | |
281 | * Bit 15 clear = secondary IDE channel does not have 80-pin cable. | |
282 | * Bit 15 set = secondary IDE channel has 80-pin cable. | |
283 | * Bit 14 clear = primary IDE channel does not have 80-pin cable. | |
284 | * Bit 14 set = primary IDE channel has 80-pin cable. | |
285 | */ | |
49521f97 | 286 | static u8 __devinit ata66_svwks_dell(ide_hwif_t *hwif) |
1da177e4 | 287 | { |
36501650 BZ |
288 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
289 | ||
1da177e4 LT |
290 | if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL && |
291 | dev->vendor == PCI_VENDOR_ID_SERVERWORKS && | |
292 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE || | |
293 | dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE)) | |
294 | return ((1 << (hwif->channel + 14)) & | |
49521f97 BZ |
295 | dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
296 | return ATA_CBL_PATA40; | |
1da177e4 LT |
297 | } |
298 | ||
299 | /* Sun Cobalt Alpine hardware avoids the 80-pin cable | |
300 | * detect issue by attaching the drives directly to the board. | |
301 | * This check follows the Dell precedent (how scary is that?!) | |
302 | * | |
303 | * WARNING: this only works on Alpine hardware! | |
304 | */ | |
49521f97 | 305 | static u8 __devinit ata66_svwks_cobalt(ide_hwif_t *hwif) |
1da177e4 | 306 | { |
36501650 BZ |
307 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
308 | ||
1da177e4 LT |
309 | if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN && |
310 | dev->vendor == PCI_VENDOR_ID_SERVERWORKS && | |
311 | dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) | |
312 | return ((1 << (hwif->channel + 14)) & | |
49521f97 BZ |
313 | dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
314 | return ATA_CBL_PATA40; | |
1da177e4 LT |
315 | } |
316 | ||
49521f97 | 317 | static u8 __devinit ata66_svwks(ide_hwif_t *hwif) |
1da177e4 | 318 | { |
36501650 | 319 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 320 | |
1da177e4 LT |
321 | /* Server Works */ |
322 | if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS) | |
323 | return ata66_svwks_svwks (hwif); | |
324 | ||
325 | /* Dell PowerEdge */ | |
326 | if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
327 | return ata66_svwks_dell (hwif); | |
328 | ||
329 | /* Cobalt Alpine */ | |
330 | if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN) | |
331 | return ata66_svwks_cobalt (hwif); | |
332 | ||
f201f504 AC |
333 | /* Per Specified Design by OEM, and ASIC Architect */ |
334 | if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || | |
335 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) | |
49521f97 | 336 | return ATA_CBL_PATA80; |
f201f504 | 337 | |
49521f97 | 338 | return ATA_CBL_PATA40; |
1da177e4 LT |
339 | } |
340 | ||
1da177e4 LT |
341 | static void __devinit init_hwif_svwks (ide_hwif_t *hwif) |
342 | { | |
36501650 BZ |
343 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
344 | ||
26bcb879 | 345 | hwif->set_pio_mode = &svwks_set_pio_mode; |
88b2b32b | 346 | hwif->set_dma_mode = &svwks_set_dma_mode; |
2d5eaa6d | 347 | hwif->udma_filter = &svwks_udma_filter; |
1da177e4 | 348 | |
1880a8d7 | 349 | if (!hwif->dma_base) |
1da177e4 | 350 | return; |
1da177e4 | 351 | |
36501650 | 352 | if (dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { |
49521f97 BZ |
353 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) |
354 | hwif->cbl = ata66_svwks(hwif); | |
946f8e4a | 355 | } |
1da177e4 LT |
356 | } |
357 | ||
4db90a14 BZ |
358 | #define IDE_HFLAGS_SVWKS \ |
359 | (IDE_HFLAG_LEGACY_IRQS | \ | |
360 | IDE_HFLAG_ABUSE_SET_DMA_MODE | \ | |
361 | IDE_HFLAG_BOOTABLE) | |
362 | ||
85620436 | 363 | static const struct ide_port_info serverworks_chipsets[] __devinitdata = { |
1da177e4 LT |
364 | { /* 0 */ |
365 | .name = "SvrWks OSB4", | |
1da177e4 LT |
366 | .init_chipset = init_chipset_svwks, |
367 | .init_hwif = init_hwif_svwks, | |
4db90a14 | 368 | .host_flags = IDE_HFLAGS_SVWKS, |
4099d143 | 369 | .pio_mask = ATA_PIO4, |
5f8b6c34 BZ |
370 | .mwdma_mask = ATA_MWDMA2, |
371 | .udma_mask = 0x00, /* UDMA is problematic on OSB4 */ | |
1da177e4 LT |
372 | },{ /* 1 */ |
373 | .name = "SvrWks CSB5", | |
1da177e4 LT |
374 | .init_chipset = init_chipset_svwks, |
375 | .init_hwif = init_hwif_svwks, | |
4db90a14 | 376 | .host_flags = IDE_HFLAGS_SVWKS, |
4099d143 | 377 | .pio_mask = ATA_PIO4, |
5f8b6c34 BZ |
378 | .mwdma_mask = ATA_MWDMA2, |
379 | .udma_mask = ATA_UDMA5, | |
1da177e4 LT |
380 | },{ /* 2 */ |
381 | .name = "SvrWks CSB6", | |
1da177e4 LT |
382 | .init_chipset = init_chipset_svwks, |
383 | .init_hwif = init_hwif_svwks, | |
4db90a14 | 384 | .host_flags = IDE_HFLAGS_SVWKS, |
4099d143 | 385 | .pio_mask = ATA_PIO4, |
5f8b6c34 BZ |
386 | .mwdma_mask = ATA_MWDMA2, |
387 | .udma_mask = ATA_UDMA5, | |
1da177e4 LT |
388 | },{ /* 3 */ |
389 | .name = "SvrWks CSB6", | |
1da177e4 LT |
390 | .init_chipset = init_chipset_svwks, |
391 | .init_hwif = init_hwif_svwks, | |
4db90a14 | 392 | .host_flags = IDE_HFLAGS_SVWKS | IDE_HFLAG_SINGLE, |
4099d143 | 393 | .pio_mask = ATA_PIO4, |
5f8b6c34 BZ |
394 | .mwdma_mask = ATA_MWDMA2, |
395 | .udma_mask = ATA_UDMA5, | |
84f57fbc NS |
396 | },{ /* 4 */ |
397 | .name = "SvrWks HT1000", | |
84f57fbc NS |
398 | .init_chipset = init_chipset_svwks, |
399 | .init_hwif = init_hwif_svwks, | |
4db90a14 | 400 | .host_flags = IDE_HFLAGS_SVWKS | IDE_HFLAG_SINGLE, |
4099d143 | 401 | .pio_mask = ATA_PIO4, |
5f8b6c34 BZ |
402 | .mwdma_mask = ATA_MWDMA2, |
403 | .udma_mask = ATA_UDMA5, | |
1da177e4 LT |
404 | } |
405 | }; | |
406 | ||
407 | /** | |
408 | * svwks_init_one - called when a OSB/CSB is found | |
409 | * @dev: the svwks device | |
410 | * @id: the matching pci id | |
411 | * | |
412 | * Called when the PCI registration layer (or the IDE initialization) | |
413 | * finds a device matching our IDE device tables. | |
414 | */ | |
415 | ||
416 | static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
417 | { | |
039788e1 | 418 | struct ide_port_info d; |
7ed58297 BZ |
419 | u8 idx = id->driver_data; |
420 | ||
421 | d = serverworks_chipsets[idx]; | |
422 | ||
8ac2b42a BZ |
423 | if (idx == 1) |
424 | d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX; | |
425 | else if (idx == 2 || idx == 3) { | |
7ed58297 BZ |
426 | if ((PCI_FUNC(dev->devfn) & 1) == 0) { |
427 | if (pci_resource_start(dev, 0) != 0x01f1) | |
428 | d.host_flags &= ~IDE_HFLAG_BOOTABLE; | |
429 | d.host_flags |= IDE_HFLAG_SINGLE; | |
430 | } else | |
431 | d.host_flags &= ~IDE_HFLAG_SINGLE; | |
432 | } | |
1da177e4 | 433 | |
7ed58297 | 434 | return ide_setup_pci_device(dev, &d); |
1da177e4 LT |
435 | } |
436 | ||
9cbcc5e3 BZ |
437 | static const struct pci_device_id svwks_pci_tbl[] = { |
438 | { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0 }, | |
439 | { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 1 }, | |
440 | { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2 }, | |
441 | { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 3 }, | |
442 | { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 }, | |
1da177e4 LT |
443 | { 0, }, |
444 | }; | |
445 | MODULE_DEVICE_TABLE(pci, svwks_pci_tbl); | |
446 | ||
447 | static struct pci_driver driver = { | |
448 | .name = "Serverworks_IDE", | |
449 | .id_table = svwks_pci_tbl, | |
450 | .probe = svwks_init_one, | |
451 | }; | |
452 | ||
82ab1eec | 453 | static int __init svwks_ide_init(void) |
1da177e4 LT |
454 | { |
455 | return ide_pci_register_driver(&driver); | |
456 | } | |
457 | ||
458 | module_init(svwks_ide_init); | |
459 | ||
460 | MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick"); | |
461 | MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE"); | |
462 | MODULE_LICENSE("GPL"); |