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drm/radeon/kms: add workaround for rn50/rv100 servers
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / radeon_combios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
27#include "drmP.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32#ifdef CONFIG_PPC_PMAC
33/* not sure which of these are needed */
34#include <asm/machdep.h>
35#include <asm/pmac_feature.h>
36#include <asm/prom.h>
37#include <asm/pci-bridge.h>
38#endif /* CONFIG_PPC_PMAC */
39
40/* from radeon_encoder.c */
41extern uint32_t
42radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac);
44extern void radeon_link_encoder_connector(struct drm_device *dev);
45
46/* from radeon_connector.c */
47extern void
48radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
51 int connector_type,
b75fad06 52 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
771fe6b9
JG		 55
56/* from radeon_legacy_encoder.c */
57extern void
58radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
59 uint32_t supported_device);
60
61/* old legacy ATI BIOS routines */
62
63/* COMBIOS table offsets */
64enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
112};
113
114enum radeon_combios_ddc {
115 DDC_NONE_DETECTED,
116 DDC_MONID,
117 DDC_DVI,
118 DDC_VGA,
119 DDC_CRT2,
120 DDC_LCD,
121 DDC_GPIO,
122};
123
124enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
133};
134
135const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
144};
145
146static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
148{
149 struct radeon_device *rdev = dev->dev_private;
150 int rev;
151 uint16_t offset = 0, check_offset;
152
153 switch (table) {
154 /* absolute offset tables */
155 case COMBIOS_ASIC_INIT_1_TABLE:
156 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
157 if (check_offset)
158 offset = check_offset;
159 break;
160 case COMBIOS_BIOS_SUPPORT_TABLE:
161 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
162 if (check_offset)
163 offset = check_offset;
164 break;
165 case COMBIOS_DAC_PROGRAMMING_TABLE:
166 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
167 if (check_offset)
168 offset = check_offset;
169 break;
170 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
171 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
172 if (check_offset)
173 offset = check_offset;
174 break;
175 case COMBIOS_CRTC_INFO_TABLE:
176 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
177 if (check_offset)
178 offset = check_offset;
179 break;
180 case COMBIOS_PLL_INFO_TABLE:
181 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
182 if (check_offset)
183 offset = check_offset;
184 break;
185 case COMBIOS_TV_INFO_TABLE:
186 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
187 if (check_offset)
188 offset = check_offset;
189 break;
190 case COMBIOS_DFP_INFO_TABLE:
191 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
192 if (check_offset)
193 offset = check_offset;
194 break;
195 case COMBIOS_HW_CONFIG_INFO_TABLE:
196 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
197 if (check_offset)
198 offset = check_offset;
199 break;
200 case COMBIOS_MULTIMEDIA_INFO_TABLE:
201 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
202 if (check_offset)
203 offset = check_offset;
204 break;
205 case COMBIOS_TV_STD_PATCH_TABLE:
206 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
207 if (check_offset)
208 offset = check_offset;
209 break;
210 case COMBIOS_LCD_INFO_TABLE:
211 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
212 if (check_offset)
213 offset = check_offset;
214 break;
215 case COMBIOS_MOBILE_INFO_TABLE:
216 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
217 if (check_offset)
218 offset = check_offset;
219 break;
220 case COMBIOS_PLL_INIT_TABLE:
221 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
222 if (check_offset)
223 offset = check_offset;
224 break;
225 case COMBIOS_MEM_CONFIG_TABLE:
226 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
227 if (check_offset)
228 offset = check_offset;
229 break;
230 case COMBIOS_SAVE_MASK_TABLE:
231 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
232 if (check_offset)
233 offset = check_offset;
234 break;
235 case COMBIOS_HARDCODED_EDID_TABLE:
236 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
237 if (check_offset)
238 offset = check_offset;
239 break;
240 case COMBIOS_ASIC_INIT_2_TABLE:
241 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
242 if (check_offset)
243 offset = check_offset;
244 break;
245 case COMBIOS_CONNECTOR_INFO_TABLE:
246 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
247 if (check_offset)
248 offset = check_offset;
249 break;
250 case COMBIOS_DYN_CLK_1_TABLE:
251 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
252 if (check_offset)
253 offset = check_offset;
254 break;
255 case COMBIOS_RESERVED_MEM_TABLE:
256 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
257 if (check_offset)
258 offset = check_offset;
259 break;
260 case COMBIOS_EXT_TMDS_INFO_TABLE:
261 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
262 if (check_offset)
263 offset = check_offset;
264 break;
265 case COMBIOS_MEM_CLK_INFO_TABLE:
266 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
267 if (check_offset)
268 offset = check_offset;
269 break;
270 case COMBIOS_EXT_DAC_INFO_TABLE:
271 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
272 if (check_offset)
273 offset = check_offset;
274 break;
275 case COMBIOS_MISC_INFO_TABLE:
276 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
277 if (check_offset)
278 offset = check_offset;
279 break;
280 case COMBIOS_CRT_INFO_TABLE:
281 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
282 if (check_offset)
283 offset = check_offset;
284 break;
285 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
286 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
287 if (check_offset)
288 offset = check_offset;
289 break;
290 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
291 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
292 if (check_offset)
293 offset = check_offset;
294 break;
295 case COMBIOS_FAN_SPEED_INFO_TABLE:
296 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
297 if (check_offset)
298 offset = check_offset;
299 break;
300 case COMBIOS_OVERDRIVE_INFO_TABLE:
301 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
302 if (check_offset)
303 offset = check_offset;
304 break;
305 case COMBIOS_OEM_INFO_TABLE:
306 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
307 if (check_offset)
308 offset = check_offset;
309 break;
310 case COMBIOS_DYN_CLK_2_TABLE:
311 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
312 if (check_offset)
313 offset = check_offset;
314 break;
315 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
316 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
317 if (check_offset)
318 offset = check_offset;
319 break;
320 case COMBIOS_I2C_INFO_TABLE:
321 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
322 if (check_offset)
323 offset = check_offset;
324 break;
325 /* relative offset tables */
326 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
327 check_offset =
328 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
329 if (check_offset) {
330 rev = RBIOS8(check_offset);
331 if (rev > 0) {
332 check_offset = RBIOS16(check_offset + 0x3);
333 if (check_offset)
334 offset = check_offset;
335 }
336 }
337 break;
338 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
339 check_offset =
340 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
341 if (check_offset) {
342 rev = RBIOS8(check_offset);
343 if (rev > 0) {
344 check_offset = RBIOS16(check_offset + 0x5);
345 if (check_offset)
346 offset = check_offset;
347 }
348 }
349 break;
350 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
351 check_offset =
352 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
353 if (check_offset) {
354 rev = RBIOS8(check_offset);
355 if (rev > 0) {
356 check_offset = RBIOS16(check_offset + 0x7);
357 if (check_offset)
358 offset = check_offset;
359 }
360 }
361 break;
362 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
363 check_offset =
364 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
365 if (check_offset) {
366 rev = RBIOS8(check_offset);
367 if (rev == 2) {
368 check_offset = RBIOS16(check_offset + 0x9);
369 if (check_offset)
370 offset = check_offset;
371 }
372 }
373 break;
374 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
375 check_offset =
376 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
377 if (check_offset) {
378 while (RBIOS8(check_offset++));
379 check_offset += 2;
380 if (check_offset)
381 offset = check_offset;
382 }
383 break;
384 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
385 check_offset =
386 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
387 if (check_offset) {
388 check_offset = RBIOS16(check_offset + 0x11);
389 if (check_offset)
390 offset = check_offset;
391 }
392 break;
393 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
394 check_offset =
395 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
396 if (check_offset) {
397 check_offset = RBIOS16(check_offset + 0x13);
398 if (check_offset)
399 offset = check_offset;
400 }
401 break;
402 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
403 check_offset =
404 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
405 if (check_offset) {
406 check_offset = RBIOS16(check_offset + 0x15);
407 if (check_offset)
408 offset = check_offset;
409 }
410 break;
411 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
412 check_offset =
413 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
414 if (check_offset) {
415 check_offset = RBIOS16(check_offset + 0x17);
416 if (check_offset)
417 offset = check_offset;
418 }
419 break;
420 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
421 check_offset =
422 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
423 if (check_offset) {
424 check_offset = RBIOS16(check_offset + 0x2);
425 if (check_offset)
426 offset = check_offset;
427 }
428 break;
429 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
430 check_offset =
431 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
432 if (check_offset) {
433 check_offset = RBIOS16(check_offset + 0x4);
434 if (check_offset)
435 offset = check_offset;
436 }
437 break;
438 default:
439 break;
440 }
441
442 return offset;
443
444}
445
6a93cb25
AD		 446static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
447 int ddc_line)
771fe6b9
JG		 448{
449 struct radeon_i2c_bus_rec i2c;
450
6a93cb25
AD		 451 if (ddc_line == RADEON_GPIOPAD_MASK) {
452 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
453 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
454 i2c.a_clk_reg = RADEON_GPIOPAD_A;
455 i2c.a_data_reg = RADEON_GPIOPAD_A;
456 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
457 i2c.en_data_reg = RADEON_GPIOPAD_EN;
458 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
459 i2c.y_data_reg = RADEON_GPIOPAD_Y;
460 } else if (ddc_line == RADEON_MDGPIO_MASK) {
461 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
462 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
463 i2c.a_clk_reg = RADEON_MDGPIO_A;
464 i2c.a_data_reg = RADEON_MDGPIO_A;
465 i2c.en_clk_reg = RADEON_MDGPIO_EN;
466 i2c.en_data_reg = RADEON_MDGPIO_EN;
467 i2c.y_clk_reg = RADEON_MDGPIO_Y;
468 i2c.y_data_reg = RADEON_MDGPIO_Y;
771fe6b9 469 } else {
6a93cb25
AD		 470 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
471 i2c.mask_data_mask = RADEON_GPIO_EN_0;
472 i2c.a_clk_mask = RADEON_GPIO_A_1;
473 i2c.a_data_mask = RADEON_GPIO_A_0;
474 i2c.en_clk_mask = RADEON_GPIO_EN_1;
475 i2c.en_data_mask = RADEON_GPIO_EN_0;
476 i2c.y_clk_mask = RADEON_GPIO_Y_1;
477 i2c.y_data_mask = RADEON_GPIO_Y_0;
478
771fe6b9
JG		 479 i2c.mask_clk_reg = ddc_line;
480 i2c.mask_data_reg = ddc_line;
481 i2c.a_clk_reg = ddc_line;
482 i2c.a_data_reg = ddc_line;
9b9fe724
AD		 483 i2c.en_clk_reg = ddc_line;
484 i2c.en_data_reg = ddc_line;
485 i2c.y_clk_reg = ddc_line;
486 i2c.y_data_reg = ddc_line;
771fe6b9
JG		 487 }
488
40bacf16
AD		 489 switch (rdev->family) {
490 case CHIP_R100:
491 case CHIP_RV100:
492 case CHIP_RS100:
493 case CHIP_RV200:
494 case CHIP_RS200:
495 case CHIP_RS300:
496 switch (ddc_line) {
497 case RADEON_GPIO_DVI_DDC:
498 /* in theory this should be hw capable,
499 * but it doesn't seem to work
500 */
501 i2c.hw_capable = false;
502 break;
503 default:
504 i2c.hw_capable = false;
505 break;
506 }
507 break;
508 case CHIP_R200:
509 switch (ddc_line) {
510 case RADEON_GPIO_DVI_DDC:
511 case RADEON_GPIO_MONID:
512 i2c.hw_capable = true;
513 break;
514 default:
515 i2c.hw_capable = false;
516 break;
517 }
518 break;
519 case CHIP_RV250:
520 case CHIP_RV280:
521 switch (ddc_line) {
522 case RADEON_GPIO_VGA_DDC:
523 case RADEON_GPIO_DVI_DDC:
524 case RADEON_GPIO_CRT2_DDC:
525 i2c.hw_capable = true;
526 break;
527 default:
528 i2c.hw_capable = false;
529 break;
530 }
531 break;
532 case CHIP_R300:
533 case CHIP_R350:
534 switch (ddc_line) {
535 case RADEON_GPIO_VGA_DDC:
536 case RADEON_GPIO_DVI_DDC:
537 i2c.hw_capable = true;
538 break;
539 default:
540 i2c.hw_capable = false;
541 break;
542 }
543 break;
544 case CHIP_RV350:
545 case CHIP_RV380:
546 case CHIP_RS400:
547 case CHIP_RS480:
6a93cb25
AD		 548 switch (ddc_line) {
549 case RADEON_GPIO_VGA_DDC:
550 case RADEON_GPIO_DVI_DDC:
551 i2c.hw_capable = true;
552 break;
553 case RADEON_GPIO_MONID:
554 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
555 * reliably on some pre-r4xx hardware; not sure why.
556 */
557 i2c.hw_capable = false;
558 break;
559 default:
560 i2c.hw_capable = false;
561 break;
562 }
40bacf16
AD		 563 break;
564 default:
565 i2c.hw_capable = false;
566 break;
6a93cb25
AD		 567 }
568 i2c.mm_i2c = false;
569 i2c.i2c_id = 0;
570
771fe6b9
JG		 571 if (ddc_line)
572 i2c.valid = true;
573 else
574 i2c.valid = false;
575
576 return i2c;
577}
578
579bool radeon_combios_get_clock_info(struct drm_device *dev)
580{
581 struct radeon_device *rdev = dev->dev_private;
582 uint16_t pll_info;
583 struct radeon_pll *p1pll = &rdev->clock.p1pll;
584 struct radeon_pll *p2pll = &rdev->clock.p2pll;
585 struct radeon_pll *spll = &rdev->clock.spll;
586 struct radeon_pll *mpll = &rdev->clock.mpll;
587 int8_t rev;
588 uint16_t sclk, mclk;
589
590 if (rdev->bios == NULL)
4b30b870 591 return false;
771fe6b9
JG		 592
593 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
594 if (pll_info) {
595 rev = RBIOS8(pll_info);
596
597 /* pixel clocks */
598 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
599 p1pll->reference_div = RBIOS16(pll_info + 0x10);
600 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
601 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
602
603 if (rev > 9) {
604 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
605 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
606 } else {
607 p1pll->pll_in_min = 40;
608 p1pll->pll_in_max = 500;
609 }
610 *p2pll = *p1pll;
611
612 /* system clock */
613 spll->reference_freq = RBIOS16(pll_info + 0x1a);
614 spll->reference_div = RBIOS16(pll_info + 0x1c);
615 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
616 spll->pll_out_max = RBIOS32(pll_info + 0x22);
617
618 if (rev > 10) {
619 spll->pll_in_min = RBIOS32(pll_info + 0x48);
620 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
621 } else {
622 /* ??? */
623 spll->pll_in_min = 40;
624 spll->pll_in_max = 500;
625 }
626
627 /* memory clock */
628 mpll->reference_freq = RBIOS16(pll_info + 0x26);
629 mpll->reference_div = RBIOS16(pll_info + 0x28);
630 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
631 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
632
633 if (rev > 10) {
634 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
635 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
636 } else {
637 /* ??? */
638 mpll->pll_in_min = 40;
639 mpll->pll_in_max = 500;
640 }
641
642 /* default sclk/mclk */
643 sclk = RBIOS16(pll_info + 0xa);
644 mclk = RBIOS16(pll_info + 0x8);
645 if (sclk == 0)
646 sclk = 200 * 100;
647 if (mclk == 0)
648 mclk = 200 * 100;
649
650 rdev->clock.default_sclk = sclk;
651 rdev->clock.default_mclk = mclk;
652
653 return true;
654 }
655 return false;
656}
657
06b6476d
AD		 658bool radeon_combios_sideport_present(struct radeon_device *rdev)
659{
660 struct drm_device *dev = rdev->ddev;
661 u16 igp_info;
662
663 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
664
665 if (igp_info) {
666 if (RBIOS16(igp_info + 0x4))
667 return true;
668 }
669 return false;
670}
671
246263cc
AD		 672static const uint32_t default_primarydac_adj[CHIP_LAST] = {
673 0x00000808, /* r100 */
674 0x00000808, /* rv100 */
675 0x00000808, /* rs100 */
676 0x00000808, /* rv200 */
677 0x00000808, /* rs200 */
678 0x00000808, /* r200 */
679 0x00000808, /* rv250 */
680 0x00000000, /* rs300 */
681 0x00000808, /* rv280 */
682 0x00000808, /* r300 */
683 0x00000808, /* r350 */
684 0x00000808, /* rv350 */
685 0x00000808, /* rv380 */
686 0x00000808, /* r420 */
687 0x00000808, /* r423 */
688 0x00000808, /* rv410 */
689 0x00000000, /* rs400 */
690 0x00000000, /* rs480 */
691};
692
693static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
694 struct radeon_encoder_primary_dac *p_dac)
695{
696 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
697 return;
698}
699
771fe6b9
JG		 700struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
701 radeon_encoder
702 *encoder)
703{
704 struct drm_device *dev = encoder->base.dev;
705 struct radeon_device *rdev = dev->dev_private;
706 uint16_t dac_info;
707 uint8_t rev, bg, dac;
708 struct radeon_encoder_primary_dac *p_dac = NULL;
246263cc 709 int found = 0;
771fe6b9 710
246263cc
AD		 711 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
712 GFP_KERNEL);
713
714 if (!p_dac)
771fe6b9
JG		 715 return NULL;
716
246263cc
AD		 717 if (rdev->bios == NULL)
718 goto out;
719
771fe6b9
JG		 720 /* check CRT table */
721 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
722 if (dac_info) {
771fe6b9
JG		 723 rev = RBIOS8(dac_info) & 0x3;
724 if (rev < 2) {
725 bg = RBIOS8(dac_info + 0x2) & 0xf;
726 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
727 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
728 } else {
729 bg = RBIOS8(dac_info + 0x2) & 0xf;
730 dac = RBIOS8(dac_info + 0x3) & 0xf;
731 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
732 }
246263cc 733 found = 1;
771fe6b9
JG		 734 }
735
246263cc
AD		 736out:
737 if (!found) /* fallback to defaults */
738 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
739
771fe6b9
JG		 740 return p_dac;
741}
742
d79766fa
AD		 743enum radeon_tv_std
744radeon_combios_get_tv_info(struct radeon_device *rdev)
771fe6b9 745{
d79766fa 746 struct drm_device *dev = rdev->ddev;
771fe6b9
JG		 747 uint16_t tv_info;
748 enum radeon_tv_std tv_std = TV_STD_NTSC;
749
11f3b59e
MD		 750 if (rdev->bios == NULL)
751 return tv_std;
752
771fe6b9
JG		 753 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
754 if (tv_info) {
755 if (RBIOS8(tv_info + 6) == 'T') {
756 switch (RBIOS8(tv_info + 7) & 0xf) {
757 case 1:
758 tv_std = TV_STD_NTSC;
759 DRM_INFO("Default TV standard: NTSC\n");
760 break;
761 case 2:
762 tv_std = TV_STD_PAL;
763 DRM_INFO("Default TV standard: PAL\n");
764 break;
765 case 3:
766 tv_std = TV_STD_PAL_M;
767 DRM_INFO("Default TV standard: PAL-M\n");
768 break;
769 case 4:
770 tv_std = TV_STD_PAL_60;
771 DRM_INFO("Default TV standard: PAL-60\n");
772 break;
773 case 5:
774 tv_std = TV_STD_NTSC_J;
775 DRM_INFO("Default TV standard: NTSC-J\n");
776 break;
777 case 6:
778 tv_std = TV_STD_SCART_PAL;
779 DRM_INFO("Default TV standard: SCART-PAL\n");
780 break;
781 default:
782 tv_std = TV_STD_NTSC;
783 DRM_INFO
784 ("Unknown TV standard; defaulting to NTSC\n");
785 break;
786 }
787
788 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
789 case 0:
790 DRM_INFO("29.498928713 MHz TV ref clk\n");
791 break;
792 case 1:
793 DRM_INFO("28.636360000 MHz TV ref clk\n");
794 break;
795 case 2:
796 DRM_INFO("14.318180000 MHz TV ref clk\n");
797 break;
798 case 3:
799 DRM_INFO("27.000000000 MHz TV ref clk\n");
800 break;
801 default:
802 break;
803 }
804 }
805 }
806 return tv_std;
807}
808
809static const uint32_t default_tvdac_adj[CHIP_LAST] = {
810 0x00000000, /* r100 */
811 0x00280000, /* rv100 */
812 0x00000000, /* rs100 */
813 0x00880000, /* rv200 */
814 0x00000000, /* rs200 */
815 0x00000000, /* r200 */
816 0x00770000, /* rv250 */
817 0x00290000, /* rs300 */
818 0x00560000, /* rv280 */
819 0x00780000, /* r300 */
820 0x00770000, /* r350 */
821 0x00780000, /* rv350 */
822 0x00780000, /* rv380 */
823 0x01080000, /* r420 */
824 0x01080000, /* r423 */
825 0x01080000, /* rv410 */
826 0x00780000, /* rs400 */
827 0x00780000, /* rs480 */
828};
829
6a719e05
DA		 830static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
831 struct radeon_encoder_tv_dac *tv_dac)
771fe6b9 832{
771fe6b9
JG		 833 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
834 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
835 tv_dac->ps2_tvdac_adj = 0x00880000;
836 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
837 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 838 return;
771fe6b9
JG		 839}
840
841struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
842 radeon_encoder
843 *encoder)
844{
845 struct drm_device *dev = encoder->base.dev;
846 struct radeon_device *rdev = dev->dev_private;
847 uint16_t dac_info;
848 uint8_t rev, bg, dac;
849 struct radeon_encoder_tv_dac *tv_dac = NULL;
6a719e05
DA		 850 int found = 0;
851
852 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
853 if (!tv_dac)
854 return NULL;
771fe6b9
JG		 855
856 if (rdev->bios == NULL)
6a719e05 857 goto out;
771fe6b9
JG		 858
859 /* first check TV table */
860 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
861 if (dac_info) {
771fe6b9
JG		 862 rev = RBIOS8(dac_info + 0x3);
863 if (rev > 4) {
864 bg = RBIOS8(dac_info + 0xc) & 0xf;
865 dac = RBIOS8(dac_info + 0xd) & 0xf;
866 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
867
868 bg = RBIOS8(dac_info + 0xe) & 0xf;
869 dac = RBIOS8(dac_info + 0xf) & 0xf;
870 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
871
872 bg = RBIOS8(dac_info + 0x10) & 0xf;
873 dac = RBIOS8(dac_info + 0x11) & 0xf;
874 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
6a719e05 875 found = 1;
771fe6b9
JG		 876 } else if (rev > 1) {
877 bg = RBIOS8(dac_info + 0xc) & 0xf;
878 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
879 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
880
881 bg = RBIOS8(dac_info + 0xd) & 0xf;
882 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
883 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
884
885 bg = RBIOS8(dac_info + 0xe) & 0xf;
886 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
887 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
6a719e05 888 found = 1;
771fe6b9 889 }
d79766fa 890 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
6a719e05
DA		 891 }
892 if (!found) {
771fe6b9
JG		 893 /* then check CRT table */
894 dac_info =
895 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
896 if (dac_info) {
771fe6b9
JG		 897 rev = RBIOS8(dac_info) & 0x3;
898 if (rev < 2) {
899 bg = RBIOS8(dac_info + 0x3) & 0xf;
900 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
901 tv_dac->ps2_tvdac_adj =
902 (bg << 16) | (dac << 20);
903 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
904 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 905 found = 1;
771fe6b9
JG		 906 } else {
907 bg = RBIOS8(dac_info + 0x4) & 0xf;
908 dac = RBIOS8(dac_info + 0x5) & 0xf;
909 tv_dac->ps2_tvdac_adj =
910 (bg << 16) | (dac << 20);
911 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
912 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 913 found = 1;
771fe6b9 914 }
6fe7ac3f
AD		 915 } else {
916 DRM_INFO("No TV DAC info found in BIOS\n");
771fe6b9
JG		 917 }
918 }
919
6a719e05
DA		 920out:
921 if (!found) /* fallback to defaults */
922 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
923
771fe6b9
JG		 924 return tv_dac;
925}
926
927static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
928 radeon_device
929 *rdev)
930{
931 struct radeon_encoder_lvds *lvds = NULL;
932 uint32_t fp_vert_stretch, fp_horz_stretch;
933 uint32_t ppll_div_sel, ppll_val;
8b5c7444 934 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
771fe6b9
JG		 935
936 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
937
938 if (!lvds)
939 return NULL;
940
941 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
942 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
943
8b5c7444
MD		 944 /* These should be fail-safe defaults, fingers crossed */
945 lvds->panel_pwr_delay = 200;
946 lvds->panel_vcc_delay = 2000;
947
948 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
949 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
950 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
951
771fe6b9 952 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
de2103e4 953 lvds->native_mode.vdisplay =
771fe6b9
JG		 954 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
955 RADEON_VERT_PANEL_SHIFT) + 1;
956 else
de2103e4 957 lvds->native_mode.vdisplay =
771fe6b9
JG		 958 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
959
960 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
de2103e4 961 lvds->native_mode.hdisplay =
771fe6b9
JG		 962 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
963 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
964 else
de2103e4 965 lvds->native_mode.hdisplay =
771fe6b9
JG		 966 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
967
de2103e4
AD		 968 if ((lvds->native_mode.hdisplay < 640) ||
969 (lvds->native_mode.vdisplay < 480)) {
970 lvds->native_mode.hdisplay = 640;
971 lvds->native_mode.vdisplay = 480;
771fe6b9
JG		 972 }
973
974 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
975 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
976 if ((ppll_val & 0x000707ff) == 0x1bb)
977 lvds->use_bios_dividers = false;
978 else {
979 lvds->panel_ref_divider =
980 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
981 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
982 lvds->panel_fb_divider = ppll_val & 0x7ff;
983
984 if ((lvds->panel_ref_divider != 0) &&
985 (lvds->panel_fb_divider > 3))
986 lvds->use_bios_dividers = true;
987 }
988 lvds->panel_vcc_delay = 200;
989
990 DRM_INFO("Panel info derived from registers\n");
de2103e4
AD		 991 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
992 lvds->native_mode.vdisplay);
771fe6b9
JG		 993
994 return lvds;
995}
996
997struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
998 *encoder)
999{
1000 struct drm_device *dev = encoder->base.dev;
1001 struct radeon_device *rdev = dev->dev_private;
1002 uint16_t lcd_info;
1003 uint32_t panel_setup;
1004 char stmp[30];
1005 int tmp, i;
1006 struct radeon_encoder_lvds *lvds = NULL;
1007
8dfaa8a7
MD		 1008 if (rdev->bios == NULL) {
1009 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1010 goto out;
1011 }
771fe6b9
JG		 1012
1013 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1014
1015 if (lcd_info) {
1016 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1017
1018 if (!lvds)
1019 return NULL;
1020
1021 for (i = 0; i < 24; i++)
1022 stmp[i] = RBIOS8(lcd_info + i + 1);
1023 stmp[24] = 0;
1024
1025 DRM_INFO("Panel ID String: %s\n", stmp);
1026
de2103e4
AD		 1027 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1028 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
771fe6b9 1029
de2103e4
AD		 1030 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1031 lvds->native_mode.vdisplay);
771fe6b9
JG		 1032
1033 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
94cf6434 1034 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
771fe6b9
JG		 1035
1036 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1037 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1038 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1039
1040 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1041 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1042 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1043 if ((lvds->panel_ref_divider != 0) &&
1044 (lvds->panel_fb_divider > 3))
1045 lvds->use_bios_dividers = true;
1046
1047 panel_setup = RBIOS32(lcd_info + 0x39);
1048 lvds->lvds_gen_cntl = 0xff00;
1049 if (panel_setup & 0x1)
1050 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1051
1052 if ((panel_setup >> 4) & 0x1)
1053 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1054
1055 switch ((panel_setup >> 8) & 0x7) {
1056 case 0:
1057 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1058 break;
1059 case 1:
1060 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1061 break;
1062 case 2:
1063 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1064 break;
1065 default:
1066 break;
1067 }
1068
1069 if ((panel_setup >> 16) & 0x1)
1070 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1071
1072 if ((panel_setup >> 17) & 0x1)
1073 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1074
1075 if ((panel_setup >> 18) & 0x1)
1076 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1077
1078 if ((panel_setup >> 23) & 0x1)
1079 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1080
1081 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1082
1083 for (i = 0; i < 32; i++) {
1084 tmp = RBIOS16(lcd_info + 64 + i * 2);
1085 if (tmp == 0)
1086 break;
1087
de2103e4 1088 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
771fe6b9 1089 (RBIOS16(tmp + 2) ==
de2103e4
AD		 1090 lvds->native_mode.vdisplay)) {
1091 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8;
1092 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8;
1093 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) +
1094 RBIOS16(tmp + 21)) * 8;
1095
1096 lvds->native_mode.vtotal = RBIOS16(tmp + 24);
1097 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff;
1098 lvds->native_mode.vsync_end =
1099 ((RBIOS16(tmp + 28) & 0xf800) >> 11) +
1100 (RBIOS16(tmp + 28) & 0x7ff);
1101
1102 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
771fe6b9 1103 lvds->native_mode.flags = 0;
de2103e4
AD		 1104 /* set crtc values */
1105 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1106
771fe6b9
JG		 1107 }
1108 }
6fe7ac3f 1109 } else {
771fe6b9 1110 DRM_INFO("No panel info found in BIOS\n");
8dfaa8a7 1111 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
6fe7ac3f 1112 }
8dfaa8a7
MD		 1113out:
1114 if (lvds)
1115 encoder->native_mode = lvds->native_mode;
771fe6b9
JG		 1116 return lvds;
1117}
1118
1119static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1120 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1121 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1122 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1123 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1124 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1125 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1126 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1127 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1128 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1129 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1130 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1131 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1132 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1133 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1134 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1135 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
fcec570b
AD		 1136 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1137 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
771fe6b9
JG		 1138};
1139
445282db
DA		 1140bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1141 struct radeon_encoder_int_tmds *tmds)
771fe6b9 1142{
445282db
DA		 1143 struct drm_device *dev = encoder->base.dev;
1144 struct radeon_device *rdev = dev->dev_private;
771fe6b9 1145 int i;
771fe6b9
JG		 1146
1147 for (i = 0; i < 4; i++) {
1148 tmds->tmds_pll[i].value =
445282db 1149 default_tmds_pll[rdev->family][i].value;
771fe6b9
JG		 1150 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1151 }
1152
445282db 1153 return true;
771fe6b9
JG		 1154}
1155
445282db
DA		 1156bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1157 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1158{
1159 struct drm_device *dev = encoder->base.dev;
1160 struct radeon_device *rdev = dev->dev_private;
1161 uint16_t tmds_info;
1162 int i, n;
1163 uint8_t ver;
771fe6b9
JG		 1164
1165 if (rdev->bios == NULL)
445282db 1166 return false;
771fe6b9
JG		 1167
1168 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1169
1170 if (tmds_info) {
771fe6b9
JG		 1171 ver = RBIOS8(tmds_info);
1172 DRM_INFO("DFP table revision: %d\n", ver);
1173 if (ver == 3) {
1174 n = RBIOS8(tmds_info + 5) + 1;
1175 if (n > 4)
1176 n = 4;
1177 for (i = 0; i < n; i++) {
1178 tmds->tmds_pll[i].value =
1179 RBIOS32(tmds_info + i * 10 + 0x08);
1180 tmds->tmds_pll[i].freq =
1181 RBIOS16(tmds_info + i * 10 + 0x10);
1182 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1183 tmds->tmds_pll[i].freq,
1184 tmds->tmds_pll[i].value);
1185 }
1186 } else if (ver == 4) {
1187 int stride = 0;
1188 n = RBIOS8(tmds_info + 5) + 1;
1189 if (n > 4)
1190 n = 4;
1191 for (i = 0; i < n; i++) {
1192 tmds->tmds_pll[i].value =
1193 RBIOS32(tmds_info + stride + 0x08);
1194 tmds->tmds_pll[i].freq =
1195 RBIOS16(tmds_info + stride + 0x10);
1196 if (i == 0)
1197 stride += 10;
1198 else
1199 stride += 6;
1200 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1201 tmds->tmds_pll[i].freq,
1202 tmds->tmds_pll[i].value);
1203 }
1204 }
fcec570b 1205 } else {
771fe6b9 1206 DRM_INFO("No TMDS info found in BIOS\n");
fcec570b
AD		 1207 return false;
1208 }
445282db
DA		 1209 return true;
1210}
1211
fcec570b
AD		 1212bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1213 struct radeon_encoder_ext_tmds *tmds)
445282db 1214{
fcec570b
AD		 1215 struct drm_device *dev = encoder->base.dev;
1216 struct radeon_device *rdev = dev->dev_private;
1217 struct radeon_i2c_bus_rec i2c_bus;
445282db 1218
fcec570b 1219 /* default for macs */
6a93cb25 1220 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
fcec570b 1221 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
445282db 1222
fcec570b
AD		 1223 /* XXX some macs have duallink chips */
1224 switch (rdev->mode_info.connector_table) {
1225 case CT_POWERBOOK_EXTERNAL:
1226 case CT_MINI_EXTERNAL:
1227 default:
1228 tmds->dvo_chip = DVO_SIL164;
1229 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1230 break;
1231 }
445282db 1232
fcec570b 1233 return true;
771fe6b9
JG		 1234}
1235
fcec570b
AD		 1236bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1237 struct radeon_encoder_ext_tmds *tmds)
771fe6b9
JG		 1238{
1239 struct drm_device *dev = encoder->base.dev;
1240 struct radeon_device *rdev = dev->dev_private;
fcec570b
AD		 1241 uint16_t offset;
1242 uint8_t ver, id, blocks, clk, data;
1243 int i;
1244 enum radeon_combios_ddc gpio;
1245 struct radeon_i2c_bus_rec i2c_bus;
771fe6b9
JG		 1246
1247 if (rdev->bios == NULL)
fcec570b 1248 return false;
771fe6b9 1249
fcec570b
AD		 1250 tmds->i2c_bus = NULL;
1251 if (rdev->flags & RADEON_IS_IGP) {
1252 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
1253 if (offset) {
1254 ver = RBIOS8(offset);
1255 DRM_INFO("GPIO Table revision: %d\n", ver);
1256 blocks = RBIOS8(offset + 2);
1257 for (i = 0; i < blocks; i++) {
1258 id = RBIOS8(offset + 3 + (i * 5) + 0);
1259 if (id == 136) {
1260 clk = RBIOS8(offset + 3 + (i * 5) + 3);
1261 data = RBIOS8(offset + 3 + (i * 5) + 4);
1262 i2c_bus.valid = true;
1263 i2c_bus.mask_clk_mask = (1 << clk);
1264 i2c_bus.mask_data_mask = (1 << data);
1265 i2c_bus.a_clk_mask = (1 << clk);
1266 i2c_bus.a_data_mask = (1 << data);
1267 i2c_bus.en_clk_mask = (1 << clk);
1268 i2c_bus.en_data_mask = (1 << data);
1269 i2c_bus.y_clk_mask = (1 << clk);
1270 i2c_bus.y_data_mask = (1 << data);
1271 i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
1272 i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
1273 i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
1274 i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
1275 i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
1276 i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
1277 i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
1278 i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
1279 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1280 tmds->dvo_chip = DVO_SIL164;
1281 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1282 break;
1283 }
1284 }
1285 }
1286 } else {
1287 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1288 if (offset) {
1289 ver = RBIOS8(offset);
1290 DRM_INFO("External TMDS Table revision: %d\n", ver);
1291 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1292 tmds->slave_addr >>= 1; /* 7 bit addressing */
1293 gpio = RBIOS8(offset + 4 + 3);
1294 switch (gpio) {
1295 case DDC_MONID:
6a93cb25 1296 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
fcec570b
AD		 1297 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1298 break;
1299 case DDC_DVI:
6a93cb25 1300 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
fcec570b
AD		 1301 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1302 break;
1303 case DDC_VGA:
6a93cb25 1304 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
fcec570b
AD		 1305 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1306 break;
1307 case DDC_CRT2:
1308 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1309 if (rdev->family >= CHIP_R300)
6a93cb25 1310 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
fcec570b 1311 else
6a93cb25 1312 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
fcec570b
AD		 1313 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1314 break;
1315 case DDC_LCD: /* MM i2c */
40bacf16
AD		 1316 i2c_bus.valid = true;
1317 i2c_bus.hw_capable = true;
1318 i2c_bus.mm_i2c = true;
1319 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
fcec570b
AD		 1320 break;
1321 default:
1322 DRM_ERROR("Unsupported gpio %d\n", gpio);
1323 break;
1324 }
1325 }
771fe6b9 1326 }
fcec570b
AD		 1327
1328 if (!tmds->i2c_bus) {
1329 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1330 return false;
1331 }
1332
1333 return true;
771fe6b9
JG		 1334}
1335
1336bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1337{
1338 struct radeon_device *rdev = dev->dev_private;
1339 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 1340 struct radeon_hpd hpd;
771fe6b9
JG		 1341
1342 rdev->mode_info.connector_table = radeon_connector_table;
1343 if (rdev->mode_info.connector_table == CT_NONE) {
1344#ifdef CONFIG_PPC_PMAC
1345 if (machine_is_compatible("PowerBook3,3")) {
1346 /* powerbook with VGA */
1347 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1348 } else if (machine_is_compatible("PowerBook3,4") ||
1349 machine_is_compatible("PowerBook3,5")) {
1350 /* powerbook with internal tmds */
1351 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1352 } else if (machine_is_compatible("PowerBook5,1") ||
1353 machine_is_compatible("PowerBook5,2") ||
1354 machine_is_compatible("PowerBook5,3") ||
1355 machine_is_compatible("PowerBook5,4") ||
1356 machine_is_compatible("PowerBook5,5")) {
1357 /* powerbook with external single link tmds (sil164) */
1358 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1359 } else if (machine_is_compatible("PowerBook5,6")) {
1360 /* powerbook with external dual or single link tmds */
1361 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1362 } else if (machine_is_compatible("PowerBook5,7") ||
1363 machine_is_compatible("PowerBook5,8") ||
1364 machine_is_compatible("PowerBook5,9")) {
1365 /* PowerBook6,2 ? */
1366 /* powerbook with external dual link tmds (sil1178?) */
1367 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1368 } else if (machine_is_compatible("PowerBook4,1") ||
1369 machine_is_compatible("PowerBook4,2") ||
1370 machine_is_compatible("PowerBook4,3") ||
1371 machine_is_compatible("PowerBook6,3") ||
1372 machine_is_compatible("PowerBook6,5") ||
1373 machine_is_compatible("PowerBook6,7")) {
1374 /* ibook */
1375 rdev->mode_info.connector_table = CT_IBOOK;
1376 } else if (machine_is_compatible("PowerMac4,4")) {
1377 /* emac */
1378 rdev->mode_info.connector_table = CT_EMAC;
1379 } else if (machine_is_compatible("PowerMac10,1")) {
1380 /* mini with internal tmds */
1381 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1382 } else if (machine_is_compatible("PowerMac10,2")) {
1383 /* mini with external tmds */
1384 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1385 } else if (machine_is_compatible("PowerMac12,1")) {
1386 /* PowerMac8,1 ? */
1387 /* imac g5 isight */
1388 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1389 } else
1390#endif /* CONFIG_PPC_PMAC */
1391 rdev->mode_info.connector_table = CT_GENERIC;
1392 }
1393
1394 switch (rdev->mode_info.connector_table) {
1395 case CT_GENERIC:
1396 DRM_INFO("Connector Table: %d (generic)\n",
1397 rdev->mode_info.connector_table);
1398 /* these are the most common settings */
1399 if (rdev->flags & RADEON_SINGLE_CRTC) {
1400 /* VGA - primary dac */
6a93cb25 1401 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1402 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1403 radeon_add_legacy_encoder(dev,
1404 radeon_get_encoder_id(dev,
1405 ATOM_DEVICE_CRT1_SUPPORT,
1406 1),
1407 ATOM_DEVICE_CRT1_SUPPORT);
1408 radeon_add_legacy_connector(dev, 0,
1409 ATOM_DEVICE_CRT1_SUPPORT,
1410 DRM_MODE_CONNECTOR_VGA,
b75fad06 1411 &ddc_i2c,
eed45b30
AD		 1412 CONNECTOR_OBJECT_ID_VGA,
1413 &hpd);
771fe6b9
JG		 1414 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1415 /* LVDS */
6a93cb25 1416 ddc_i2c = combios_setup_i2c_bus(rdev, 0);
eed45b30 1417 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1418 radeon_add_legacy_encoder(dev,
1419 radeon_get_encoder_id(dev,
1420 ATOM_DEVICE_LCD1_SUPPORT,
1421 0),
1422 ATOM_DEVICE_LCD1_SUPPORT);
1423 radeon_add_legacy_connector(dev, 0,
1424 ATOM_DEVICE_LCD1_SUPPORT,
1425 DRM_MODE_CONNECTOR_LVDS,
b75fad06 1426 &ddc_i2c,
eed45b30
AD		 1427 CONNECTOR_OBJECT_ID_LVDS,
1428 &hpd);
771fe6b9
JG		 1429
1430 /* VGA - primary dac */
6a93cb25 1431 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1432 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1433 radeon_add_legacy_encoder(dev,
1434 radeon_get_encoder_id(dev,
1435 ATOM_DEVICE_CRT1_SUPPORT,
1436 1),
1437 ATOM_DEVICE_CRT1_SUPPORT);
1438 radeon_add_legacy_connector(dev, 1,
1439 ATOM_DEVICE_CRT1_SUPPORT,
1440 DRM_MODE_CONNECTOR_VGA,
b75fad06 1441 &ddc_i2c,
eed45b30
AD		 1442 CONNECTOR_OBJECT_ID_VGA,
1443 &hpd);
771fe6b9
JG		 1444 } else {
1445 /* DVI-I - tv dac, int tmds */
6a93cb25 1446 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1447 hpd.hpd = RADEON_HPD_1;
771fe6b9
JG		 1448 radeon_add_legacy_encoder(dev,
1449 radeon_get_encoder_id(dev,
1450 ATOM_DEVICE_DFP1_SUPPORT,
1451 0),
1452 ATOM_DEVICE_DFP1_SUPPORT);
1453 radeon_add_legacy_encoder(dev,
1454 radeon_get_encoder_id(dev,
1455 ATOM_DEVICE_CRT2_SUPPORT,
1456 2),
1457 ATOM_DEVICE_CRT2_SUPPORT);
1458 radeon_add_legacy_connector(dev, 0,
1459 ATOM_DEVICE_DFP1_SUPPORT |
1460 ATOM_DEVICE_CRT2_SUPPORT,
1461 DRM_MODE_CONNECTOR_DVII,
b75fad06 1462 &ddc_i2c,
eed45b30
AD		 1463 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1464 &hpd);
771fe6b9
JG		 1465
1466 /* VGA - primary dac */
6a93cb25 1467 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1468 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1469 radeon_add_legacy_encoder(dev,
1470 radeon_get_encoder_id(dev,
1471 ATOM_DEVICE_CRT1_SUPPORT,
1472 1),
1473 ATOM_DEVICE_CRT1_SUPPORT);
1474 radeon_add_legacy_connector(dev, 1,
1475 ATOM_DEVICE_CRT1_SUPPORT,
1476 DRM_MODE_CONNECTOR_VGA,
b75fad06 1477 &ddc_i2c,
eed45b30
AD		 1478 CONNECTOR_OBJECT_ID_VGA,
1479 &hpd);
771fe6b9
JG		 1480 }
1481
1482 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1483 /* TV - tv dac */
eed45b30
AD		 1484 ddc_i2c.valid = false;
1485 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1486 radeon_add_legacy_encoder(dev,
1487 radeon_get_encoder_id(dev,
1488 ATOM_DEVICE_TV1_SUPPORT,
1489 2),
1490 ATOM_DEVICE_TV1_SUPPORT);
1491 radeon_add_legacy_connector(dev, 2,
1492 ATOM_DEVICE_TV1_SUPPORT,
1493 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1494 &ddc_i2c,
eed45b30
AD		 1495 CONNECTOR_OBJECT_ID_SVIDEO,
1496 &hpd);
771fe6b9
JG		 1497 }
1498 break;
1499 case CT_IBOOK:
1500 DRM_INFO("Connector Table: %d (ibook)\n",
1501 rdev->mode_info.connector_table);
1502 /* LVDS */
6a93cb25 1503 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1504 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1505 radeon_add_legacy_encoder(dev,
1506 radeon_get_encoder_id(dev,
1507 ATOM_DEVICE_LCD1_SUPPORT,
1508 0),
1509 ATOM_DEVICE_LCD1_SUPPORT);
1510 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1511 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1512 CONNECTOR_OBJECT_ID_LVDS,
1513 &hpd);
771fe6b9 1514 /* VGA - TV DAC */
6a93cb25 1515 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1516 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1517 radeon_add_legacy_encoder(dev,
1518 radeon_get_encoder_id(dev,
1519 ATOM_DEVICE_CRT2_SUPPORT,
1520 2),
1521 ATOM_DEVICE_CRT2_SUPPORT);
1522 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1523 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1524 CONNECTOR_OBJECT_ID_VGA,
1525 &hpd);
771fe6b9 1526 /* TV - TV DAC */
eed45b30
AD		 1527 ddc_i2c.valid = false;
1528 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1529 radeon_add_legacy_encoder(dev,
1530 radeon_get_encoder_id(dev,
1531 ATOM_DEVICE_TV1_SUPPORT,
1532 2),
1533 ATOM_DEVICE_TV1_SUPPORT);
1534 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1535 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1536 &ddc_i2c,
eed45b30
AD		 1537 CONNECTOR_OBJECT_ID_SVIDEO,
1538 &hpd);
771fe6b9
JG		 1539 break;
1540 case CT_POWERBOOK_EXTERNAL:
1541 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1542 rdev->mode_info.connector_table);
1543 /* LVDS */
6a93cb25 1544 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1545 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1546 radeon_add_legacy_encoder(dev,
1547 radeon_get_encoder_id(dev,
1548 ATOM_DEVICE_LCD1_SUPPORT,
1549 0),
1550 ATOM_DEVICE_LCD1_SUPPORT);
1551 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1552 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1553 CONNECTOR_OBJECT_ID_LVDS,
1554 &hpd);
771fe6b9 1555 /* DVI-I - primary dac, ext tmds */
6a93cb25 1556 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1557 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9
JG		 1558 radeon_add_legacy_encoder(dev,
1559 radeon_get_encoder_id(dev,
1560 ATOM_DEVICE_DFP2_SUPPORT,
1561 0),
1562 ATOM_DEVICE_DFP2_SUPPORT);
1563 radeon_add_legacy_encoder(dev,
1564 radeon_get_encoder_id(dev,
1565 ATOM_DEVICE_CRT1_SUPPORT,
1566 1),
1567 ATOM_DEVICE_CRT1_SUPPORT);
b75fad06 1568 /* XXX some are SL */
771fe6b9
JG		 1569 radeon_add_legacy_connector(dev, 1,
1570 ATOM_DEVICE_DFP2_SUPPORT |
1571 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1572 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1573 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1574 &hpd);
771fe6b9 1575 /* TV - TV DAC */
eed45b30
AD		 1576 ddc_i2c.valid = false;
1577 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1578 radeon_add_legacy_encoder(dev,
1579 radeon_get_encoder_id(dev,
1580 ATOM_DEVICE_TV1_SUPPORT,
1581 2),
1582 ATOM_DEVICE_TV1_SUPPORT);
1583 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1584 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1585 &ddc_i2c,
eed45b30
AD		 1586 CONNECTOR_OBJECT_ID_SVIDEO,
1587 &hpd);
771fe6b9
JG		 1588 break;
1589 case CT_POWERBOOK_INTERNAL:
1590 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1591 rdev->mode_info.connector_table);
1592 /* LVDS */
6a93cb25 1593 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1594 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1595 radeon_add_legacy_encoder(dev,
1596 radeon_get_encoder_id(dev,
1597 ATOM_DEVICE_LCD1_SUPPORT,
1598 0),
1599 ATOM_DEVICE_LCD1_SUPPORT);
1600 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1601 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1602 CONNECTOR_OBJECT_ID_LVDS,
1603 &hpd);
771fe6b9 1604 /* DVI-I - primary dac, int tmds */
6a93cb25 1605 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1606 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9
JG		 1607 radeon_add_legacy_encoder(dev,
1608 radeon_get_encoder_id(dev,
1609 ATOM_DEVICE_DFP1_SUPPORT,
1610 0),
1611 ATOM_DEVICE_DFP1_SUPPORT);
1612 radeon_add_legacy_encoder(dev,
1613 radeon_get_encoder_id(dev,
1614 ATOM_DEVICE_CRT1_SUPPORT,
1615 1),
1616 ATOM_DEVICE_CRT1_SUPPORT);
1617 radeon_add_legacy_connector(dev, 1,
1618 ATOM_DEVICE_DFP1_SUPPORT |
1619 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1620 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1621 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1622 &hpd);
771fe6b9 1623 /* TV - TV DAC */
eed45b30
AD		 1624 ddc_i2c.valid = false;
1625 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1626 radeon_add_legacy_encoder(dev,
1627 radeon_get_encoder_id(dev,
1628 ATOM_DEVICE_TV1_SUPPORT,
1629 2),
1630 ATOM_DEVICE_TV1_SUPPORT);
1631 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1632 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1633 &ddc_i2c,
eed45b30
AD		 1634 CONNECTOR_OBJECT_ID_SVIDEO,
1635 &hpd);
771fe6b9
JG		 1636 break;
1637 case CT_POWERBOOK_VGA:
1638 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1639 rdev->mode_info.connector_table);
1640 /* LVDS */
6a93cb25 1641 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1642 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1643 radeon_add_legacy_encoder(dev,
1644 radeon_get_encoder_id(dev,
1645 ATOM_DEVICE_LCD1_SUPPORT,
1646 0),
1647 ATOM_DEVICE_LCD1_SUPPORT);
1648 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1649 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1650 CONNECTOR_OBJECT_ID_LVDS,
1651 &hpd);
771fe6b9 1652 /* VGA - primary dac */
6a93cb25 1653 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1654 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1655 radeon_add_legacy_encoder(dev,
1656 radeon_get_encoder_id(dev,
1657 ATOM_DEVICE_CRT1_SUPPORT,
1658 1),
1659 ATOM_DEVICE_CRT1_SUPPORT);
1660 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1661 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1662 CONNECTOR_OBJECT_ID_VGA,
1663 &hpd);
771fe6b9 1664 /* TV - TV DAC */
eed45b30
AD		 1665 ddc_i2c.valid = false;
1666 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1667 radeon_add_legacy_encoder(dev,
1668 radeon_get_encoder_id(dev,
1669 ATOM_DEVICE_TV1_SUPPORT,
1670 2),
1671 ATOM_DEVICE_TV1_SUPPORT);
1672 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1673 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1674 &ddc_i2c,
eed45b30
AD		 1675 CONNECTOR_OBJECT_ID_SVIDEO,
1676 &hpd);
771fe6b9
JG		 1677 break;
1678 case CT_MINI_EXTERNAL:
1679 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1680 rdev->mode_info.connector_table);
1681 /* DVI-I - tv dac, ext tmds */
6a93cb25 1682 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
eed45b30 1683 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9
JG		 1684 radeon_add_legacy_encoder(dev,
1685 radeon_get_encoder_id(dev,
1686 ATOM_DEVICE_DFP2_SUPPORT,
1687 0),
1688 ATOM_DEVICE_DFP2_SUPPORT);
1689 radeon_add_legacy_encoder(dev,
1690 radeon_get_encoder_id(dev,
1691 ATOM_DEVICE_CRT2_SUPPORT,
1692 2),
1693 ATOM_DEVICE_CRT2_SUPPORT);
b75fad06 1694 /* XXX are any DL? */
771fe6b9
JG		 1695 radeon_add_legacy_connector(dev, 0,
1696 ATOM_DEVICE_DFP2_SUPPORT |
1697 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1698 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1699 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1700 &hpd);
771fe6b9 1701 /* TV - TV DAC */
eed45b30
AD		 1702 ddc_i2c.valid = false;
1703 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1704 radeon_add_legacy_encoder(dev,
1705 radeon_get_encoder_id(dev,
1706 ATOM_DEVICE_TV1_SUPPORT,
1707 2),
1708 ATOM_DEVICE_TV1_SUPPORT);
1709 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1710 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1711 &ddc_i2c,
eed45b30
AD		 1712 CONNECTOR_OBJECT_ID_SVIDEO,
1713 &hpd);
771fe6b9
JG		 1714 break;
1715 case CT_MINI_INTERNAL:
1716 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1717 rdev->mode_info.connector_table);
1718 /* DVI-I - tv dac, int tmds */
6a93cb25 1719 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
eed45b30 1720 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9
JG		 1721 radeon_add_legacy_encoder(dev,
1722 radeon_get_encoder_id(dev,
1723 ATOM_DEVICE_DFP1_SUPPORT,
1724 0),
1725 ATOM_DEVICE_DFP1_SUPPORT);
1726 radeon_add_legacy_encoder(dev,
1727 radeon_get_encoder_id(dev,
1728 ATOM_DEVICE_CRT2_SUPPORT,
1729 2),
1730 ATOM_DEVICE_CRT2_SUPPORT);
1731 radeon_add_legacy_connector(dev, 0,
1732 ATOM_DEVICE_DFP1_SUPPORT |
1733 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1734 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1735 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1736 &hpd);
771fe6b9 1737 /* TV - TV DAC */
eed45b30
AD		 1738 ddc_i2c.valid = false;
1739 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1740 radeon_add_legacy_encoder(dev,
1741 radeon_get_encoder_id(dev,
1742 ATOM_DEVICE_TV1_SUPPORT,
1743 2),
1744 ATOM_DEVICE_TV1_SUPPORT);
1745 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1746 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1747 &ddc_i2c,
eed45b30
AD		 1748 CONNECTOR_OBJECT_ID_SVIDEO,
1749 &hpd);
771fe6b9
JG		 1750 break;
1751 case CT_IMAC_G5_ISIGHT:
1752 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1753 rdev->mode_info.connector_table);
1754 /* DVI-D - int tmds */
6a93cb25 1755 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
eed45b30 1756 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9
JG		 1757 radeon_add_legacy_encoder(dev,
1758 radeon_get_encoder_id(dev,
1759 ATOM_DEVICE_DFP1_SUPPORT,
1760 0),
1761 ATOM_DEVICE_DFP1_SUPPORT);
1762 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
b75fad06 1763 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
eed45b30
AD		 1764 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1765 &hpd);
771fe6b9 1766 /* VGA - tv dac */
6a93cb25 1767 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1768 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1769 radeon_add_legacy_encoder(dev,
1770 radeon_get_encoder_id(dev,
1771 ATOM_DEVICE_CRT2_SUPPORT,
1772 2),
1773 ATOM_DEVICE_CRT2_SUPPORT);
1774 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1775 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1776 CONNECTOR_OBJECT_ID_VGA,
1777 &hpd);
771fe6b9 1778 /* TV - TV DAC */
eed45b30
AD		 1779 ddc_i2c.valid = false;
1780 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1781 radeon_add_legacy_encoder(dev,
1782 radeon_get_encoder_id(dev,
1783 ATOM_DEVICE_TV1_SUPPORT,
1784 2),
1785 ATOM_DEVICE_TV1_SUPPORT);
1786 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1787 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1788 &ddc_i2c,
eed45b30
AD		 1789 CONNECTOR_OBJECT_ID_SVIDEO,
1790 &hpd);
771fe6b9
JG		 1791 break;
1792 case CT_EMAC:
1793 DRM_INFO("Connector Table: %d (emac)\n",
1794 rdev->mode_info.connector_table);
1795 /* VGA - primary dac */
6a93cb25 1796 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1797 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1798 radeon_add_legacy_encoder(dev,
1799 radeon_get_encoder_id(dev,
1800 ATOM_DEVICE_CRT1_SUPPORT,
1801 1),
1802 ATOM_DEVICE_CRT1_SUPPORT);
1803 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1804 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1805 CONNECTOR_OBJECT_ID_VGA,
1806 &hpd);
771fe6b9 1807 /* VGA - tv dac */
6a93cb25 1808 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
eed45b30 1809 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1810 radeon_add_legacy_encoder(dev,
1811 radeon_get_encoder_id(dev,
1812 ATOM_DEVICE_CRT2_SUPPORT,
1813 2),
1814 ATOM_DEVICE_CRT2_SUPPORT);
1815 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1816 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1817 CONNECTOR_OBJECT_ID_VGA,
1818 &hpd);
771fe6b9 1819 /* TV - TV DAC */
eed45b30
AD		 1820 ddc_i2c.valid = false;
1821 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1822 radeon_add_legacy_encoder(dev,
1823 radeon_get_encoder_id(dev,
1824 ATOM_DEVICE_TV1_SUPPORT,
1825 2),
1826 ATOM_DEVICE_TV1_SUPPORT);
1827 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1828 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1829 &ddc_i2c,
eed45b30
AD		 1830 CONNECTOR_OBJECT_ID_SVIDEO,
1831 &hpd);
771fe6b9
JG		 1832 break;
1833 default:
1834 DRM_INFO("Connector table: %d (invalid)\n",
1835 rdev->mode_info.connector_table);
1836 return false;
1837 }
1838
1839 radeon_link_encoder_connector(dev);
1840
1841 return true;
1842}
1843
1844static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1845 int bios_index,
1846 enum radeon_combios_connector
1847 *legacy_connector,
eed45b30
AD		 1848 struct radeon_i2c_bus_rec *ddc_i2c,
1849 struct radeon_hpd *hpd)
771fe6b9
JG		 1850{
1851 struct radeon_device *rdev = dev->dev_private;
1852
1853 /* XPRESS DDC quirks */
1854 if ((rdev->family == CHIP_RS400 ||
1855 rdev->family == CHIP_RS480) &&
1856 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
6a93cb25 1857 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
771fe6b9
JG		 1858 else if ((rdev->family == CHIP_RS400 ||
1859 rdev->family == CHIP_RS480) &&
1860 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
6a93cb25 1861 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK);
771fe6b9
JG		 1862 ddc_i2c->mask_clk_mask = (0x20 << 8);
1863 ddc_i2c->mask_data_mask = 0x80;
1864 ddc_i2c->a_clk_mask = (0x20 << 8);
1865 ddc_i2c->a_data_mask = 0x80;
9b9fe724
AD		 1866 ddc_i2c->en_clk_mask = (0x20 << 8);
1867 ddc_i2c->en_data_mask = 0x80;
1868 ddc_i2c->y_clk_mask = (0x20 << 8);
1869 ddc_i2c->y_data_mask = 0x80;
771fe6b9
JG		 1870 }
1871
fcec570b
AD		 1872 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1873 if ((rdev->family >= CHIP_R300) &&
1874 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
6a93cb25 1875 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
fcec570b 1876
771fe6b9
JG		 1877 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1878 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1879 if (dev->pdev->device == 0x515e &&
1880 dev->pdev->subsystem_vendor == 0x1014) {
1881 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1882 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1883 return false;
1884 }
1885
1886 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1887 if (dev->pdev->device == 0x5159 &&
1888 dev->pdev->subsystem_vendor == 0x1002 &&
1889 dev->pdev->subsystem_device == 0x013a) {
1890 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1891 *legacy_connector = CONNECTOR_CRT_LEGACY;
1892
1893 }
1894
1895 /* X300 card with extra non-existent DVI port */
1896 if (dev->pdev->device == 0x5B60 &&
1897 dev->pdev->subsystem_vendor == 0x17af &&
1898 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1899 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1900 return false;
1901 }
1902
1903 return true;
1904}
1905
790cfb34
AD		 1906static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
1907{
1908 /* Acer 5102 has non-existent TV port */
1909 if (dev->pdev->device == 0x5975 &&
1910 dev->pdev->subsystem_vendor == 0x1025 &&
1911 dev->pdev->subsystem_device == 0x009f)
1912 return false;
1913
fc7f7119
AD		 1914 /* HP dc5750 has non-existent TV port */
1915 if (dev->pdev->device == 0x5974 &&
1916 dev->pdev->subsystem_vendor == 0x103c &&
1917 dev->pdev->subsystem_device == 0x280a)
1918 return false;
1919
fd874ad0
AD		 1920 /* MSI S270 has non-existent TV port */
1921 if (dev->pdev->device == 0x5955 &&
1922 dev->pdev->subsystem_vendor == 0x1462 &&
1923 dev->pdev->subsystem_device == 0x0131)
1924 return false;
1925
790cfb34
AD		 1926 return true;
1927}
1928
b75fad06
AD		 1929static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
1930{
1931 struct radeon_device *rdev = dev->dev_private;
1932 uint32_t ext_tmds_info;
1933
1934 if (rdev->flags & RADEON_IS_IGP) {
1935 if (is_dvi_d)
1936 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1937 else
1938 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1939 }
1940 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1941 if (ext_tmds_info) {
1942 uint8_t rev = RBIOS8(ext_tmds_info);
1943 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
1944 if (rev >= 3) {
1945 if (is_dvi_d)
1946 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1947 else
1948 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1949 } else {
1950 if (flags & 1) {
1951 if (is_dvi_d)
1952 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1953 else
1954 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1955 }
1956 }
1957 }
1958 if (is_dvi_d)
1959 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1960 else
1961 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1962}
1963
771fe6b9
JG		 1964bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1965{
1966 struct radeon_device *rdev = dev->dev_private;
1967 uint32_t conn_info, entry, devices;
b75fad06 1968 uint16_t tmp, connector_object_id;
771fe6b9
JG		 1969 enum radeon_combios_ddc ddc_type;
1970 enum radeon_combios_connector connector;
1971 int i = 0;
1972 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 1973 struct radeon_hpd hpd;
771fe6b9
JG		 1974
1975 if (rdev->bios == NULL)
1976 return false;
1977
1978 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
1979 if (conn_info) {
1980 for (i = 0; i < 4; i++) {
1981 entry = conn_info + 2 + i * 2;
1982
1983 if (!RBIOS16(entry))
1984 break;
1985
1986 tmp = RBIOS16(entry);
1987
1988 connector = (tmp >> 12) & 0xf;
1989
1990 ddc_type = (tmp >> 8) & 0xf;
1991 switch (ddc_type) {
1992 case DDC_MONID:
1993 ddc_i2c =
6a93cb25 1994 combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
771fe6b9
JG		 1995 break;
1996 case DDC_DVI:
1997 ddc_i2c =
6a93cb25 1998 combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
771fe6b9
JG		 1999 break;
2000 case DDC_VGA:
2001 ddc_i2c =
6a93cb25 2002 combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
771fe6b9
JG		 2003 break;
2004 case DDC_CRT2:
2005 ddc_i2c =
6a93cb25 2006 combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
771fe6b9
JG		 2007 break;
2008 default:
2009 break;
2010 }
2011
eed45b30
AD		 2012 switch (connector) {
2013 case CONNECTOR_PROPRIETARY_LEGACY:
2014 case CONNECTOR_DVI_I_LEGACY:
2015 case CONNECTOR_DVI_D_LEGACY:
2016 if ((tmp >> 4) & 0x1)
2017 hpd.hpd = RADEON_HPD_2;
2018 else
2019 hpd.hpd = RADEON_HPD_1;
2020 break;
2021 default:
2022 hpd.hpd = RADEON_HPD_NONE;
2023 break;
2024 }
2025
2d152c6b 2026 if (!radeon_apply_legacy_quirks(dev, i, &connector,
eed45b30 2027 &ddc_i2c, &hpd))
2d152c6b 2028 continue;
771fe6b9
JG		 2029
2030 switch (connector) {
2031 case CONNECTOR_PROPRIETARY_LEGACY:
2032 if ((tmp >> 4) & 0x1)
2033 devices = ATOM_DEVICE_DFP2_SUPPORT;
2034 else
2035 devices = ATOM_DEVICE_DFP1_SUPPORT;
2036 radeon_add_legacy_encoder(dev,
2037 radeon_get_encoder_id
2038 (dev, devices, 0),
2039 devices);
2040 radeon_add_legacy_connector(dev, i, devices,
2041 legacy_connector_convert
2042 [connector],
b75fad06 2043 &ddc_i2c,
eed45b30
AD		 2044 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2045 &hpd);
771fe6b9
JG		 2046 break;
2047 case CONNECTOR_CRT_LEGACY:
2048 if (tmp & 0x1) {
2049 devices = ATOM_DEVICE_CRT2_SUPPORT;
2050 radeon_add_legacy_encoder(dev,
2051 radeon_get_encoder_id
2052 (dev,
2053 ATOM_DEVICE_CRT2_SUPPORT,
2054 2),
2055 ATOM_DEVICE_CRT2_SUPPORT);
2056 } else {
2057 devices = ATOM_DEVICE_CRT1_SUPPORT;
2058 radeon_add_legacy_encoder(dev,
2059 radeon_get_encoder_id
2060 (dev,
2061 ATOM_DEVICE_CRT1_SUPPORT,
2062 1),
2063 ATOM_DEVICE_CRT1_SUPPORT);
2064 }
2065 radeon_add_legacy_connector(dev,
2066 i,
2067 devices,
2068 legacy_connector_convert
2069 [connector],
b75fad06 2070 &ddc_i2c,
eed45b30
AD		 2071 CONNECTOR_OBJECT_ID_VGA,
2072 &hpd);
771fe6b9
JG		 2073 break;
2074 case CONNECTOR_DVI_I_LEGACY:
2075 devices = 0;
2076 if (tmp & 0x1) {
2077 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2078 radeon_add_legacy_encoder(dev,
2079 radeon_get_encoder_id
2080 (dev,
2081 ATOM_DEVICE_CRT2_SUPPORT,
2082 2),
2083 ATOM_DEVICE_CRT2_SUPPORT);
2084 } else {
2085 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2086 radeon_add_legacy_encoder(dev,
2087 radeon_get_encoder_id
2088 (dev,
2089 ATOM_DEVICE_CRT1_SUPPORT,
2090 1),
2091 ATOM_DEVICE_CRT1_SUPPORT);
2092 }
2093 if ((tmp >> 4) & 0x1) {
2094 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2095 radeon_add_legacy_encoder(dev,
2096 radeon_get_encoder_id
2097 (dev,
2098 ATOM_DEVICE_DFP2_SUPPORT,
2099 0),
2100 ATOM_DEVICE_DFP2_SUPPORT);
b75fad06 2101 connector_object_id = combios_check_dl_dvi(dev, 0);
771fe6b9
JG		 2102 } else {
2103 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2104 radeon_add_legacy_encoder(dev,
2105 radeon_get_encoder_id
2106 (dev,
2107 ATOM_DEVICE_DFP1_SUPPORT,
2108 0),
2109 ATOM_DEVICE_DFP1_SUPPORT);
b75fad06 2110 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
771fe6b9
JG		 2111 }
2112 radeon_add_legacy_connector(dev,
2113 i,
2114 devices,
2115 legacy_connector_convert
2116 [connector],
b75fad06 2117 &ddc_i2c,
eed45b30
AD		 2118 connector_object_id,
2119 &hpd);
771fe6b9
JG		 2120 break;
2121 case CONNECTOR_DVI_D_LEGACY:
b75fad06 2122 if ((tmp >> 4) & 0x1) {
771fe6b9 2123 devices = ATOM_DEVICE_DFP2_SUPPORT;
b75fad06
AD		 2124 connector_object_id = combios_check_dl_dvi(dev, 1);
2125 } else {
771fe6b9 2126 devices = ATOM_DEVICE_DFP1_SUPPORT;
b75fad06
AD		 2127 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2128 }
771fe6b9
JG		 2129 radeon_add_legacy_encoder(dev,
2130 radeon_get_encoder_id
2131 (dev, devices, 0),
2132 devices);
2133 radeon_add_legacy_connector(dev, i, devices,
2134 legacy_connector_convert
2135 [connector],
b75fad06 2136 &ddc_i2c,
eed45b30
AD		 2137 connector_object_id,
2138 &hpd);
771fe6b9
JG		 2139 break;
2140 case CONNECTOR_CTV_LEGACY:
2141 case CONNECTOR_STV_LEGACY:
2142 radeon_add_legacy_encoder(dev,
2143 radeon_get_encoder_id
2144 (dev,
2145 ATOM_DEVICE_TV1_SUPPORT,
2146 2),
2147 ATOM_DEVICE_TV1_SUPPORT);
2148 radeon_add_legacy_connector(dev, i,
2149 ATOM_DEVICE_TV1_SUPPORT,
2150 legacy_connector_convert
2151 [connector],
b75fad06 2152 &ddc_i2c,
eed45b30
AD		 2153 CONNECTOR_OBJECT_ID_SVIDEO,
2154 &hpd);
771fe6b9
JG		 2155 break;
2156 default:
2157 DRM_ERROR("Unknown connector type: %d\n",
2158 connector);
2159 continue;
2160 }
2161
2162 }
2163 } else {
2164 uint16_t tmds_info =
2165 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2166 if (tmds_info) {
2167 DRM_DEBUG("Found DFP table, assuming DVI connector\n");
2168
2169 radeon_add_legacy_encoder(dev,
2170 radeon_get_encoder_id(dev,
2171 ATOM_DEVICE_CRT1_SUPPORT,
2172 1),
2173 ATOM_DEVICE_CRT1_SUPPORT);
2174 radeon_add_legacy_encoder(dev,
2175 radeon_get_encoder_id(dev,
2176 ATOM_DEVICE_DFP1_SUPPORT,
2177 0),
2178 ATOM_DEVICE_DFP1_SUPPORT);
2179
6a93cb25 2180 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 2181 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 2182 radeon_add_legacy_connector(dev,
2183 0,
2184 ATOM_DEVICE_CRT1_SUPPORT |
2185 ATOM_DEVICE_DFP1_SUPPORT,
2186 DRM_MODE_CONNECTOR_DVII,
b75fad06 2187 &ddc_i2c,
eed45b30
AD		 2188 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2189 &hpd);
771fe6b9 2190 } else {
d0c403e9
AD		 2191 uint16_t crt_info =
2192 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2193 DRM_DEBUG("Found CRT table, assuming VGA connector\n");
2194 if (crt_info) {
2195 radeon_add_legacy_encoder(dev,
2196 radeon_get_encoder_id(dev,
2197 ATOM_DEVICE_CRT1_SUPPORT,
2198 1),
2199 ATOM_DEVICE_CRT1_SUPPORT);
6a93cb25 2200 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 2201 hpd.hpd = RADEON_HPD_NONE;
d0c403e9
AD		 2202 radeon_add_legacy_connector(dev,
2203 0,
2204 ATOM_DEVICE_CRT1_SUPPORT,
2205 DRM_MODE_CONNECTOR_VGA,
b75fad06 2206 &ddc_i2c,
eed45b30
AD		 2207 CONNECTOR_OBJECT_ID_VGA,
2208 &hpd);
d0c403e9
AD		 2209 } else {
2210 DRM_DEBUG("No connector info found\n");
2211 return false;
2212 }
771fe6b9
JG		 2213 }
2214 }
2215
2216 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2217 uint16_t lcd_info =
2218 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2219 if (lcd_info) {
2220 uint16_t lcd_ddc_info =
2221 combios_get_table_offset(dev,
2222 COMBIOS_LCD_DDC_INFO_TABLE);
2223
2224 radeon_add_legacy_encoder(dev,
2225 radeon_get_encoder_id(dev,
2226 ATOM_DEVICE_LCD1_SUPPORT,
2227 0),
2228 ATOM_DEVICE_LCD1_SUPPORT);
2229
2230 if (lcd_ddc_info) {
2231 ddc_type = RBIOS8(lcd_ddc_info + 2);
2232 switch (ddc_type) {
2233 case DDC_MONID:
2234 ddc_i2c =
2235 combios_setup_i2c_bus
6a93cb25 2236 (rdev, RADEON_GPIO_MONID);
771fe6b9
JG		 2237 break;
2238 case DDC_DVI:
2239 ddc_i2c =
2240 combios_setup_i2c_bus
6a93cb25 2241 (rdev, RADEON_GPIO_DVI_DDC);
771fe6b9
JG		 2242 break;
2243 case DDC_VGA:
2244 ddc_i2c =
2245 combios_setup_i2c_bus
6a93cb25 2246 (rdev, RADEON_GPIO_VGA_DDC);
771fe6b9
JG		 2247 break;
2248 case DDC_CRT2:
2249 ddc_i2c =
2250 combios_setup_i2c_bus
6a93cb25 2251 (rdev, RADEON_GPIO_CRT2_DDC);
771fe6b9
JG		 2252 break;
2253 case DDC_LCD:
2254 ddc_i2c =
2255 combios_setup_i2c_bus
6a93cb25 2256 (rdev, RADEON_GPIOPAD_MASK);
771fe6b9
JG		 2257 ddc_i2c.mask_clk_mask =
2258 RBIOS32(lcd_ddc_info + 3);
2259 ddc_i2c.mask_data_mask =
2260 RBIOS32(lcd_ddc_info + 7);
2261 ddc_i2c.a_clk_mask =
2262 RBIOS32(lcd_ddc_info + 3);
2263 ddc_i2c.a_data_mask =
2264 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2265 ddc_i2c.en_clk_mask =
771fe6b9 2266 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2267 ddc_i2c.en_data_mask =
771fe6b9 2268 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2269 ddc_i2c.y_clk_mask =
771fe6b9 2270 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2271 ddc_i2c.y_data_mask =
771fe6b9
JG		 2272 RBIOS32(lcd_ddc_info + 7);
2273 break;
2274 case DDC_GPIO:
2275 ddc_i2c =
2276 combios_setup_i2c_bus
6a93cb25 2277 (rdev, RADEON_MDGPIO_MASK);
771fe6b9
JG		 2278 ddc_i2c.mask_clk_mask =
2279 RBIOS32(lcd_ddc_info + 3);
2280 ddc_i2c.mask_data_mask =
2281 RBIOS32(lcd_ddc_info + 7);
2282 ddc_i2c.a_clk_mask =
2283 RBIOS32(lcd_ddc_info + 3);
2284 ddc_i2c.a_data_mask =
2285 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2286 ddc_i2c.en_clk_mask =
771fe6b9 2287 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2288 ddc_i2c.en_data_mask =
771fe6b9 2289 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2290 ddc_i2c.y_clk_mask =
771fe6b9 2291 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2292 ddc_i2c.y_data_mask =
771fe6b9
JG		 2293 RBIOS32(lcd_ddc_info + 7);
2294 break;
2295 default:
2296 ddc_i2c.valid = false;
2297 break;
2298 }
2299 DRM_DEBUG("LCD DDC Info Table found!\n");
2300 } else
2301 ddc_i2c.valid = false;
2302
eed45b30 2303 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 2304 radeon_add_legacy_connector(dev,
2305 5,
2306 ATOM_DEVICE_LCD1_SUPPORT,
2307 DRM_MODE_CONNECTOR_LVDS,
b75fad06 2308 &ddc_i2c,
eed45b30
AD		 2309 CONNECTOR_OBJECT_ID_LVDS,
2310 &hpd);
771fe6b9
JG		 2311 }
2312 }
2313
2314 /* check TV table */
2315 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2316 uint32_t tv_info =
2317 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2318 if (tv_info) {
2319 if (RBIOS8(tv_info + 6) == 'T') {
790cfb34 2320 if (radeon_apply_legacy_tv_quirks(dev)) {
eed45b30 2321 hpd.hpd = RADEON_HPD_NONE;
790cfb34
AD		 2322 radeon_add_legacy_encoder(dev,
2323 radeon_get_encoder_id
2324 (dev,
2325 ATOM_DEVICE_TV1_SUPPORT,
2326 2),
2327 ATOM_DEVICE_TV1_SUPPORT);
2328 radeon_add_legacy_connector(dev, 6,
2329 ATOM_DEVICE_TV1_SUPPORT,
2330 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 2331 &ddc_i2c,
eed45b30
AD		 2332 CONNECTOR_OBJECT_ID_SVIDEO,
2333 &hpd);
790cfb34 2334 }
771fe6b9
JG		 2335 }
2336 }
2337 }
2338
2339 radeon_link_encoder_connector(dev);
2340
2341 return true;
2342}
2343
fcec570b
AD		 2344void radeon_external_tmds_setup(struct drm_encoder *encoder)
2345{
2346 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2347 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2348
2349 if (!tmds)
2350 return;
2351
2352 switch (tmds->dvo_chip) {
2353 case DVO_SIL164:
2354 /* sil 164 */
5a6f98f5
AD		 2355 radeon_i2c_put_byte(tmds->i2c_bus,
2356 tmds->slave_addr,
2357 0x08, 0x30);
2358 radeon_i2c_put_byte(tmds->i2c_bus,
fcec570b
AD		 2359 tmds->slave_addr,
2360 0x09, 0x00);
5a6f98f5
AD		 2361 radeon_i2c_put_byte(tmds->i2c_bus,
2362 tmds->slave_addr,
2363 0x0a, 0x90);
2364 radeon_i2c_put_byte(tmds->i2c_bus,
2365 tmds->slave_addr,
2366 0x0c, 0x89);
2367 radeon_i2c_put_byte(tmds->i2c_bus,
fcec570b
AD		 2368 tmds->slave_addr,
2369 0x08, 0x3b);
fcec570b
AD		 2370 break;
2371 case DVO_SIL1178:
2372 /* sil 1178 - untested */
2373 /*
2374 * 0x0f, 0x44
2375 * 0x0f, 0x4c
2376 * 0x0e, 0x01
2377 * 0x0a, 0x80
2378 * 0x09, 0x30
2379 * 0x0c, 0xc9
2380 * 0x0d, 0x70
2381 * 0x08, 0x32
2382 * 0x08, 0x33
2383 */
2384 break;
2385 default:
2386 break;
2387 }
2388
2389}
2390
2391bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2392{
2393 struct drm_device *dev = encoder->dev;
2394 struct radeon_device *rdev = dev->dev_private;
2395 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2396 uint16_t offset;
2397 uint8_t blocks, slave_addr, rev;
2398 uint32_t index, id;
2399 uint32_t reg, val, and_mask, or_mask;
2400 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2401
2402 if (rdev->bios == NULL)
2403 return false;
2404
2405 if (!tmds)
2406 return false;
2407
2408 if (rdev->flags & RADEON_IS_IGP) {
2409 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2410 rev = RBIOS8(offset);
2411 if (offset) {
2412 rev = RBIOS8(offset);
2413 if (rev > 1) {
2414 blocks = RBIOS8(offset + 3);
2415 index = offset + 4;
2416 while (blocks > 0) {
2417 id = RBIOS16(index);
2418 index += 2;
2419 switch (id >> 13) {
2420 case 0:
2421 reg = (id & 0x1fff) * 4;
2422 val = RBIOS32(index);
2423 index += 4;
2424 WREG32(reg, val);
2425 break;
2426 case 2:
2427 reg = (id & 0x1fff) * 4;
2428 and_mask = RBIOS32(index);
2429 index += 4;
2430 or_mask = RBIOS32(index);
2431 index += 4;
2432 val = RREG32(reg);
2433 val = (val & and_mask) | or_mask;
2434 WREG32(reg, val);
2435 break;
2436 case 3:
2437 val = RBIOS16(index);
2438 index += 2;
2439 udelay(val);
2440 break;
2441 case 4:
2442 val = RBIOS16(index);
2443 index += 2;
2444 udelay(val * 1000);
2445 break;
2446 case 6:
2447 slave_addr = id & 0xff;
2448 slave_addr >>= 1; /* 7 bit addressing */
2449 index++;
2450 reg = RBIOS8(index);
2451 index++;
2452 val = RBIOS8(index);
2453 index++;
5a6f98f5
AD		 2454 radeon_i2c_put_byte(tmds->i2c_bus,
2455 slave_addr,
2456 reg, val);
fcec570b
AD		 2457 break;
2458 default:
2459 DRM_ERROR("Unknown id %d\n", id >> 13);
2460 break;
2461 }
2462 blocks--;
2463 }
2464 return true;
2465 }
2466 }
2467 } else {
2468 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2469 if (offset) {
2470 index = offset + 10;
2471 id = RBIOS16(index);
2472 while (id != 0xffff) {
2473 index += 2;
2474 switch (id >> 13) {
2475 case 0:
2476 reg = (id & 0x1fff) * 4;
2477 val = RBIOS32(index);
2478 WREG32(reg, val);
2479 break;
2480 case 2:
2481 reg = (id & 0x1fff) * 4;
2482 and_mask = RBIOS32(index);
2483 index += 4;
2484 or_mask = RBIOS32(index);
2485 index += 4;
2486 val = RREG32(reg);
2487 val = (val & and_mask) | or_mask;
2488 WREG32(reg, val);
2489 break;
2490 case 4:
2491 val = RBIOS16(index);
2492 index += 2;
2493 udelay(val);
2494 break;
2495 case 5:
2496 reg = id & 0x1fff;
2497 and_mask = RBIOS32(index);
2498 index += 4;
2499 or_mask = RBIOS32(index);
2500 index += 4;
2501 val = RREG32_PLL(reg);
2502 val = (val & and_mask) | or_mask;
2503 WREG32_PLL(reg, val);
2504 break;
2505 case 6:
2506 reg = id & 0x1fff;
2507 val = RBIOS8(index);
2508 index += 1;
5a6f98f5
AD		 2509 radeon_i2c_put_byte(tmds->i2c_bus,
2510 tmds->slave_addr,
2511 reg, val);
fcec570b
AD		 2512 break;
2513 default:
2514 DRM_ERROR("Unknown id %d\n", id >> 13);
2515 break;
2516 }
2517 id = RBIOS16(index);
2518 }
2519 return true;
2520 }
2521 }
2522 return false;
2523}
2524
771fe6b9
JG		 2525static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2526{
2527 struct radeon_device *rdev = dev->dev_private;
2528
2529 if (offset) {
2530 while (RBIOS16(offset)) {
2531 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2532 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2533 uint32_t val, and_mask, or_mask;
2534 uint32_t tmp;
2535
2536 offset += 2;
2537 switch (cmd) {
2538 case 0:
2539 val = RBIOS32(offset);
2540 offset += 4;
2541 WREG32(addr, val);
2542 break;
2543 case 1:
2544 val = RBIOS32(offset);
2545 offset += 4;
2546 WREG32(addr, val);
2547 break;
2548 case 2:
2549 and_mask = RBIOS32(offset);
2550 offset += 4;
2551 or_mask = RBIOS32(offset);
2552 offset += 4;
2553 tmp = RREG32(addr);
2554 tmp &= and_mask;
2555 tmp |= or_mask;
2556 WREG32(addr, tmp);
2557 break;
2558 case 3:
2559 and_mask = RBIOS32(offset);
2560 offset += 4;
2561 or_mask = RBIOS32(offset);
2562 offset += 4;
2563 tmp = RREG32(addr);
2564 tmp &= and_mask;
2565 tmp |= or_mask;
2566 WREG32(addr, tmp);
2567 break;
2568 case 4:
2569 val = RBIOS16(offset);
2570 offset += 2;
2571 udelay(val);
2572 break;
2573 case 5:
2574 val = RBIOS16(offset);
2575 offset += 2;
2576 switch (addr) {
2577 case 8:
2578 while (val--) {
2579 if (!
2580 (RREG32_PLL
2581 (RADEON_CLK_PWRMGT_CNTL) &
2582 RADEON_MC_BUSY))
2583 break;
2584 }
2585 break;
2586 case 9:
2587 while (val--) {
2588 if ((RREG32(RADEON_MC_STATUS) &
2589 RADEON_MC_IDLE))
2590 break;
2591 }
2592 break;
2593 default:
2594 break;
2595 }
2596 break;
2597 default:
2598 break;
2599 }
2600 }
2601 }
2602}
2603
2604static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2605{
2606 struct radeon_device *rdev = dev->dev_private;
2607
2608 if (offset) {
2609 while (RBIOS8(offset)) {
2610 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2611 uint8_t addr = (RBIOS8(offset) & 0x3f);
2612 uint32_t val, shift, tmp;
2613 uint32_t and_mask, or_mask;
2614
2615 offset++;
2616 switch (cmd) {
2617 case 0:
2618 val = RBIOS32(offset);
2619 offset += 4;
2620 WREG32_PLL(addr, val);
2621 break;
2622 case 1:
2623 shift = RBIOS8(offset) * 8;
2624 offset++;
2625 and_mask = RBIOS8(offset) << shift;
2626 and_mask |= ~(0xff << shift);
2627 offset++;
2628 or_mask = RBIOS8(offset) << shift;
2629 offset++;
2630 tmp = RREG32_PLL(addr);
2631 tmp &= and_mask;
2632 tmp |= or_mask;
2633 WREG32_PLL(addr, tmp);
2634 break;
2635 case 2:
2636 case 3:
2637 tmp = 1000;
2638 switch (addr) {
2639 case 1:
2640 udelay(150);
2641 break;
2642 case 2:
2643 udelay(1000);
2644 break;
2645 case 3:
2646 while (tmp--) {
2647 if (!
2648 (RREG32_PLL
2649 (RADEON_CLK_PWRMGT_CNTL) &
2650 RADEON_MC_BUSY))
2651 break;
2652 }
2653 break;
2654 case 4:
2655 while (tmp--) {
2656 if (RREG32_PLL
2657 (RADEON_CLK_PWRMGT_CNTL) &
2658 RADEON_DLL_READY)
2659 break;
2660 }
2661 break;
2662 case 5:
2663 tmp =
2664 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2665 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2666#if 0
2667 uint32_t mclk_cntl =
2668 RREG32_PLL
2669 (RADEON_MCLK_CNTL);
2670 mclk_cntl &= 0xffff0000;
2671 /*mclk_cntl |= 0x00001111;*//* ??? */
2672 WREG32_PLL(RADEON_MCLK_CNTL,
2673 mclk_cntl);
2674 udelay(10000);
2675#endif
2676 WREG32_PLL
2677 (RADEON_CLK_PWRMGT_CNTL,
2678 tmp &
2679 ~RADEON_CG_NO1_DEBUG_0);
2680 udelay(10000);
2681 }
2682 break;
2683 default:
2684 break;
2685 }
2686 break;
2687 default:
2688 break;
2689 }
2690 }
2691 }
2692}
2693
2694static void combios_parse_ram_reset_table(struct drm_device *dev,
2695 uint16_t offset)
2696{
2697 struct radeon_device *rdev = dev->dev_private;
2698 uint32_t tmp;
2699
2700 if (offset) {
2701 uint8_t val = RBIOS8(offset);
2702 while (val != 0xff) {
2703 offset++;
2704
2705 if (val == 0x0f) {
2706 uint32_t channel_complete_mask;
2707
2708 if (ASIC_IS_R300(rdev))
2709 channel_complete_mask =
2710 R300_MEM_PWRUP_COMPLETE;
2711 else
2712 channel_complete_mask =
2713 RADEON_MEM_PWRUP_COMPLETE;
2714 tmp = 20000;
2715 while (tmp--) {
2716 if ((RREG32(RADEON_MEM_STR_CNTL) &
2717 channel_complete_mask) ==
2718 channel_complete_mask)
2719 break;
2720 }
2721 } else {
2722 uint32_t or_mask = RBIOS16(offset);
2723 offset += 2;
2724
2725 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2726 tmp &= RADEON_SDRAM_MODE_MASK;
2727 tmp |= or_mask;
2728 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2729
2730 or_mask = val << 24;
2731 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2732 tmp &= RADEON_B3MEM_RESET_MASK;
2733 tmp |= or_mask;
2734 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2735 }
2736 val = RBIOS8(offset);
2737 }
2738 }
2739}
2740
2741static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2742 int mem_addr_mapping)
2743{
2744 struct radeon_device *rdev = dev->dev_private;
2745 uint32_t mem_cntl;
2746 uint32_t mem_size;
2747 uint32_t addr = 0;
2748
2749 mem_cntl = RREG32(RADEON_MEM_CNTL);
2750 if (mem_cntl & RV100_HALF_MODE)
2751 ram /= 2;
2752 mem_size = ram;
2753 mem_cntl &= ~(0xff << 8);
2754 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2755 WREG32(RADEON_MEM_CNTL, mem_cntl);
2756 RREG32(RADEON_MEM_CNTL);
2757
2758 /* sdram reset ? */
2759
2760 /* something like this???? */
2761 while (ram--) {
2762 addr = ram * 1024 * 1024;
2763 /* write to each page */
2764 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2765 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2766 /* read back and verify */
2767 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2768 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2769 return 0;
2770 }
2771
2772 return mem_size;
2773}
2774
2775static void combios_write_ram_size(struct drm_device *dev)
2776{
2777 struct radeon_device *rdev = dev->dev_private;
2778 uint8_t rev;
2779 uint16_t offset;
2780 uint32_t mem_size = 0;
2781 uint32_t mem_cntl = 0;
2782
2783 /* should do something smarter here I guess... */
2784 if (rdev->flags & RADEON_IS_IGP)
2785 return;
2786
2787 /* first check detected mem table */
2788 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2789 if (offset) {
2790 rev = RBIOS8(offset);
2791 if (rev < 3) {
2792 mem_cntl = RBIOS32(offset + 1);
2793 mem_size = RBIOS16(offset + 5);
2794 if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2795 ((dev->pdev->device != 0x515e)
2796 && (dev->pdev->device != 0x5969)))
2797 WREG32(RADEON_MEM_CNTL, mem_cntl);
2798 }
2799 }
2800
2801 if (!mem_size) {
2802 offset =
2803 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2804 if (offset) {
2805 rev = RBIOS8(offset - 1);
2806 if (rev < 1) {
2807 if (((rdev->flags & RADEON_FAMILY_MASK) <
2808 CHIP_R200)
2809 && ((dev->pdev->device != 0x515e)
2810 && (dev->pdev->device != 0x5969))) {
2811 int ram = 0;
2812 int mem_addr_mapping = 0;
2813
2814 while (RBIOS8(offset)) {
2815 ram = RBIOS8(offset);
2816 mem_addr_mapping =
2817 RBIOS8(offset + 1);
2818 if (mem_addr_mapping != 0x25)
2819 ram *= 2;
2820 mem_size =
2821 combios_detect_ram(dev, ram,
2822 mem_addr_mapping);
2823 if (mem_size)
2824 break;
2825 offset += 2;
2826 }
2827 } else
2828 mem_size = RBIOS8(offset);
2829 } else {
2830 mem_size = RBIOS8(offset);
2831 mem_size *= 2; /* convert to MB */
2832 }
2833 }
2834 }
2835
2836 mem_size *= (1024 * 1024); /* convert to bytes */
2837 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2838}
2839
2840void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2841{
2842 uint16_t dyn_clk_info =
2843 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2844
2845 if (dyn_clk_info)
2846 combios_parse_pll_table(dev, dyn_clk_info);
2847}
2848
2849void radeon_combios_asic_init(struct drm_device *dev)
2850{
2851 struct radeon_device *rdev = dev->dev_private;
2852 uint16_t table;
2853
2854 /* port hardcoded mac stuff from radeonfb */
2855 if (rdev->bios == NULL)
2856 return;
2857
2858 /* ASIC INIT 1 */
2859 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2860 if (table)
2861 combios_parse_mmio_table(dev, table);
2862
2863 /* PLL INIT */
2864 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2865 if (table)
2866 combios_parse_pll_table(dev, table);
2867
2868 /* ASIC INIT 2 */
2869 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
2870 if (table)
2871 combios_parse_mmio_table(dev, table);
2872
2873 if (!(rdev->flags & RADEON_IS_IGP)) {
2874 /* ASIC INIT 4 */
2875 table =
2876 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
2877 if (table)
2878 combios_parse_mmio_table(dev, table);
2879
2880 /* RAM RESET */
2881 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
2882 if (table)
2883 combios_parse_ram_reset_table(dev, table);
2884
2885 /* ASIC INIT 3 */
2886 table =
2887 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
2888 if (table)
2889 combios_parse_mmio_table(dev, table);
2890
2891 /* write CONFIG_MEMSIZE */
2892 combios_write_ram_size(dev);
2893 }
2894
2895 /* DYN CLK 1 */
2896 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2897 if (table)
2898 combios_parse_pll_table(dev, table);
2899
2900}
2901
2902void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
2903{
2904 struct radeon_device *rdev = dev->dev_private;
2905 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
2906
2907 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2908 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2909 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
2910
2911 /* let the bios control the backlight */
2912 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
2913
2914 /* tell the bios not to handle mode switching */
2915 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
2916 RADEON_ACC_MODE_CHANGE);
2917
2918 /* tell the bios a driver is loaded */
2919 bios_7_scratch |= RADEON_DRV_LOADED;
2920
2921 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2922 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2923 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
2924}
2925
2926void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
2927{
2928 struct drm_device *dev = encoder->dev;
2929 struct radeon_device *rdev = dev->dev_private;
2930 uint32_t bios_6_scratch;
2931
2932 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2933
2934 if (lock)
2935 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
2936 else
2937 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
2938
2939 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2940}
2941
2942void
2943radeon_combios_connected_scratch_regs(struct drm_connector *connector,
2944 struct drm_encoder *encoder,
2945 bool connected)
2946{
2947 struct drm_device *dev = connector->dev;
2948 struct radeon_device *rdev = dev->dev_private;
2949 struct radeon_connector *radeon_connector =
2950 to_radeon_connector(connector);
2951 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2952 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
2953 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2954
2955 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2956 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2957 if (connected) {
2958 DRM_DEBUG("TV1 connected\n");
2959 /* fix me */
2960 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
2961 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
2962 bios_5_scratch |= RADEON_TV1_ON;
2963 bios_5_scratch |= RADEON_ACC_REQ_TV1;
2964 } else {
2965 DRM_DEBUG("TV1 disconnected\n");
2966 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
2967 bios_5_scratch &= ~RADEON_TV1_ON;
2968 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
2969 }
2970 }
2971 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2972 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2973 if (connected) {
2974 DRM_DEBUG("LCD1 connected\n");
2975 bios_4_scratch |= RADEON_LCD1_ATTACHED;
2976 bios_5_scratch |= RADEON_LCD1_ON;
2977 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
2978 } else {
2979 DRM_DEBUG("LCD1 disconnected\n");
2980 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
2981 bios_5_scratch &= ~RADEON_LCD1_ON;
2982 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
2983 }
2984 }
2985 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2986 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2987 if (connected) {
2988 DRM_DEBUG("CRT1 connected\n");
2989 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
2990 bios_5_scratch |= RADEON_CRT1_ON;
2991 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
2992 } else {
2993 DRM_DEBUG("CRT1 disconnected\n");
2994 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
2995 bios_5_scratch &= ~RADEON_CRT1_ON;
2996 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
2997 }
2998 }
2999 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3000 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3001 if (connected) {
3002 DRM_DEBUG("CRT2 connected\n");
3003 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3004 bios_5_scratch |= RADEON_CRT2_ON;
3005 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3006 } else {
3007 DRM_DEBUG("CRT2 disconnected\n");
3008 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3009 bios_5_scratch &= ~RADEON_CRT2_ON;
3010 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3011 }
3012 }
3013 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3014 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3015 if (connected) {
3016 DRM_DEBUG("DFP1 connected\n");
3017 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3018 bios_5_scratch |= RADEON_DFP1_ON;
3019 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3020 } else {
3021 DRM_DEBUG("DFP1 disconnected\n");
3022 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3023 bios_5_scratch &= ~RADEON_DFP1_ON;
3024 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3025 }
3026 }
3027 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3028 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3029 if (connected) {
3030 DRM_DEBUG("DFP2 connected\n");
3031 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3032 bios_5_scratch |= RADEON_DFP2_ON;
3033 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3034 } else {
3035 DRM_DEBUG("DFP2 disconnected\n");
3036 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3037 bios_5_scratch &= ~RADEON_DFP2_ON;
3038 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3039 }
3040 }
3041 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3042 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3043}
3044
3045void
3046radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3047{
3048 struct drm_device *dev = encoder->dev;
3049 struct radeon_device *rdev = dev->dev_private;
3050 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3051 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3052
3053 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3054 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3055 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3056 }
3057 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3058 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3059 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3060 }
3061 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3062 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3063 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3064 }
3065 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3066 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3067 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3068 }
3069 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3070 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3071 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3072 }
3073 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3074 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3075 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3076 }
3077 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3078}
3079
3080void
3081radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3082{
3083 struct drm_device *dev = encoder->dev;
3084 struct radeon_device *rdev = dev->dev_private;
3085 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3086 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3087
3088 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3089 if (on)
3090 bios_6_scratch |= RADEON_TV_DPMS_ON;
3091 else
3092 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3093 }
3094 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3095 if (on)
3096 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3097 else
3098 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3099 }
3100 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3101 if (on)
3102 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3103 else
3104 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3105 }
3106 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3107 if (on)
3108 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3109 else
3110 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3111 }
3112 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3113}
kernel source for telekom puls (alcatel/mediatek)