Commit | Line | Data |
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2ec1d359 AR |
1 | /* |
2 | * Generic GPIO driver for logic cells found in the Nomadik SoC | |
3 | * | |
4 | * Copyright (C) 2008,2009 STMicroelectronics | |
5 | * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> | |
6 | * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> | |
33d78647 | 7 | * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org> |
2ec1d359 AR |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/device.h> | |
3e3c62ca | 17 | #include <linux/platform_device.h> |
2ec1d359 | 18 | #include <linux/io.h> |
af7dc228 RV |
19 | #include <linux/clk.h> |
20 | #include <linux/err.h> | |
2ec1d359 AR |
21 | #include <linux/gpio.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/irq.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
2ec1d359 | 26 | |
adfed159 WD |
27 | #include <asm/mach/irq.h> |
28 | ||
378be066 | 29 | #include <plat/pincfg.h> |
0f332861 | 30 | #include <plat/gpio-nomadik.h> |
2ec1d359 | 31 | #include <mach/hardware.h> |
75482dc3 | 32 | #include <asm/gpio.h> |
2ec1d359 AR |
33 | |
34 | /* | |
35 | * The GPIO module in the Nomadik family of Systems-on-Chip is an | |
36 | * AMBA device, managing 32 pins and alternate functions. The logic block | |
9c66ee6f | 37 | * is currently used in the Nomadik and ux500. |
2ec1d359 AR |
38 | * |
39 | * Symbols in this file are called "nmk_gpio" for "nomadik gpio" | |
40 | */ | |
41 | ||
01727e61 RV |
42 | #define NMK_GPIO_PER_CHIP 32 |
43 | ||
2ec1d359 AR |
44 | struct nmk_gpio_chip { |
45 | struct gpio_chip chip; | |
46 | void __iomem *addr; | |
af7dc228 | 47 | struct clk *clk; |
33b744b3 | 48 | unsigned int bank; |
2ec1d359 | 49 | unsigned int parent_irq; |
2c8bb0eb | 50 | int secondary_parent_irq; |
33b744b3 | 51 | u32 (*get_secondary_status)(unsigned int bank); |
01727e61 | 52 | void (*set_ioforce)(bool enable); |
c0fcb8db | 53 | spinlock_t lock; |
33d78647 | 54 | bool sleepmode; |
2ec1d359 AR |
55 | /* Keep track of configured edges */ |
56 | u32 edge_rising; | |
57 | u32 edge_falling; | |
b9df468d RV |
58 | u32 real_wake; |
59 | u32 rwimsc; | |
60 | u32 fwimsc; | |
bc6f5cf6 | 61 | u32 pull_up; |
2ec1d359 AR |
62 | }; |
63 | ||
01727e61 RV |
64 | static struct nmk_gpio_chip * |
65 | nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)]; | |
66 | ||
67 | static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); | |
68 | ||
69 | #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) | |
70 | ||
6f9a974c RV |
71 | static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, |
72 | unsigned offset, int gpio_mode) | |
73 | { | |
74 | u32 bit = 1 << offset; | |
75 | u32 afunc, bfunc; | |
76 | ||
77 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; | |
78 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; | |
79 | if (gpio_mode & NMK_GPIO_ALT_A) | |
80 | afunc |= bit; | |
81 | if (gpio_mode & NMK_GPIO_ALT_B) | |
82 | bfunc |= bit; | |
83 | writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); | |
84 | writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); | |
85 | } | |
86 | ||
81a3c298 RV |
87 | static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, |
88 | unsigned offset, enum nmk_gpio_slpm mode) | |
89 | { | |
90 | u32 bit = 1 << offset; | |
91 | u32 slpm; | |
92 | ||
93 | slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); | |
94 | if (mode == NMK_GPIO_SLPM_NOCHANGE) | |
95 | slpm |= bit; | |
96 | else | |
97 | slpm &= ~bit; | |
98 | writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); | |
99 | } | |
100 | ||
5b327edf RV |
101 | static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, |
102 | unsigned offset, enum nmk_gpio_pull pull) | |
103 | { | |
104 | u32 bit = 1 << offset; | |
105 | u32 pdis; | |
106 | ||
107 | pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); | |
bc6f5cf6 | 108 | if (pull == NMK_GPIO_PULL_NONE) { |
5b327edf | 109 | pdis |= bit; |
bc6f5cf6 RA |
110 | nmk_chip->pull_up &= ~bit; |
111 | } else { | |
5b327edf | 112 | pdis &= ~bit; |
bc6f5cf6 RA |
113 | } |
114 | ||
5b327edf RV |
115 | writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); |
116 | ||
bc6f5cf6 RA |
117 | if (pull == NMK_GPIO_PULL_UP) { |
118 | nmk_chip->pull_up |= bit; | |
5b327edf | 119 | writel(bit, nmk_chip->addr + NMK_GPIO_DATS); |
bc6f5cf6 RA |
120 | } else if (pull == NMK_GPIO_PULL_DOWN) { |
121 | nmk_chip->pull_up &= ~bit; | |
5b327edf | 122 | writel(bit, nmk_chip->addr + NMK_GPIO_DATC); |
bc6f5cf6 | 123 | } |
5b327edf RV |
124 | } |
125 | ||
378be066 RV |
126 | static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, |
127 | unsigned offset) | |
128 | { | |
129 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); | |
130 | } | |
131 | ||
6720db7c RV |
132 | static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, |
133 | unsigned offset, int val) | |
134 | { | |
135 | if (val) | |
136 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); | |
137 | else | |
138 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); | |
139 | } | |
140 | ||
141 | static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, | |
142 | unsigned offset, int val) | |
143 | { | |
144 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); | |
145 | __nmk_gpio_set_output(nmk_chip, offset, val); | |
146 | } | |
147 | ||
01727e61 RV |
148 | static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, |
149 | unsigned offset, int gpio_mode, | |
150 | bool glitch) | |
151 | { | |
3c4bee04 LW |
152 | u32 rwimsc = readl(nmk_chip->addr + NMK_GPIO_RWIMSC); |
153 | u32 fwimsc = readl(nmk_chip->addr + NMK_GPIO_FWIMSC); | |
01727e61 RV |
154 | |
155 | if (glitch && nmk_chip->set_ioforce) { | |
156 | u32 bit = BIT(offset); | |
157 | ||
01727e61 RV |
158 | /* Prevent spurious wakeups */ |
159 | writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
160 | writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
161 | ||
162 | nmk_chip->set_ioforce(true); | |
163 | } | |
164 | ||
165 | __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); | |
166 | ||
167 | if (glitch && nmk_chip->set_ioforce) { | |
168 | nmk_chip->set_ioforce(false); | |
169 | ||
170 | writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
171 | writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
172 | } | |
173 | } | |
174 | ||
378be066 | 175 | static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, |
01727e61 | 176 | pin_cfg_t cfg, bool sleep, unsigned int *slpmregs) |
378be066 RV |
177 | { |
178 | static const char *afnames[] = { | |
179 | [NMK_GPIO_ALT_GPIO] = "GPIO", | |
180 | [NMK_GPIO_ALT_A] = "A", | |
181 | [NMK_GPIO_ALT_B] = "B", | |
182 | [NMK_GPIO_ALT_C] = "C" | |
183 | }; | |
184 | static const char *pullnames[] = { | |
185 | [NMK_GPIO_PULL_NONE] = "none", | |
186 | [NMK_GPIO_PULL_UP] = "up", | |
187 | [NMK_GPIO_PULL_DOWN] = "down", | |
188 | [3] /* illegal */ = "??" | |
189 | }; | |
190 | static const char *slpmnames[] = { | |
7e3f7e59 RV |
191 | [NMK_GPIO_SLPM_INPUT] = "input/wakeup", |
192 | [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", | |
378be066 RV |
193 | }; |
194 | ||
195 | int pin = PIN_NUM(cfg); | |
196 | int pull = PIN_PULL(cfg); | |
197 | int af = PIN_ALT(cfg); | |
198 | int slpm = PIN_SLPM(cfg); | |
6720db7c RV |
199 | int output = PIN_DIR(cfg); |
200 | int val = PIN_VAL(cfg); | |
01727e61 | 201 | bool glitch = af == NMK_GPIO_ALT_C; |
378be066 | 202 | |
dacdc96c RV |
203 | dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n", |
204 | pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm], | |
6720db7c RV |
205 | output ? "output " : "input", |
206 | output ? (val ? "high" : "low") : ""); | |
207 | ||
dacdc96c RV |
208 | if (sleep) { |
209 | int slpm_pull = PIN_SLPM_PULL(cfg); | |
210 | int slpm_output = PIN_SLPM_DIR(cfg); | |
211 | int slpm_val = PIN_SLPM_VAL(cfg); | |
212 | ||
3546d15c RV |
213 | af = NMK_GPIO_ALT_GPIO; |
214 | ||
dacdc96c RV |
215 | /* |
216 | * The SLPM_* values are normal values + 1 to allow zero to | |
217 | * mean "same as normal". | |
218 | */ | |
219 | if (slpm_pull) | |
220 | pull = slpm_pull - 1; | |
221 | if (slpm_output) | |
222 | output = slpm_output - 1; | |
223 | if (slpm_val) | |
224 | val = slpm_val - 1; | |
225 | ||
226 | dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", | |
227 | pin, | |
228 | slpm_pull ? pullnames[pull] : "same", | |
229 | slpm_output ? (output ? "output" : "input") : "same", | |
230 | slpm_val ? (val ? "high" : "low") : "same"); | |
231 | } | |
232 | ||
6720db7c RV |
233 | if (output) |
234 | __nmk_gpio_make_output(nmk_chip, offset, val); | |
235 | else { | |
236 | __nmk_gpio_make_input(nmk_chip, offset); | |
237 | __nmk_gpio_set_pull(nmk_chip, offset, pull); | |
238 | } | |
378be066 | 239 | |
01727e61 RV |
240 | /* |
241 | * If we've backed up the SLPM registers (glitch workaround), modify | |
242 | * the backups since they will be restored. | |
243 | */ | |
244 | if (slpmregs) { | |
245 | if (slpm == NMK_GPIO_SLPM_NOCHANGE) | |
246 | slpmregs[nmk_chip->bank] |= BIT(offset); | |
247 | else | |
248 | slpmregs[nmk_chip->bank] &= ~BIT(offset); | |
249 | } else | |
250 | __nmk_gpio_set_slpm(nmk_chip, offset, slpm); | |
251 | ||
252 | __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch); | |
253 | } | |
254 | ||
255 | /* | |
256 | * Safe sequence used to switch IOs between GPIO and Alternate-C mode: | |
257 | * - Save SLPM registers | |
258 | * - Set SLPM=0 for the IOs you want to switch and others to 1 | |
259 | * - Configure the GPIO registers for the IOs that are being switched | |
260 | * - Set IOFORCE=1 | |
261 | * - Modify the AFLSA/B registers for the IOs that are being switched | |
262 | * - Set IOFORCE=0 | |
263 | * - Restore SLPM registers | |
264 | * - Any spurious wake up event during switch sequence to be ignored and | |
265 | * cleared | |
266 | */ | |
267 | static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) | |
268 | { | |
269 | int i; | |
270 | ||
271 | for (i = 0; i < NUM_BANKS; i++) { | |
272 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
273 | unsigned int temp = slpm[i]; | |
274 | ||
275 | if (!chip) | |
276 | break; | |
277 | ||
3c0227d2 RV |
278 | clk_enable(chip->clk); |
279 | ||
01727e61 RV |
280 | slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); |
281 | writel(temp, chip->addr + NMK_GPIO_SLPC); | |
282 | } | |
283 | } | |
284 | ||
285 | static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) | |
286 | { | |
287 | int i; | |
288 | ||
289 | for (i = 0; i < NUM_BANKS; i++) { | |
290 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
291 | ||
292 | if (!chip) | |
293 | break; | |
294 | ||
295 | writel(slpm[i], chip->addr + NMK_GPIO_SLPC); | |
3c0227d2 RV |
296 | |
297 | clk_disable(chip->clk); | |
01727e61 RV |
298 | } |
299 | } | |
300 | ||
301 | static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) | |
302 | { | |
303 | static unsigned int slpm[NUM_BANKS]; | |
304 | unsigned long flags; | |
305 | bool glitch = false; | |
306 | int ret = 0; | |
307 | int i; | |
308 | ||
309 | for (i = 0; i < num; i++) { | |
310 | if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) { | |
311 | glitch = true; | |
312 | break; | |
313 | } | |
314 | } | |
315 | ||
316 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | |
317 | ||
318 | if (glitch) { | |
319 | memset(slpm, 0xff, sizeof(slpm)); | |
320 | ||
321 | for (i = 0; i < num; i++) { | |
322 | int pin = PIN_NUM(cfgs[i]); | |
323 | int offset = pin % NMK_GPIO_PER_CHIP; | |
324 | ||
325 | if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) | |
326 | slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset); | |
327 | } | |
328 | ||
329 | nmk_gpio_glitch_slpm_init(slpm); | |
330 | } | |
331 | ||
332 | for (i = 0; i < num; i++) { | |
333 | struct nmk_gpio_chip *nmk_chip; | |
334 | int pin = PIN_NUM(cfgs[i]); | |
335 | ||
6845664a | 336 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin)); |
01727e61 RV |
337 | if (!nmk_chip) { |
338 | ret = -EINVAL; | |
339 | break; | |
340 | } | |
341 | ||
3c0227d2 | 342 | clk_enable(nmk_chip->clk); |
01727e61 RV |
343 | spin_lock(&nmk_chip->lock); |
344 | __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base, | |
345 | cfgs[i], sleep, glitch ? slpm : NULL); | |
346 | spin_unlock(&nmk_chip->lock); | |
3c0227d2 | 347 | clk_disable(nmk_chip->clk); |
01727e61 RV |
348 | } |
349 | ||
350 | if (glitch) | |
351 | nmk_gpio_glitch_slpm_restore(slpm); | |
352 | ||
353 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
354 | ||
355 | return ret; | |
378be066 RV |
356 | } |
357 | ||
358 | /** | |
359 | * nmk_config_pin - configure a pin's mux attributes | |
360 | * @cfg: pin confguration | |
361 | * | |
362 | * Configures a pin's mode (alternate function or GPIO), its pull up status, | |
363 | * and its sleep mode based on the specified configuration. The @cfg is | |
364 | * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These | |
365 | * are constructed using, and can be further enhanced with, the macros in | |
366 | * plat/pincfg.h. | |
367 | * | |
368 | * If a pin's mode is set to GPIO, it is configured as an input to avoid | |
369 | * side-effects. The gpio can be manipulated later using standard GPIO API | |
370 | * calls. | |
371 | */ | |
dacdc96c | 372 | int nmk_config_pin(pin_cfg_t cfg, bool sleep) |
378be066 | 373 | { |
01727e61 | 374 | return __nmk_config_pins(&cfg, 1, sleep); |
378be066 RV |
375 | } |
376 | EXPORT_SYMBOL(nmk_config_pin); | |
377 | ||
378 | /** | |
379 | * nmk_config_pins - configure several pins at once | |
380 | * @cfgs: array of pin configurations | |
381 | * @num: number of elments in the array | |
382 | * | |
383 | * Configures several pins using nmk_config_pin(). Refer to that function for | |
384 | * further information. | |
385 | */ | |
386 | int nmk_config_pins(pin_cfg_t *cfgs, int num) | |
387 | { | |
01727e61 | 388 | return __nmk_config_pins(cfgs, num, false); |
378be066 RV |
389 | } |
390 | EXPORT_SYMBOL(nmk_config_pins); | |
391 | ||
dacdc96c RV |
392 | int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num) |
393 | { | |
01727e61 | 394 | return __nmk_config_pins(cfgs, num, true); |
dacdc96c RV |
395 | } |
396 | EXPORT_SYMBOL(nmk_config_pins_sleep); | |
397 | ||
81a3c298 RV |
398 | /** |
399 | * nmk_gpio_set_slpm() - configure the sleep mode of a pin | |
400 | * @gpio: pin number | |
401 | * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE, | |
402 | * | |
33d78647 LW |
403 | * This register is actually in the pinmux layer, not the GPIO block itself. |
404 | * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP | |
405 | * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code). | |
406 | * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is | |
407 | * HIGH, overriding the normal setting defined by GPIO_AFSELx registers. | |
408 | * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit), | |
409 | * the GPIOs return to the normal setting defined by GPIO_AFSELx registers. | |
7e3f7e59 | 410 | * |
33d78647 LW |
411 | * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO |
412 | * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is | |
413 | * entered) regardless of the altfunction selected. Also wake-up detection is | |
414 | * ENABLED. | |
415 | * | |
416 | * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains | |
417 | * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS | |
418 | * (for altfunction GPIO) or respective on-chip peripherals (for other | |
419 | * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED. | |
420 | * | |
421 | * Note that enable_irq_wake() will automatically enable wakeup detection. | |
81a3c298 RV |
422 | */ |
423 | int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) | |
424 | { | |
425 | struct nmk_gpio_chip *nmk_chip; | |
426 | unsigned long flags; | |
427 | ||
6845664a | 428 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
81a3c298 RV |
429 | if (!nmk_chip) |
430 | return -EINVAL; | |
431 | ||
3c0227d2 | 432 | clk_enable(nmk_chip->clk); |
01727e61 RV |
433 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
434 | spin_lock(&nmk_chip->lock); | |
435 | ||
81a3c298 | 436 | __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode); |
01727e61 RV |
437 | |
438 | spin_unlock(&nmk_chip->lock); | |
439 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 440 | clk_disable(nmk_chip->clk); |
81a3c298 RV |
441 | |
442 | return 0; | |
443 | } | |
444 | ||
5b327edf RV |
445 | /** |
446 | * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio | |
447 | * @gpio: pin number | |
448 | * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE | |
449 | * | |
450 | * Enables/disables pull up/down on a specified pin. This only takes effect if | |
451 | * the pin is configured as an input (either explicitly or by the alternate | |
452 | * function). | |
453 | * | |
454 | * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is | |
455 | * configured as an input. Otherwise, due to the way the controller registers | |
456 | * work, this function will change the value output on the pin. | |
457 | */ | |
458 | int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) | |
459 | { | |
460 | struct nmk_gpio_chip *nmk_chip; | |
461 | unsigned long flags; | |
462 | ||
6845664a | 463 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
5b327edf RV |
464 | if (!nmk_chip) |
465 | return -EINVAL; | |
466 | ||
3c0227d2 | 467 | clk_enable(nmk_chip->clk); |
5b327edf RV |
468 | spin_lock_irqsave(&nmk_chip->lock, flags); |
469 | __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull); | |
470 | spin_unlock_irqrestore(&nmk_chip->lock, flags); | |
3c0227d2 | 471 | clk_disable(nmk_chip->clk); |
5b327edf RV |
472 | |
473 | return 0; | |
474 | } | |
475 | ||
2ec1d359 | 476 | /* Mode functions */ |
9c66ee6f JA |
477 | /** |
478 | * nmk_gpio_set_mode() - set the mux mode of a gpio pin | |
479 | * @gpio: pin number | |
480 | * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A, | |
481 | * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C | |
482 | * | |
483 | * Sets the mode of the specified pin to one of the alternate functions or | |
484 | * plain GPIO. | |
485 | */ | |
2ec1d359 AR |
486 | int nmk_gpio_set_mode(int gpio, int gpio_mode) |
487 | { | |
488 | struct nmk_gpio_chip *nmk_chip; | |
489 | unsigned long flags; | |
2ec1d359 | 490 | |
6845664a | 491 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
2ec1d359 AR |
492 | if (!nmk_chip) |
493 | return -EINVAL; | |
494 | ||
3c0227d2 | 495 | clk_enable(nmk_chip->clk); |
2ec1d359 | 496 | spin_lock_irqsave(&nmk_chip->lock, flags); |
6f9a974c | 497 | __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode); |
2ec1d359 | 498 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 499 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
500 | |
501 | return 0; | |
502 | } | |
503 | EXPORT_SYMBOL(nmk_gpio_set_mode); | |
504 | ||
505 | int nmk_gpio_get_mode(int gpio) | |
506 | { | |
507 | struct nmk_gpio_chip *nmk_chip; | |
508 | u32 afunc, bfunc, bit; | |
509 | ||
6845664a | 510 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
2ec1d359 AR |
511 | if (!nmk_chip) |
512 | return -EINVAL; | |
513 | ||
514 | bit = 1 << (gpio - nmk_chip->chip.base); | |
515 | ||
3c0227d2 RV |
516 | clk_enable(nmk_chip->clk); |
517 | ||
2ec1d359 AR |
518 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; |
519 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; | |
520 | ||
3c0227d2 RV |
521 | clk_disable(nmk_chip->clk); |
522 | ||
2ec1d359 AR |
523 | return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); |
524 | } | |
525 | EXPORT_SYMBOL(nmk_gpio_get_mode); | |
526 | ||
527 | ||
528 | /* IRQ functions */ | |
529 | static inline int nmk_gpio_get_bitmask(int gpio) | |
530 | { | |
531 | return 1 << (gpio % 32); | |
532 | } | |
533 | ||
f272c00e | 534 | static void nmk_gpio_irq_ack(struct irq_data *d) |
2ec1d359 AR |
535 | { |
536 | int gpio; | |
537 | struct nmk_gpio_chip *nmk_chip; | |
538 | ||
f272c00e LB |
539 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
540 | nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 AR |
541 | if (!nmk_chip) |
542 | return; | |
3c0227d2 RV |
543 | |
544 | clk_enable(nmk_chip->clk); | |
2ec1d359 | 545 | writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC); |
3c0227d2 | 546 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
547 | } |
548 | ||
4d4e20f7 RV |
549 | enum nmk_gpio_irq_type { |
550 | NORMAL, | |
551 | WAKE, | |
552 | }; | |
553 | ||
040e5ecd | 554 | static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, |
4d4e20f7 RV |
555 | int gpio, enum nmk_gpio_irq_type which, |
556 | bool enable) | |
2ec1d359 | 557 | { |
4d4e20f7 RV |
558 | u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC; |
559 | u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC; | |
040e5ecd RV |
560 | u32 bitmask = nmk_gpio_get_bitmask(gpio); |
561 | u32 reg; | |
2ec1d359 | 562 | |
040e5ecd | 563 | /* we must individually set/clear the two edges */ |
2ec1d359 | 564 | if (nmk_chip->edge_rising & bitmask) { |
4d4e20f7 | 565 | reg = readl(nmk_chip->addr + rimsc); |
040e5ecd RV |
566 | if (enable) |
567 | reg |= bitmask; | |
568 | else | |
569 | reg &= ~bitmask; | |
4d4e20f7 | 570 | writel(reg, nmk_chip->addr + rimsc); |
2ec1d359 AR |
571 | } |
572 | if (nmk_chip->edge_falling & bitmask) { | |
4d4e20f7 | 573 | reg = readl(nmk_chip->addr + fimsc); |
040e5ecd RV |
574 | if (enable) |
575 | reg |= bitmask; | |
576 | else | |
577 | reg &= ~bitmask; | |
4d4e20f7 | 578 | writel(reg, nmk_chip->addr + fimsc); |
2ec1d359 | 579 | } |
040e5ecd | 580 | } |
2ec1d359 | 581 | |
b9df468d RV |
582 | static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, |
583 | int gpio, bool on) | |
584 | { | |
b982ff0e RV |
585 | /* |
586 | * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is | |
587 | * disabled, since setting SLPM to 1 increases power consumption, and | |
588 | * wakeup is anyhow controlled by the RIMSC and FIMSC registers. | |
589 | */ | |
590 | if (nmk_chip->sleepmode && on) { | |
33d78647 | 591 | __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, |
b982ff0e | 592 | NMK_GPIO_SLPM_WAKEUP_ENABLE); |
33d78647 LW |
593 | } |
594 | ||
b9df468d RV |
595 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); |
596 | } | |
597 | ||
598 | static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) | |
2ec1d359 AR |
599 | { |
600 | int gpio; | |
601 | struct nmk_gpio_chip *nmk_chip; | |
602 | unsigned long flags; | |
040e5ecd | 603 | u32 bitmask; |
2ec1d359 | 604 | |
f272c00e LB |
605 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
606 | nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 AR |
607 | bitmask = nmk_gpio_get_bitmask(gpio); |
608 | if (!nmk_chip) | |
4d4e20f7 | 609 | return -EINVAL; |
2ec1d359 | 610 | |
3c0227d2 | 611 | clk_enable(nmk_chip->clk); |
b9df468d RV |
612 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
613 | spin_lock(&nmk_chip->lock); | |
614 | ||
615 | __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, enable); | |
616 | ||
617 | if (!(nmk_chip->real_wake & bitmask)) | |
618 | __nmk_gpio_set_wake(nmk_chip, gpio, enable); | |
619 | ||
620 | spin_unlock(&nmk_chip->lock); | |
621 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 622 | clk_disable(nmk_chip->clk); |
4d4e20f7 RV |
623 | |
624 | return 0; | |
2ec1d359 AR |
625 | } |
626 | ||
f272c00e | 627 | static void nmk_gpio_irq_mask(struct irq_data *d) |
040e5ecd | 628 | { |
b9df468d | 629 | nmk_gpio_irq_maskunmask(d, false); |
4d4e20f7 | 630 | } |
040e5ecd | 631 | |
f272c00e | 632 | static void nmk_gpio_irq_unmask(struct irq_data *d) |
040e5ecd | 633 | { |
b9df468d | 634 | nmk_gpio_irq_maskunmask(d, true); |
4d4e20f7 RV |
635 | } |
636 | ||
f272c00e | 637 | static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) |
4d4e20f7 | 638 | { |
7e3f7e59 RV |
639 | struct nmk_gpio_chip *nmk_chip; |
640 | unsigned long flags; | |
b9df468d | 641 | u32 bitmask; |
7e3f7e59 RV |
642 | int gpio; |
643 | ||
f272c00e LB |
644 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
645 | nmk_chip = irq_data_get_irq_chip_data(d); | |
7e3f7e59 RV |
646 | if (!nmk_chip) |
647 | return -EINVAL; | |
b9df468d | 648 | bitmask = nmk_gpio_get_bitmask(gpio); |
7e3f7e59 | 649 | |
3c0227d2 | 650 | clk_enable(nmk_chip->clk); |
01727e61 RV |
651 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
652 | spin_lock(&nmk_chip->lock); | |
653 | ||
479a0c7e | 654 | if (irqd_irq_disabled(d)) |
b9df468d RV |
655 | __nmk_gpio_set_wake(nmk_chip, gpio, on); |
656 | ||
657 | if (on) | |
658 | nmk_chip->real_wake |= bitmask; | |
659 | else | |
660 | nmk_chip->real_wake &= ~bitmask; | |
01727e61 RV |
661 | |
662 | spin_unlock(&nmk_chip->lock); | |
663 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 664 | clk_disable(nmk_chip->clk); |
7e3f7e59 RV |
665 | |
666 | return 0; | |
040e5ecd RV |
667 | } |
668 | ||
f272c00e | 669 | static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
2ec1d359 | 670 | { |
479a0c7e | 671 | bool enabled = !irqd_irq_disabled(d); |
3c0227d2 | 672 | bool wake = irqd_is_wakeup_set(d); |
2ec1d359 AR |
673 | int gpio; |
674 | struct nmk_gpio_chip *nmk_chip; | |
675 | unsigned long flags; | |
676 | u32 bitmask; | |
677 | ||
f272c00e LB |
678 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
679 | nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 AR |
680 | bitmask = nmk_gpio_get_bitmask(gpio); |
681 | if (!nmk_chip) | |
682 | return -EINVAL; | |
683 | ||
684 | if (type & IRQ_TYPE_LEVEL_HIGH) | |
685 | return -EINVAL; | |
686 | if (type & IRQ_TYPE_LEVEL_LOW) | |
687 | return -EINVAL; | |
688 | ||
3c0227d2 | 689 | clk_enable(nmk_chip->clk); |
2ec1d359 AR |
690 | spin_lock_irqsave(&nmk_chip->lock, flags); |
691 | ||
7a852d80 | 692 | if (enabled) |
4d4e20f7 RV |
693 | __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false); |
694 | ||
b9df468d | 695 | if (enabled || wake) |
4d4e20f7 | 696 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false); |
7a852d80 | 697 | |
2ec1d359 AR |
698 | nmk_chip->edge_rising &= ~bitmask; |
699 | if (type & IRQ_TYPE_EDGE_RISING) | |
700 | nmk_chip->edge_rising |= bitmask; | |
2ec1d359 AR |
701 | |
702 | nmk_chip->edge_falling &= ~bitmask; | |
703 | if (type & IRQ_TYPE_EDGE_FALLING) | |
704 | nmk_chip->edge_falling |= bitmask; | |
2ec1d359 | 705 | |
7a852d80 | 706 | if (enabled) |
4d4e20f7 RV |
707 | __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true); |
708 | ||
b9df468d | 709 | if (enabled || wake) |
4d4e20f7 | 710 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true); |
2ec1d359 | 711 | |
7a852d80 | 712 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 713 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
714 | |
715 | return 0; | |
716 | } | |
717 | ||
3c0227d2 RV |
718 | static unsigned int nmk_gpio_irq_startup(struct irq_data *d) |
719 | { | |
720 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 | 721 | |
3c0227d2 RV |
722 | clk_enable(nmk_chip->clk); |
723 | nmk_gpio_irq_unmask(d); | |
2ec1d359 AR |
724 | return 0; |
725 | } | |
726 | ||
3c0227d2 RV |
727 | static void nmk_gpio_irq_shutdown(struct irq_data *d) |
728 | { | |
729 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
730 | ||
731 | nmk_gpio_irq_mask(d); | |
732 | clk_disable(nmk_chip->clk); | |
733 | } | |
734 | ||
2ec1d359 AR |
735 | static struct irq_chip nmk_gpio_irq_chip = { |
736 | .name = "Nomadik-GPIO", | |
f272c00e LB |
737 | .irq_ack = nmk_gpio_irq_ack, |
738 | .irq_mask = nmk_gpio_irq_mask, | |
739 | .irq_unmask = nmk_gpio_irq_unmask, | |
740 | .irq_set_type = nmk_gpio_irq_set_type, | |
741 | .irq_set_wake = nmk_gpio_irq_set_wake, | |
3c0227d2 RV |
742 | .irq_startup = nmk_gpio_irq_startup, |
743 | .irq_shutdown = nmk_gpio_irq_shutdown, | |
2ec1d359 AR |
744 | }; |
745 | ||
33b744b3 RV |
746 | static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, |
747 | u32 status) | |
2ec1d359 AR |
748 | { |
749 | struct nmk_gpio_chip *nmk_chip; | |
6845664a | 750 | struct irq_chip *host_chip = irq_get_chip(irq); |
2ec1d359 AR |
751 | unsigned int first_irq; |
752 | ||
adfed159 | 753 | chained_irq_enter(host_chip, desc); |
aaedaa2b | 754 | |
6845664a | 755 | nmk_chip = irq_get_handler_data(irq); |
2ec1d359 | 756 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); |
33b744b3 RV |
757 | while (status) { |
758 | int bit = __ffs(status); | |
759 | ||
760 | generic_handle_irq(first_irq + bit); | |
761 | status &= ~BIT(bit); | |
2ec1d359 | 762 | } |
aaedaa2b | 763 | |
adfed159 | 764 | chained_irq_exit(host_chip, desc); |
2ec1d359 AR |
765 | } |
766 | ||
33b744b3 RV |
767 | static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
768 | { | |
6845664a | 769 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
3c0227d2 RV |
770 | u32 status; |
771 | ||
772 | clk_enable(nmk_chip->clk); | |
773 | status = readl(nmk_chip->addr + NMK_GPIO_IS); | |
774 | clk_disable(nmk_chip->clk); | |
33b744b3 RV |
775 | |
776 | __nmk_gpio_irq_handler(irq, desc, status); | |
777 | } | |
778 | ||
779 | static void nmk_gpio_secondary_irq_handler(unsigned int irq, | |
780 | struct irq_desc *desc) | |
781 | { | |
6845664a | 782 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
33b744b3 RV |
783 | u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); |
784 | ||
785 | __nmk_gpio_irq_handler(irq, desc, status); | |
786 | } | |
787 | ||
2ec1d359 AR |
788 | static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) |
789 | { | |
790 | unsigned int first_irq; | |
791 | int i; | |
792 | ||
793 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); | |
e493e06f | 794 | for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) { |
f38c02f3 TG |
795 | irq_set_chip_and_handler(i, &nmk_gpio_irq_chip, |
796 | handle_edge_irq); | |
2ec1d359 | 797 | set_irq_flags(i, IRQF_VALID); |
6845664a TG |
798 | irq_set_chip_data(i, nmk_chip); |
799 | irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING); | |
2ec1d359 | 800 | } |
33b744b3 | 801 | |
6845664a TG |
802 | irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); |
803 | irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); | |
33b744b3 RV |
804 | |
805 | if (nmk_chip->secondary_parent_irq >= 0) { | |
6845664a | 806 | irq_set_chained_handler(nmk_chip->secondary_parent_irq, |
33b744b3 | 807 | nmk_gpio_secondary_irq_handler); |
6845664a | 808 | irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip); |
33b744b3 RV |
809 | } |
810 | ||
2ec1d359 AR |
811 | return 0; |
812 | } | |
813 | ||
814 | /* I/O Functions */ | |
815 | static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) | |
816 | { | |
817 | struct nmk_gpio_chip *nmk_chip = | |
818 | container_of(chip, struct nmk_gpio_chip, chip); | |
819 | ||
3c0227d2 RV |
820 | clk_enable(nmk_chip->clk); |
821 | ||
2ec1d359 | 822 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); |
3c0227d2 RV |
823 | |
824 | clk_disable(nmk_chip->clk); | |
825 | ||
2ec1d359 AR |
826 | return 0; |
827 | } | |
828 | ||
2ec1d359 AR |
829 | static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) |
830 | { | |
831 | struct nmk_gpio_chip *nmk_chip = | |
832 | container_of(chip, struct nmk_gpio_chip, chip); | |
833 | u32 bit = 1 << offset; | |
3c0227d2 RV |
834 | int value; |
835 | ||
836 | clk_enable(nmk_chip->clk); | |
2ec1d359 | 837 | |
3c0227d2 | 838 | value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; |
2ec1d359 | 839 | |
3c0227d2 RV |
840 | clk_disable(nmk_chip->clk); |
841 | ||
842 | return value; | |
2ec1d359 AR |
843 | } |
844 | ||
845 | static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, | |
846 | int val) | |
847 | { | |
848 | struct nmk_gpio_chip *nmk_chip = | |
849 | container_of(chip, struct nmk_gpio_chip, chip); | |
2ec1d359 | 850 | |
3c0227d2 RV |
851 | clk_enable(nmk_chip->clk); |
852 | ||
6720db7c | 853 | __nmk_gpio_set_output(nmk_chip, offset, val); |
3c0227d2 RV |
854 | |
855 | clk_disable(nmk_chip->clk); | |
2ec1d359 AR |
856 | } |
857 | ||
6647c6c0 RV |
858 | static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, |
859 | int val) | |
860 | { | |
861 | struct nmk_gpio_chip *nmk_chip = | |
862 | container_of(chip, struct nmk_gpio_chip, chip); | |
863 | ||
3c0227d2 RV |
864 | clk_enable(nmk_chip->clk); |
865 | ||
6720db7c | 866 | __nmk_gpio_make_output(nmk_chip, offset, val); |
6647c6c0 | 867 | |
3c0227d2 RV |
868 | clk_disable(nmk_chip->clk); |
869 | ||
6647c6c0 RV |
870 | return 0; |
871 | } | |
872 | ||
0d2aec9c RV |
873 | static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
874 | { | |
875 | struct nmk_gpio_chip *nmk_chip = | |
876 | container_of(chip, struct nmk_gpio_chip, chip); | |
877 | ||
878 | return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset; | |
879 | } | |
880 | ||
d0b543c7 RV |
881 | #ifdef CONFIG_DEBUG_FS |
882 | ||
883 | #include <linux/seq_file.h> | |
884 | ||
885 | static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
886 | { | |
887 | int mode; | |
888 | unsigned i; | |
889 | unsigned gpio = chip->base; | |
890 | int is_out; | |
891 | struct nmk_gpio_chip *nmk_chip = | |
892 | container_of(chip, struct nmk_gpio_chip, chip); | |
893 | const char *modes[] = { | |
894 | [NMK_GPIO_ALT_GPIO] = "gpio", | |
895 | [NMK_GPIO_ALT_A] = "altA", | |
896 | [NMK_GPIO_ALT_B] = "altB", | |
897 | [NMK_GPIO_ALT_C] = "altC", | |
898 | }; | |
899 | ||
3c0227d2 RV |
900 | clk_enable(nmk_chip->clk); |
901 | ||
d0b543c7 RV |
902 | for (i = 0; i < chip->ngpio; i++, gpio++) { |
903 | const char *label = gpiochip_is_requested(chip, i); | |
904 | bool pull; | |
905 | u32 bit = 1 << i; | |
906 | ||
d0b543c7 RV |
907 | is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit; |
908 | pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); | |
909 | mode = nmk_gpio_get_mode(gpio); | |
910 | seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", | |
8ea72a30 | 911 | gpio, label ?: "(none)", |
d0b543c7 RV |
912 | is_out ? "out" : "in ", |
913 | chip->get | |
914 | ? (chip->get(chip, i) ? "hi" : "lo") | |
915 | : "? ", | |
916 | (mode < 0) ? "unknown" : modes[mode], | |
917 | pull ? "pull" : "none"); | |
8ea72a30 RV |
918 | |
919 | if (label && !is_out) { | |
920 | int irq = gpio_to_irq(gpio); | |
921 | struct irq_desc *desc = irq_to_desc(irq); | |
922 | ||
923 | /* This races with request_irq(), set_irq_type(), | |
924 | * and set_irq_wake() ... but those are "rare". | |
925 | */ | |
926 | if (irq >= 0 && desc->action) { | |
927 | char *trigger; | |
928 | u32 bitmask = nmk_gpio_get_bitmask(gpio); | |
929 | ||
930 | if (nmk_chip->edge_rising & bitmask) | |
931 | trigger = "edge-rising"; | |
932 | else if (nmk_chip->edge_falling & bitmask) | |
933 | trigger = "edge-falling"; | |
934 | else | |
935 | trigger = "edge-undefined"; | |
936 | ||
937 | seq_printf(s, " irq-%d %s%s", | |
938 | irq, trigger, | |
939 | irqd_is_wakeup_set(&desc->irq_data) | |
940 | ? " wakeup" : ""); | |
941 | } | |
942 | } | |
943 | ||
d0b543c7 RV |
944 | seq_printf(s, "\n"); |
945 | } | |
3c0227d2 RV |
946 | |
947 | clk_disable(nmk_chip->clk); | |
d0b543c7 RV |
948 | } |
949 | ||
950 | #else | |
951 | #define nmk_gpio_dbg_show NULL | |
952 | #endif | |
953 | ||
2ec1d359 AR |
954 | /* This structure is replicated for each GPIO block allocated at probe time */ |
955 | static struct gpio_chip nmk_gpio_template = { | |
956 | .direction_input = nmk_gpio_make_input, | |
957 | .get = nmk_gpio_get_input, | |
958 | .direction_output = nmk_gpio_make_output, | |
959 | .set = nmk_gpio_set_output, | |
0d2aec9c | 960 | .to_irq = nmk_gpio_to_irq, |
d0b543c7 | 961 | .dbg_show = nmk_gpio_dbg_show, |
2ec1d359 AR |
962 | .can_sleep = 0, |
963 | }; | |
964 | ||
3c0227d2 RV |
965 | void nmk_gpio_clocks_enable(void) |
966 | { | |
967 | int i; | |
968 | ||
969 | for (i = 0; i < NUM_BANKS; i++) { | |
970 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
971 | ||
972 | if (!chip) | |
973 | continue; | |
974 | ||
975 | clk_enable(chip->clk); | |
976 | } | |
977 | } | |
978 | ||
979 | void nmk_gpio_clocks_disable(void) | |
980 | { | |
981 | int i; | |
982 | ||
983 | for (i = 0; i < NUM_BANKS; i++) { | |
984 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
985 | ||
986 | if (!chip) | |
987 | continue; | |
988 | ||
989 | clk_disable(chip->clk); | |
990 | } | |
991 | } | |
992 | ||
b9df468d RV |
993 | /* |
994 | * Called from the suspend/resume path to only keep the real wakeup interrupts | |
995 | * (those that have had set_irq_wake() called on them) as wakeup interrupts, | |
996 | * and not the rest of the interrupts which we needed to have as wakeups for | |
997 | * cpuidle. | |
998 | * | |
999 | * PM ops are not used since this needs to be done at the end, after all the | |
1000 | * other drivers are done with their suspend callbacks. | |
1001 | */ | |
1002 | void nmk_gpio_wakeups_suspend(void) | |
1003 | { | |
1004 | int i; | |
1005 | ||
1006 | for (i = 0; i < NUM_BANKS; i++) { | |
1007 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1008 | ||
1009 | if (!chip) | |
1010 | break; | |
1011 | ||
3c0227d2 RV |
1012 | clk_enable(chip->clk); |
1013 | ||
b9df468d RV |
1014 | chip->rwimsc = readl(chip->addr + NMK_GPIO_RWIMSC); |
1015 | chip->fwimsc = readl(chip->addr + NMK_GPIO_FWIMSC); | |
1016 | ||
1017 | writel(chip->rwimsc & chip->real_wake, | |
1018 | chip->addr + NMK_GPIO_RWIMSC); | |
1019 | writel(chip->fwimsc & chip->real_wake, | |
1020 | chip->addr + NMK_GPIO_FWIMSC); | |
1021 | ||
3c0227d2 | 1022 | clk_disable(chip->clk); |
b9df468d RV |
1023 | } |
1024 | } | |
1025 | ||
1026 | void nmk_gpio_wakeups_resume(void) | |
1027 | { | |
1028 | int i; | |
1029 | ||
1030 | for (i = 0; i < NUM_BANKS; i++) { | |
1031 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1032 | ||
1033 | if (!chip) | |
1034 | break; | |
1035 | ||
3c0227d2 RV |
1036 | clk_enable(chip->clk); |
1037 | ||
b9df468d RV |
1038 | writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); |
1039 | writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); | |
1040 | ||
3c0227d2 | 1041 | clk_disable(chip->clk); |
b9df468d RV |
1042 | } |
1043 | } | |
1044 | ||
bc6f5cf6 RA |
1045 | /* |
1046 | * Read the pull up/pull down status. | |
1047 | * A bit set in 'pull_up' means that pull up | |
1048 | * is selected if pull is enabled in PDIS register. | |
1049 | * Note: only pull up/down set via this driver can | |
1050 | * be detected due to HW limitations. | |
1051 | */ | |
1052 | void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) | |
1053 | { | |
1054 | if (gpio_bank < NUM_BANKS) { | |
1055 | struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; | |
1056 | ||
1057 | if (!chip) | |
1058 | return; | |
1059 | ||
1060 | *pull_up = chip->pull_up; | |
1061 | } | |
1062 | } | |
1063 | ||
fd0d67d6 | 1064 | static int __devinit nmk_gpio_probe(struct platform_device *dev) |
2ec1d359 | 1065 | { |
3e3c62ca | 1066 | struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; |
2ec1d359 AR |
1067 | struct nmk_gpio_chip *nmk_chip; |
1068 | struct gpio_chip *chip; | |
3e3c62ca | 1069 | struct resource *res; |
af7dc228 | 1070 | struct clk *clk; |
33b744b3 | 1071 | int secondary_irq; |
3e3c62ca | 1072 | int irq; |
2ec1d359 AR |
1073 | int ret; |
1074 | ||
3e3c62ca RV |
1075 | if (!pdata) |
1076 | return -ENODEV; | |
1077 | ||
1078 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
1079 | if (!res) { | |
1080 | ret = -ENOENT; | |
1081 | goto out; | |
1082 | } | |
1083 | ||
1084 | irq = platform_get_irq(dev, 0); | |
1085 | if (irq < 0) { | |
1086 | ret = irq; | |
1087 | goto out; | |
1088 | } | |
1089 | ||
33b744b3 RV |
1090 | secondary_irq = platform_get_irq(dev, 1); |
1091 | if (secondary_irq >= 0 && !pdata->get_secondary_status) { | |
1092 | ret = -EINVAL; | |
1093 | goto out; | |
1094 | } | |
1095 | ||
3e3c62ca RV |
1096 | if (request_mem_region(res->start, resource_size(res), |
1097 | dev_name(&dev->dev)) == NULL) { | |
1098 | ret = -EBUSY; | |
1099 | goto out; | |
1100 | } | |
2ec1d359 | 1101 | |
af7dc228 RV |
1102 | clk = clk_get(&dev->dev, NULL); |
1103 | if (IS_ERR(clk)) { | |
1104 | ret = PTR_ERR(clk); | |
1105 | goto out_release; | |
1106 | } | |
1107 | ||
2ec1d359 AR |
1108 | nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL); |
1109 | if (!nmk_chip) { | |
1110 | ret = -ENOMEM; | |
af7dc228 | 1111 | goto out_clk; |
2ec1d359 AR |
1112 | } |
1113 | /* | |
1114 | * The virt address in nmk_chip->addr is in the nomadik register space, | |
1115 | * so we can simply convert the resource address, without remapping | |
1116 | */ | |
33b744b3 | 1117 | nmk_chip->bank = dev->id; |
af7dc228 | 1118 | nmk_chip->clk = clk; |
3e3c62ca | 1119 | nmk_chip->addr = io_p2v(res->start); |
2ec1d359 | 1120 | nmk_chip->chip = nmk_gpio_template; |
3e3c62ca | 1121 | nmk_chip->parent_irq = irq; |
33b744b3 RV |
1122 | nmk_chip->secondary_parent_irq = secondary_irq; |
1123 | nmk_chip->get_secondary_status = pdata->get_secondary_status; | |
01727e61 | 1124 | nmk_chip->set_ioforce = pdata->set_ioforce; |
33d78647 | 1125 | nmk_chip->sleepmode = pdata->supports_sleepmode; |
c0fcb8db | 1126 | spin_lock_init(&nmk_chip->lock); |
2ec1d359 AR |
1127 | |
1128 | chip = &nmk_chip->chip; | |
1129 | chip->base = pdata->first_gpio; | |
e493e06f | 1130 | chip->ngpio = pdata->num_gpio; |
8d568ae5 | 1131 | chip->label = pdata->name ?: dev_name(&dev->dev); |
2ec1d359 AR |
1132 | chip->dev = &dev->dev; |
1133 | chip->owner = THIS_MODULE; | |
1134 | ||
1135 | ret = gpiochip_add(&nmk_chip->chip); | |
1136 | if (ret) | |
1137 | goto out_free; | |
1138 | ||
01727e61 RV |
1139 | BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); |
1140 | ||
1141 | nmk_gpio_chips[nmk_chip->bank] = nmk_chip; | |
3e3c62ca | 1142 | platform_set_drvdata(dev, nmk_chip); |
2ec1d359 AR |
1143 | |
1144 | nmk_gpio_init_irq(nmk_chip); | |
1145 | ||
64842aad GL |
1146 | dev_info(&dev->dev, "at address %p\n", |
1147 | nmk_chip->addr); | |
2ec1d359 AR |
1148 | return 0; |
1149 | ||
3e3c62ca | 1150 | out_free: |
2ec1d359 | 1151 | kfree(nmk_chip); |
af7dc228 RV |
1152 | out_clk: |
1153 | clk_disable(clk); | |
1154 | clk_put(clk); | |
3e3c62ca RV |
1155 | out_release: |
1156 | release_mem_region(res->start, resource_size(res)); | |
1157 | out: | |
2ec1d359 AR |
1158 | dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret, |
1159 | pdata->first_gpio, pdata->first_gpio+31); | |
1160 | return ret; | |
1161 | } | |
1162 | ||
3e3c62ca RV |
1163 | static struct platform_driver nmk_gpio_driver = { |
1164 | .driver = { | |
2ec1d359 AR |
1165 | .owner = THIS_MODULE, |
1166 | .name = "gpio", | |
5317e4d1 | 1167 | }, |
2ec1d359 | 1168 | .probe = nmk_gpio_probe, |
2ec1d359 AR |
1169 | }; |
1170 | ||
1171 | static int __init nmk_gpio_init(void) | |
1172 | { | |
3e3c62ca | 1173 | return platform_driver_register(&nmk_gpio_driver); |
2ec1d359 AR |
1174 | } |
1175 | ||
33f45ea9 | 1176 | core_initcall(nmk_gpio_init); |
2ec1d359 AR |
1177 | |
1178 | MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); | |
1179 | MODULE_DESCRIPTION("Nomadik GPIO Driver"); | |
1180 | MODULE_LICENSE("GPL"); |