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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpio / gpio-nomadik.c
CommitLineData
2ec1d359
AR		 1/*
2 * Generic GPIO driver for logic cells found in the Nomadik SoC
3 *
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
33d78647 7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
2ec1d359
AR		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/device.h>
3e3c62ca 17#include <linux/platform_device.h>
2ec1d359 18#include <linux/io.h>
af7dc228
RV		 19#include <linux/clk.h>
20#include <linux/err.h>
2ec1d359
AR		 21#include <linux/gpio.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
5a0e3ad6 25#include <linux/slab.h>
2ec1d359 26
adfed159
WD		 27#include <asm/mach/irq.h>
28
378be066 29#include <plat/pincfg.h>
0f332861 30#include <plat/gpio-nomadik.h>
2ec1d359 31#include <mach/hardware.h>
75482dc3 32#include <asm/gpio.h>
2ec1d359
AR		 33
34/*
35 * The GPIO module in the Nomadik family of Systems-on-Chip is an
36 * AMBA device, managing 32 pins and alternate functions. The logic block
9c66ee6f 37 * is currently used in the Nomadik and ux500.
2ec1d359
AR		 38 *
39 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
40 */
41
01727e61
RV		 42#define NMK_GPIO_PER_CHIP 32
43
2ec1d359
AR		 44struct nmk_gpio_chip {
45 struct gpio_chip chip;
46 void __iomem *addr;
af7dc228 47 struct clk *clk;
33b744b3 48 unsigned int bank;
2ec1d359 49 unsigned int parent_irq;
2c8bb0eb 50 int secondary_parent_irq;
33b744b3 51 u32 (*get_secondary_status)(unsigned int bank);
01727e61 52 void (*set_ioforce)(bool enable);
c0fcb8db 53 spinlock_t lock;
33d78647 54 bool sleepmode;
2ec1d359
AR		 55 /* Keep track of configured edges */
56 u32 edge_rising;
57 u32 edge_falling;
b9df468d
RV		 58 u32 real_wake;
59 u32 rwimsc;
60 u32 fwimsc;
61 u32 slpm;
bc6f5cf6 62 u32 pull_up;
2ec1d359
AR		 63};
64
01727e61
RV		 65static struct nmk_gpio_chip *
66nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
67
68static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
69
70#define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
71
6f9a974c
RV		 72static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
73 unsigned offset, int gpio_mode)
74{
75 u32 bit = 1 << offset;
76 u32 afunc, bfunc;
77
78 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
79 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
80 if (gpio_mode & NMK_GPIO_ALT_A)
81 afunc |= bit;
82 if (gpio_mode & NMK_GPIO_ALT_B)
83 bfunc |= bit;
84 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
85 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
86}
87
81a3c298
RV		 88static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
89 unsigned offset, enum nmk_gpio_slpm mode)
90{
91 u32 bit = 1 << offset;
92 u32 slpm;
93
94 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
95 if (mode == NMK_GPIO_SLPM_NOCHANGE)
96 slpm |= bit;
97 else
98 slpm &= ~bit;
99 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
100}
101
5b327edf
RV		 102static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
103 unsigned offset, enum nmk_gpio_pull pull)
104{
105 u32 bit = 1 << offset;
106 u32 pdis;
107
108 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
bc6f5cf6 109 if (pull == NMK_GPIO_PULL_NONE) {
5b327edf 110 pdis |= bit;
bc6f5cf6
RA		 111 nmk_chip->pull_up &= ~bit;
112 } else {
5b327edf 113 pdis &= ~bit;
bc6f5cf6
RA		 114 }
115
5b327edf
RV		 116 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
117
bc6f5cf6
RA		 118 if (pull == NMK_GPIO_PULL_UP) {
119 nmk_chip->pull_up |= bit;
5b327edf 120 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
bc6f5cf6
RA		 121 } else if (pull == NMK_GPIO_PULL_DOWN) {
122 nmk_chip->pull_up &= ~bit;
5b327edf 123 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
bc6f5cf6 124 }
5b327edf
RV		 125}
126
378be066
RV		 127static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
128 unsigned offset)
129{
130 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
131}
132
6720db7c
RV		 133static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
134 unsigned offset, int val)
135{
136 if (val)
137 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
138 else
139 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
140}
141
142static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
143 unsigned offset, int val)
144{
145 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
146 __nmk_gpio_set_output(nmk_chip, offset, val);
147}
148
01727e61
RV		 149static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
150 unsigned offset, int gpio_mode,
151 bool glitch)
152{
3c4bee04
LW		 153 u32 rwimsc = readl(nmk_chip->addr + NMK_GPIO_RWIMSC);
154 u32 fwimsc = readl(nmk_chip->addr + NMK_GPIO_FWIMSC);
01727e61
RV		 155
156 if (glitch && nmk_chip->set_ioforce) {
157 u32 bit = BIT(offset);
158
01727e61
RV		 159 /* Prevent spurious wakeups */
160 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
161 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
162
163 nmk_chip->set_ioforce(true);
164 }
165
166 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
167
168 if (glitch && nmk_chip->set_ioforce) {
169 nmk_chip->set_ioforce(false);
170
171 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
172 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
173 }
174}
175
378be066 176static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
01727e61 177 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
378be066
RV		 178{
179 static const char *afnames[] = {
180 [NMK_GPIO_ALT_GPIO] = "GPIO",
181 [NMK_GPIO_ALT_A] = "A",
182 [NMK_GPIO_ALT_B] = "B",
183 [NMK_GPIO_ALT_C] = "C"
184 };
185 static const char *pullnames[] = {
186 [NMK_GPIO_PULL_NONE] = "none",
187 [NMK_GPIO_PULL_UP] = "up",
188 [NMK_GPIO_PULL_DOWN] = "down",
189 [3] /* illegal */ = "??"
190 };
191 static const char *slpmnames[] = {
7e3f7e59
RV		 192 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
193 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
378be066
RV		 194 };
195
196 int pin = PIN_NUM(cfg);
197 int pull = PIN_PULL(cfg);
198 int af = PIN_ALT(cfg);
199 int slpm = PIN_SLPM(cfg);
6720db7c
RV		 200 int output = PIN_DIR(cfg);
201 int val = PIN_VAL(cfg);
01727e61 202 bool glitch = af == NMK_GPIO_ALT_C;
378be066 203
dacdc96c
RV		 204 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
205 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
6720db7c
RV		 206 output ? "output " : "input",
207 output ? (val ? "high" : "low") : "");
208
dacdc96c
RV		 209 if (sleep) {
210 int slpm_pull = PIN_SLPM_PULL(cfg);
211 int slpm_output = PIN_SLPM_DIR(cfg);
212 int slpm_val = PIN_SLPM_VAL(cfg);
213
3546d15c
RV		 214 af = NMK_GPIO_ALT_GPIO;
215
dacdc96c
RV		 216 /*
217 * The SLPM_* values are normal values + 1 to allow zero to
218 * mean "same as normal".
219 */
220 if (slpm_pull)
221 pull = slpm_pull - 1;
222 if (slpm_output)
223 output = slpm_output - 1;
224 if (slpm_val)
225 val = slpm_val - 1;
226
227 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
228 pin,
229 slpm_pull ? pullnames[pull] : "same",
230 slpm_output ? (output ? "output" : "input") : "same",
231 slpm_val ? (val ? "high" : "low") : "same");
232 }
233
6720db7c
RV		 234 if (output)
235 __nmk_gpio_make_output(nmk_chip, offset, val);
236 else {
237 __nmk_gpio_make_input(nmk_chip, offset);
238 __nmk_gpio_set_pull(nmk_chip, offset, pull);
239 }
378be066 240
01727e61
RV		 241 /*
242 * If we've backed up the SLPM registers (glitch workaround), modify
243 * the backups since they will be restored.
244 */
245 if (slpmregs) {
246 if (slpm == NMK_GPIO_SLPM_NOCHANGE)
247 slpmregs[nmk_chip->bank] |= BIT(offset);
248 else
249 slpmregs[nmk_chip->bank] &= ~BIT(offset);
250 } else
251 __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
252
253 __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
254}
255
256/*
257 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
258 * - Save SLPM registers
259 * - Set SLPM=0 for the IOs you want to switch and others to 1
260 * - Configure the GPIO registers for the IOs that are being switched
261 * - Set IOFORCE=1
262 * - Modify the AFLSA/B registers for the IOs that are being switched
263 * - Set IOFORCE=0
264 * - Restore SLPM registers
265 * - Any spurious wake up event during switch sequence to be ignored and
266 * cleared
267 */
268static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
269{
270 int i;
271
272 for (i = 0; i < NUM_BANKS; i++) {
273 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
274 unsigned int temp = slpm[i];
275
276 if (!chip)
277 break;
278
3c0227d2
RV		 279 clk_enable(chip->clk);
280
01727e61
RV		 281 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
282 writel(temp, chip->addr + NMK_GPIO_SLPC);
283 }
284}
285
286static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
287{
288 int i;
289
290 for (i = 0; i < NUM_BANKS; i++) {
291 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
292
293 if (!chip)
294 break;
295
296 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
3c0227d2
RV		 297
298 clk_disable(chip->clk);
01727e61
RV		 299 }
300}
301
302static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
303{
304 static unsigned int slpm[NUM_BANKS];
305 unsigned long flags;
306 bool glitch = false;
307 int ret = 0;
308 int i;
309
310 for (i = 0; i < num; i++) {
311 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
312 glitch = true;
313 break;
314 }
315 }
316
317 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
318
319 if (glitch) {
320 memset(slpm, 0xff, sizeof(slpm));
321
322 for (i = 0; i < num; i++) {
323 int pin = PIN_NUM(cfgs[i]);
324 int offset = pin % NMK_GPIO_PER_CHIP;
325
326 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
327 slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
328 }
329
330 nmk_gpio_glitch_slpm_init(slpm);
331 }
332
333 for (i = 0; i < num; i++) {
334 struct nmk_gpio_chip *nmk_chip;
335 int pin = PIN_NUM(cfgs[i]);
336
6845664a 337 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin));
01727e61
RV		 338 if (!nmk_chip) {
339 ret = -EINVAL;
340 break;
341 }
342
3c0227d2 343 clk_enable(nmk_chip->clk);
01727e61
RV		 344 spin_lock(&nmk_chip->lock);
345 __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base,
346 cfgs[i], sleep, glitch ? slpm : NULL);
347 spin_unlock(&nmk_chip->lock);
3c0227d2 348 clk_disable(nmk_chip->clk);
01727e61
RV		 349 }
350
351 if (glitch)
352 nmk_gpio_glitch_slpm_restore(slpm);
353
354 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
355
356 return ret;
378be066
RV		 357}
358
359/**
360 * nmk_config_pin - configure a pin's mux attributes
361 * @cfg: pin confguration
362 *
363 * Configures a pin's mode (alternate function or GPIO), its pull up status,
364 * and its sleep mode based on the specified configuration. The @cfg is
365 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
366 * are constructed using, and can be further enhanced with, the macros in
367 * plat/pincfg.h.
368 *
369 * If a pin's mode is set to GPIO, it is configured as an input to avoid
370 * side-effects. The gpio can be manipulated later using standard GPIO API
371 * calls.
372 */
dacdc96c 373int nmk_config_pin(pin_cfg_t cfg, bool sleep)
378be066 374{
01727e61 375 return __nmk_config_pins(&cfg, 1, sleep);
378be066
RV		 376}
377EXPORT_SYMBOL(nmk_config_pin);
378
379/**
380 * nmk_config_pins - configure several pins at once
381 * @cfgs: array of pin configurations
382 * @num: number of elments in the array
383 *
384 * Configures several pins using nmk_config_pin(). Refer to that function for
385 * further information.
386 */
387int nmk_config_pins(pin_cfg_t *cfgs, int num)
388{
01727e61 389 return __nmk_config_pins(cfgs, num, false);
378be066
RV		 390}
391EXPORT_SYMBOL(nmk_config_pins);
392
dacdc96c
RV		 393int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
394{
01727e61 395 return __nmk_config_pins(cfgs, num, true);
dacdc96c
RV		 396}
397EXPORT_SYMBOL(nmk_config_pins_sleep);
398
81a3c298
RV		 399/**
400 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
401 * @gpio: pin number
402 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
403 *
33d78647
LW		 404 * This register is actually in the pinmux layer, not the GPIO block itself.
405 * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP
406 * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code).
407 * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is
408 * HIGH, overriding the normal setting defined by GPIO_AFSELx registers.
409 * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit),
410 * the GPIOs return to the normal setting defined by GPIO_AFSELx registers.
7e3f7e59 411 *
33d78647
LW		 412 * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO
413 * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is
414 * entered) regardless of the altfunction selected. Also wake-up detection is
415 * ENABLED.
416 *
417 * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains
418 * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS
419 * (for altfunction GPIO) or respective on-chip peripherals (for other
420 * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED.
421 *
422 * Note that enable_irq_wake() will automatically enable wakeup detection.
81a3c298
RV		 423 */
424int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
425{
426 struct nmk_gpio_chip *nmk_chip;
427 unsigned long flags;
428
6845664a 429 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
81a3c298
RV		 430 if (!nmk_chip)
431 return -EINVAL;
432
3c0227d2 433 clk_enable(nmk_chip->clk);
01727e61
RV		 434 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
435 spin_lock(&nmk_chip->lock);
436
81a3c298 437 __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode);
01727e61
RV		 438
439 spin_unlock(&nmk_chip->lock);
440 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
3c0227d2 441 clk_disable(nmk_chip->clk);
81a3c298
RV		 442
443 return 0;
444}
445
5b327edf
RV		 446/**
447 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
448 * @gpio: pin number
449 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
450 *
451 * Enables/disables pull up/down on a specified pin. This only takes effect if
452 * the pin is configured as an input (either explicitly or by the alternate
453 * function).
454 *
455 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
456 * configured as an input. Otherwise, due to the way the controller registers
457 * work, this function will change the value output on the pin.
458 */
459int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
460{
461 struct nmk_gpio_chip *nmk_chip;
462 unsigned long flags;
463
6845664a 464 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
5b327edf
RV		 465 if (!nmk_chip)
466 return -EINVAL;
467
3c0227d2 468 clk_enable(nmk_chip->clk);
5b327edf
RV		 469 spin_lock_irqsave(&nmk_chip->lock, flags);
470 __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull);
471 spin_unlock_irqrestore(&nmk_chip->lock, flags);
3c0227d2 472 clk_disable(nmk_chip->clk);
5b327edf
RV		 473
474 return 0;
475}
476
2ec1d359 477/* Mode functions */
9c66ee6f
JA		 478/**
479 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
480 * @gpio: pin number
481 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
482 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
483 *
484 * Sets the mode of the specified pin to one of the alternate functions or
485 * plain GPIO.
486 */
2ec1d359
AR		 487int nmk_gpio_set_mode(int gpio, int gpio_mode)
488{
489 struct nmk_gpio_chip *nmk_chip;
490 unsigned long flags;
2ec1d359 491
6845664a 492 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
2ec1d359
AR		 493 if (!nmk_chip)
494 return -EINVAL;
495
3c0227d2 496 clk_enable(nmk_chip->clk);
2ec1d359 497 spin_lock_irqsave(&nmk_chip->lock, flags);
6f9a974c 498 __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode);
2ec1d359 499 spin_unlock_irqrestore(&nmk_chip->lock, flags);
3c0227d2 500 clk_disable(nmk_chip->clk);
2ec1d359
AR		 501
502 return 0;
503}
504EXPORT_SYMBOL(nmk_gpio_set_mode);
505
506int nmk_gpio_get_mode(int gpio)
507{
508 struct nmk_gpio_chip *nmk_chip;
509 u32 afunc, bfunc, bit;
510
6845664a 511 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
2ec1d359
AR		 512 if (!nmk_chip)
513 return -EINVAL;
514
515 bit = 1 << (gpio - nmk_chip->chip.base);
516
3c0227d2
RV		 517 clk_enable(nmk_chip->clk);
518
2ec1d359
AR		 519 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
520 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
521
3c0227d2
RV		 522 clk_disable(nmk_chip->clk);
523
2ec1d359
AR		 524 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
525}
526EXPORT_SYMBOL(nmk_gpio_get_mode);
527
528
529/* IRQ functions */
530static inline int nmk_gpio_get_bitmask(int gpio)
531{
532 return 1 << (gpio % 32);
533}
534
f272c00e 535static void nmk_gpio_irq_ack(struct irq_data *d)
2ec1d359
AR		 536{
537 int gpio;
538 struct nmk_gpio_chip *nmk_chip;
539
f272c00e
LB		 540 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
541 nmk_chip = irq_data_get_irq_chip_data(d);
2ec1d359
AR		 542 if (!nmk_chip)
543 return;
3c0227d2
RV		 544
545 clk_enable(nmk_chip->clk);
2ec1d359 546 writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC);
3c0227d2 547 clk_disable(nmk_chip->clk);
2ec1d359
AR		 548}
549
4d4e20f7
RV		 550enum nmk_gpio_irq_type {
551 NORMAL,
552 WAKE,
553};
554
040e5ecd 555static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
4d4e20f7
RV		 556 int gpio, enum nmk_gpio_irq_type which,
557 bool enable)
2ec1d359 558{
4d4e20f7
RV		 559 u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC;
560 u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC;
040e5ecd
RV		 561 u32 bitmask = nmk_gpio_get_bitmask(gpio);
562 u32 reg;
2ec1d359 563
040e5ecd 564 /* we must individually set/clear the two edges */
2ec1d359 565 if (nmk_chip->edge_rising & bitmask) {
4d4e20f7 566 reg = readl(nmk_chip->addr + rimsc);
040e5ecd
RV		 567 if (enable)
568 reg |= bitmask;
569 else
570 reg &= ~bitmask;
4d4e20f7 571 writel(reg, nmk_chip->addr + rimsc);
2ec1d359
AR		 572 }
573 if (nmk_chip->edge_falling & bitmask) {
4d4e20f7 574 reg = readl(nmk_chip->addr + fimsc);
040e5ecd
RV		 575 if (enable)
576 reg |= bitmask;
577 else
578 reg &= ~bitmask;
4d4e20f7 579 writel(reg, nmk_chip->addr + fimsc);
2ec1d359 580 }
040e5ecd 581}
2ec1d359 582
b9df468d
RV		 583static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
584 int gpio, bool on)
585{
33d78647
LW		 586 if (nmk_chip->sleepmode) {
587 __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base,
588 on ? NMK_GPIO_SLPM_WAKEUP_ENABLE
589 : NMK_GPIO_SLPM_WAKEUP_DISABLE);
590 }
591
b9df468d
RV		 592 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
593}
594
595static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
2ec1d359
AR		 596{
597 int gpio;
598 struct nmk_gpio_chip *nmk_chip;
599 unsigned long flags;
040e5ecd 600 u32 bitmask;
2ec1d359 601
f272c00e
LB		 602 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
603 nmk_chip = irq_data_get_irq_chip_data(d);
2ec1d359
AR		 604 bitmask = nmk_gpio_get_bitmask(gpio);
605 if (!nmk_chip)
4d4e20f7 606 return -EINVAL;
2ec1d359 607
3c0227d2 608 clk_enable(nmk_chip->clk);
b9df468d
RV		 609 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
610 spin_lock(&nmk_chip->lock);
611
612 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, enable);
613
614 if (!(nmk_chip->real_wake & bitmask))
615 __nmk_gpio_set_wake(nmk_chip, gpio, enable);
616
617 spin_unlock(&nmk_chip->lock);
618 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
3c0227d2 619 clk_disable(nmk_chip->clk);
4d4e20f7
RV		 620
621 return 0;
2ec1d359
AR		 622}
623
f272c00e 624static void nmk_gpio_irq_mask(struct irq_data *d)
040e5ecd 625{
b9df468d 626 nmk_gpio_irq_maskunmask(d, false);
4d4e20f7 627}
040e5ecd 628
f272c00e 629static void nmk_gpio_irq_unmask(struct irq_data *d)
040e5ecd 630{
b9df468d 631 nmk_gpio_irq_maskunmask(d, true);
4d4e20f7
RV		 632}
633
f272c00e 634static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
4d4e20f7 635{
7e3f7e59
RV		 636 struct nmk_gpio_chip *nmk_chip;
637 unsigned long flags;
b9df468d 638 u32 bitmask;
7e3f7e59
RV		 639 int gpio;
640
f272c00e
LB		 641 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
642 nmk_chip = irq_data_get_irq_chip_data(d);
7e3f7e59
RV		 643 if (!nmk_chip)
644 return -EINVAL;
b9df468d 645 bitmask = nmk_gpio_get_bitmask(gpio);
7e3f7e59 646
3c0227d2 647 clk_enable(nmk_chip->clk);
01727e61
RV		 648 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
649 spin_lock(&nmk_chip->lock);
650
479a0c7e 651 if (irqd_irq_disabled(d))
b9df468d
RV		 652 __nmk_gpio_set_wake(nmk_chip, gpio, on);
653
654 if (on)
655 nmk_chip->real_wake |= bitmask;
656 else
657 nmk_chip->real_wake &= ~bitmask;
01727e61
RV		 658
659 spin_unlock(&nmk_chip->lock);
660 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
3c0227d2 661 clk_disable(nmk_chip->clk);
7e3f7e59
RV		 662
663 return 0;
040e5ecd
RV		 664}
665
f272c00e 666static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
2ec1d359 667{
479a0c7e 668 bool enabled = !irqd_irq_disabled(d);
3c0227d2 669 bool wake = irqd_is_wakeup_set(d);
2ec1d359
AR		 670 int gpio;
671 struct nmk_gpio_chip *nmk_chip;
672 unsigned long flags;
673 u32 bitmask;
674
f272c00e
LB		 675 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
676 nmk_chip = irq_data_get_irq_chip_data(d);
2ec1d359
AR		 677 bitmask = nmk_gpio_get_bitmask(gpio);
678 if (!nmk_chip)
679 return -EINVAL;
680
681 if (type & IRQ_TYPE_LEVEL_HIGH)
682 return -EINVAL;
683 if (type & IRQ_TYPE_LEVEL_LOW)
684 return -EINVAL;
685
3c0227d2 686 clk_enable(nmk_chip->clk);
2ec1d359
AR		 687 spin_lock_irqsave(&nmk_chip->lock, flags);
688
7a852d80 689 if (enabled)
4d4e20f7
RV		 690 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false);
691
b9df468d 692 if (enabled || wake)
4d4e20f7 693 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false);
7a852d80 694
2ec1d359
AR		 695 nmk_chip->edge_rising &= ~bitmask;
696 if (type & IRQ_TYPE_EDGE_RISING)
697 nmk_chip->edge_rising |= bitmask;
2ec1d359
AR		 698
699 nmk_chip->edge_falling &= ~bitmask;
700 if (type & IRQ_TYPE_EDGE_FALLING)
701 nmk_chip->edge_falling |= bitmask;
2ec1d359 702
7a852d80 703 if (enabled)
4d4e20f7
RV		 704 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true);
705
b9df468d 706 if (enabled || wake)
4d4e20f7 707 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true);
2ec1d359 708
7a852d80 709 spin_unlock_irqrestore(&nmk_chip->lock, flags);
3c0227d2 710 clk_disable(nmk_chip->clk);
2ec1d359
AR		 711
712 return 0;
713}
714
3c0227d2
RV		 715static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
716{
717 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
2ec1d359 718
3c0227d2
RV		 719 clk_enable(nmk_chip->clk);
720 nmk_gpio_irq_unmask(d);
2ec1d359
AR		 721 return 0;
722}
723
3c0227d2
RV		 724static void nmk_gpio_irq_shutdown(struct irq_data *d)
725{
726 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
727
728 nmk_gpio_irq_mask(d);
729 clk_disable(nmk_chip->clk);
730}
731
2ec1d359
AR		 732static struct irq_chip nmk_gpio_irq_chip = {
733 .name = "Nomadik-GPIO",
f272c00e
LB		 734 .irq_ack = nmk_gpio_irq_ack,
735 .irq_mask = nmk_gpio_irq_mask,
736 .irq_unmask = nmk_gpio_irq_unmask,
737 .irq_set_type = nmk_gpio_irq_set_type,
738 .irq_set_wake = nmk_gpio_irq_set_wake,
3c0227d2
RV		 739 .irq_startup = nmk_gpio_irq_startup,
740 .irq_shutdown = nmk_gpio_irq_shutdown,
2ec1d359
AR		 741};
742
33b744b3
RV		 743static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
744 u32 status)
2ec1d359
AR		 745{
746 struct nmk_gpio_chip *nmk_chip;
6845664a 747 struct irq_chip *host_chip = irq_get_chip(irq);
2ec1d359
AR		 748 unsigned int first_irq;
749
adfed159 750 chained_irq_enter(host_chip, desc);
aaedaa2b 751
6845664a 752 nmk_chip = irq_get_handler_data(irq);
2ec1d359 753 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
33b744b3
RV		 754 while (status) {
755 int bit = __ffs(status);
756
757 generic_handle_irq(first_irq + bit);
758 status &= ~BIT(bit);
2ec1d359 759 }
aaedaa2b 760
adfed159 761 chained_irq_exit(host_chip, desc);
2ec1d359
AR		 762}
763
33b744b3
RV		 764static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
765{
6845664a 766 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
3c0227d2
RV		 767 u32 status;
768
769 clk_enable(nmk_chip->clk);
770 status = readl(nmk_chip->addr + NMK_GPIO_IS);
771 clk_disable(nmk_chip->clk);
33b744b3
RV		 772
773 __nmk_gpio_irq_handler(irq, desc, status);
774}
775
776static void nmk_gpio_secondary_irq_handler(unsigned int irq,
777 struct irq_desc *desc)
778{
6845664a 779 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
33b744b3
RV		 780 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
781
782 __nmk_gpio_irq_handler(irq, desc, status);
783}
784
2ec1d359
AR		 785static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
786{
787 unsigned int first_irq;
788 int i;
789
790 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
e493e06f 791 for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) {
f38c02f3
TG		 792 irq_set_chip_and_handler(i, &nmk_gpio_irq_chip,
793 handle_edge_irq);
2ec1d359 794 set_irq_flags(i, IRQF_VALID);
6845664a
TG		 795 irq_set_chip_data(i, nmk_chip);
796 irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING);
2ec1d359 797 }
33b744b3 798
6845664a
TG		 799 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
800 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
33b744b3
RV		 801
802 if (nmk_chip->secondary_parent_irq >= 0) {
6845664a 803 irq_set_chained_handler(nmk_chip->secondary_parent_irq,
33b744b3 804 nmk_gpio_secondary_irq_handler);
6845664a 805 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
33b744b3
RV		 806 }
807
2ec1d359
AR		 808 return 0;
809}
810
811/* I/O Functions */
812static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
813{
814 struct nmk_gpio_chip *nmk_chip =
815 container_of(chip, struct nmk_gpio_chip, chip);
816
3c0227d2
RV		 817 clk_enable(nmk_chip->clk);
818
2ec1d359 819 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
3c0227d2
RV		 820
821 clk_disable(nmk_chip->clk);
822
2ec1d359
AR		 823 return 0;
824}
825
2ec1d359
AR		 826static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
827{
828 struct nmk_gpio_chip *nmk_chip =
829 container_of(chip, struct nmk_gpio_chip, chip);
830 u32 bit = 1 << offset;
3c0227d2
RV		 831 int value;
832
833 clk_enable(nmk_chip->clk);
2ec1d359 834
3c0227d2 835 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
2ec1d359 836
3c0227d2
RV		 837 clk_disable(nmk_chip->clk);
838
839 return value;
2ec1d359
AR		 840}
841
842static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
843 int val)
844{
845 struct nmk_gpio_chip *nmk_chip =
846 container_of(chip, struct nmk_gpio_chip, chip);
2ec1d359 847
3c0227d2
RV		 848 clk_enable(nmk_chip->clk);
849
6720db7c 850 __nmk_gpio_set_output(nmk_chip, offset, val);
3c0227d2
RV		 851
852 clk_disable(nmk_chip->clk);
2ec1d359
AR		 853}
854
6647c6c0
RV		 855static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
856 int val)
857{
858 struct nmk_gpio_chip *nmk_chip =
859 container_of(chip, struct nmk_gpio_chip, chip);
860
3c0227d2
RV		 861 clk_enable(nmk_chip->clk);
862
6720db7c 863 __nmk_gpio_make_output(nmk_chip, offset, val);
6647c6c0 864
3c0227d2
RV		 865 clk_disable(nmk_chip->clk);
866
6647c6c0
RV		 867 return 0;
868}
869
0d2aec9c
RV		 870static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
871{
872 struct nmk_gpio_chip *nmk_chip =
873 container_of(chip, struct nmk_gpio_chip, chip);
874
875 return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset;
876}
877
d0b543c7
RV		 878#ifdef CONFIG_DEBUG_FS
879
880#include <linux/seq_file.h>
881
882static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
883{
884 int mode;
885 unsigned i;
886 unsigned gpio = chip->base;
887 int is_out;
888 struct nmk_gpio_chip *nmk_chip =
889 container_of(chip, struct nmk_gpio_chip, chip);
890 const char *modes[] = {
891 [NMK_GPIO_ALT_GPIO] = "gpio",
892 [NMK_GPIO_ALT_A] = "altA",
893 [NMK_GPIO_ALT_B] = "altB",
894 [NMK_GPIO_ALT_C] = "altC",
895 };
896
3c0227d2
RV		 897 clk_enable(nmk_chip->clk);
898
d0b543c7
RV		 899 for (i = 0; i < chip->ngpio; i++, gpio++) {
900 const char *label = gpiochip_is_requested(chip, i);
901 bool pull;
902 u32 bit = 1 << i;
903
d0b543c7
RV		 904 is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit;
905 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
906 mode = nmk_gpio_get_mode(gpio);
907 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
8ea72a30 908 gpio, label ?: "(none)",
d0b543c7
RV		 909 is_out ? "out" : "in ",
910 chip->get
911 ? (chip->get(chip, i) ? "hi" : "lo")
912 : "? ",
913 (mode < 0) ? "unknown" : modes[mode],
914 pull ? "pull" : "none");
8ea72a30
RV		 915
916 if (label && !is_out) {
917 int irq = gpio_to_irq(gpio);
918 struct irq_desc *desc = irq_to_desc(irq);
919
920 /* This races with request_irq(), set_irq_type(),
921 * and set_irq_wake() ... but those are "rare".
922 */
923 if (irq >= 0 && desc->action) {
924 char *trigger;
925 u32 bitmask = nmk_gpio_get_bitmask(gpio);
926
927 if (nmk_chip->edge_rising & bitmask)
928 trigger = "edge-rising";
929 else if (nmk_chip->edge_falling & bitmask)
930 trigger = "edge-falling";
931 else
932 trigger = "edge-undefined";
933
934 seq_printf(s, " irq-%d %s%s",
935 irq, trigger,
936 irqd_is_wakeup_set(&desc->irq_data)
937 ? " wakeup" : "");
938 }
939 }
940
d0b543c7
RV		 941 seq_printf(s, "\n");
942 }
3c0227d2
RV		 943
944 clk_disable(nmk_chip->clk);
d0b543c7
RV		 945}
946
947#else
948#define nmk_gpio_dbg_show NULL
949#endif
950
2ec1d359
AR		 951/* This structure is replicated for each GPIO block allocated at probe time */
952static struct gpio_chip nmk_gpio_template = {
953 .direction_input = nmk_gpio_make_input,
954 .get = nmk_gpio_get_input,
955 .direction_output = nmk_gpio_make_output,
956 .set = nmk_gpio_set_output,
0d2aec9c 957 .to_irq = nmk_gpio_to_irq,
d0b543c7 958 .dbg_show = nmk_gpio_dbg_show,
2ec1d359
AR		 959 .can_sleep = 0,
960};
961
3c0227d2
RV		 962void nmk_gpio_clocks_enable(void)
963{
964 int i;
965
966 for (i = 0; i < NUM_BANKS; i++) {
967 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
968
969 if (!chip)
970 continue;
971
972 clk_enable(chip->clk);
973 }
974}
975
976void nmk_gpio_clocks_disable(void)
977{
978 int i;
979
980 for (i = 0; i < NUM_BANKS; i++) {
981 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
982
983 if (!chip)
984 continue;
985
986 clk_disable(chip->clk);
987 }
988}
989
b9df468d
RV		 990/*
991 * Called from the suspend/resume path to only keep the real wakeup interrupts
992 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
993 * and not the rest of the interrupts which we needed to have as wakeups for
994 * cpuidle.
995 *
996 * PM ops are not used since this needs to be done at the end, after all the
997 * other drivers are done with their suspend callbacks.
998 */
999void nmk_gpio_wakeups_suspend(void)
1000{
1001 int i;
1002
1003 for (i = 0; i < NUM_BANKS; i++) {
1004 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1005
1006 if (!chip)
1007 break;
1008
3c0227d2
RV		 1009 clk_enable(chip->clk);
1010
b9df468d
RV		 1011 chip->rwimsc = readl(chip->addr + NMK_GPIO_RWIMSC);
1012 chip->fwimsc = readl(chip->addr + NMK_GPIO_FWIMSC);
1013
1014 writel(chip->rwimsc & chip->real_wake,
1015 chip->addr + NMK_GPIO_RWIMSC);
1016 writel(chip->fwimsc & chip->real_wake,
1017 chip->addr + NMK_GPIO_FWIMSC);
1018
33d78647 1019 if (chip->sleepmode) {
b9df468d
RV		 1020 chip->slpm = readl(chip->addr + NMK_GPIO_SLPC);
1021
1022 /* 0 -> wakeup enable */
1023 writel(~chip->real_wake, chip->addr + NMK_GPIO_SLPC);
1024 }
3c0227d2
RV		 1025
1026 clk_disable(chip->clk);
b9df468d
RV		 1027 }
1028}
1029
1030void nmk_gpio_wakeups_resume(void)
1031{
1032 int i;
1033
1034 for (i = 0; i < NUM_BANKS; i++) {
1035 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1036
1037 if (!chip)
1038 break;
1039
3c0227d2
RV		 1040 clk_enable(chip->clk);
1041
b9df468d
RV		 1042 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
1043 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
1044
33d78647 1045 if (chip->sleepmode)
b9df468d 1046 writel(chip->slpm, chip->addr + NMK_GPIO_SLPC);
3c0227d2
RV		 1047
1048 clk_disable(chip->clk);
b9df468d
RV		 1049 }
1050}
1051
bc6f5cf6
RA		 1052/*
1053 * Read the pull up/pull down status.
1054 * A bit set in 'pull_up' means that pull up
1055 * is selected if pull is enabled in PDIS register.
1056 * Note: only pull up/down set via this driver can
1057 * be detected due to HW limitations.
1058 */
1059void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
1060{
1061 if (gpio_bank < NUM_BANKS) {
1062 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
1063
1064 if (!chip)
1065 return;
1066
1067 *pull_up = chip->pull_up;
1068 }
1069}
1070
fd0d67d6 1071static int __devinit nmk_gpio_probe(struct platform_device *dev)
2ec1d359 1072{
3e3c62ca 1073 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
2ec1d359
AR		 1074 struct nmk_gpio_chip *nmk_chip;
1075 struct gpio_chip *chip;
3e3c62ca 1076 struct resource *res;
af7dc228 1077 struct clk *clk;
33b744b3 1078 int secondary_irq;
3e3c62ca 1079 int irq;
2ec1d359
AR		 1080 int ret;
1081
3e3c62ca
RV		 1082 if (!pdata)
1083 return -ENODEV;
1084
1085 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1086 if (!res) {
1087 ret = -ENOENT;
1088 goto out;
1089 }
1090
1091 irq = platform_get_irq(dev, 0);
1092 if (irq < 0) {
1093 ret = irq;
1094 goto out;
1095 }
1096
33b744b3
RV		 1097 secondary_irq = platform_get_irq(dev, 1);
1098 if (secondary_irq >= 0 && !pdata->get_secondary_status) {
1099 ret = -EINVAL;
1100 goto out;
1101 }
1102
3e3c62ca
RV		 1103 if (request_mem_region(res->start, resource_size(res),
1104 dev_name(&dev->dev)) == NULL) {
1105 ret = -EBUSY;
1106 goto out;
1107 }
2ec1d359 1108
af7dc228
RV		 1109 clk = clk_get(&dev->dev, NULL);
1110 if (IS_ERR(clk)) {
1111 ret = PTR_ERR(clk);
1112 goto out_release;
1113 }
1114
2ec1d359
AR		 1115 nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL);
1116 if (!nmk_chip) {
1117 ret = -ENOMEM;
af7dc228 1118 goto out_clk;
2ec1d359
AR		 1119 }
1120 /*
1121 * The virt address in nmk_chip->addr is in the nomadik register space,
1122 * so we can simply convert the resource address, without remapping
1123 */
33b744b3 1124 nmk_chip->bank = dev->id;
af7dc228 1125 nmk_chip->clk = clk;
3e3c62ca 1126 nmk_chip->addr = io_p2v(res->start);
2ec1d359 1127 nmk_chip->chip = nmk_gpio_template;
3e3c62ca 1128 nmk_chip->parent_irq = irq;
33b744b3
RV		 1129 nmk_chip->secondary_parent_irq = secondary_irq;
1130 nmk_chip->get_secondary_status = pdata->get_secondary_status;
01727e61 1131 nmk_chip->set_ioforce = pdata->set_ioforce;
33d78647 1132 nmk_chip->sleepmode = pdata->supports_sleepmode;
c0fcb8db 1133 spin_lock_init(&nmk_chip->lock);
2ec1d359
AR		 1134
1135 chip = &nmk_chip->chip;
1136 chip->base = pdata->first_gpio;
e493e06f 1137 chip->ngpio = pdata->num_gpio;
8d568ae5 1138 chip->label = pdata->name ?: dev_name(&dev->dev);
2ec1d359
AR		 1139 chip->dev = &dev->dev;
1140 chip->owner = THIS_MODULE;
1141
1142 ret = gpiochip_add(&nmk_chip->chip);
1143 if (ret)
1144 goto out_free;
1145
01727e61
RV		 1146 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1147
1148 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
3e3c62ca 1149 platform_set_drvdata(dev, nmk_chip);
2ec1d359
AR		 1150
1151 nmk_gpio_init_irq(nmk_chip);
1152
64842aad
GL		 1153 dev_info(&dev->dev, "at address %p\n",
1154 nmk_chip->addr);
2ec1d359
AR		 1155 return 0;
1156
3e3c62ca 1157out_free:
2ec1d359 1158 kfree(nmk_chip);
af7dc228
RV		 1159out_clk:
1160 clk_disable(clk);
1161 clk_put(clk);
3e3c62ca
RV		 1162out_release:
1163 release_mem_region(res->start, resource_size(res));
1164out:
2ec1d359
AR		 1165 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
1166 pdata->first_gpio, pdata->first_gpio+31);
1167 return ret;
1168}
1169
3e3c62ca
RV		 1170static struct platform_driver nmk_gpio_driver = {
1171 .driver = {
2ec1d359
AR		 1172 .owner = THIS_MODULE,
1173 .name = "gpio",
5317e4d1 1174 },
2ec1d359 1175 .probe = nmk_gpio_probe,
2ec1d359
AR		 1176};
1177
1178static int __init nmk_gpio_init(void)
1179{
3e3c62ca 1180 return platform_driver_register(&nmk_gpio_driver);
2ec1d359
AR		 1181}
1182
33f45ea9 1183core_initcall(nmk_gpio_init);
2ec1d359
AR		 1184
1185MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1186MODULE_DESCRIPTION("Nomadik GPIO Driver");
1187MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)