dmatest: allocate memory for pq_coefs from heap
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / dma / dmatest.c
CommitLineData
4a776f0a
HS
1/*
2 * DMA Engine test module
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/delay.h>
b7f080cf 11#include <linux/dma-mapping.h>
4a776f0a 12#include <linux/dmaengine.h>
981ed70d 13#include <linux/freezer.h>
4a776f0a
HS
14#include <linux/init.h>
15#include <linux/kthread.h>
16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/random.h>
5a0e3ad6 19#include <linux/slab.h>
4a776f0a
HS
20#include <linux/wait.h>
21
22static unsigned int test_buf_size = 16384;
23module_param(test_buf_size, uint, S_IRUGO);
24MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
25
06190d84 26static char test_channel[20];
4a776f0a
HS
27module_param_string(channel, test_channel, sizeof(test_channel), S_IRUGO);
28MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
29
06190d84 30static char test_device[20];
4a776f0a
HS
31module_param_string(device, test_device, sizeof(test_device), S_IRUGO);
32MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
33
34static unsigned int threads_per_chan = 1;
35module_param(threads_per_chan, uint, S_IRUGO);
36MODULE_PARM_DESC(threads_per_chan,
37 "Number of threads to start per channel (default: 1)");
38
39static unsigned int max_channels;
40module_param(max_channels, uint, S_IRUGO);
33df8ca0 41MODULE_PARM_DESC(max_channels,
4a776f0a
HS
42 "Maximum number of channels to use (default: all)");
43
0a2ff57d
NF
44static unsigned int iterations;
45module_param(iterations, uint, S_IRUGO);
46MODULE_PARM_DESC(iterations,
47 "Iterations before stopping test (default: infinite)");
48
b54d5cb9
DW
49static unsigned int xor_sources = 3;
50module_param(xor_sources, uint, S_IRUGO);
51MODULE_PARM_DESC(xor_sources,
52 "Number of xor source buffers (default: 3)");
53
58691d64
DW
54static unsigned int pq_sources = 3;
55module_param(pq_sources, uint, S_IRUGO);
56MODULE_PARM_DESC(pq_sources,
57 "Number of p+q source buffers (default: 3)");
58
d42efe6b
VK
59static int timeout = 3000;
60module_param(timeout, uint, S_IRUGO);
85ee7a1d
JP
61MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
62 "Pass -1 for infinite timeout");
d42efe6b 63
4a776f0a
HS
64/*
65 * Initialization patterns. All bytes in the source buffer has bit 7
66 * set, all bytes in the destination buffer has bit 7 cleared.
67 *
68 * Bit 6 is set for all bytes which are to be copied by the DMA
69 * engine. Bit 5 is set for all bytes which are to be overwritten by
70 * the DMA engine.
71 *
72 * The remaining bits are the inverse of a counter which increments by
73 * one for each byte address.
74 */
75#define PATTERN_SRC 0x80
76#define PATTERN_DST 0x00
77#define PATTERN_COPY 0x40
78#define PATTERN_OVERWRITE 0x20
79#define PATTERN_COUNT_MASK 0x1f
80
81struct dmatest_thread {
82 struct list_head node;
83 struct task_struct *task;
84 struct dma_chan *chan;
b54d5cb9
DW
85 u8 **srcs;
86 u8 **dsts;
87 enum dma_transaction_type type;
4a776f0a
HS
88};
89
90struct dmatest_chan {
91 struct list_head node;
92 struct dma_chan *chan;
93 struct list_head threads;
94};
95
96/*
97 * These are protected by dma_list_mutex since they're only used by
33df8ca0 98 * the DMA filter function callback
4a776f0a
HS
99 */
100static LIST_HEAD(dmatest_channels);
101static unsigned int nr_channels;
102
103static bool dmatest_match_channel(struct dma_chan *chan)
104{
105 if (test_channel[0] == '\0')
106 return true;
41d5e59c 107 return strcmp(dma_chan_name(chan), test_channel) == 0;
4a776f0a
HS
108}
109
110static bool dmatest_match_device(struct dma_device *device)
111{
112 if (test_device[0] == '\0')
113 return true;
06190d84 114 return strcmp(dev_name(device->dev), test_device) == 0;
4a776f0a
HS
115}
116
117static unsigned long dmatest_random(void)
118{
119 unsigned long buf;
120
121 get_random_bytes(&buf, sizeof(buf));
122 return buf;
123}
124
b54d5cb9 125static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len)
4a776f0a
HS
126{
127 unsigned int i;
b54d5cb9
DW
128 u8 *buf;
129
130 for (; (buf = *bufs); bufs++) {
131 for (i = 0; i < start; i++)
132 buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
133 for ( ; i < start + len; i++)
134 buf[i] = PATTERN_SRC | PATTERN_COPY
c019894e 135 | (~i & PATTERN_COUNT_MASK);
b54d5cb9
DW
136 for ( ; i < test_buf_size; i++)
137 buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
138 buf++;
139 }
4a776f0a
HS
140}
141
b54d5cb9 142static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len)
4a776f0a
HS
143{
144 unsigned int i;
b54d5cb9
DW
145 u8 *buf;
146
147 for (; (buf = *bufs); bufs++) {
148 for (i = 0; i < start; i++)
149 buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
150 for ( ; i < start + len; i++)
151 buf[i] = PATTERN_DST | PATTERN_OVERWRITE
152 | (~i & PATTERN_COUNT_MASK);
153 for ( ; i < test_buf_size; i++)
154 buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
155 }
4a776f0a
HS
156}
157
158static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
159 unsigned int counter, bool is_srcbuf)
160{
161 u8 diff = actual ^ pattern;
162 u8 expected = pattern | (~counter & PATTERN_COUNT_MASK);
163 const char *thread_name = current->comm;
164
165 if (is_srcbuf)
166 pr_warning("%s: srcbuf[0x%x] overwritten!"
167 " Expected %02x, got %02x\n",
168 thread_name, index, expected, actual);
169 else if ((pattern & PATTERN_COPY)
170 && (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
171 pr_warning("%s: dstbuf[0x%x] not copied!"
172 " Expected %02x, got %02x\n",
173 thread_name, index, expected, actual);
174 else if (diff & PATTERN_SRC)
175 pr_warning("%s: dstbuf[0x%x] was copied!"
176 " Expected %02x, got %02x\n",
177 thread_name, index, expected, actual);
178 else
179 pr_warning("%s: dstbuf[0x%x] mismatch!"
180 " Expected %02x, got %02x\n",
181 thread_name, index, expected, actual);
182}
183
b54d5cb9 184static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
4a776f0a
HS
185 unsigned int end, unsigned int counter, u8 pattern,
186 bool is_srcbuf)
187{
188 unsigned int i;
189 unsigned int error_count = 0;
190 u8 actual;
b54d5cb9
DW
191 u8 expected;
192 u8 *buf;
193 unsigned int counter_orig = counter;
194
195 for (; (buf = *bufs); bufs++) {
196 counter = counter_orig;
197 for (i = start; i < end; i++) {
198 actual = buf[i];
199 expected = pattern | (~counter & PATTERN_COUNT_MASK);
200 if (actual != expected) {
201 if (error_count < 32)
202 dmatest_mismatch(actual, pattern, i,
203 counter, is_srcbuf);
204 error_count++;
205 }
206 counter++;
4a776f0a 207 }
4a776f0a
HS
208 }
209
210 if (error_count > 32)
211 pr_warning("%s: %u errors suppressed\n",
212 current->comm, error_count - 32);
213
214 return error_count;
215}
216
adfa543e
TH
217/* poor man's completion - we want to use wait_event_freezable() on it */
218struct dmatest_done {
219 bool done;
220 wait_queue_head_t *wait;
221};
222
223static void dmatest_callback(void *arg)
e44e0aa3 224{
adfa543e
TH
225 struct dmatest_done *done = arg;
226
227 done->done = true;
228 wake_up_all(done->wait);
e44e0aa3
DW
229}
230
632fd283
AS
231static inline void unmap_src(struct device *dev, dma_addr_t *addr, size_t len,
232 unsigned int count)
233{
234 while (count--)
235 dma_unmap_single(dev, addr[count], len, DMA_TO_DEVICE);
236}
237
238static inline void unmap_dst(struct device *dev, dma_addr_t *addr, size_t len,
239 unsigned int count)
240{
241 while (count--)
242 dma_unmap_single(dev, addr[count], len, DMA_BIDIRECTIONAL);
243}
244
8be9e32b
AM
245static unsigned int min_odd(unsigned int x, unsigned int y)
246{
247 unsigned int val = min(x, y);
248
249 return val % 2 ? val : val - 1;
250}
251
4a776f0a
HS
252/*
253 * This function repeatedly tests DMA transfers of various lengths and
b54d5cb9
DW
254 * offsets for a given operation type until it is told to exit by
255 * kthread_stop(). There may be multiple threads running this function
256 * in parallel for a single channel, and there may be multiple channels
257 * being tested in parallel.
4a776f0a
HS
258 *
259 * Before each test, the source and destination buffer is initialized
260 * with a known pattern. This pattern is different depending on
261 * whether it's in an area which is supposed to be copied or
262 * overwritten, and different in the source and destination buffers.
263 * So if the DMA engine doesn't copy exactly what we tell it to copy,
264 * we'll notice.
265 */
266static int dmatest_func(void *data)
267{
adfa543e 268 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(done_wait);
4a776f0a 269 struct dmatest_thread *thread = data;
adfa543e 270 struct dmatest_done done = { .wait = &done_wait };
4a776f0a 271 struct dma_chan *chan;
8be9e32b 272 struct dma_device *dev;
4a776f0a
HS
273 const char *thread_name;
274 unsigned int src_off, dst_off, len;
275 unsigned int error_count;
276 unsigned int failed_tests = 0;
277 unsigned int total_tests = 0;
278 dma_cookie_t cookie;
279 enum dma_status status;
b54d5cb9 280 enum dma_ctrl_flags flags;
945b5af3 281 u8 *pq_coefs = NULL;
4a776f0a 282 int ret;
b54d5cb9
DW
283 int src_cnt;
284 int dst_cnt;
285 int i;
4a776f0a
HS
286
287 thread_name = current->comm;
adfa543e 288 set_freezable();
4a776f0a
HS
289
290 ret = -ENOMEM;
4a776f0a
HS
291
292 smp_rmb();
293 chan = thread->chan;
8be9e32b 294 dev = chan->device;
b54d5cb9
DW
295 if (thread->type == DMA_MEMCPY)
296 src_cnt = dst_cnt = 1;
297 else if (thread->type == DMA_XOR) {
8be9e32b
AM
298 /* force odd to ensure dst = src */
299 src_cnt = min_odd(xor_sources | 1, dev->max_xor);
b54d5cb9 300 dst_cnt = 1;
58691d64 301 } else if (thread->type == DMA_PQ) {
8be9e32b
AM
302 /* force odd to ensure dst = src */
303 src_cnt = min_odd(pq_sources | 1, dma_maxpq(dev, 0));
58691d64 304 dst_cnt = 2;
945b5af3
AS
305
306 pq_coefs = kmalloc(pq_sources+1, GFP_KERNEL);
307 if (!pq_coefs)
308 goto err_thread_type;
309
94de648d 310 for (i = 0; i < src_cnt; i++)
58691d64 311 pq_coefs[i] = 1;
b54d5cb9 312 } else
945b5af3 313 goto err_thread_type;
b54d5cb9
DW
314
315 thread->srcs = kcalloc(src_cnt+1, sizeof(u8 *), GFP_KERNEL);
316 if (!thread->srcs)
317 goto err_srcs;
318 for (i = 0; i < src_cnt; i++) {
319 thread->srcs[i] = kmalloc(test_buf_size, GFP_KERNEL);
320 if (!thread->srcs[i])
321 goto err_srcbuf;
322 }
323 thread->srcs[i] = NULL;
324
325 thread->dsts = kcalloc(dst_cnt+1, sizeof(u8 *), GFP_KERNEL);
326 if (!thread->dsts)
327 goto err_dsts;
328 for (i = 0; i < dst_cnt; i++) {
329 thread->dsts[i] = kmalloc(test_buf_size, GFP_KERNEL);
330 if (!thread->dsts[i])
331 goto err_dstbuf;
332 }
333 thread->dsts[i] = NULL;
334
e44e0aa3
DW
335 set_user_nice(current, 10);
336
b203bd3f
IS
337 /*
338 * src buffers are freed by the DMAEngine code with dma_unmap_single()
339 * dst buffers are freed by ourselves below
340 */
341 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT
342 | DMA_COMPL_SKIP_DEST_UNMAP | DMA_COMPL_SRC_UNMAP_SINGLE;
4a776f0a 343
0a2ff57d
NF
344 while (!kthread_should_stop()
345 && !(iterations && total_tests >= iterations)) {
b54d5cb9
DW
346 struct dma_async_tx_descriptor *tx = NULL;
347 dma_addr_t dma_srcs[src_cnt];
348 dma_addr_t dma_dsts[dst_cnt];
83544ae9 349 u8 align = 0;
d86be86e 350
4a776f0a
HS
351 total_tests++;
352
83544ae9
DW
353 /* honor alignment restrictions */
354 if (thread->type == DMA_MEMCPY)
355 align = dev->copy_align;
356 else if (thread->type == DMA_XOR)
357 align = dev->xor_align;
358 else if (thread->type == DMA_PQ)
359 align = dev->pq_align;
360
cfe4f275
GL
361 if (1 << align > test_buf_size) {
362 pr_err("%u-byte buffer too small for %d-byte alignment\n",
363 test_buf_size, 1 << align);
364 break;
365 }
366
367 len = dmatest_random() % test_buf_size + 1;
83544ae9 368 len = (len >> align) << align;
cfe4f275
GL
369 if (!len)
370 len = 1 << align;
371 src_off = dmatest_random() % (test_buf_size - len + 1);
372 dst_off = dmatest_random() % (test_buf_size - len + 1);
373
83544ae9
DW
374 src_off = (src_off >> align) << align;
375 dst_off = (dst_off >> align) << align;
376
b54d5cb9
DW
377 dmatest_init_srcs(thread->srcs, src_off, len);
378 dmatest_init_dsts(thread->dsts, dst_off, len);
4a776f0a 379
b54d5cb9
DW
380 for (i = 0; i < src_cnt; i++) {
381 u8 *buf = thread->srcs[i] + src_off;
382
383 dma_srcs[i] = dma_map_single(dev->dev, buf, len,
384 DMA_TO_DEVICE);
afde3be1
AS
385 ret = dma_mapping_error(dev->dev, dma_srcs[i]);
386 if (ret) {
387 unmap_src(dev->dev, dma_srcs, len, i);
388 pr_warn("%s: #%u: mapping error %d with "
389 "src_off=0x%x len=0x%x\n",
390 thread_name, total_tests - 1, ret,
391 src_off, len);
392 failed_tests++;
393 continue;
394 }
b54d5cb9 395 }
d86be86e 396 /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
b54d5cb9
DW
397 for (i = 0; i < dst_cnt; i++) {
398 dma_dsts[i] = dma_map_single(dev->dev, thread->dsts[i],
399 test_buf_size,
400 DMA_BIDIRECTIONAL);
afde3be1
AS
401 ret = dma_mapping_error(dev->dev, dma_dsts[i]);
402 if (ret) {
403 unmap_src(dev->dev, dma_srcs, len, src_cnt);
404 unmap_dst(dev->dev, dma_dsts, test_buf_size, i);
405 pr_warn("%s: #%u: mapping error %d with "
406 "dst_off=0x%x len=0x%x\n",
407 thread_name, total_tests - 1, ret,
408 dst_off, test_buf_size);
409 failed_tests++;
410 continue;
411 }
b54d5cb9
DW
412 }
413
414 if (thread->type == DMA_MEMCPY)
415 tx = dev->device_prep_dma_memcpy(chan,
416 dma_dsts[0] + dst_off,
417 dma_srcs[0], len,
418 flags);
419 else if (thread->type == DMA_XOR)
420 tx = dev->device_prep_dma_xor(chan,
421 dma_dsts[0] + dst_off,
67b9124f 422 dma_srcs, src_cnt,
b54d5cb9 423 len, flags);
58691d64
DW
424 else if (thread->type == DMA_PQ) {
425 dma_addr_t dma_pq[dst_cnt];
426
427 for (i = 0; i < dst_cnt; i++)
428 dma_pq[i] = dma_dsts[i] + dst_off;
429 tx = dev->device_prep_dma_pq(chan, dma_pq, dma_srcs,
94de648d 430 src_cnt, pq_coefs,
58691d64
DW
431 len, flags);
432 }
d86be86e 433
d86be86e 434 if (!tx) {
632fd283
AS
435 unmap_src(dev->dev, dma_srcs, len, src_cnt);
436 unmap_dst(dev->dev, dma_dsts, test_buf_size, dst_cnt);
d86be86e
AN
437 pr_warning("%s: #%u: prep error with src_off=0x%x "
438 "dst_off=0x%x len=0x%x\n",
439 thread_name, total_tests - 1,
440 src_off, dst_off, len);
441 msleep(100);
442 failed_tests++;
443 continue;
444 }
e44e0aa3 445
adfa543e 446 done.done = false;
e44e0aa3 447 tx->callback = dmatest_callback;
adfa543e 448 tx->callback_param = &done;
d86be86e
AN
449 cookie = tx->tx_submit(tx);
450
4a776f0a
HS
451 if (dma_submit_error(cookie)) {
452 pr_warning("%s: #%u: submit error %d with src_off=0x%x "
453 "dst_off=0x%x len=0x%x\n",
454 thread_name, total_tests - 1, cookie,
455 src_off, dst_off, len);
456 msleep(100);
457 failed_tests++;
458 continue;
459 }
b54d5cb9 460 dma_async_issue_pending(chan);
4a776f0a 461
77101ce5
AS
462 wait_event_freezable_timeout(done_wait,
463 done.done || kthread_should_stop(),
adfa543e 464 msecs_to_jiffies(timeout));
981ed70d 465
e44e0aa3 466 status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
4a776f0a 467
adfa543e
TH
468 if (!done.done) {
469 /*
470 * We're leaving the timed out dma operation with
471 * dangling pointer to done_wait. To make this
472 * correct, we'll need to allocate wait_done for
473 * each test iteration and perform "who's gonna
474 * free it this time?" dancing. For now, just
475 * leave it dangling.
476 */
e44e0aa3
DW
477 pr_warning("%s: #%u: test timed out\n",
478 thread_name, total_tests - 1);
479 failed_tests++;
480 continue;
481 } else if (status != DMA_SUCCESS) {
482 pr_warning("%s: #%u: got completion callback,"
483 " but status is \'%s\'\n",
484 thread_name, total_tests - 1,
485 status == DMA_ERROR ? "error" : "in progress");
4a776f0a
HS
486 failed_tests++;
487 continue;
488 }
e44e0aa3 489
d86be86e 490 /* Unmap by myself (see DMA_COMPL_SKIP_DEST_UNMAP above) */
632fd283 491 unmap_dst(dev->dev, dma_dsts, test_buf_size, dst_cnt);
4a776f0a
HS
492
493 error_count = 0;
494
495 pr_debug("%s: verifying source buffer...\n", thread_name);
b54d5cb9 496 error_count += dmatest_verify(thread->srcs, 0, src_off,
4a776f0a 497 0, PATTERN_SRC, true);
b54d5cb9 498 error_count += dmatest_verify(thread->srcs, src_off,
4a776f0a
HS
499 src_off + len, src_off,
500 PATTERN_SRC | PATTERN_COPY, true);
b54d5cb9 501 error_count += dmatest_verify(thread->srcs, src_off + len,
4a776f0a
HS
502 test_buf_size, src_off + len,
503 PATTERN_SRC, true);
504
505 pr_debug("%s: verifying dest buffer...\n",
506 thread->task->comm);
b54d5cb9 507 error_count += dmatest_verify(thread->dsts, 0, dst_off,
4a776f0a 508 0, PATTERN_DST, false);
b54d5cb9 509 error_count += dmatest_verify(thread->dsts, dst_off,
4a776f0a
HS
510 dst_off + len, src_off,
511 PATTERN_SRC | PATTERN_COPY, false);
b54d5cb9 512 error_count += dmatest_verify(thread->dsts, dst_off + len,
4a776f0a
HS
513 test_buf_size, dst_off + len,
514 PATTERN_DST, false);
515
516 if (error_count) {
517 pr_warning("%s: #%u: %u errors with "
518 "src_off=0x%x dst_off=0x%x len=0x%x\n",
519 thread_name, total_tests - 1, error_count,
520 src_off, dst_off, len);
521 failed_tests++;
522 } else {
523 pr_debug("%s: #%u: No errors with "
524 "src_off=0x%x dst_off=0x%x len=0x%x\n",
525 thread_name, total_tests - 1,
526 src_off, dst_off, len);
527 }
528 }
529
530 ret = 0;
b54d5cb9
DW
531 for (i = 0; thread->dsts[i]; i++)
532 kfree(thread->dsts[i]);
4a776f0a 533err_dstbuf:
b54d5cb9
DW
534 kfree(thread->dsts);
535err_dsts:
536 for (i = 0; thread->srcs[i]; i++)
537 kfree(thread->srcs[i]);
4a776f0a 538err_srcbuf:
b54d5cb9
DW
539 kfree(thread->srcs);
540err_srcs:
945b5af3
AS
541 kfree(pq_coefs);
542err_thread_type:
4a776f0a
HS
543 pr_notice("%s: terminating after %u tests, %u failures (status %d)\n",
544 thread_name, total_tests, failed_tests, ret);
0a2ff57d 545
9704efaa 546 /* terminate all transfers on specified channels */
5e034f7b
SH
547 if (ret)
548 dmaengine_terminate_all(chan);
549
0a2ff57d
NF
550 if (iterations > 0)
551 while (!kthread_should_stop()) {
b953df7c 552 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wait_dmatest_exit);
0a2ff57d
NF
553 interruptible_sleep_on(&wait_dmatest_exit);
554 }
555
4a776f0a
HS
556 return ret;
557}
558
559static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
560{
561 struct dmatest_thread *thread;
562 struct dmatest_thread *_thread;
563 int ret;
564
565 list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
566 ret = kthread_stop(thread->task);
567 pr_debug("dmatest: thread %s exited with status %d\n",
568 thread->task->comm, ret);
569 list_del(&thread->node);
570 kfree(thread);
571 }
9704efaa
VK
572
573 /* terminate all transfers on specified channels */
944ea4dd 574 dmaengine_terminate_all(dtc->chan);
9704efaa 575
4a776f0a
HS
576 kfree(dtc);
577}
578
b54d5cb9 579static int dmatest_add_threads(struct dmatest_chan *dtc, enum dma_transaction_type type)
4a776f0a 580{
b54d5cb9
DW
581 struct dmatest_thread *thread;
582 struct dma_chan *chan = dtc->chan;
583 char *op;
584 unsigned int i;
4a776f0a 585
b54d5cb9
DW
586 if (type == DMA_MEMCPY)
587 op = "copy";
588 else if (type == DMA_XOR)
589 op = "xor";
58691d64
DW
590 else if (type == DMA_PQ)
591 op = "pq";
b54d5cb9
DW
592 else
593 return -EINVAL;
4a776f0a
HS
594
595 for (i = 0; i < threads_per_chan; i++) {
596 thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
597 if (!thread) {
b54d5cb9
DW
598 pr_warning("dmatest: No memory for %s-%s%u\n",
599 dma_chan_name(chan), op, i);
600
4a776f0a
HS
601 break;
602 }
603 thread->chan = dtc->chan;
b54d5cb9 604 thread->type = type;
4a776f0a 605 smp_wmb();
b54d5cb9
DW
606 thread->task = kthread_run(dmatest_func, thread, "%s-%s%u",
607 dma_chan_name(chan), op, i);
4a776f0a 608 if (IS_ERR(thread->task)) {
b54d5cb9
DW
609 pr_warning("dmatest: Failed to run thread %s-%s%u\n",
610 dma_chan_name(chan), op, i);
4a776f0a
HS
611 kfree(thread);
612 break;
613 }
614
615 /* srcbuf and dstbuf are allocated by the thread itself */
616
617 list_add_tail(&thread->node, &dtc->threads);
618 }
619
b54d5cb9
DW
620 return i;
621}
622
623static int dmatest_add_channel(struct dma_chan *chan)
624{
625 struct dmatest_chan *dtc;
626 struct dma_device *dma_dev = chan->device;
627 unsigned int thread_count = 0;
b9033e68 628 int cnt;
b54d5cb9
DW
629
630 dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
631 if (!dtc) {
632 pr_warning("dmatest: No memory for %s\n", dma_chan_name(chan));
633 return -ENOMEM;
634 }
635
636 dtc->chan = chan;
637 INIT_LIST_HEAD(&dtc->threads);
638
639 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
640 cnt = dmatest_add_threads(dtc, DMA_MEMCPY);
f1aef8b6 641 thread_count += cnt > 0 ? cnt : 0;
b54d5cb9
DW
642 }
643 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
644 cnt = dmatest_add_threads(dtc, DMA_XOR);
f1aef8b6 645 thread_count += cnt > 0 ? cnt : 0;
b54d5cb9 646 }
58691d64
DW
647 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
648 cnt = dmatest_add_threads(dtc, DMA_PQ);
d07a74a5 649 thread_count += cnt > 0 ? cnt : 0;
58691d64 650 }
b54d5cb9
DW
651
652 pr_info("dmatest: Started %u threads using %s\n",
653 thread_count, dma_chan_name(chan));
4a776f0a
HS
654
655 list_add_tail(&dtc->node, &dmatest_channels);
656 nr_channels++;
657
33df8ca0 658 return 0;
4a776f0a
HS
659}
660
7dd60251 661static bool filter(struct dma_chan *chan, void *param)
4a776f0a 662{
33df8ca0 663 if (!dmatest_match_channel(chan) || !dmatest_match_device(chan->device))
7dd60251 664 return false;
33df8ca0 665 else
7dd60251 666 return true;
4a776f0a
HS
667}
668
4a776f0a
HS
669static int __init dmatest_init(void)
670{
33df8ca0
DW
671 dma_cap_mask_t mask;
672 struct dma_chan *chan;
673 int err = 0;
674
675 dma_cap_zero(mask);
676 dma_cap_set(DMA_MEMCPY, mask);
677 for (;;) {
678 chan = dma_request_channel(mask, filter, NULL);
679 if (chan) {
680 err = dmatest_add_channel(chan);
c56c81ab 681 if (err) {
33df8ca0
DW
682 dma_release_channel(chan);
683 break; /* add_channel failed, punt */
684 }
685 } else
686 break; /* no more channels available */
687 if (max_channels && nr_channels >= max_channels)
688 break; /* we have all we need */
689 }
4a776f0a 690
33df8ca0 691 return err;
4a776f0a 692}
33df8ca0
DW
693/* when compiled-in wait for drivers to load first */
694late_initcall(dmatest_init);
4a776f0a
HS
695
696static void __exit dmatest_exit(void)
697{
33df8ca0 698 struct dmatest_chan *dtc, *_dtc;
7cbd4877 699 struct dma_chan *chan;
33df8ca0
DW
700
701 list_for_each_entry_safe(dtc, _dtc, &dmatest_channels, node) {
702 list_del(&dtc->node);
7cbd4877 703 chan = dtc->chan;
33df8ca0
DW
704 dmatest_cleanup_channel(dtc);
705 pr_debug("dmatest: dropped channel %s\n",
7cbd4877
DW
706 dma_chan_name(chan));
707 dma_release_channel(chan);
33df8ca0 708 }
4a776f0a
HS
709}
710module_exit(dmatest_exit);
711
e05503ef 712MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
4a776f0a 713MODULE_LICENSE("GPL v2");