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KVM: VMX: Simplify vmx_get_nmi_mask()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
5a0e3ad6 42#include <linux/slab.h>
ff9d07a0 43#include <linux/perf_event.h>
aec51dc4 44#include <trace/events/kvm.h>
2ed152af 45
229456fc
MT		 46#define CREATE_TRACE_POINTS
47#include "trace.h"
043405e1 48
24f1e32c 49#include <asm/debugreg.h>
043405e1 50#include <asm/uaccess.h>
d825ed0a 51#include <asm/msr.h>
a5f61300 52#include <asm/desc.h>
0bed3b56 53#include <asm/mtrr.h>
890ca9ae 54#include <asm/mce.h>
043405e1 55
313a3dc7 56#define MAX_IO_MSRS 256
a03490ed
CO		 57#define CR0_RESERVED_BITS \
58 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
59 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
60 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
61#define CR4_RESERVED_BITS \
62 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
63 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
64 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
65 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
66
67#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 68
69#define KVM_MAX_MCE_BANKS 32
70#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
71
50a37eb4
JR		 72/* EFER defaults:
73 * - enable syscall per default because its emulated by KVM
74 * - enable LME and LMA per default on 64 bit KVM
75 */
76#ifdef CONFIG_X86_64
77static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
78#else
79static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
80#endif
313a3dc7 81
ba1389b7
AK		 82#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
83#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 84
cb142eb7 85static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 86static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
87 struct kvm_cpuid_entry2 __user *entries);
88
97896d04 89struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 90EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 91
ed85c068
AP		 92int ignore_msrs = 0;
93module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
94
18863bdd
AK		 95#define KVM_NR_SHARED_MSRS 16
96
97struct kvm_shared_msrs_global {
98 int nr;
2bf78fa7 99 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 100};
101
102struct kvm_shared_msrs {
103 struct user_return_notifier urn;
104 bool registered;
2bf78fa7
SY		 105 struct kvm_shared_msr_values {
106 u64 host;
107 u64 curr;
108 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 109};
110
111static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
112static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
113
417bc304 114struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 115 { "pf_fixed", VCPU_STAT(pf_fixed) },
116 { "pf_guest", VCPU_STAT(pf_guest) },
117 { "tlb_flush", VCPU_STAT(tlb_flush) },
118 { "invlpg", VCPU_STAT(invlpg) },
119 { "exits", VCPU_STAT(exits) },
120 { "io_exits", VCPU_STAT(io_exits) },
121 { "mmio_exits", VCPU_STAT(mmio_exits) },
122 { "signal_exits", VCPU_STAT(signal_exits) },
123 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 124 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 125 { "halt_exits", VCPU_STAT(halt_exits) },
126 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 127 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 128 { "request_irq", VCPU_STAT(request_irq_exits) },
129 { "irq_exits", VCPU_STAT(irq_exits) },
130 { "host_state_reload", VCPU_STAT(host_state_reload) },
131 { "efer_reload", VCPU_STAT(efer_reload) },
132 { "fpu_reload", VCPU_STAT(fpu_reload) },
133 { "insn_emulation", VCPU_STAT(insn_emulation) },
134 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 135 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 136 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 137 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
138 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
139 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
140 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
141 { "mmu_flooded", VM_STAT(mmu_flooded) },
142 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 143 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 144 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 145 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 146 { "largepages", VM_STAT(lpages) },
417bc304
HB		 147 { NULL }
148};
149
18863bdd
AK		 150static void kvm_on_user_return(struct user_return_notifier *urn)
151{
152 unsigned slot;
18863bdd
AK		 153 struct kvm_shared_msrs *locals
154 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 155 struct kvm_shared_msr_values *values;
18863bdd
AK		 156
157 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 158 values = &locals->values[slot];
159 if (values->host != values->curr) {
160 wrmsrl(shared_msrs_global.msrs[slot], values->host);
161 values->curr = values->host;
18863bdd
AK		 162 }
163 }
164 locals->registered = false;
165 user_return_notifier_unregister(urn);
166}
167
2bf78fa7 168static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 169{
2bf78fa7 170 struct kvm_shared_msrs *smsr;
18863bdd
AK		 171 u64 value;
172
2bf78fa7
SY		 173 smsr = &__get_cpu_var(shared_msrs);
174 /* only read, and nobody should modify it at this time,
175 * so don't need lock */
176 if (slot >= shared_msrs_global.nr) {
177 printk(KERN_ERR "kvm: invalid MSR slot!");
178 return;
179 }
180 rdmsrl_safe(msr, &value);
181 smsr->values[slot].host = value;
182 smsr->values[slot].curr = value;
183}
184
185void kvm_define_shared_msr(unsigned slot, u32 msr)
186{
18863bdd
AK		 187 if (slot >= shared_msrs_global.nr)
188 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 189 shared_msrs_global.msrs[slot] = msr;
190 /* we need ensured the shared_msr_global have been updated */
191 smp_wmb();
18863bdd
AK		 192}
193EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
194
195static void kvm_shared_msr_cpu_online(void)
196{
197 unsigned i;
18863bdd
AK		 198
199 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 200 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 201}
202
d5696725 203void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 204{
205 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
206
2bf78fa7 207 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 208 return;
2bf78fa7
SY		 209 smsr->values[slot].curr = value;
210 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 211 if (!smsr->registered) {
212 smsr->urn.on_user_return = kvm_on_user_return;
213 user_return_notifier_register(&smsr->urn);
214 smsr->registered = true;
215 }
216}
217EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
218
3548bab5
AK		 219static void drop_user_return_notifiers(void *ignore)
220{
221 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
222
223 if (smsr->registered)
224 kvm_on_user_return(&smsr->urn);
225}
226
6866b83e
CO		 227u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
228{
229 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 230 return vcpu->arch.apic_base;
6866b83e 231 else
ad312c7c 232 return vcpu->arch.apic_base;
6866b83e
CO		 233}
234EXPORT_SYMBOL_GPL(kvm_get_apic_base);
235
236void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
237{
238 /* TODO: reserve bits check */
239 if (irqchip_in_kernel(vcpu->kvm))
240 kvm_lapic_set_base(vcpu, data);
241 else
ad312c7c 242 vcpu->arch.apic_base = data;
6866b83e
CO		 243}
244EXPORT_SYMBOL_GPL(kvm_set_apic_base);
245
3fd28fce
ED		 246#define EXCPT_BENIGN 0
247#define EXCPT_CONTRIBUTORY 1
248#define EXCPT_PF 2
249
250static int exception_class(int vector)
251{
252 switch (vector) {
253 case PF_VECTOR:
254 return EXCPT_PF;
255 case DE_VECTOR:
256 case TS_VECTOR:
257 case NP_VECTOR:
258 case SS_VECTOR:
259 case GP_VECTOR:
260 return EXCPT_CONTRIBUTORY;
261 default:
262 break;
263 }
264 return EXCPT_BENIGN;
265}
266
267static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 268 unsigned nr, bool has_error, u32 error_code,
269 bool reinject)
3fd28fce
ED		 270{
271 u32 prev_nr;
272 int class1, class2;
273
274 if (!vcpu->arch.exception.pending) {
275 queue:
276 vcpu->arch.exception.pending = true;
277 vcpu->arch.exception.has_error_code = has_error;
278 vcpu->arch.exception.nr = nr;
279 vcpu->arch.exception.error_code = error_code;
3f0fd292 280 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 281 return;
282 }
283
284 /* to check exception */
285 prev_nr = vcpu->arch.exception.nr;
286 if (prev_nr == DF_VECTOR) {
287 /* triple fault -> shutdown */
288 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
289 return;
290 }
291 class1 = exception_class(prev_nr);
292 class2 = exception_class(nr);
293 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
294 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
295 /* generate double fault per SDM Table 5-5 */
296 vcpu->arch.exception.pending = true;
297 vcpu->arch.exception.has_error_code = true;
298 vcpu->arch.exception.nr = DF_VECTOR;
299 vcpu->arch.exception.error_code = 0;
300 } else
301 /* replace previous exception with a new one in a hope
302 that instruction re-execution will regenerate lost
303 exception */
304 goto queue;
305}
306
298101da
AK		 307void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
308{
ce7ddec4 309 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 310}
311EXPORT_SYMBOL_GPL(kvm_queue_exception);
312
ce7ddec4
JR		 313void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
314{
315 kvm_multiple_exception(vcpu, nr, false, 0, true);
316}
317EXPORT_SYMBOL_GPL(kvm_requeue_exception);
318
c3c91fee
AK		 319void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
320 u32 error_code)
321{
322 ++vcpu->stat.pf_guest;
ad312c7c 323 vcpu->arch.cr2 = addr;
c3c91fee
AK		 324 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
325}
326
3419ffc8
SY		 327void kvm_inject_nmi(struct kvm_vcpu *vcpu)
328{
329 vcpu->arch.nmi_pending = 1;
330}
331EXPORT_SYMBOL_GPL(kvm_inject_nmi);
332
298101da
AK		 333void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
334{
ce7ddec4 335 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 336}
337EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
338
ce7ddec4
JR		 339void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
340{
341 kvm_multiple_exception(vcpu, nr, true, error_code, true);
342}
343EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
344
0a79b009
AK		 345/*
346 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
347 * a #GP and return false.
348 */
349bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 350{
0a79b009
AK		 351 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
352 return true;
353 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
354 return false;
298101da 355}
0a79b009 356EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 357
a03490ed
CO		 358/*
359 * Load the pae pdptrs. Return true is they are all valid.
360 */
361int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
362{
363 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
364 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
365 int i;
366 int ret;
ad312c7c 367 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 368
a03490ed
CO		 369 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
370 offset * sizeof(u64), sizeof(pdpte));
371 if (ret < 0) {
372 ret = 0;
373 goto out;
374 }
375 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 376 if (is_present_gpte(pdpte[i]) &&
20c466b5 377 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 378 ret = 0;
379 goto out;
380 }
381 }
382 ret = 1;
383
ad312c7c 384 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 385 __set_bit(VCPU_EXREG_PDPTR,
386 (unsigned long *)&vcpu->arch.regs_avail);
387 __set_bit(VCPU_EXREG_PDPTR,
388 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 389out:
a03490ed
CO		 390
391 return ret;
392}
cc4b6871 393EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 394
d835dfec
AK		 395static bool pdptrs_changed(struct kvm_vcpu *vcpu)
396{
ad312c7c 397 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 398 bool changed = true;
399 int r;
400
401 if (is_long_mode(vcpu) || !is_pae(vcpu))
402 return false;
403
6de4f3ad
AK		 404 if (!test_bit(VCPU_EXREG_PDPTR,
405 (unsigned long *)&vcpu->arch.regs_avail))
406 return true;
407
ad312c7c 408 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 409 if (r < 0)
410 goto out;
ad312c7c 411 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 412out:
d835dfec
AK		 413
414 return changed;
415}
416
2d3ad1f4 417void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 418{
f9a48e6a
AK		 419 cr0 |= X86_CR0_ET;
420
ab344828
GN		 421#ifdef CONFIG_X86_64
422 if (cr0 & 0xffffffff00000000UL) {
c1a5d4f9 423 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 424 return;
425 }
ab344828
GN		 426#endif
427
428 cr0 &= ~CR0_RESERVED_BITS;
a03490ed
CO		 429
430 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
c1a5d4f9 431 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 432 return;
433 }
434
435 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
c1a5d4f9 436 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 437 return;
438 }
439
440 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
441#ifdef CONFIG_X86_64
f6801dff 442 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 443 int cs_db, cs_l;
444
445 if (!is_pae(vcpu)) {
c1a5d4f9 446 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 447 return;
448 }
449 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
450 if (cs_l) {
c1a5d4f9 451 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 452 return;
453
454 }
455 } else
456#endif
ad312c7c 457 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 458 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 459 return;
460 }
461
462 }
463
464 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 465
a03490ed 466 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 467 return;
468}
2d3ad1f4 469EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 470
2d3ad1f4 471void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 472{
f78e9176 473 kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 474}
2d3ad1f4 475EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 476
2d3ad1f4 477void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 478{
fc78f519 479 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 480 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
481
a03490ed 482 if (cr4 & CR4_RESERVED_BITS) {
c1a5d4f9 483 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 484 return;
485 }
486
487 if (is_long_mode(vcpu)) {
488 if (!(cr4 & X86_CR4_PAE)) {
c1a5d4f9 489 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 490 return;
491 }
a2edf57f
AK		 492 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
493 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 494 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 495 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 496 return;
497 }
498
499 if (cr4 & X86_CR4_VMXE) {
c1a5d4f9 500 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 501 return;
502 }
503 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 504 vcpu->arch.cr4 = cr4;
a03490ed 505 kvm_mmu_reset_context(vcpu);
a03490ed 506}
2d3ad1f4 507EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 508
2d3ad1f4 509void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 510{
ad312c7c 511 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 512 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 513 kvm_mmu_flush_tlb(vcpu);
514 return;
515 }
516
a03490ed
CO		 517 if (is_long_mode(vcpu)) {
518 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
c1a5d4f9 519 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 520 return;
521 }
522 } else {
523 if (is_pae(vcpu)) {
524 if (cr3 & CR3_PAE_RESERVED_BITS) {
c1a5d4f9 525 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 526 return;
527 }
528 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
c1a5d4f9 529 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 530 return;
531 }
532 }
533 /*
534 * We don't check reserved bits in nonpae mode, because
535 * this isn't enforced, and VMware depends on this.
536 */
537 }
538
a03490ed
CO		 539 /*
540 * Does the new cr3 value map to physical memory? (Note, we
541 * catch an invalid cr3 even in real-mode, because it would
542 * cause trouble later on when we turn on paging anyway.)
543 *
544 * A real CPU would silently accept an invalid cr3 and would
545 * attempt to use it - with largely undefined (and often hard
546 * to debug) behavior on the guest side.
547 */
548 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 549 kvm_inject_gp(vcpu, 0);
a03490ed 550 else {
ad312c7c
ZX		 551 vcpu->arch.cr3 = cr3;
552 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 553 }
a03490ed 554}
2d3ad1f4 555EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 556
2d3ad1f4 557void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 558{
559 if (cr8 & CR8_RESERVED_BITS) {
c1a5d4f9 560 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 561 return;
562 }
563 if (irqchip_in_kernel(vcpu->kvm))
564 kvm_lapic_set_tpr(vcpu, cr8);
565 else
ad312c7c 566 vcpu->arch.cr8 = cr8;
a03490ed 567}
2d3ad1f4 568EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 569
2d3ad1f4 570unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 571{
572 if (irqchip_in_kernel(vcpu->kvm))
573 return kvm_lapic_get_cr8(vcpu);
574 else
ad312c7c 575 return vcpu->arch.cr8;
a03490ed 576}
2d3ad1f4 577EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 578
020df079
GN		 579int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
580{
581 switch (dr) {
582 case 0 ... 3:
583 vcpu->arch.db[dr] = val;
584 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
585 vcpu->arch.eff_db[dr] = val;
586 break;
587 case 4:
588 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
589 kvm_queue_exception(vcpu, UD_VECTOR);
590 return 1;
591 }
592 /* fall through */
593 case 6:
594 if (val & 0xffffffff00000000ULL) {
595 kvm_inject_gp(vcpu, 0);
596 return 1;
597 }
598 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
599 break;
600 case 5:
601 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
602 kvm_queue_exception(vcpu, UD_VECTOR);
603 return 1;
604 }
605 /* fall through */
606 default: /* 7 */
607 if (val & 0xffffffff00000000ULL) {
608 kvm_inject_gp(vcpu, 0);
609 return 1;
610 }
611 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
612 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
613 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
614 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
615 }
616 break;
617 }
618
619 return 0;
620}
621EXPORT_SYMBOL_GPL(kvm_set_dr);
622
623int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
624{
625 switch (dr) {
626 case 0 ... 3:
627 *val = vcpu->arch.db[dr];
628 break;
629 case 4:
630 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
631 kvm_queue_exception(vcpu, UD_VECTOR);
632 return 1;
633 }
634 /* fall through */
635 case 6:
636 *val = vcpu->arch.dr6;
637 break;
638 case 5:
639 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
640 kvm_queue_exception(vcpu, UD_VECTOR);
641 return 1;
642 }
643 /* fall through */
644 default: /* 7 */
645 *val = vcpu->arch.dr7;
646 break;
647 }
648
649 return 0;
650}
651EXPORT_SYMBOL_GPL(kvm_get_dr);
652
d8017474
AG		 653static inline u32 bit(int bitno)
654{
655 return 1 << (bitno & 31);
656}
657
043405e1
CO		 658/*
659 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
660 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
661 *
662 * This list is modified at module load time to reflect the
e3267cbb
GC		 663 * capabilities of the host cpu. This capabilities test skips MSRs that are
664 * kvm-specific. Those are put in the beginning of the list.
043405e1 665 */
e3267cbb 666
11c6bffa 667#define KVM_SAVE_MSRS_BEGIN 7
043405e1 668static u32 msrs_to_save[] = {
e3267cbb 669 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 670 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 671 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 672 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1
CO		 673 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
674 MSR_K6_STAR,
675#ifdef CONFIG_X86_64
676 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
677#endif
e3267cbb 678 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 679};
680
681static unsigned num_msrs_to_save;
682
683static u32 emulated_msrs[] = {
684 MSR_IA32_MISC_ENABLE,
685};
686
b69e8cae 687static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 688{
b69e8cae
RJ		 689 if (efer & efer_reserved_bits)
690 return 1;
15c4a640
CO		 691
692 if (is_paging(vcpu)
b69e8cae
RJ		 693 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
694 return 1;
15c4a640 695
1b2fd70c
AG		 696 if (efer & EFER_FFXSR) {
697 struct kvm_cpuid_entry2 *feat;
698
699 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 700 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
701 return 1;
1b2fd70c
AG		 702 }
703
d8017474
AG		 704 if (efer & EFER_SVME) {
705 struct kvm_cpuid_entry2 *feat;
706
707 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 708 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
709 return 1;
d8017474
AG		 710 }
711
15c4a640 712 efer &= ~EFER_LMA;
f6801dff 713 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 714
a3d204e2
SY		 715 kvm_x86_ops->set_efer(vcpu, efer);
716
f6801dff 717 vcpu->arch.efer = efer;
9645bb56
AK		 718
719 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
720 kvm_mmu_reset_context(vcpu);
b69e8cae
RJ		 721
722 return 0;
15c4a640
CO		 723}
724
f2b4b7dd
JR		 725void kvm_enable_efer_bits(u64 mask)
726{
727 efer_reserved_bits &= ~mask;
728}
729EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
730
731
15c4a640
CO		 732/*
733 * Writes msr value into into the appropriate "register".
734 * Returns 0 on success, non-0 otherwise.
735 * Assumes vcpu_load() was already called.
736 */
737int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
738{
739 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
740}
741
313a3dc7
CO		 742/*
743 * Adapt set_msr() to msr_io()'s calling convention
744 */
745static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
746{
747 return kvm_set_msr(vcpu, index, *data);
748}
749
18068523
GOC		 750static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
751{
9ed3c444
AK		 752 int version;
753 int r;
50d0a0f9 754 struct pvclock_wall_clock wc;
923de3cf 755 struct timespec boot;
18068523
GOC		 756
757 if (!wall_clock)
758 return;
759
9ed3c444
AK		 760 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
761 if (r)
762 return;
763
764 if (version & 1)
765 ++version; /* first time write, random junk */
766
767 ++version;
18068523 768
18068523
GOC		 769 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
770
50d0a0f9
GH		 771 /*
772 * The guest calculates current wall clock time by adding
773 * system time (updated by kvm_write_guest_time below) to the
774 * wall clock specified here. guest system time equals host
775 * system time for us, thus we must fill in host boot time here.
776 */
923de3cf 777 getboottime(&boot);
50d0a0f9
GH		 778
779 wc.sec = boot.tv_sec;
780 wc.nsec = boot.tv_nsec;
781 wc.version = version;
18068523
GOC		 782
783 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
784
785 version++;
786 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 787}
788
50d0a0f9
GH		 789static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
790{
791 uint32_t quotient, remainder;
792
793 /* Don't try to replace with do_div(), this one calculates
794 * "(dividend << 32) / divisor" */
795 __asm__ ( "divl %4"
796 : "=a" (quotient), "=d" (remainder)
797 : "0" (0), "1" (dividend), "r" (divisor) );
798 return quotient;
799}
800
801static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
802{
803 uint64_t nsecs = 1000000000LL;
804 int32_t shift = 0;
805 uint64_t tps64;
806 uint32_t tps32;
807
808 tps64 = tsc_khz * 1000LL;
809 while (tps64 > nsecs*2) {
810 tps64 >>= 1;
811 shift--;
812 }
813
814 tps32 = (uint32_t)tps64;
815 while (tps32 <= (uint32_t)nsecs) {
816 tps32 <<= 1;
817 shift++;
818 }
819
820 hv_clock->tsc_shift = shift;
821 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
822
823 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 824 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 825 hv_clock->tsc_to_system_mul);
826}
827
c8076604
GH		 828static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
829
18068523
GOC		 830static void kvm_write_guest_time(struct kvm_vcpu *v)
831{
832 struct timespec ts;
833 unsigned long flags;
834 struct kvm_vcpu_arch *vcpu = &v->arch;
835 void *shared_kaddr;
463656c0 836 unsigned long this_tsc_khz;
18068523
GOC		 837
838 if ((!vcpu->time_page))
839 return;
840
463656c0
AK		 841 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
842 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
843 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
844 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 845 }
463656c0 846 put_cpu_var(cpu_tsc_khz);
50d0a0f9 847
18068523
GOC		 848 /* Keep irq disabled to prevent changes to the clock */
849 local_irq_save(flags);
af24a4e4 850 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 851 ktime_get_ts(&ts);
923de3cf 852 monotonic_to_bootbased(&ts);
18068523
GOC		 853 local_irq_restore(flags);
854
855 /* With all the info we got, fill in the values */
856
857 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 858 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
859
371bcf64
GC		 860 vcpu->hv_clock.flags = 0;
861
18068523
GOC		 862 /*
863 * The interface expects us to write an even number signaling that the
864 * update is finished. Since the guest won't see the intermediate
50d0a0f9 865 * state, we just increase by 2 at the end.
18068523 866 */
50d0a0f9 867 vcpu->hv_clock.version += 2;
18068523
GOC		 868
869 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
870
871 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 872 sizeof(vcpu->hv_clock));
18068523
GOC		 873
874 kunmap_atomic(shared_kaddr, KM_USER0);
875
876 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
877}
878
c8076604
GH		 879static int kvm_request_guest_time_update(struct kvm_vcpu *v)
880{
881 struct kvm_vcpu_arch *vcpu = &v->arch;
882
883 if (!vcpu->time_page)
884 return 0;
885 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
886 return 1;
887}
888
9ba075a6
AK		 889static bool msr_mtrr_valid(unsigned msr)
890{
891 switch (msr) {
892 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
893 case MSR_MTRRfix64K_00000:
894 case MSR_MTRRfix16K_80000:
895 case MSR_MTRRfix16K_A0000:
896 case MSR_MTRRfix4K_C0000:
897 case MSR_MTRRfix4K_C8000:
898 case MSR_MTRRfix4K_D0000:
899 case MSR_MTRRfix4K_D8000:
900 case MSR_MTRRfix4K_E0000:
901 case MSR_MTRRfix4K_E8000:
902 case MSR_MTRRfix4K_F0000:
903 case MSR_MTRRfix4K_F8000:
904 case MSR_MTRRdefType:
905 case MSR_IA32_CR_PAT:
906 return true;
907 case 0x2f8:
908 return true;
909 }
910 return false;
911}
912
d6289b93
MT		 913static bool valid_pat_type(unsigned t)
914{
915 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
916}
917
918static bool valid_mtrr_type(unsigned t)
919{
920 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
921}
922
923static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
924{
925 int i;
926
927 if (!msr_mtrr_valid(msr))
928 return false;
929
930 if (msr == MSR_IA32_CR_PAT) {
931 for (i = 0; i < 8; i++)
932 if (!valid_pat_type((data >> (i * 8)) & 0xff))
933 return false;
934 return true;
935 } else if (msr == MSR_MTRRdefType) {
936 if (data & ~0xcff)
937 return false;
938 return valid_mtrr_type(data & 0xff);
939 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
940 for (i = 0; i < 8 ; i++)
941 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
942 return false;
943 return true;
944 }
945
946 /* variable MTRRs */
947 return valid_mtrr_type(data & 0xff);
948}
949
9ba075a6
AK		 950static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
951{
0bed3b56
SY		 952 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
953
d6289b93 954 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 955 return 1;
956
0bed3b56
SY		 957 if (msr == MSR_MTRRdefType) {
958 vcpu->arch.mtrr_state.def_type = data;
959 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
960 } else if (msr == MSR_MTRRfix64K_00000)
961 p[0] = data;
962 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
963 p[1 + msr - MSR_MTRRfix16K_80000] = data;
964 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
965 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
966 else if (msr == MSR_IA32_CR_PAT)
967 vcpu->arch.pat = data;
968 else { /* Variable MTRRs */
969 int idx, is_mtrr_mask;
970 u64 *pt;
971
972 idx = (msr - 0x200) / 2;
973 is_mtrr_mask = msr - 0x200 - 2 * idx;
974 if (!is_mtrr_mask)
975 pt =
976 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
977 else
978 pt =
979 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
980 *pt = data;
981 }
982
983 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 984 return 0;
985}
15c4a640 986
890ca9ae 987static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 988{
890ca9ae
HY		 989 u64 mcg_cap = vcpu->arch.mcg_cap;
990 unsigned bank_num = mcg_cap & 0xff;
991
15c4a640 992 switch (msr) {
15c4a640 993 case MSR_IA32_MCG_STATUS:
890ca9ae 994 vcpu->arch.mcg_status = data;
15c4a640 995 break;
c7ac679c 996 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 997 if (!(mcg_cap & MCG_CTL_P))
998 return 1;
999 if (data != 0 && data != ~(u64)0)
1000 return -1;
1001 vcpu->arch.mcg_ctl = data;
1002 break;
1003 default:
1004 if (msr >= MSR_IA32_MC0_CTL &&
1005 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1006 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1007 /* only 0 or all 1s can be written to IA32_MCi_CTL
1008 * some Linux kernels though clear bit 10 in bank 4 to
1009 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1010 * this to avoid an uncatched #GP in the guest
1011 */
890ca9ae 1012 if ((offset & 0x3) == 0 &&
114be429 1013 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1014 return -1;
1015 vcpu->arch.mce_banks[offset] = data;
1016 break;
1017 }
1018 return 1;
1019 }
1020 return 0;
1021}
1022
ffde22ac
ES		 1023static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1024{
1025 struct kvm *kvm = vcpu->kvm;
1026 int lm = is_long_mode(vcpu);
1027 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1028 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1029 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1030 : kvm->arch.xen_hvm_config.blob_size_32;
1031 u32 page_num = data & ~PAGE_MASK;
1032 u64 page_addr = data & PAGE_MASK;
1033 u8 *page;
1034 int r;
1035
1036 r = -E2BIG;
1037 if (page_num >= blob_size)
1038 goto out;
1039 r = -ENOMEM;
1040 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1041 if (!page)
1042 goto out;
1043 r = -EFAULT;
1044 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1045 goto out_free;
1046 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1047 goto out_free;
1048 r = 0;
1049out_free:
1050 kfree(page);
1051out:
1052 return r;
1053}
1054
55cd8e5a
GN		 1055static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1056{
1057 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1058}
1059
1060static bool kvm_hv_msr_partition_wide(u32 msr)
1061{
1062 bool r = false;
1063 switch (msr) {
1064 case HV_X64_MSR_GUEST_OS_ID:
1065 case HV_X64_MSR_HYPERCALL:
1066 r = true;
1067 break;
1068 }
1069
1070 return r;
1071}
1072
1073static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1074{
1075 struct kvm *kvm = vcpu->kvm;
1076
1077 switch (msr) {
1078 case HV_X64_MSR_GUEST_OS_ID:
1079 kvm->arch.hv_guest_os_id = data;
1080 /* setting guest os id to zero disables hypercall page */
1081 if (!kvm->arch.hv_guest_os_id)
1082 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1083 break;
1084 case HV_X64_MSR_HYPERCALL: {
1085 u64 gfn;
1086 unsigned long addr;
1087 u8 instructions[4];
1088
1089 /* if guest os id is not set hypercall should remain disabled */
1090 if (!kvm->arch.hv_guest_os_id)
1091 break;
1092 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1093 kvm->arch.hv_hypercall = data;
1094 break;
1095 }
1096 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1097 addr = gfn_to_hva(kvm, gfn);
1098 if (kvm_is_error_hva(addr))
1099 return 1;
1100 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1101 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1102 if (copy_to_user((void __user *)addr, instructions, 4))
1103 return 1;
1104 kvm->arch.hv_hypercall = data;
1105 break;
1106 }
1107 default:
1108 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1109 "data 0x%llx\n", msr, data);
1110 return 1;
1111 }
1112 return 0;
1113}
1114
1115static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1116{
10388a07
GN		 1117 switch (msr) {
1118 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1119 unsigned long addr;
55cd8e5a 1120
10388a07
GN		 1121 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1122 vcpu->arch.hv_vapic = data;
1123 break;
1124 }
1125 addr = gfn_to_hva(vcpu->kvm, data >>
1126 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1127 if (kvm_is_error_hva(addr))
1128 return 1;
1129 if (clear_user((void __user *)addr, PAGE_SIZE))
1130 return 1;
1131 vcpu->arch.hv_vapic = data;
1132 break;
1133 }
1134 case HV_X64_MSR_EOI:
1135 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1136 case HV_X64_MSR_ICR:
1137 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1138 case HV_X64_MSR_TPR:
1139 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1140 default:
1141 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1142 "data 0x%llx\n", msr, data);
1143 return 1;
1144 }
1145
1146 return 0;
55cd8e5a
GN		 1147}
1148
15c4a640
CO		 1149int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1150{
1151 switch (msr) {
15c4a640 1152 case MSR_EFER:
b69e8cae 1153 return set_efer(vcpu, data);
8f1589d9
AP		 1154 case MSR_K7_HWCR:
1155 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1156 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1157 if (data != 0) {
1158 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1159 data);
1160 return 1;
1161 }
15c4a640 1162 break;
f7c6d140
AP		 1163 case MSR_FAM10H_MMIO_CONF_BASE:
1164 if (data != 0) {
1165 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1166 "0x%llx\n", data);
1167 return 1;
1168 }
15c4a640 1169 break;
c323c0e5 1170 case MSR_AMD64_NB_CFG:
c7ac679c 1171 break;
b5e2fec0
AG		 1172 case MSR_IA32_DEBUGCTLMSR:
1173 if (!data) {
1174 /* We support the non-activated case already */
1175 break;
1176 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1177 /* Values other than LBR and BTF are vendor-specific,
1178 thus reserved and should throw a #GP */
1179 return 1;
1180 }
1181 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1182 __func__, data);
1183 break;
15c4a640
CO		 1184 case MSR_IA32_UCODE_REV:
1185 case MSR_IA32_UCODE_WRITE:
61a6bd67 1186 case MSR_VM_HSAVE_PA:
6098ca93 1187 case MSR_AMD64_PATCH_LOADER:
15c4a640 1188 break;
9ba075a6
AK		 1189 case 0x200 ... 0x2ff:
1190 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1191 case MSR_IA32_APICBASE:
1192 kvm_set_apic_base(vcpu, data);
1193 break;
0105d1a5
GN		 1194 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1195 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1196 case MSR_IA32_MISC_ENABLE:
ad312c7c 1197 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1198 break;
11c6bffa 1199 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1200 case MSR_KVM_WALL_CLOCK:
1201 vcpu->kvm->arch.wall_clock = data;
1202 kvm_write_wall_clock(vcpu->kvm, data);
1203 break;
11c6bffa 1204 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1205 case MSR_KVM_SYSTEM_TIME: {
1206 if (vcpu->arch.time_page) {
1207 kvm_release_page_dirty(vcpu->arch.time_page);
1208 vcpu->arch.time_page = NULL;
1209 }
1210
1211 vcpu->arch.time = data;
1212
1213 /* we verify if the enable bit is set... */
1214 if (!(data & 1))
1215 break;
1216
1217 /* ...but clean it before doing the actual write */
1218 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1219
18068523
GOC		 1220 vcpu->arch.time_page =
1221 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1222
1223 if (is_error_page(vcpu->arch.time_page)) {
1224 kvm_release_page_clean(vcpu->arch.time_page);
1225 vcpu->arch.time_page = NULL;
1226 }
1227
c8076604 1228 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1229 break;
1230 }
890ca9ae
HY		 1231 case MSR_IA32_MCG_CTL:
1232 case MSR_IA32_MCG_STATUS:
1233 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1234 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1235
1236 /* Performance counters are not protected by a CPUID bit,
1237 * so we should check all of them in the generic path for the sake of
1238 * cross vendor migration.
1239 * Writing a zero into the event select MSRs disables them,
1240 * which we perfectly emulate ;-). Any other value should be at least
1241 * reported, some guests depend on them.
1242 */
1243 case MSR_P6_EVNTSEL0:
1244 case MSR_P6_EVNTSEL1:
1245 case MSR_K7_EVNTSEL0:
1246 case MSR_K7_EVNTSEL1:
1247 case MSR_K7_EVNTSEL2:
1248 case MSR_K7_EVNTSEL3:
1249 if (data != 0)
1250 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1251 "0x%x data 0x%llx\n", msr, data);
1252 break;
1253 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1254 * so we ignore writes to make it happy.
1255 */
1256 case MSR_P6_PERFCTR0:
1257 case MSR_P6_PERFCTR1:
1258 case MSR_K7_PERFCTR0:
1259 case MSR_K7_PERFCTR1:
1260 case MSR_K7_PERFCTR2:
1261 case MSR_K7_PERFCTR3:
1262 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1263 "0x%x data 0x%llx\n", msr, data);
1264 break;
55cd8e5a
GN		 1265 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1266 if (kvm_hv_msr_partition_wide(msr)) {
1267 int r;
1268 mutex_lock(&vcpu->kvm->lock);
1269 r = set_msr_hyperv_pw(vcpu, msr, data);
1270 mutex_unlock(&vcpu->kvm->lock);
1271 return r;
1272 } else
1273 return set_msr_hyperv(vcpu, msr, data);
1274 break;
15c4a640 1275 default:
ffde22ac
ES		 1276 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1277 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1278 if (!ignore_msrs) {
1279 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1280 msr, data);
1281 return 1;
1282 } else {
1283 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1284 msr, data);
1285 break;
1286 }
15c4a640
CO		 1287 }
1288 return 0;
1289}
1290EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1291
1292
1293/*
1294 * Reads an msr value (of 'msr_index') into 'pdata'.
1295 * Returns 0 on success, non-0 otherwise.
1296 * Assumes vcpu_load() was already called.
1297 */
1298int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1299{
1300 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1301}
1302
9ba075a6
AK		 1303static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1304{
0bed3b56
SY		 1305 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1306
9ba075a6
AK		 1307 if (!msr_mtrr_valid(msr))
1308 return 1;
1309
0bed3b56
SY		 1310 if (msr == MSR_MTRRdefType)
1311 *pdata = vcpu->arch.mtrr_state.def_type +
1312 (vcpu->arch.mtrr_state.enabled << 10);
1313 else if (msr == MSR_MTRRfix64K_00000)
1314 *pdata = p[0];
1315 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1316 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1317 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1318 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1319 else if (msr == MSR_IA32_CR_PAT)
1320 *pdata = vcpu->arch.pat;
1321 else { /* Variable MTRRs */
1322 int idx, is_mtrr_mask;
1323 u64 *pt;
1324
1325 idx = (msr - 0x200) / 2;
1326 is_mtrr_mask = msr - 0x200 - 2 * idx;
1327 if (!is_mtrr_mask)
1328 pt =
1329 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1330 else
1331 pt =
1332 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1333 *pdata = *pt;
1334 }
1335
9ba075a6
AK		 1336 return 0;
1337}
1338
890ca9ae 1339static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1340{
1341 u64 data;
890ca9ae
HY		 1342 u64 mcg_cap = vcpu->arch.mcg_cap;
1343 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1344
1345 switch (msr) {
15c4a640
CO		 1346 case MSR_IA32_P5_MC_ADDR:
1347 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1348 data = 0;
1349 break;
15c4a640 1350 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1351 data = vcpu->arch.mcg_cap;
1352 break;
c7ac679c 1353 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1354 if (!(mcg_cap & MCG_CTL_P))
1355 return 1;
1356 data = vcpu->arch.mcg_ctl;
1357 break;
1358 case MSR_IA32_MCG_STATUS:
1359 data = vcpu->arch.mcg_status;
1360 break;
1361 default:
1362 if (msr >= MSR_IA32_MC0_CTL &&
1363 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1364 u32 offset = msr - MSR_IA32_MC0_CTL;
1365 data = vcpu->arch.mce_banks[offset];
1366 break;
1367 }
1368 return 1;
1369 }
1370 *pdata = data;
1371 return 0;
1372}
1373
55cd8e5a
GN		 1374static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1375{
1376 u64 data = 0;
1377 struct kvm *kvm = vcpu->kvm;
1378
1379 switch (msr) {
1380 case HV_X64_MSR_GUEST_OS_ID:
1381 data = kvm->arch.hv_guest_os_id;
1382 break;
1383 case HV_X64_MSR_HYPERCALL:
1384 data = kvm->arch.hv_hypercall;
1385 break;
1386 default:
1387 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1388 return 1;
1389 }
1390
1391 *pdata = data;
1392 return 0;
1393}
1394
1395static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1396{
1397 u64 data = 0;
1398
1399 switch (msr) {
1400 case HV_X64_MSR_VP_INDEX: {
1401 int r;
1402 struct kvm_vcpu *v;
1403 kvm_for_each_vcpu(r, v, vcpu->kvm)
1404 if (v == vcpu)
1405 data = r;
1406 break;
1407 }
10388a07
GN		 1408 case HV_X64_MSR_EOI:
1409 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1410 case HV_X64_MSR_ICR:
1411 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1412 case HV_X64_MSR_TPR:
1413 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1414 default:
1415 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1416 return 1;
1417 }
1418 *pdata = data;
1419 return 0;
1420}
1421
890ca9ae
HY		 1422int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1423{
1424 u64 data;
1425
1426 switch (msr) {
890ca9ae 1427 case MSR_IA32_PLATFORM_ID:
15c4a640 1428 case MSR_IA32_UCODE_REV:
15c4a640 1429 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1430 case MSR_IA32_DEBUGCTLMSR:
1431 case MSR_IA32_LASTBRANCHFROMIP:
1432 case MSR_IA32_LASTBRANCHTOIP:
1433 case MSR_IA32_LASTINTFROMIP:
1434 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1435 case MSR_K8_SYSCFG:
1436 case MSR_K7_HWCR:
61a6bd67 1437 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1438 case MSR_P6_PERFCTR0:
1439 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1440 case MSR_P6_EVNTSEL0:
1441 case MSR_P6_EVNTSEL1:
9e699624 1442 case MSR_K7_EVNTSEL0:
1f3ee616 1443 case MSR_K7_PERFCTR0:
1fdbd48c 1444 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1445 case MSR_AMD64_NB_CFG:
f7c6d140 1446 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1447 data = 0;
1448 break;
9ba075a6
AK		 1449 case MSR_MTRRcap:
1450 data = 0x500 | KVM_NR_VAR_MTRR;
1451 break;
1452 case 0x200 ... 0x2ff:
1453 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1454 case 0xcd: /* fsb frequency */
1455 data = 3;
1456 break;
1457 case MSR_IA32_APICBASE:
1458 data = kvm_get_apic_base(vcpu);
1459 break;
0105d1a5
GN		 1460 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1461 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1462 break;
15c4a640 1463 case MSR_IA32_MISC_ENABLE:
ad312c7c 1464 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1465 break;
847f0ad8
AG		 1466 case MSR_IA32_PERF_STATUS:
1467 /* TSC increment by tick */
1468 data = 1000ULL;
1469 /* CPU multiplier */
1470 data |= (((uint64_t)4ULL) << 40);
1471 break;
15c4a640 1472 case MSR_EFER:
f6801dff 1473 data = vcpu->arch.efer;
15c4a640 1474 break;
18068523 1475 case MSR_KVM_WALL_CLOCK:
11c6bffa 1476 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1477 data = vcpu->kvm->arch.wall_clock;
1478 break;
1479 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1480 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1481 data = vcpu->arch.time;
1482 break;
890ca9ae
HY		 1483 case MSR_IA32_P5_MC_ADDR:
1484 case MSR_IA32_P5_MC_TYPE:
1485 case MSR_IA32_MCG_CAP:
1486 case MSR_IA32_MCG_CTL:
1487 case MSR_IA32_MCG_STATUS:
1488 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1489 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1490 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1491 if (kvm_hv_msr_partition_wide(msr)) {
1492 int r;
1493 mutex_lock(&vcpu->kvm->lock);
1494 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1495 mutex_unlock(&vcpu->kvm->lock);
1496 return r;
1497 } else
1498 return get_msr_hyperv(vcpu, msr, pdata);
1499 break;
15c4a640 1500 default:
ed85c068
AP		 1501 if (!ignore_msrs) {
1502 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1503 return 1;
1504 } else {
1505 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1506 data = 0;
1507 }
1508 break;
15c4a640
CO		 1509 }
1510 *pdata = data;
1511 return 0;
1512}
1513EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1514
313a3dc7
CO		 1515/*
1516 * Read or write a bunch of msrs. All parameters are kernel addresses.
1517 *
1518 * @return number of msrs set successfully.
1519 */
1520static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1521 struct kvm_msr_entry *entries,
1522 int (*do_msr)(struct kvm_vcpu *vcpu,
1523 unsigned index, u64 *data))
1524{
f656ce01 1525 int i, idx;
313a3dc7
CO		 1526
1527 vcpu_load(vcpu);
1528
f656ce01 1529 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1530 for (i = 0; i < msrs->nmsrs; ++i)
1531 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1532 break;
f656ce01 1533 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7
CO		 1534
1535 vcpu_put(vcpu);
1536
1537 return i;
1538}
1539
1540/*
1541 * Read or write a bunch of msrs. Parameters are user addresses.
1542 *
1543 * @return number of msrs set successfully.
1544 */
1545static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1546 int (*do_msr)(struct kvm_vcpu *vcpu,
1547 unsigned index, u64 *data),
1548 int writeback)
1549{
1550 struct kvm_msrs msrs;
1551 struct kvm_msr_entry *entries;
1552 int r, n;
1553 unsigned size;
1554
1555 r = -EFAULT;
1556 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1557 goto out;
1558
1559 r = -E2BIG;
1560 if (msrs.nmsrs >= MAX_IO_MSRS)
1561 goto out;
1562
1563 r = -ENOMEM;
1564 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1565 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1566 if (!entries)
1567 goto out;
1568
1569 r = -EFAULT;
1570 if (copy_from_user(entries, user_msrs->entries, size))
1571 goto out_free;
1572
1573 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1574 if (r < 0)
1575 goto out_free;
1576
1577 r = -EFAULT;
1578 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1579 goto out_free;
1580
1581 r = n;
1582
1583out_free:
7a73c028 1584 kfree(entries);
313a3dc7
CO		 1585out:
1586 return r;
1587}
1588
018d00d2
ZX		 1589int kvm_dev_ioctl_check_extension(long ext)
1590{
1591 int r;
1592
1593 switch (ext) {
1594 case KVM_CAP_IRQCHIP:
1595 case KVM_CAP_HLT:
1596 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1597 case KVM_CAP_SET_TSS_ADDR:
07716717 1598 case KVM_CAP_EXT_CPUID:
c8076604 1599 case KVM_CAP_CLOCKSOURCE:
7837699f 1600 case KVM_CAP_PIT:
a28e4f5a 1601 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1602 case KVM_CAP_MP_STATE:
ed848624 1603 case KVM_CAP_SYNC_MMU:
52d939a0 1604 case KVM_CAP_REINJECT_CONTROL:
4925663a 1605 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1606 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1607 case KVM_CAP_IRQFD:
d34e6b17 1608 case KVM_CAP_IOEVENTFD:
c5ff41ce 1609 case KVM_CAP_PIT2:
e9f42757 1610 case KVM_CAP_PIT_STATE2:
b927a3ce 1611 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1612 case KVM_CAP_XEN_HVM:
afbcf7ab 1613 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1614 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1615 case KVM_CAP_HYPERV:
10388a07 1616 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1617 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1618 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1619 case KVM_CAP_DEBUGREGS:
d2be1651 1620 case KVM_CAP_X86_ROBUST_SINGLESTEP:
018d00d2
ZX		 1621 r = 1;
1622 break;
542472b5
LV		 1623 case KVM_CAP_COALESCED_MMIO:
1624 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1625 break;
774ead3a
AK		 1626 case KVM_CAP_VAPIC:
1627 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1628 break;
f725230a
AK		 1629 case KVM_CAP_NR_VCPUS:
1630 r = KVM_MAX_VCPUS;
1631 break;
a988b910
AK		 1632 case KVM_CAP_NR_MEMSLOTS:
1633 r = KVM_MEMORY_SLOTS;
1634 break;
a68a6a72
MT		 1635 case KVM_CAP_PV_MMU: /* obsolete */
1636 r = 0;
2f333bcb 1637 break;
62c476c7 1638 case KVM_CAP_IOMMU:
19de40a8 1639 r = iommu_found();
62c476c7 1640 break;
890ca9ae
HY		 1641 case KVM_CAP_MCE:
1642 r = KVM_MAX_MCE_BANKS;
1643 break;
018d00d2
ZX		 1644 default:
1645 r = 0;
1646 break;
1647 }
1648 return r;
1649
1650}
1651
043405e1
CO		 1652long kvm_arch_dev_ioctl(struct file *filp,
1653 unsigned int ioctl, unsigned long arg)
1654{
1655 void __user *argp = (void __user *)arg;
1656 long r;
1657
1658 switch (ioctl) {
1659 case KVM_GET_MSR_INDEX_LIST: {
1660 struct kvm_msr_list __user *user_msr_list = argp;
1661 struct kvm_msr_list msr_list;
1662 unsigned n;
1663
1664 r = -EFAULT;
1665 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1666 goto out;
1667 n = msr_list.nmsrs;
1668 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1669 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1670 goto out;
1671 r = -E2BIG;
e125e7b6 1672 if (n < msr_list.nmsrs)
043405e1
CO		 1673 goto out;
1674 r = -EFAULT;
1675 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1676 num_msrs_to_save * sizeof(u32)))
1677 goto out;
e125e7b6 1678 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1679 &emulated_msrs,
1680 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1681 goto out;
1682 r = 0;
1683 break;
1684 }
674eea0f
AK		 1685 case KVM_GET_SUPPORTED_CPUID: {
1686 struct kvm_cpuid2 __user *cpuid_arg = argp;
1687 struct kvm_cpuid2 cpuid;
1688
1689 r = -EFAULT;
1690 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1691 goto out;
1692 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1693 cpuid_arg->entries);
674eea0f
AK		 1694 if (r)
1695 goto out;
1696
1697 r = -EFAULT;
1698 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1699 goto out;
1700 r = 0;
1701 break;
1702 }
890ca9ae
HY		 1703 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1704 u64 mce_cap;
1705
1706 mce_cap = KVM_MCE_CAP_SUPPORTED;
1707 r = -EFAULT;
1708 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1709 goto out;
1710 r = 0;
1711 break;
1712 }
043405e1
CO		 1713 default:
1714 r = -EINVAL;
1715 }
1716out:
1717 return r;
1718}
1719
313a3dc7
CO		 1720void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1721{
1722 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1723 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1724 unsigned long khz = cpufreq_quick_get(cpu);
1725 if (!khz)
1726 khz = tsc_khz;
1727 per_cpu(cpu_tsc_khz, cpu) = khz;
1728 }
c8076604 1729 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1730}
1731
1732void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1733{
9327fd11 1734 kvm_put_guest_fpu(vcpu);
02daab21 1735 kvm_x86_ops->vcpu_put(vcpu);
313a3dc7
CO		 1736}
1737
07716717 1738static int is_efer_nx(void)
313a3dc7 1739{
e286e86e 1740 unsigned long long efer = 0;
313a3dc7 1741
e286e86e 1742 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1743 return efer & EFER_NX;
1744}
1745
1746static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1747{
1748 int i;
1749 struct kvm_cpuid_entry2 *e, *entry;
1750
313a3dc7 1751 entry = NULL;
ad312c7c
ZX		 1752 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1753 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1754 if (e->function == 0x80000001) {
1755 entry = e;
1756 break;
1757 }
1758 }
07716717 1759 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1760 entry->edx &= ~(1 << 20);
1761 printk(KERN_INFO "kvm: guest NX capability removed\n");
1762 }
1763}
1764
07716717 1765/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1766static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1767 struct kvm_cpuid *cpuid,
1768 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1769{
1770 int r, i;
1771 struct kvm_cpuid_entry *cpuid_entries;
1772
1773 r = -E2BIG;
1774 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1775 goto out;
1776 r = -ENOMEM;
1777 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1778 if (!cpuid_entries)
1779 goto out;
1780 r = -EFAULT;
1781 if (copy_from_user(cpuid_entries, entries,
1782 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1783 goto out_free;
fe19c5a4 1784 vcpu_load(vcpu);
07716717 1785 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1786 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1787 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1788 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1789 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1790 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1791 vcpu->arch.cpuid_entries[i].index = 0;
1792 vcpu->arch.cpuid_entries[i].flags = 0;
1793 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1794 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1795 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1796 }
1797 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1798 cpuid_fix_nx_cap(vcpu);
1799 r = 0;
fc61b800 1800 kvm_apic_set_version(vcpu);
0e851880 1801 kvm_x86_ops->cpuid_update(vcpu);
fe19c5a4 1802 vcpu_put(vcpu);
07716717
DK		 1803
1804out_free:
1805 vfree(cpuid_entries);
1806out:
1807 return r;
1808}
1809
1810static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1811 struct kvm_cpuid2 *cpuid,
1812 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1813{
1814 int r;
1815
1816 r = -E2BIG;
1817 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1818 goto out;
1819 r = -EFAULT;
ad312c7c 1820 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1821 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1822 goto out;
fe19c5a4 1823 vcpu_load(vcpu);
ad312c7c 1824 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1825 kvm_apic_set_version(vcpu);
0e851880 1826 kvm_x86_ops->cpuid_update(vcpu);
fe19c5a4 1827 vcpu_put(vcpu);
313a3dc7
CO		 1828 return 0;
1829
1830out:
1831 return r;
1832}
1833
07716717 1834static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1835 struct kvm_cpuid2 *cpuid,
1836 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1837{
1838 int r;
1839
8fbf065d 1840 vcpu_load(vcpu);
07716717 1841 r = -E2BIG;
ad312c7c 1842 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1843 goto out;
1844 r = -EFAULT;
ad312c7c 1845 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1846 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1847 goto out;
1848 return 0;
1849
1850out:
ad312c7c 1851 cpuid->nent = vcpu->arch.cpuid_nent;
8fbf065d 1852 vcpu_put(vcpu);
07716717
DK		 1853 return r;
1854}
1855
07716717 1856static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1857 u32 index)
07716717
DK		 1858{
1859 entry->function = function;
1860 entry->index = index;
1861 cpuid_count(entry->function, entry->index,
19355475 1862 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1863 entry->flags = 0;
1864}
1865
7faa4ee1
AK		 1866#define F(x) bit(X86_FEATURE_##x)
1867
07716717
DK		 1868static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1869 u32 index, int *nent, int maxnent)
1870{
7faa4ee1 1871 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1872#ifdef CONFIG_X86_64
17cc3935
SY		 1873 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1874 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1875 unsigned f_lm = F(LM);
1876#else
17cc3935 1877 unsigned f_gbpages = 0;
7faa4ee1 1878 unsigned f_lm = 0;
07716717 1879#endif
4e47c7a6 1880 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1881
1882 /* cpuid 1.edx */
1883 const u32 kvm_supported_word0_x86_features =
1884 F(FPU) | F(VME) | F(DE) | F(PSE) |
1885 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1886 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1887 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1888 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1889 0 /* Reserved, DS, ACPI */ | F(MMX) |
1890 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1891 0 /* HTT, TM, Reserved, PBE */;
1892 /* cpuid 0x80000001.edx */
1893 const u32 kvm_supported_word1_x86_features =
1894 F(FPU) | F(VME) | F(DE) | F(PSE) |
1895 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1896 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1897 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1898 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1899 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1900 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1901 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1902 /* cpuid 1.ecx */
1903 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1904 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1905 0 /* DS-CPL, VMX, SMX, EST */ |
1906 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1907 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1908 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1909 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1910 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1911 /* cpuid 0x80000001.ecx */
07716717 1912 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1913 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1914 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1915 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1916 0 /* SKINIT */ | 0 /* WDT */;
07716717 1917
19355475 1918 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1919 get_cpu();
1920 do_cpuid_1_ent(entry, function, index);
1921 ++*nent;
1922
1923 switch (function) {
1924 case 0:
1925 entry->eax = min(entry->eax, (u32)0xb);
1926 break;
1927 case 1:
1928 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1929 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1930 /* we support x2apic emulation even if host does not support
1931 * it since we emulate x2apic in software */
1932 entry->ecx |= F(X2APIC);
07716717
DK		 1933 break;
1934 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1935 * may return different values. This forces us to get_cpu() before
1936 * issuing the first command, and also to emulate this annoying behavior
1937 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1938 case 2: {
1939 int t, times = entry->eax & 0xff;
1940
1941 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1942 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1943 for (t = 1; t < times && *nent < maxnent; ++t) {
1944 do_cpuid_1_ent(&entry[t], function, 0);
1945 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1946 ++*nent;
1947 }
1948 break;
1949 }
1950 /* function 4 and 0xb have additional index. */
1951 case 4: {
14af3f3c 1952 int i, cache_type;
07716717
DK		 1953
1954 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1955 /* read more entries until cache_type is zero */
14af3f3c
HH		 1956 for (i = 1; *nent < maxnent; ++i) {
1957 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1958 if (!cache_type)
1959 break;
14af3f3c
HH		 1960 do_cpuid_1_ent(&entry[i], function, i);
1961 entry[i].flags |=
07716717
DK		 1962 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1963 ++*nent;
1964 }
1965 break;
1966 }
1967 case 0xb: {
14af3f3c 1968 int i, level_type;
07716717
DK		 1969
1970 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1971 /* read more entries until level_type is zero */
14af3f3c 1972 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1973 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1974 if (!level_type)
1975 break;
14af3f3c
HH		 1976 do_cpuid_1_ent(&entry[i], function, i);
1977 entry[i].flags |=
07716717
DK		 1978 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1979 ++*nent;
1980 }
1981 break;
1982 }
84478c82
GC		 1983 case KVM_CPUID_SIGNATURE: {
1984 char signature[12] = "KVMKVMKVM\0\0";
1985 u32 *sigptr = (u32 *)signature;
1986 entry->eax = 0;
1987 entry->ebx = sigptr[0];
1988 entry->ecx = sigptr[1];
1989 entry->edx = sigptr[2];
1990 break;
1991 }
1992 case KVM_CPUID_FEATURES:
1993 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
1994 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 1995 (1 << KVM_FEATURE_CLOCKSOURCE2) |
1996 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 1997 entry->ebx = 0;
1998 entry->ecx = 0;
1999 entry->edx = 0;
2000 break;
07716717
DK		 2001 case 0x80000000:
2002 entry->eax = min(entry->eax, 0x8000001a);
2003 break;
2004 case 0x80000001:
2005 entry->edx &= kvm_supported_word1_x86_features;
2006 entry->ecx &= kvm_supported_word6_x86_features;
2007 break;
2008 }
d4330ef2
JR		 2009
2010 kvm_x86_ops->set_supported_cpuid(function, entry);
2011
07716717
DK		 2012 put_cpu();
2013}
2014
7faa4ee1
AK		 2015#undef F
2016
674eea0f 2017static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2018 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2019{
2020 struct kvm_cpuid_entry2 *cpuid_entries;
2021 int limit, nent = 0, r = -E2BIG;
2022 u32 func;
2023
2024 if (cpuid->nent < 1)
2025 goto out;
6a544355
AK		 2026 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2027 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2028 r = -ENOMEM;
2029 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2030 if (!cpuid_entries)
2031 goto out;
2032
2033 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2034 limit = cpuid_entries[0].eax;
2035 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2036 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2037 &nent, cpuid->nent);
07716717
DK		 2038 r = -E2BIG;
2039 if (nent >= cpuid->nent)
2040 goto out_free;
2041
2042 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2043 limit = cpuid_entries[nent - 1].eax;
2044 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2045 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2046 &nent, cpuid->nent);
84478c82
GC		 2047
2048
2049
2050 r = -E2BIG;
2051 if (nent >= cpuid->nent)
2052 goto out_free;
2053
2054 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2055 cpuid->nent);
2056
2057 r = -E2BIG;
2058 if (nent >= cpuid->nent)
2059 goto out_free;
2060
2061 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2062 cpuid->nent);
2063
cb007648
MM		 2064 r = -E2BIG;
2065 if (nent >= cpuid->nent)
2066 goto out_free;
2067
07716717
DK		 2068 r = -EFAULT;
2069 if (copy_to_user(entries, cpuid_entries,
19355475 2070 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2071 goto out_free;
2072 cpuid->nent = nent;
2073 r = 0;
2074
2075out_free:
2076 vfree(cpuid_entries);
2077out:
2078 return r;
2079}
2080
313a3dc7
CO		 2081static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2082 struct kvm_lapic_state *s)
2083{
2084 vcpu_load(vcpu);
ad312c7c 2085 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2086 vcpu_put(vcpu);
2087
2088 return 0;
2089}
2090
2091static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2092 struct kvm_lapic_state *s)
2093{
2094 vcpu_load(vcpu);
ad312c7c 2095 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2096 kvm_apic_post_state_restore(vcpu);
cb142eb7 2097 update_cr8_intercept(vcpu);
313a3dc7
CO		 2098 vcpu_put(vcpu);
2099
2100 return 0;
2101}
2102
f77bc6a4
ZX		 2103static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2104 struct kvm_interrupt *irq)
2105{
2106 if (irq->irq < 0 || irq->irq >= 256)
2107 return -EINVAL;
2108 if (irqchip_in_kernel(vcpu->kvm))
2109 return -ENXIO;
2110 vcpu_load(vcpu);
2111
66fd3f7f 2112 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 2113
2114 vcpu_put(vcpu);
2115
2116 return 0;
2117}
2118
c4abb7c9
JK		 2119static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2120{
2121 vcpu_load(vcpu);
2122 kvm_inject_nmi(vcpu);
2123 vcpu_put(vcpu);
2124
2125 return 0;
2126}
2127
b209749f
AK		 2128static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2129 struct kvm_tpr_access_ctl *tac)
2130{
2131 if (tac->flags)
2132 return -EINVAL;
2133 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2134 return 0;
2135}
2136
890ca9ae
HY		 2137static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2138 u64 mcg_cap)
2139{
2140 int r;
2141 unsigned bank_num = mcg_cap & 0xff, bank;
2142
8fbf065d 2143 vcpu_load(vcpu);
890ca9ae 2144 r = -EINVAL;
a9e38c3e 2145 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2146 goto out;
2147 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2148 goto out;
2149 r = 0;
2150 vcpu->arch.mcg_cap = mcg_cap;
2151 /* Init IA32_MCG_CTL to all 1s */
2152 if (mcg_cap & MCG_CTL_P)
2153 vcpu->arch.mcg_ctl = ~(u64)0;
2154 /* Init IA32_MCi_CTL to all 1s */
2155 for (bank = 0; bank < bank_num; bank++)
2156 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2157out:
8fbf065d 2158 vcpu_put(vcpu);
890ca9ae
HY		 2159 return r;
2160}
2161
2162static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2163 struct kvm_x86_mce *mce)
2164{
2165 u64 mcg_cap = vcpu->arch.mcg_cap;
2166 unsigned bank_num = mcg_cap & 0xff;
2167 u64 *banks = vcpu->arch.mce_banks;
2168
2169 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2170 return -EINVAL;
2171 /*
2172 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2173 * reporting is disabled
2174 */
2175 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2176 vcpu->arch.mcg_ctl != ~(u64)0)
2177 return 0;
2178 banks += 4 * mce->bank;
2179 /*
2180 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2181 * reporting is disabled for the bank
2182 */
2183 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2184 return 0;
2185 if (mce->status & MCI_STATUS_UC) {
2186 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2187 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2188 printk(KERN_DEBUG "kvm: set_mce: "
2189 "injects mce exception while "
2190 "previous one is in progress!\n");
2191 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2192 return 0;
2193 }
2194 if (banks[1] & MCI_STATUS_VAL)
2195 mce->status |= MCI_STATUS_OVER;
2196 banks[2] = mce->addr;
2197 banks[3] = mce->misc;
2198 vcpu->arch.mcg_status = mce->mcg_status;
2199 banks[1] = mce->status;
2200 kvm_queue_exception(vcpu, MC_VECTOR);
2201 } else if (!(banks[1] & MCI_STATUS_VAL)
2202 || !(banks[1] & MCI_STATUS_UC)) {
2203 if (banks[1] & MCI_STATUS_VAL)
2204 mce->status |= MCI_STATUS_OVER;
2205 banks[2] = mce->addr;
2206 banks[3] = mce->misc;
2207 banks[1] = mce->status;
2208 } else
2209 banks[1] |= MCI_STATUS_OVER;
2210 return 0;
2211}
2212
3cfc3092
JK		 2213static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2214 struct kvm_vcpu_events *events)
2215{
2216 vcpu_load(vcpu);
2217
03b82a30
JK		 2218 events->exception.injected =
2219 vcpu->arch.exception.pending &&
2220 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2221 events->exception.nr = vcpu->arch.exception.nr;
2222 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2223 events->exception.error_code = vcpu->arch.exception.error_code;
2224
03b82a30
JK		 2225 events->interrupt.injected =
2226 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2227 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2228 events->interrupt.soft = 0;
48005f64
JK		 2229 events->interrupt.shadow =
2230 kvm_x86_ops->get_interrupt_shadow(vcpu,
2231 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2232
2233 events->nmi.injected = vcpu->arch.nmi_injected;
2234 events->nmi.pending = vcpu->arch.nmi_pending;
2235 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2236
2237 events->sipi_vector = vcpu->arch.sipi_vector;
2238
dab4b911 2239 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2240 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2241 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2242
2243 vcpu_put(vcpu);
2244}
2245
2246static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2247 struct kvm_vcpu_events *events)
2248{
dab4b911 2249 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2250 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2251 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2252 return -EINVAL;
2253
2254 vcpu_load(vcpu);
2255
2256 vcpu->arch.exception.pending = events->exception.injected;
2257 vcpu->arch.exception.nr = events->exception.nr;
2258 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2259 vcpu->arch.exception.error_code = events->exception.error_code;
2260
2261 vcpu->arch.interrupt.pending = events->interrupt.injected;
2262 vcpu->arch.interrupt.nr = events->interrupt.nr;
2263 vcpu->arch.interrupt.soft = events->interrupt.soft;
2264 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2265 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2266 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2267 kvm_x86_ops->set_interrupt_shadow(vcpu,
2268 events->interrupt.shadow);
3cfc3092
JK		 2269
2270 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2271 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2272 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2273 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2274
dab4b911
JK		 2275 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2276 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 2277
2278 vcpu_put(vcpu);
2279
2280 return 0;
2281}
2282
a1efbe77
JK		 2283static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2284 struct kvm_debugregs *dbgregs)
2285{
2286 vcpu_load(vcpu);
2287
2288 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2289 dbgregs->dr6 = vcpu->arch.dr6;
2290 dbgregs->dr7 = vcpu->arch.dr7;
2291 dbgregs->flags = 0;
2292
2293 vcpu_put(vcpu);
2294}
2295
2296static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2297 struct kvm_debugregs *dbgregs)
2298{
2299 if (dbgregs->flags)
2300 return -EINVAL;
2301
2302 vcpu_load(vcpu);
2303
2304 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2305 vcpu->arch.dr6 = dbgregs->dr6;
2306 vcpu->arch.dr7 = dbgregs->dr7;
2307
2308 vcpu_put(vcpu);
2309
2310 return 0;
2311}
2312
313a3dc7
CO		 2313long kvm_arch_vcpu_ioctl(struct file *filp,
2314 unsigned int ioctl, unsigned long arg)
2315{
2316 struct kvm_vcpu *vcpu = filp->private_data;
2317 void __user *argp = (void __user *)arg;
2318 int r;
b772ff36 2319 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2320
2321 switch (ioctl) {
2322 case KVM_GET_LAPIC: {
2204ae3c
MT		 2323 r = -EINVAL;
2324 if (!vcpu->arch.apic)
2325 goto out;
b772ff36 2326 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2327
b772ff36
DH		 2328 r = -ENOMEM;
2329 if (!lapic)
2330 goto out;
2331 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2332 if (r)
2333 goto out;
2334 r = -EFAULT;
b772ff36 2335 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2336 goto out;
2337 r = 0;
2338 break;
2339 }
2340 case KVM_SET_LAPIC: {
2204ae3c
MT		 2341 r = -EINVAL;
2342 if (!vcpu->arch.apic)
2343 goto out;
b772ff36
DH		 2344 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2345 r = -ENOMEM;
2346 if (!lapic)
2347 goto out;
313a3dc7 2348 r = -EFAULT;
b772ff36 2349 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2350 goto out;
b772ff36 2351 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2352 if (r)
2353 goto out;
2354 r = 0;
2355 break;
2356 }
f77bc6a4
ZX		 2357 case KVM_INTERRUPT: {
2358 struct kvm_interrupt irq;
2359
2360 r = -EFAULT;
2361 if (copy_from_user(&irq, argp, sizeof irq))
2362 goto out;
2363 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2364 if (r)
2365 goto out;
2366 r = 0;
2367 break;
2368 }
c4abb7c9
JK		 2369 case KVM_NMI: {
2370 r = kvm_vcpu_ioctl_nmi(vcpu);
2371 if (r)
2372 goto out;
2373 r = 0;
2374 break;
2375 }
313a3dc7
CO		 2376 case KVM_SET_CPUID: {
2377 struct kvm_cpuid __user *cpuid_arg = argp;
2378 struct kvm_cpuid cpuid;
2379
2380 r = -EFAULT;
2381 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2382 goto out;
2383 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2384 if (r)
2385 goto out;
2386 break;
2387 }
07716717
DK		 2388 case KVM_SET_CPUID2: {
2389 struct kvm_cpuid2 __user *cpuid_arg = argp;
2390 struct kvm_cpuid2 cpuid;
2391
2392 r = -EFAULT;
2393 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2394 goto out;
2395 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2396 cpuid_arg->entries);
07716717
DK		 2397 if (r)
2398 goto out;
2399 break;
2400 }
2401 case KVM_GET_CPUID2: {
2402 struct kvm_cpuid2 __user *cpuid_arg = argp;
2403 struct kvm_cpuid2 cpuid;
2404
2405 r = -EFAULT;
2406 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2407 goto out;
2408 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2409 cpuid_arg->entries);
07716717
DK		 2410 if (r)
2411 goto out;
2412 r = -EFAULT;
2413 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2414 goto out;
2415 r = 0;
2416 break;
2417 }
313a3dc7
CO		 2418 case KVM_GET_MSRS:
2419 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2420 break;
2421 case KVM_SET_MSRS:
2422 r = msr_io(vcpu, argp, do_set_msr, 0);
2423 break;
b209749f
AK		 2424 case KVM_TPR_ACCESS_REPORTING: {
2425 struct kvm_tpr_access_ctl tac;
2426
2427 r = -EFAULT;
2428 if (copy_from_user(&tac, argp, sizeof tac))
2429 goto out;
2430 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2431 if (r)
2432 goto out;
2433 r = -EFAULT;
2434 if (copy_to_user(argp, &tac, sizeof tac))
2435 goto out;
2436 r = 0;
2437 break;
2438 };
b93463aa
AK		 2439 case KVM_SET_VAPIC_ADDR: {
2440 struct kvm_vapic_addr va;
2441
2442 r = -EINVAL;
2443 if (!irqchip_in_kernel(vcpu->kvm))
2444 goto out;
2445 r = -EFAULT;
2446 if (copy_from_user(&va, argp, sizeof va))
2447 goto out;
2448 r = 0;
2449 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2450 break;
2451 }
890ca9ae
HY		 2452 case KVM_X86_SETUP_MCE: {
2453 u64 mcg_cap;
2454
2455 r = -EFAULT;
2456 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2457 goto out;
2458 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2459 break;
2460 }
2461 case KVM_X86_SET_MCE: {
2462 struct kvm_x86_mce mce;
2463
2464 r = -EFAULT;
2465 if (copy_from_user(&mce, argp, sizeof mce))
2466 goto out;
8fbf065d 2467 vcpu_load(vcpu);
890ca9ae 2468 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
8fbf065d 2469 vcpu_put(vcpu);
890ca9ae
HY		 2470 break;
2471 }
3cfc3092
JK		 2472 case KVM_GET_VCPU_EVENTS: {
2473 struct kvm_vcpu_events events;
2474
2475 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2476
2477 r = -EFAULT;
2478 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2479 break;
2480 r = 0;
2481 break;
2482 }
2483 case KVM_SET_VCPU_EVENTS: {
2484 struct kvm_vcpu_events events;
2485
2486 r = -EFAULT;
2487 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2488 break;
2489
2490 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2491 break;
2492 }
a1efbe77
JK		 2493 case KVM_GET_DEBUGREGS: {
2494 struct kvm_debugregs dbgregs;
2495
2496 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2497
2498 r = -EFAULT;
2499 if (copy_to_user(argp, &dbgregs,
2500 sizeof(struct kvm_debugregs)))
2501 break;
2502 r = 0;
2503 break;
2504 }
2505 case KVM_SET_DEBUGREGS: {
2506 struct kvm_debugregs dbgregs;
2507
2508 r = -EFAULT;
2509 if (copy_from_user(&dbgregs, argp,
2510 sizeof(struct kvm_debugregs)))
2511 break;
2512
2513 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2514 break;
2515 }
313a3dc7
CO		 2516 default:
2517 r = -EINVAL;
2518 }
2519out:
7a6ce84c 2520 kfree(lapic);
313a3dc7
CO		 2521 return r;
2522}
2523
1fe779f8
CO		 2524static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2525{
2526 int ret;
2527
2528 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2529 return -1;
2530 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2531 return ret;
2532}
2533
b927a3ce
SY		 2534static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2535 u64 ident_addr)
2536{
2537 kvm->arch.ept_identity_map_addr = ident_addr;
2538 return 0;
2539}
2540
1fe779f8
CO		 2541static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2542 u32 kvm_nr_mmu_pages)
2543{
2544 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2545 return -EINVAL;
2546
79fac95e 2547 mutex_lock(&kvm->slots_lock);
7c8a83b7 2548 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2549
2550 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2551 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2552
7c8a83b7 2553 spin_unlock(&kvm->mmu_lock);
79fac95e 2554 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2555 return 0;
2556}
2557
2558static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2559{
f05e70ac 2560 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2561}
2562
a983fb23
MT		 2563gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2564{
2565 int i;
2566 struct kvm_mem_alias *alias;
2567 struct kvm_mem_aliases *aliases;
2568
90d83dc3 2569 aliases = kvm_aliases(kvm);
a983fb23
MT		 2570
2571 for (i = 0; i < aliases->naliases; ++i) {
2572 alias = &aliases->aliases[i];
2573 if (alias->flags & KVM_ALIAS_INVALID)
2574 continue;
2575 if (gfn >= alias->base_gfn
2576 && gfn < alias->base_gfn + alias->npages)
2577 return alias->target_gfn + gfn - alias->base_gfn;
2578 }
2579 return gfn;
2580}
2581
e9f85cde
ZX		 2582gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2583{
2584 int i;
2585 struct kvm_mem_alias *alias;
a983fb23
MT		 2586 struct kvm_mem_aliases *aliases;
2587
90d83dc3 2588 aliases = kvm_aliases(kvm);
e9f85cde 2589
fef9cce0
MT		 2590 for (i = 0; i < aliases->naliases; ++i) {
2591 alias = &aliases->aliases[i];
e9f85cde
ZX		 2592 if (gfn >= alias->base_gfn
2593 && gfn < alias->base_gfn + alias->npages)
2594 return alias->target_gfn + gfn - alias->base_gfn;
2595 }
2596 return gfn;
2597}
2598
1fe779f8
CO		 2599/*
2600 * Set a new alias region. Aliases map a portion of physical memory into
2601 * another portion. This is useful for memory windows, for example the PC
2602 * VGA region.
2603 */
2604static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2605 struct kvm_memory_alias *alias)
2606{
2607 int r, n;
2608 struct kvm_mem_alias *p;
a983fb23 2609 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2610
2611 r = -EINVAL;
2612 /* General sanity checks */
2613 if (alias->memory_size & (PAGE_SIZE - 1))
2614 goto out;
2615 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2616 goto out;
2617 if (alias->slot >= KVM_ALIAS_SLOTS)
2618 goto out;
2619 if (alias->guest_phys_addr + alias->memory_size
2620 < alias->guest_phys_addr)
2621 goto out;
2622 if (alias->target_phys_addr + alias->memory_size
2623 < alias->target_phys_addr)
2624 goto out;
2625
a983fb23
MT		 2626 r = -ENOMEM;
2627 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2628 if (!aliases)
2629 goto out;
2630
79fac95e 2631 mutex_lock(&kvm->slots_lock);
1fe779f8 2632
a983fb23
MT		 2633 /* invalidate any gfn reference in case of deletion/shrinking */
2634 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2635 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2636 old_aliases = kvm->arch.aliases;
2637 rcu_assign_pointer(kvm->arch.aliases, aliases);
2638 synchronize_srcu_expedited(&kvm->srcu);
2639 kvm_mmu_zap_all(kvm);
2640 kfree(old_aliases);
2641
2642 r = -ENOMEM;
2643 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2644 if (!aliases)
2645 goto out_unlock;
2646
2647 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2648
2649 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2650 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2651 p->npages = alias->memory_size >> PAGE_SHIFT;
2652 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2653 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2654
2655 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2656 if (aliases->aliases[n - 1].npages)
1fe779f8 2657 break;
fef9cce0 2658 aliases->naliases = n;
1fe779f8 2659
a983fb23
MT		 2660 old_aliases = kvm->arch.aliases;
2661 rcu_assign_pointer(kvm->arch.aliases, aliases);
2662 synchronize_srcu_expedited(&kvm->srcu);
2663 kfree(old_aliases);
2664 r = 0;
1fe779f8 2665
a983fb23 2666out_unlock:
79fac95e 2667 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2668out:
2669 return r;
2670}
2671
2672static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2673{
2674 int r;
2675
2676 r = 0;
2677 switch (chip->chip_id) {
2678 case KVM_IRQCHIP_PIC_MASTER:
2679 memcpy(&chip->chip.pic,
2680 &pic_irqchip(kvm)->pics[0],
2681 sizeof(struct kvm_pic_state));
2682 break;
2683 case KVM_IRQCHIP_PIC_SLAVE:
2684 memcpy(&chip->chip.pic,
2685 &pic_irqchip(kvm)->pics[1],
2686 sizeof(struct kvm_pic_state));
2687 break;
2688 case KVM_IRQCHIP_IOAPIC:
eba0226b 2689 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2690 break;
2691 default:
2692 r = -EINVAL;
2693 break;
2694 }
2695 return r;
2696}
2697
2698static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2699{
2700 int r;
2701
2702 r = 0;
2703 switch (chip->chip_id) {
2704 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2705 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2706 memcpy(&pic_irqchip(kvm)->pics[0],
2707 &chip->chip.pic,
2708 sizeof(struct kvm_pic_state));
fa8273e9 2709 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2710 break;
2711 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2712 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2713 memcpy(&pic_irqchip(kvm)->pics[1],
2714 &chip->chip.pic,
2715 sizeof(struct kvm_pic_state));
fa8273e9 2716 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2717 break;
2718 case KVM_IRQCHIP_IOAPIC:
eba0226b 2719 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2720 break;
2721 default:
2722 r = -EINVAL;
2723 break;
2724 }
2725 kvm_pic_update_irq(pic_irqchip(kvm));
2726 return r;
2727}
2728
e0f63cb9
SY		 2729static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2730{
2731 int r = 0;
2732
894a9c55 2733 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2734 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2735 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2736 return r;
2737}
2738
2739static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2740{
2741 int r = 0;
2742
894a9c55 2743 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2744 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2745 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2746 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2747 return r;
2748}
2749
2750static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2751{
2752 int r = 0;
2753
2754 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2755 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2756 sizeof(ps->channels));
2757 ps->flags = kvm->arch.vpit->pit_state.flags;
2758 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2759 return r;
2760}
2761
2762static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2763{
2764 int r = 0, start = 0;
2765 u32 prev_legacy, cur_legacy;
2766 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2767 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2768 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2769 if (!prev_legacy && cur_legacy)
2770 start = 1;
2771 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2772 sizeof(kvm->arch.vpit->pit_state.channels));
2773 kvm->arch.vpit->pit_state.flags = ps->flags;
2774 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2775 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2776 return r;
2777}
2778
52d939a0
MT		 2779static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2780 struct kvm_reinject_control *control)
2781{
2782 if (!kvm->arch.vpit)
2783 return -ENXIO;
894a9c55 2784 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2785 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2786 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2787 return 0;
2788}
2789
5bb064dc
ZX		 2790/*
2791 * Get (and clear) the dirty memory log for a memory slot.
2792 */
2793int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2794 struct kvm_dirty_log *log)
2795{
87bf6e7d 2796 int r, i;
5bb064dc 2797 struct kvm_memory_slot *memslot;
87bf6e7d 2798 unsigned long n;
b050b015
MT		 2799 unsigned long is_dirty = 0;
2800 unsigned long *dirty_bitmap = NULL;
5bb064dc 2801
79fac95e 2802 mutex_lock(&kvm->slots_lock);
5bb064dc 2803
b050b015
MT		 2804 r = -EINVAL;
2805 if (log->slot >= KVM_MEMORY_SLOTS)
2806 goto out;
2807
2808 memslot = &kvm->memslots->memslots[log->slot];
2809 r = -ENOENT;
2810 if (!memslot->dirty_bitmap)
2811 goto out;
2812
87bf6e7d 2813 n = kvm_dirty_bitmap_bytes(memslot);
b050b015
MT		 2814
2815 r = -ENOMEM;
2816 dirty_bitmap = vmalloc(n);
2817 if (!dirty_bitmap)
5bb064dc 2818 goto out;
b050b015
MT		 2819 memset(dirty_bitmap, 0, n);
2820
2821 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2822 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2823
2824 /* If nothing is dirty, don't bother messing with page tables. */
2825 if (is_dirty) {
b050b015
MT		 2826 struct kvm_memslots *slots, *old_slots;
2827
7c8a83b7 2828 spin_lock(&kvm->mmu_lock);
5bb064dc 2829 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2830 spin_unlock(&kvm->mmu_lock);
b050b015
MT		 2831
2832 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2833 if (!slots)
2834 goto out_free;
2835
2836 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2837 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2838
2839 old_slots = kvm->memslots;
2840 rcu_assign_pointer(kvm->memslots, slots);
2841 synchronize_srcu_expedited(&kvm->srcu);
2842 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2843 kfree(old_slots);
5bb064dc 2844 }
b050b015 2845
5bb064dc 2846 r = 0;
b050b015
MT		 2847 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
2848 r = -EFAULT;
2849out_free:
2850 vfree(dirty_bitmap);
5bb064dc 2851out:
79fac95e 2852 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2853 return r;
2854}
2855
1fe779f8
CO		 2856long kvm_arch_vm_ioctl(struct file *filp,
2857 unsigned int ioctl, unsigned long arg)
2858{
2859 struct kvm *kvm = filp->private_data;
2860 void __user *argp = (void __user *)arg;
367e1319 2861 int r = -ENOTTY;
f0d66275
DH		 2862 /*
2863 * This union makes it completely explicit to gcc-3.x
2864 * that these two variables' stack usage should be
2865 * combined, not added together.
2866 */
2867 union {
2868 struct kvm_pit_state ps;
e9f42757 2869 struct kvm_pit_state2 ps2;
f0d66275 2870 struct kvm_memory_alias alias;
c5ff41ce 2871 struct kvm_pit_config pit_config;
f0d66275 2872 } u;
1fe779f8
CO		 2873
2874 switch (ioctl) {
2875 case KVM_SET_TSS_ADDR:
2876 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2877 if (r < 0)
2878 goto out;
2879 break;
b927a3ce
SY		 2880 case KVM_SET_IDENTITY_MAP_ADDR: {
2881 u64 ident_addr;
2882
2883 r = -EFAULT;
2884 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2885 goto out;
2886 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2887 if (r < 0)
2888 goto out;
2889 break;
2890 }
1fe779f8
CO		 2891 case KVM_SET_MEMORY_REGION: {
2892 struct kvm_memory_region kvm_mem;
2893 struct kvm_userspace_memory_region kvm_userspace_mem;
2894
2895 r = -EFAULT;
2896 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2897 goto out;
2898 kvm_userspace_mem.slot = kvm_mem.slot;
2899 kvm_userspace_mem.flags = kvm_mem.flags;
2900 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2901 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2902 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2903 if (r)
2904 goto out;
2905 break;
2906 }
2907 case KVM_SET_NR_MMU_PAGES:
2908 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2909 if (r)
2910 goto out;
2911 break;
2912 case KVM_GET_NR_MMU_PAGES:
2913 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2914 break;
f0d66275 2915 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2916 r = -EFAULT;
f0d66275 2917 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2918 goto out;
f0d66275 2919 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2920 if (r)
2921 goto out;
2922 break;
3ddea128
MT		 2923 case KVM_CREATE_IRQCHIP: {
2924 struct kvm_pic *vpic;
2925
2926 mutex_lock(&kvm->lock);
2927 r = -EEXIST;
2928 if (kvm->arch.vpic)
2929 goto create_irqchip_unlock;
1fe779f8 2930 r = -ENOMEM;
3ddea128
MT		 2931 vpic = kvm_create_pic(kvm);
2932 if (vpic) {
1fe779f8
CO		 2933 r = kvm_ioapic_init(kvm);
2934 if (r) {
72bb2fcd
WY		 2935 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
2936 &vpic->dev);
3ddea128
MT		 2937 kfree(vpic);
2938 goto create_irqchip_unlock;
1fe779f8
CO		 2939 }
2940 } else
3ddea128
MT		 2941 goto create_irqchip_unlock;
2942 smp_wmb();
2943 kvm->arch.vpic = vpic;
2944 smp_wmb();
399ec807
AK		 2945 r = kvm_setup_default_irq_routing(kvm);
2946 if (r) {
3ddea128 2947 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 2948 kvm_ioapic_destroy(kvm);
2949 kvm_destroy_pic(kvm);
3ddea128 2950 mutex_unlock(&kvm->irq_lock);
399ec807 2951 }
3ddea128
MT		 2952 create_irqchip_unlock:
2953 mutex_unlock(&kvm->lock);
1fe779f8 2954 break;
3ddea128 2955 }
7837699f 2956 case KVM_CREATE_PIT:
c5ff41ce
JK		 2957 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2958 goto create_pit;
2959 case KVM_CREATE_PIT2:
2960 r = -EFAULT;
2961 if (copy_from_user(&u.pit_config, argp,
2962 sizeof(struct kvm_pit_config)))
2963 goto out;
2964 create_pit:
79fac95e 2965 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 2966 r = -EEXIST;
2967 if (kvm->arch.vpit)
2968 goto create_pit_unlock;
7837699f 2969 r = -ENOMEM;
c5ff41ce 2970 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2971 if (kvm->arch.vpit)
2972 r = 0;
269e05e4 2973 create_pit_unlock:
79fac95e 2974 mutex_unlock(&kvm->slots_lock);
7837699f 2975 break;
4925663a 2976 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2977 case KVM_IRQ_LINE: {
2978 struct kvm_irq_level irq_event;
2979
2980 r = -EFAULT;
2981 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2982 goto out;
160d2f6c 2983 r = -ENXIO;
1fe779f8 2984 if (irqchip_in_kernel(kvm)) {
4925663a 2985 __s32 status;
4925663a
GN		 2986 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2987 irq_event.irq, irq_event.level);
4925663a 2988 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 2989 r = -EFAULT;
4925663a
GN		 2990 irq_event.status = status;
2991 if (copy_to_user(argp, &irq_event,
2992 sizeof irq_event))
2993 goto out;
2994 }
1fe779f8
CO		 2995 r = 0;
2996 }
2997 break;
2998 }
2999 case KVM_GET_IRQCHIP: {
3000 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3001 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3002
f0d66275
DH		 3003 r = -ENOMEM;
3004 if (!chip)
1fe779f8 3005 goto out;
f0d66275
DH		 3006 r = -EFAULT;
3007 if (copy_from_user(chip, argp, sizeof *chip))
3008 goto get_irqchip_out;
1fe779f8
CO		 3009 r = -ENXIO;
3010 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3011 goto get_irqchip_out;
3012 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3013 if (r)
f0d66275 3014 goto get_irqchip_out;
1fe779f8 3015 r = -EFAULT;
f0d66275
DH		 3016 if (copy_to_user(argp, chip, sizeof *chip))
3017 goto get_irqchip_out;
1fe779f8 3018 r = 0;
f0d66275
DH		 3019 get_irqchip_out:
3020 kfree(chip);
3021 if (r)
3022 goto out;
1fe779f8
CO		 3023 break;
3024 }
3025 case KVM_SET_IRQCHIP: {
3026 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3027 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3028
f0d66275
DH		 3029 r = -ENOMEM;
3030 if (!chip)
1fe779f8 3031 goto out;
f0d66275
DH		 3032 r = -EFAULT;
3033 if (copy_from_user(chip, argp, sizeof *chip))
3034 goto set_irqchip_out;
1fe779f8
CO		 3035 r = -ENXIO;
3036 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3037 goto set_irqchip_out;
3038 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3039 if (r)
f0d66275 3040 goto set_irqchip_out;
1fe779f8 3041 r = 0;
f0d66275
DH		 3042 set_irqchip_out:
3043 kfree(chip);
3044 if (r)
3045 goto out;
1fe779f8
CO		 3046 break;
3047 }
e0f63cb9 3048 case KVM_GET_PIT: {
e0f63cb9 3049 r = -EFAULT;
f0d66275 3050 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3051 goto out;
3052 r = -ENXIO;
3053 if (!kvm->arch.vpit)
3054 goto out;
f0d66275 3055 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3056 if (r)
3057 goto out;
3058 r = -EFAULT;
f0d66275 3059 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3060 goto out;
3061 r = 0;
3062 break;
3063 }
3064 case KVM_SET_PIT: {
e0f63cb9 3065 r = -EFAULT;
f0d66275 3066 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3067 goto out;
3068 r = -ENXIO;
3069 if (!kvm->arch.vpit)
3070 goto out;
f0d66275 3071 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3072 if (r)
3073 goto out;
3074 r = 0;
3075 break;
3076 }
e9f42757
BK		 3077 case KVM_GET_PIT2: {
3078 r = -ENXIO;
3079 if (!kvm->arch.vpit)
3080 goto out;
3081 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3082 if (r)
3083 goto out;
3084 r = -EFAULT;
3085 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3086 goto out;
3087 r = 0;
3088 break;
3089 }
3090 case KVM_SET_PIT2: {
3091 r = -EFAULT;
3092 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3093 goto out;
3094 r = -ENXIO;
3095 if (!kvm->arch.vpit)
3096 goto out;
3097 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3098 if (r)
3099 goto out;
3100 r = 0;
3101 break;
3102 }
52d939a0
MT		 3103 case KVM_REINJECT_CONTROL: {
3104 struct kvm_reinject_control control;
3105 r = -EFAULT;
3106 if (copy_from_user(&control, argp, sizeof(control)))
3107 goto out;
3108 r = kvm_vm_ioctl_reinject(kvm, &control);
3109 if (r)
3110 goto out;
3111 r = 0;
3112 break;
3113 }
ffde22ac
ES		 3114 case KVM_XEN_HVM_CONFIG: {
3115 r = -EFAULT;
3116 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3117 sizeof(struct kvm_xen_hvm_config)))
3118 goto out;
3119 r = -EINVAL;
3120 if (kvm->arch.xen_hvm_config.flags)
3121 goto out;
3122 r = 0;
3123 break;
3124 }
afbcf7ab
GC		 3125 case KVM_SET_CLOCK: {
3126 struct timespec now;
3127 struct kvm_clock_data user_ns;
3128 u64 now_ns;
3129 s64 delta;
3130
3131 r = -EFAULT;
3132 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3133 goto out;
3134
3135 r = -EINVAL;
3136 if (user_ns.flags)
3137 goto out;
3138
3139 r = 0;
3140 ktime_get_ts(&now);
3141 now_ns = timespec_to_ns(&now);
3142 delta = user_ns.clock - now_ns;
3143 kvm->arch.kvmclock_offset = delta;
3144 break;
3145 }
3146 case KVM_GET_CLOCK: {
3147 struct timespec now;
3148 struct kvm_clock_data user_ns;
3149 u64 now_ns;
3150
3151 ktime_get_ts(&now);
3152 now_ns = timespec_to_ns(&now);
3153 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3154 user_ns.flags = 0;
3155
3156 r = -EFAULT;
3157 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3158 goto out;
3159 r = 0;
3160 break;
3161 }
3162
1fe779f8
CO		 3163 default:
3164 ;
3165 }
3166out:
3167 return r;
3168}
3169
a16b043c 3170static void kvm_init_msr_list(void)
043405e1
CO		 3171{
3172 u32 dummy[2];
3173 unsigned i, j;
3174
e3267cbb
GC		 3175 /* skip the first msrs in the list. KVM-specific */
3176 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3177 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3178 continue;
3179 if (j < i)
3180 msrs_to_save[j] = msrs_to_save[i];
3181 j++;
3182 }
3183 num_msrs_to_save = j;
3184}
3185
bda9020e
MT		 3186static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3187 const void *v)
bbd9b64e 3188{
bda9020e
MT		 3189 if (vcpu->arch.apic &&
3190 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3191 return 0;
bbd9b64e 3192
e93f8a0f 3193 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3194}
3195
bda9020e 3196static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3197{
bda9020e
MT		 3198 if (vcpu->arch.apic &&
3199 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3200 return 0;
bbd9b64e 3201
e93f8a0f 3202 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3203}
3204
2dafc6c2
GN		 3205static void kvm_set_segment(struct kvm_vcpu *vcpu,
3206 struct kvm_segment *var, int seg)
3207{
3208 kvm_x86_ops->set_segment(vcpu, var, seg);
3209}
3210
3211void kvm_get_segment(struct kvm_vcpu *vcpu,
3212 struct kvm_segment *var, int seg)
3213{
3214 kvm_x86_ops->get_segment(vcpu, var, seg);
3215}
3216
1871c602
GN		 3217gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3218{
3219 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3220 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3221}
3222
3223 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3224{
3225 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3226 access |= PFERR_FETCH_MASK;
3227 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3228}
3229
3230gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3231{
3232 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3233 access |= PFERR_WRITE_MASK;
3234 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3235}
3236
3237/* uses this to access any guest's mapped memory without checking CPL */
3238gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3239{
3240 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3241}
3242
3243static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3244 struct kvm_vcpu *vcpu, u32 access,
3245 u32 *error)
bbd9b64e
CO		 3246{
3247 void *data = val;
10589a46 3248 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3249
3250 while (bytes) {
1871c602 3251 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3252 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3253 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3254 int ret;
3255
10589a46
MT		 3256 if (gpa == UNMAPPED_GVA) {
3257 r = X86EMUL_PROPAGATE_FAULT;
3258 goto out;
3259 }
77c2002e 3260 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 3261 if (ret < 0) {
3262 r = X86EMUL_UNHANDLEABLE;
3263 goto out;
3264 }
bbd9b64e 3265
77c2002e
IE		 3266 bytes -= toread;
3267 data += toread;
3268 addr += toread;
bbd9b64e 3269 }
10589a46 3270out:
10589a46 3271 return r;
bbd9b64e 3272}
77c2002e 3273
1871c602
GN		 3274/* used for instruction fetching */
3275static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3276 struct kvm_vcpu *vcpu, u32 *error)
3277{
3278 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3279 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3280 access | PFERR_FETCH_MASK, error);
3281}
3282
3283static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3284 struct kvm_vcpu *vcpu, u32 *error)
3285{
3286 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3287 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3288 error);
3289}
3290
3291static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3292 struct kvm_vcpu *vcpu, u32 *error)
3293{
3294 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3295}
3296
7972995b 3297static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3298 unsigned int bytes,
7972995b 3299 struct kvm_vcpu *vcpu,
2dafc6c2 3300 u32 *error)
77c2002e
IE		 3301{
3302 void *data = val;
3303 int r = X86EMUL_CONTINUE;
3304
3305 while (bytes) {
7972995b
GN		 3306 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr,
3307 PFERR_WRITE_MASK, error);
77c2002e
IE		 3308 unsigned offset = addr & (PAGE_SIZE-1);
3309 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3310 int ret;
3311
3312 if (gpa == UNMAPPED_GVA) {
3313 r = X86EMUL_PROPAGATE_FAULT;
3314 goto out;
3315 }
3316 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3317 if (ret < 0) {
3318 r = X86EMUL_UNHANDLEABLE;
3319 goto out;
3320 }
3321
3322 bytes -= towrite;
3323 data += towrite;
3324 addr += towrite;
3325 }
3326out:
3327 return r;
3328}
3329
bbd9b64e
CO		 3330static int emulator_read_emulated(unsigned long addr,
3331 void *val,
3332 unsigned int bytes,
3333 struct kvm_vcpu *vcpu)
3334{
bbd9b64e 3335 gpa_t gpa;
1871c602 3336 u32 error_code;
bbd9b64e
CO		 3337
3338 if (vcpu->mmio_read_completed) {
3339 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3340 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3341 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3342 vcpu->mmio_read_completed = 0;
3343 return X86EMUL_CONTINUE;
3344 }
3345
1871c602
GN		 3346 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, &error_code);
3347
3348 if (gpa == UNMAPPED_GVA) {
3349 kvm_inject_page_fault(vcpu, addr, error_code);
3350 return X86EMUL_PROPAGATE_FAULT;
3351 }
bbd9b64e
CO		 3352
3353 /* For APIC access vmexit */
3354 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3355 goto mmio;
3356
1871c602 3357 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3358 == X86EMUL_CONTINUE)
bbd9b64e 3359 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3360
3361mmio:
3362 /*
3363 * Is this MMIO handled locally?
3364 */
aec51dc4
AK		 3365 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3366 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3367 return X86EMUL_CONTINUE;
3368 }
aec51dc4
AK		 3369
3370 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3371
3372 vcpu->mmio_needed = 1;
3373 vcpu->mmio_phys_addr = gpa;
3374 vcpu->mmio_size = bytes;
3375 vcpu->mmio_is_write = 0;
3376
3377 return X86EMUL_UNHANDLEABLE;
3378}
3379
3200f405 3380int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3381 const void *val, int bytes)
bbd9b64e
CO		 3382{
3383 int ret;
3384
3385 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3386 if (ret < 0)
bbd9b64e 3387 return 0;
ad218f85 3388 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3389 return 1;
3390}
3391
3392static int emulator_write_emulated_onepage(unsigned long addr,
3393 const void *val,
3394 unsigned int bytes,
3395 struct kvm_vcpu *vcpu)
3396{
10589a46 3397 gpa_t gpa;
1871c602 3398 u32 error_code;
10589a46 3399
1871c602 3400 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, &error_code);
bbd9b64e
CO		 3401
3402 if (gpa == UNMAPPED_GVA) {
1871c602 3403 kvm_inject_page_fault(vcpu, addr, error_code);
bbd9b64e
CO		 3404 return X86EMUL_PROPAGATE_FAULT;
3405 }
3406
3407 /* For APIC access vmexit */
3408 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3409 goto mmio;
3410
3411 if (emulator_write_phys(vcpu, gpa, val, bytes))
3412 return X86EMUL_CONTINUE;
3413
3414mmio:
aec51dc4 3415 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3416 /*
3417 * Is this MMIO handled locally?
3418 */
bda9020e 3419 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3420 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3421
3422 vcpu->mmio_needed = 1;
3423 vcpu->mmio_phys_addr = gpa;
3424 vcpu->mmio_size = bytes;
3425 vcpu->mmio_is_write = 1;
3426 memcpy(vcpu->mmio_data, val, bytes);
3427
3428 return X86EMUL_CONTINUE;
3429}
3430
3431int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3432 const void *val,
3433 unsigned int bytes,
3434 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3435{
3436 /* Crossing a page boundary? */
3437 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3438 int rc, now;
3439
3440 now = -addr & ~PAGE_MASK;
3441 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
3442 if (rc != X86EMUL_CONTINUE)
3443 return rc;
3444 addr += now;
3445 val += now;
3446 bytes -= now;
3447 }
3448 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
3449}
3450EXPORT_SYMBOL_GPL(emulator_write_emulated);
3451
daea3e73
AK		 3452#define CMPXCHG_TYPE(t, ptr, old, new) \
3453 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3454
3455#ifdef CONFIG_X86_64
3456# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3457#else
3458# define CMPXCHG64(ptr, old, new) \
9749a6c0 3459 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3460#endif
3461
bbd9b64e
CO		 3462static int emulator_cmpxchg_emulated(unsigned long addr,
3463 const void *old,
3464 const void *new,
3465 unsigned int bytes,
3466 struct kvm_vcpu *vcpu)
3467{
daea3e73
AK		 3468 gpa_t gpa;
3469 struct page *page;
3470 char *kaddr;
3471 bool exchanged;
2bacc55c 3472
daea3e73
AK		 3473 /* guests cmpxchg8b have to be emulated atomically */
3474 if (bytes > 8 || (bytes & (bytes - 1)))
3475 goto emul_write;
10589a46 3476
daea3e73 3477 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3478
daea3e73
AK		 3479 if (gpa == UNMAPPED_GVA ||
3480 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3481 goto emul_write;
2bacc55c 3482
daea3e73
AK		 3483 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3484 goto emul_write;
72dc67a6 3485
daea3e73 3486 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3487
daea3e73
AK		 3488 kaddr = kmap_atomic(page, KM_USER0);
3489 kaddr += offset_in_page(gpa);
3490 switch (bytes) {
3491 case 1:
3492 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3493 break;
3494 case 2:
3495 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3496 break;
3497 case 4:
3498 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3499 break;
3500 case 8:
3501 exchanged = CMPXCHG64(kaddr, old, new);
3502 break;
3503 default:
3504 BUG();
2bacc55c 3505 }
daea3e73
AK		 3506 kunmap_atomic(kaddr, KM_USER0);
3507 kvm_release_page_dirty(page);
3508
3509 if (!exchanged)
3510 return X86EMUL_CMPXCHG_FAILED;
3511
8f6abd06
GN		 3512 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3513
3514 return X86EMUL_CONTINUE;
4a5f48f6 3515
3200f405 3516emul_write:
daea3e73 3517 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3518
bbd9b64e
CO		 3519 return emulator_write_emulated(addr, new, bytes, vcpu);
3520}
3521
cf8f70bf
GN		 3522static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3523{
3524 /* TODO: String I/O for in kernel device */
3525 int r;
3526
3527 if (vcpu->arch.pio.in)
3528 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3529 vcpu->arch.pio.size, pd);
3530 else
3531 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3532 vcpu->arch.pio.port, vcpu->arch.pio.size,
3533 pd);
3534 return r;
3535}
3536
3537
3538static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3539 unsigned int count, struct kvm_vcpu *vcpu)
3540{
7972995b 3541 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3542 goto data_avail;
3543
3544 trace_kvm_pio(1, port, size, 1);
3545
3546 vcpu->arch.pio.port = port;
3547 vcpu->arch.pio.in = 1;
7972995b 3548 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3549 vcpu->arch.pio.size = size;
3550
3551 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3552 data_avail:
3553 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3554 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3555 return 1;
3556 }
3557
3558 vcpu->run->exit_reason = KVM_EXIT_IO;
3559 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3560 vcpu->run->io.size = size;
3561 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3562 vcpu->run->io.count = count;
3563 vcpu->run->io.port = port;
3564
3565 return 0;
3566}
3567
3568static int emulator_pio_out_emulated(int size, unsigned short port,
3569 const void *val, unsigned int count,
3570 struct kvm_vcpu *vcpu)
3571{
3572 trace_kvm_pio(0, port, size, 1);
3573
3574 vcpu->arch.pio.port = port;
3575 vcpu->arch.pio.in = 0;
7972995b 3576 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3577 vcpu->arch.pio.size = size;
3578
3579 memcpy(vcpu->arch.pio_data, val, size * count);
3580
3581 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3582 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3583 return 1;
3584 }
3585
3586 vcpu->run->exit_reason = KVM_EXIT_IO;
3587 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3588 vcpu->run->io.size = size;
3589 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3590 vcpu->run->io.count = count;
3591 vcpu->run->io.port = port;
3592
3593 return 0;
3594}
3595
bbd9b64e
CO		 3596static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3597{
3598 return kvm_x86_ops->get_segment_base(vcpu, seg);
3599}
3600
3601int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3602{
a7052897 3603 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3604 return X86EMUL_CONTINUE;
3605}
3606
3607int emulate_clts(struct kvm_vcpu *vcpu)
3608{
4d4ec087 3609 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3610 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3611 return X86EMUL_CONTINUE;
3612}
3613
3614int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
3615{
020df079 3616 return kvm_get_dr(ctxt->vcpu, dr, dest);
bbd9b64e
CO		 3617}
3618
3619int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
3620{
3621 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
bbd9b64e 3622
020df079 3623 return kvm_set_dr(ctxt->vcpu, dr, value & mask);
bbd9b64e
CO		 3624}
3625
3626void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
3627{
bbd9b64e 3628 u8 opcodes[4];
5fdbf976 3629 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 3630 unsigned long rip_linear;
3631
f76c710d 3632 if (!printk_ratelimit())
bbd9b64e
CO		 3633 return;
3634
25be4608
GC		 3635 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
3636
1871c602 3637 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu, NULL);
bbd9b64e
CO		 3638
3639 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
3640 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 3641}
3642EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
3643
52a46617 3644static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 3645{
52a46617 3646 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 3647}
3648
52a46617 3649static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 3650{
52a46617
GN		 3651 unsigned long value;
3652
3653 switch (cr) {
3654 case 0:
3655 value = kvm_read_cr0(vcpu);
3656 break;
3657 case 2:
3658 value = vcpu->arch.cr2;
3659 break;
3660 case 3:
3661 value = vcpu->arch.cr3;
3662 break;
3663 case 4:
3664 value = kvm_read_cr4(vcpu);
3665 break;
3666 case 8:
3667 value = kvm_get_cr8(vcpu);
3668 break;
3669 default:
3670 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3671 return 0;
3672 }
3673
3674 return value;
3675}
3676
3677static void emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
3678{
3679 switch (cr) {
3680 case 0:
3681 kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
3682 break;
3683 case 2:
3684 vcpu->arch.cr2 = val;
3685 break;
3686 case 3:
3687 kvm_set_cr3(vcpu, val);
3688 break;
3689 case 4:
3690 kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
3691 break;
3692 case 8:
3693 kvm_set_cr8(vcpu, val & 0xfUL);
3694 break;
3695 default:
3696 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3697 }
3698}
3699
9c537244
GN		 3700static int emulator_get_cpl(struct kvm_vcpu *vcpu)
3701{
3702 return kvm_x86_ops->get_cpl(vcpu);
3703}
3704
2dafc6c2
GN		 3705static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3706{
3707 kvm_x86_ops->get_gdt(vcpu, dt);
3708}
3709
3710static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
3711 struct kvm_vcpu *vcpu)
3712{
3713 struct kvm_segment var;
3714
3715 kvm_get_segment(vcpu, &var, seg);
3716
3717 if (var.unusable)
3718 return false;
3719
3720 if (var.g)
3721 var.limit >>= 12;
3722 set_desc_limit(desc, var.limit);
3723 set_desc_base(desc, (unsigned long)var.base);
3724 desc->type = var.type;
3725 desc->s = var.s;
3726 desc->dpl = var.dpl;
3727 desc->p = var.present;
3728 desc->avl = var.avl;
3729 desc->l = var.l;
3730 desc->d = var.db;
3731 desc->g = var.g;
3732
3733 return true;
3734}
3735
3736static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
3737 struct kvm_vcpu *vcpu)
3738{
3739 struct kvm_segment var;
3740
3741 /* needed to preserve selector */
3742 kvm_get_segment(vcpu, &var, seg);
3743
3744 var.base = get_desc_base(desc);
3745 var.limit = get_desc_limit(desc);
3746 if (desc->g)
3747 var.limit = (var.limit << 12) | 0xfff;
3748 var.type = desc->type;
3749 var.present = desc->p;
3750 var.dpl = desc->dpl;
3751 var.db = desc->d;
3752 var.s = desc->s;
3753 var.l = desc->l;
3754 var.g = desc->g;
3755 var.avl = desc->avl;
3756 var.present = desc->p;
3757 var.unusable = !var.present;
3758 var.padding = 0;
3759
3760 kvm_set_segment(vcpu, &var, seg);
3761 return;
3762}
3763
3764static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
3765{
3766 struct kvm_segment kvm_seg;
3767
3768 kvm_get_segment(vcpu, &kvm_seg, seg);
3769 return kvm_seg.selector;
3770}
3771
3772static void emulator_set_segment_selector(u16 sel, int seg,
3773 struct kvm_vcpu *vcpu)
3774{
3775 struct kvm_segment kvm_seg;
3776
3777 kvm_get_segment(vcpu, &kvm_seg, seg);
3778 kvm_seg.selector = sel;
3779 kvm_set_segment(vcpu, &kvm_seg, seg);
3780}
3781
482ac18a
GN		 3782static void emulator_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
3783{
3784 kvm_x86_ops->set_rflags(vcpu, rflags);
3785}
3786
14af3f3c 3787static struct x86_emulate_ops emulate_ops = {
1871c602 3788 .read_std = kvm_read_guest_virt_system,
2dafc6c2 3789 .write_std = kvm_write_guest_virt_system,
1871c602 3790 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3791 .read_emulated = emulator_read_emulated,
3792 .write_emulated = emulator_write_emulated,
3793 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 3794 .pio_in_emulated = emulator_pio_in_emulated,
3795 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 3796 .get_cached_descriptor = emulator_get_cached_descriptor,
3797 .set_cached_descriptor = emulator_set_cached_descriptor,
3798 .get_segment_selector = emulator_get_segment_selector,
3799 .set_segment_selector = emulator_set_segment_selector,
3800 .get_gdt = emulator_get_gdt,
52a46617
GN		 3801 .get_cr = emulator_get_cr,
3802 .set_cr = emulator_set_cr,
9c537244 3803 .cpl = emulator_get_cpl,
482ac18a 3804 .set_rflags = emulator_set_rflags,
bbd9b64e
CO		 3805};
3806
5fdbf976
MT		 3807static void cache_all_regs(struct kvm_vcpu *vcpu)
3808{
3809 kvm_register_read(vcpu, VCPU_REGS_RAX);
3810 kvm_register_read(vcpu, VCPU_REGS_RSP);
3811 kvm_register_read(vcpu, VCPU_REGS_RIP);
3812 vcpu->arch.regs_dirty = ~0;
3813}
3814
bbd9b64e 3815int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3816 unsigned long cr2,
3817 u16 error_code,
571008da 3818 int emulation_type)
bbd9b64e 3819{
310b5d30 3820 int r, shadow_mask;
571008da 3821 struct decode_cache *c;
851ba692 3822 struct kvm_run *run = vcpu->run;
bbd9b64e 3823
26eef70c 3824 kvm_clear_exception_queue(vcpu);
ad312c7c 3825 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3826 /*
56e82318 3827 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3828 * instead of direct ->regs accesses, can save hundred cycles
3829 * on Intel for instructions that don't read/change RSP, for
3830 * for example.
3831 */
3832 cache_all_regs(vcpu);
bbd9b64e
CO		 3833
3834 vcpu->mmio_is_write = 0;
bbd9b64e 3835
571008da 3836 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3837 int cs_db, cs_l;
3838 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3839
ad312c7c 3840 vcpu->arch.emulate_ctxt.vcpu = vcpu;
83bf0002 3841 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
063db061 3842 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
ad312c7c 3843 vcpu->arch.emulate_ctxt.mode =
a0044755 3844 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3845 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3846 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3847 ? X86EMUL_MODE_PROT64 : cs_db
3848 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3849
ad312c7c 3850 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
e46479f8 3851 trace_kvm_emulate_insn_start(vcpu);
571008da 3852
0cb5762e
AP		 3853 /* Only allow emulation of specific instructions on #UD
3854 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 3855 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 3856 if (emulation_type & EMULTYPE_TRAP_UD) {
3857 if (!c->twobyte)
3858 return EMULATE_FAIL;
3859 switch (c->b) {
3860 case 0x01: /* VMMCALL */
3861 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3862 return EMULATE_FAIL;
3863 break;
3864 case 0x34: /* sysenter */
3865 case 0x35: /* sysexit */
3866 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3867 return EMULATE_FAIL;
3868 break;
3869 case 0x05: /* syscall */
3870 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3871 return EMULATE_FAIL;
3872 break;
3873 default:
3874 return EMULATE_FAIL;
3875 }
3876
3877 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3878 return EMULATE_FAIL;
3879 }
571008da 3880
f2b5756b 3881 ++vcpu->stat.insn_emulation;
bbd9b64e 3882 if (r) {
f2b5756b 3883 ++vcpu->stat.insn_emulation_fail;
e46479f8 3884 trace_kvm_emulate_insn_failed(vcpu);
bbd9b64e
CO		 3885 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3886 return EMULATE_DONE;
3887 return EMULATE_FAIL;
3888 }
3889 }
3890
ba8afb6b
GN		 3891 if (emulation_type & EMULTYPE_SKIP) {
3892 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3893 return EMULATE_DONE;
3894 }
3895
5cd21917 3896restart:
ad312c7c 3897 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 3898 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3899
3900 if (r == 0)
3901 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 3902
7972995b 3903 if (vcpu->arch.pio.count) {
cf8f70bf 3904 if (!vcpu->arch.pio.in)
7972995b 3905 vcpu->arch.pio.count = 0;
bbd9b64e 3906 return EMULATE_DO_MMIO;
cf8f70bf 3907 }
bbd9b64e 3908
112592da 3909 if (r || vcpu->mmio_is_write) {
bbd9b64e
CO		 3910 run->exit_reason = KVM_EXIT_MMIO;
3911 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3912 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3913 run->mmio.len = vcpu->mmio_size;
3914 run->mmio.is_write = vcpu->mmio_is_write;
3915 }
3916
3917 if (r) {
3918 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
5cd21917 3919 goto done;
bbd9b64e 3920 if (!vcpu->mmio_needed) {
e46479f8
AK		 3921 ++vcpu->stat.insn_emulation_fail;
3922 trace_kvm_emulate_insn_failed(vcpu);
bbd9b64e
CO		 3923 kvm_report_emulation_failure(vcpu, "mmio");
3924 return EMULATE_FAIL;
3925 }
3926 return EMULATE_DO_MMIO;
3927 }
3928
bbd9b64e
CO		 3929 if (vcpu->mmio_is_write) {
3930 vcpu->mmio_needed = 0;
3931 return EMULATE_DO_MMIO;
3932 }
3933
5cd21917
GN		 3934done:
3935 if (vcpu->arch.exception.pending)
3936 vcpu->arch.emulate_ctxt.restart = false;
de7d789a 3937
5cd21917
GN		 3938 if (vcpu->arch.emulate_ctxt.restart)
3939 goto restart;
f850e2e6 3940
bbd9b64e 3941 return EMULATE_DONE;
de7d789a 3942}
bbd9b64e 3943EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 3944
cf8f70bf 3945int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 3946{
cf8f70bf
GN		 3947 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3948 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
3949 /* do not return to emulator after return from userspace */
7972995b 3950 vcpu->arch.pio.count = 0;
de7d789a
CO		 3951 return ret;
3952}
cf8f70bf 3953EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 3954
c8076604
GH		 3955static void bounce_off(void *info)
3956{
3957 /* nothing */
3958}
3959
c8076604
GH		 3960static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3961 void *data)
3962{
3963 struct cpufreq_freqs *freq = data;
3964 struct kvm *kvm;
3965 struct kvm_vcpu *vcpu;
3966 int i, send_ipi = 0;
3967
c8076604
GH		 3968 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3969 return 0;
3970 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3971 return 0;
0cca7907 3972 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3973
3974 spin_lock(&kvm_lock);
3975 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3976 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3977 if (vcpu->cpu != freq->cpu)
3978 continue;
3979 if (!kvm_request_guest_time_update(vcpu))
3980 continue;
3981 if (vcpu->cpu != smp_processor_id())
3982 send_ipi++;
3983 }
3984 }
3985 spin_unlock(&kvm_lock);
3986
3987 if (freq->old < freq->new && send_ipi) {
3988 /*
3989 * We upscale the frequency. Must make the guest
3990 * doesn't see old kvmclock values while running with
3991 * the new frequency, otherwise we risk the guest sees
3992 * time go backwards.
3993 *
3994 * In case we update the frequency for another cpu
3995 * (which might be in guest context) send an interrupt
3996 * to kick the cpu out of guest context. Next time
3997 * guest context is entered kvmclock will be updated,
3998 * so the guest will not see stale values.
3999 */
4000 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
4001 }
4002 return 0;
4003}
4004
4005static struct notifier_block kvmclock_cpufreq_notifier_block = {
4006 .notifier_call = kvmclock_cpufreq_notifier
4007};
4008
b820cc0c
ZA		 4009static void kvm_timer_init(void)
4010{
4011 int cpu;
4012
b820cc0c 4013 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 4014 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4015 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 4016 for_each_online_cpu(cpu) {
4017 unsigned long khz = cpufreq_get(cpu);
4018 if (!khz)
4019 khz = tsc_khz;
4020 per_cpu(cpu_tsc_khz, cpu) = khz;
4021 }
0cca7907
ZA		 4022 } else {
4023 for_each_possible_cpu(cpu)
4024 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 4025 }
4026}
4027
ff9d07a0
ZY		 4028static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4029
4030static int kvm_is_in_guest(void)
4031{
4032 return percpu_read(current_vcpu) != NULL;
4033}
4034
4035static int kvm_is_user_mode(void)
4036{
4037 int user_mode = 3;
dcf46b94 4038
ff9d07a0
ZY		 4039 if (percpu_read(current_vcpu))
4040 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4041
ff9d07a0
ZY		 4042 return user_mode != 0;
4043}
4044
4045static unsigned long kvm_get_guest_ip(void)
4046{
4047 unsigned long ip = 0;
dcf46b94 4048
ff9d07a0
ZY		 4049 if (percpu_read(current_vcpu))
4050 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4051
ff9d07a0
ZY		 4052 return ip;
4053}
4054
4055static struct perf_guest_info_callbacks kvm_guest_cbs = {
4056 .is_in_guest = kvm_is_in_guest,
4057 .is_user_mode = kvm_is_user_mode,
4058 .get_guest_ip = kvm_get_guest_ip,
4059};
4060
4061void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4062{
4063 percpu_write(current_vcpu, vcpu);
4064}
4065EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4066
4067void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4068{
4069 percpu_write(current_vcpu, NULL);
4070}
4071EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4072
f8c16bba 4073int kvm_arch_init(void *opaque)
043405e1 4074{
b820cc0c 4075 int r;
f8c16bba
ZX		 4076 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4077
f8c16bba
ZX		 4078 if (kvm_x86_ops) {
4079 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4080 r = -EEXIST;
4081 goto out;
f8c16bba
ZX		 4082 }
4083
4084 if (!ops->cpu_has_kvm_support()) {
4085 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4086 r = -EOPNOTSUPP;
4087 goto out;
f8c16bba
ZX		 4088 }
4089 if (ops->disabled_by_bios()) {
4090 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4091 r = -EOPNOTSUPP;
4092 goto out;
f8c16bba
ZX		 4093 }
4094
97db56ce
AK		 4095 r = kvm_mmu_module_init();
4096 if (r)
4097 goto out;
4098
4099 kvm_init_msr_list();
4100
f8c16bba 4101 kvm_x86_ops = ops;
56c6d28a 4102 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4103 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4104 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4105 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4106
b820cc0c 4107 kvm_timer_init();
c8076604 4108
ff9d07a0
ZY		 4109 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4110
f8c16bba 4111 return 0;
56c6d28a
ZX		 4112
4113out:
56c6d28a 4114 return r;
043405e1 4115}
8776e519 4116
f8c16bba
ZX		 4117void kvm_arch_exit(void)
4118{
ff9d07a0
ZY		 4119 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4120
888d256e
JK		 4121 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4122 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4123 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 4124 kvm_x86_ops = NULL;
56c6d28a
ZX		 4125 kvm_mmu_module_exit();
4126}
f8c16bba 4127
8776e519
HB		 4128int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4129{
4130 ++vcpu->stat.halt_exits;
4131 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4132 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4133 return 1;
4134 } else {
4135 vcpu->run->exit_reason = KVM_EXIT_HLT;
4136 return 0;
4137 }
4138}
4139EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4140
2f333bcb
MT		 4141static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4142 unsigned long a1)
4143{
4144 if (is_long_mode(vcpu))
4145 return a0;
4146 else
4147 return a0 | ((gpa_t)a1 << 32);
4148}
4149
55cd8e5a
GN		 4150int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4151{
4152 u64 param, ingpa, outgpa, ret;
4153 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4154 bool fast, longmode;
4155 int cs_db, cs_l;
4156
4157 /*
4158 * hypercall generates UD from non zero cpl and real mode
4159 * per HYPER-V spec
4160 */
3eeb3288 4161 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4162 kvm_queue_exception(vcpu, UD_VECTOR);
4163 return 0;
4164 }
4165
4166 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4167 longmode = is_long_mode(vcpu) && cs_l == 1;
4168
4169 if (!longmode) {
ccd46936
GN		 4170 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4171 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4172 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4173 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4174 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4175 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4176 }
4177#ifdef CONFIG_X86_64
4178 else {
4179 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4180 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4181 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4182 }
4183#endif
4184
4185 code = param & 0xffff;
4186 fast = (param >> 16) & 0x1;
4187 rep_cnt = (param >> 32) & 0xfff;
4188 rep_idx = (param >> 48) & 0xfff;
4189
4190 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4191
c25bc163
GN		 4192 switch (code) {
4193 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4194 kvm_vcpu_on_spin(vcpu);
4195 break;
4196 default:
4197 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4198 break;
4199 }
55cd8e5a
GN		 4200
4201 ret = res | (((u64)rep_done & 0xfff) << 32);
4202 if (longmode) {
4203 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4204 } else {
4205 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4206 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4207 }
4208
4209 return 1;
4210}
4211
8776e519
HB		 4212int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4213{
4214 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4215 int r = 1;
8776e519 4216
55cd8e5a
GN		 4217 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4218 return kvm_hv_hypercall(vcpu);
4219
5fdbf976
MT		 4220 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4221 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4222 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4223 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4224 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4225
229456fc 4226 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4227
8776e519
HB		 4228 if (!is_long_mode(vcpu)) {
4229 nr &= 0xFFFFFFFF;
4230 a0 &= 0xFFFFFFFF;
4231 a1 &= 0xFFFFFFFF;
4232 a2 &= 0xFFFFFFFF;
4233 a3 &= 0xFFFFFFFF;
4234 }
4235
07708c4a
JK		 4236 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4237 ret = -KVM_EPERM;
4238 goto out;
4239 }
4240
8776e519 4241 switch (nr) {
b93463aa
AK		 4242 case KVM_HC_VAPIC_POLL_IRQ:
4243 ret = 0;
4244 break;
2f333bcb
MT		 4245 case KVM_HC_MMU_OP:
4246 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4247 break;
8776e519
HB		 4248 default:
4249 ret = -KVM_ENOSYS;
4250 break;
4251 }
07708c4a 4252out:
5fdbf976 4253 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4254 ++vcpu->stat.hypercalls;
2f333bcb 4255 return r;
8776e519
HB		 4256}
4257EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4258
4259int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4260{
4261 char instruction[3];
5fdbf976 4262 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4263
8776e519
HB		 4264 /*
4265 * Blow out the MMU to ensure that no other VCPU has an active mapping
4266 * to ensure that the updated hypercall appears atomically across all
4267 * VCPUs.
4268 */
4269 kvm_mmu_zap_all(vcpu->kvm);
4270
8776e519 4271 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4272
7edcface 4273 return emulator_write_emulated(rip, instruction, 3, vcpu);
8776e519
HB		 4274}
4275
8776e519
HB		 4276void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4277{
89a27f4d 4278 struct desc_ptr dt = { limit, base };
8776e519
HB		 4279
4280 kvm_x86_ops->set_gdt(vcpu, &dt);
4281}
4282
4283void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4284{
89a27f4d 4285 struct desc_ptr dt = { limit, base };
8776e519
HB		 4286
4287 kvm_x86_ops->set_idt(vcpu, &dt);
4288}
4289
07716717
DK		 4290static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4291{
ad312c7c
ZX		 4292 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4293 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4294
4295 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4296 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4297 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4298 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4299 if (ej->function == e->function) {
4300 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4301 return j;
4302 }
4303 }
4304 return 0; /* silence gcc, even though control never reaches here */
4305}
4306
4307/* find an entry with matching function, matching index (if needed), and that
4308 * should be read next (if it's stateful) */
4309static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4310 u32 function, u32 index)
4311{
4312 if (e->function != function)
4313 return 0;
4314 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4315 return 0;
4316 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4317 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4318 return 0;
4319 return 1;
4320}
4321
d8017474
AG		 4322struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4323 u32 function, u32 index)
8776e519
HB		 4324{
4325 int i;
d8017474 4326 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4327
ad312c7c 4328 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4329 struct kvm_cpuid_entry2 *e;
4330
ad312c7c 4331 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4332 if (is_matching_cpuid_entry(e, function, index)) {
4333 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4334 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4335 best = e;
4336 break;
4337 }
4338 /*
4339 * Both basic or both extended?
4340 */
4341 if (((e->function ^ function) & 0x80000000) == 0)
4342 if (!best || e->function > best->function)
4343 best = e;
4344 }
d8017474
AG		 4345 return best;
4346}
0e851880 4347EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4348
82725b20
DE		 4349int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4350{
4351 struct kvm_cpuid_entry2 *best;
4352
f7a71197
AK		 4353 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4354 if (!best || best->eax < 0x80000008)
4355 goto not_found;
82725b20
DE		 4356 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4357 if (best)
4358 return best->eax & 0xff;
f7a71197 4359not_found:
82725b20
DE		 4360 return 36;
4361}
4362
d8017474
AG		 4363void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4364{
4365 u32 function, index;
4366 struct kvm_cpuid_entry2 *best;
4367
4368 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4369 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4370 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4371 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4372 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4373 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4374 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4375 if (best) {
5fdbf976
MT		 4376 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4377 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4378 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4379 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4380 }
8776e519 4381 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4382 trace_kvm_cpuid(function,
4383 kvm_register_read(vcpu, VCPU_REGS_RAX),
4384 kvm_register_read(vcpu, VCPU_REGS_RBX),
4385 kvm_register_read(vcpu, VCPU_REGS_RCX),
4386 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4387}
4388EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4389
b6c7a5dc
HB		 4390/*
4391 * Check if userspace requested an interrupt window, and that the
4392 * interrupt window is open.
4393 *
4394 * No need to exit to userspace if we already have an interrupt queued.
4395 */
851ba692 4396static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4397{
8061823a 4398 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4399 vcpu->run->request_interrupt_window &&
5df56646 4400 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4401}
4402
851ba692 4403static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4404{
851ba692
AK		 4405 struct kvm_run *kvm_run = vcpu->run;
4406
91586a3b 4407 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4408 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4409 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4410 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4411 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4412 else
b6c7a5dc 4413 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4414 kvm_arch_interrupt_allowed(vcpu) &&
4415 !kvm_cpu_has_interrupt(vcpu) &&
4416 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4417}
4418
b93463aa
AK		 4419static void vapic_enter(struct kvm_vcpu *vcpu)
4420{
4421 struct kvm_lapic *apic = vcpu->arch.apic;
4422 struct page *page;
4423
4424 if (!apic || !apic->vapic_addr)
4425 return;
4426
4427 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4428
4429 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4430}
4431
4432static void vapic_exit(struct kvm_vcpu *vcpu)
4433{
4434 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4435 int idx;
b93463aa
AK		 4436
4437 if (!apic || !apic->vapic_addr)
4438 return;
4439
f656ce01 4440 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4441 kvm_release_page_dirty(apic->vapic_page);
4442 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4443 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4444}
4445
95ba8273
GN		 4446static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4447{
4448 int max_irr, tpr;
4449
4450 if (!kvm_x86_ops->update_cr8_intercept)
4451 return;
4452
88c808fd
AK		 4453 if (!vcpu->arch.apic)
4454 return;
4455
8db3baa2
GN		 4456 if (!vcpu->arch.apic->vapic_addr)
4457 max_irr = kvm_lapic_find_highest_irr(vcpu);
4458 else
4459 max_irr = -1;
95ba8273
GN		 4460
4461 if (max_irr != -1)
4462 max_irr >>= 4;
4463
4464 tpr = kvm_lapic_get_cr8(vcpu);
4465
4466 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4467}
4468
851ba692 4469static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4470{
4471 /* try to reinject previous events if any */
b59bb7bd 4472 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4473 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4474 vcpu->arch.exception.has_error_code,
4475 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4476 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4477 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4478 vcpu->arch.exception.error_code,
4479 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4480 return;
4481 }
4482
95ba8273
GN		 4483 if (vcpu->arch.nmi_injected) {
4484 kvm_x86_ops->set_nmi(vcpu);
4485 return;
4486 }
4487
4488 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4489 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4490 return;
4491 }
4492
4493 /* try to inject new event if pending */
4494 if (vcpu->arch.nmi_pending) {
4495 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4496 vcpu->arch.nmi_pending = false;
4497 vcpu->arch.nmi_injected = true;
4498 kvm_x86_ops->set_nmi(vcpu);
4499 }
4500 } else if (kvm_cpu_has_interrupt(vcpu)) {
4501 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4502 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4503 false);
4504 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4505 }
4506 }
4507}
4508
851ba692 4509static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4510{
4511 int r;
6a8b1d13 4512 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4513 vcpu->run->request_interrupt_window;
b6c7a5dc 4514
2e53d63a
MT		 4515 if (vcpu->requests)
4516 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
4517 kvm_mmu_unload(vcpu);
4518
b6c7a5dc
HB		 4519 r = kvm_mmu_reload(vcpu);
4520 if (unlikely(r))
4521 goto out;
4522
2f52d58c
AK		 4523 if (vcpu->requests) {
4524 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 4525 __kvm_migrate_timers(vcpu);
c8076604
GH		 4526 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
4527 kvm_write_guest_time(vcpu);
4731d4c7
MT		 4528 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
4529 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 4530 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
4531 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 4532 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
4533 &vcpu->requests)) {
851ba692 4534 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4535 r = 0;
4536 goto out;
4537 }
71c4dfaf 4538 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4539 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4540 r = 0;
4541 goto out;
4542 }
02daab21
AK		 4543 if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
4544 vcpu->fpu_active = 0;
4545 kvm_x86_ops->fpu_deactivate(vcpu);
4546 }
2f52d58c 4547 }
b93463aa 4548
b6c7a5dc
HB		 4549 preempt_disable();
4550
4551 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4552 if (vcpu->fpu_active)
4553 kvm_load_guest_fpu(vcpu);
b6c7a5dc
HB		 4554
4555 local_irq_disable();
4556
32f88400
MT		 4557 clear_bit(KVM_REQ_KICK, &vcpu->requests);
4558 smp_mb__after_clear_bit();
4559
d7690175 4560 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 4561 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 4562 local_irq_enable();
4563 preempt_enable();
4564 r = 1;
4565 goto out;
4566 }
4567
851ba692 4568 inject_pending_event(vcpu);
b6c7a5dc 4569
6a8b1d13
GN		 4570 /* enable NMI/IRQ window open exits if needed */
4571 if (vcpu->arch.nmi_pending)
4572 kvm_x86_ops->enable_nmi_window(vcpu);
4573 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4574 kvm_x86_ops->enable_irq_window(vcpu);
4575
95ba8273 4576 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4577 update_cr8_intercept(vcpu);
4578 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4579 }
b93463aa 4580
f656ce01 4581 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4582
b6c7a5dc
HB		 4583 kvm_guest_enter();
4584
42dbaa5a 4585 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4586 set_debugreg(0, 7);
4587 set_debugreg(vcpu->arch.eff_db[0], 0);
4588 set_debugreg(vcpu->arch.eff_db[1], 1);
4589 set_debugreg(vcpu->arch.eff_db[2], 2);
4590 set_debugreg(vcpu->arch.eff_db[3], 3);
4591 }
b6c7a5dc 4592
229456fc 4593 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4594 kvm_x86_ops->run(vcpu);
b6c7a5dc 4595
24f1e32c
FW		 4596 /*
4597 * If the guest has used debug registers, at least dr7
4598 * will be disabled while returning to the host.
4599 * If we don't have active breakpoints in the host, we don't
4600 * care about the messed up debug address registers. But if
4601 * we have some of them active, restore the old state.
4602 */
59d8eb53 4603 if (hw_breakpoint_active())
24f1e32c 4604 hw_breakpoint_restore();
42dbaa5a 4605
32f88400 4606 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 4607 local_irq_enable();
4608
4609 ++vcpu->stat.exits;
4610
4611 /*
4612 * We must have an instruction between local_irq_enable() and
4613 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4614 * the interrupt shadow. The stat.exits increment will do nicely.
4615 * But we need to prevent reordering, hence this barrier():
4616 */
4617 barrier();
4618
4619 kvm_guest_exit();
4620
4621 preempt_enable();
4622
f656ce01 4623 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4624
b6c7a5dc
HB		 4625 /*
4626 * Profile KVM exit RIPs:
4627 */
4628 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4629 unsigned long rip = kvm_rip_read(vcpu);
4630 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4631 }
4632
298101da 4633
b93463aa
AK		 4634 kvm_lapic_sync_from_vapic(vcpu);
4635
851ba692 4636 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4637out:
4638 return r;
4639}
b6c7a5dc 4640
09cec754 4641
851ba692 4642static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4643{
4644 int r;
f656ce01 4645 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4646
4647 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4648 pr_debug("vcpu %d received sipi with vector # %x\n",
4649 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4650 kvm_lapic_reset(vcpu);
5f179287 4651 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4652 if (r)
4653 return r;
4654 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4655 }
4656
f656ce01 4657 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4658 vapic_enter(vcpu);
4659
4660 r = 1;
4661 while (r > 0) {
af2152f5 4662 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4663 r = vcpu_enter_guest(vcpu);
d7690175 4664 else {
f656ce01 4665 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4666 kvm_vcpu_block(vcpu);
f656ce01 4667 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4668 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4669 {
4670 switch(vcpu->arch.mp_state) {
4671 case KVM_MP_STATE_HALTED:
d7690175 4672 vcpu->arch.mp_state =
09cec754
GN		 4673 KVM_MP_STATE_RUNNABLE;
4674 case KVM_MP_STATE_RUNNABLE:
4675 break;
4676 case KVM_MP_STATE_SIPI_RECEIVED:
4677 default:
4678 r = -EINTR;
4679 break;
4680 }
4681 }
d7690175
MT		 4682 }
4683
09cec754
GN		 4684 if (r <= 0)
4685 break;
4686
4687 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4688 if (kvm_cpu_has_pending_timer(vcpu))
4689 kvm_inject_pending_timer_irqs(vcpu);
4690
851ba692 4691 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4692 r = -EINTR;
851ba692 4693 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4694 ++vcpu->stat.request_irq_exits;
4695 }
4696 if (signal_pending(current)) {
4697 r = -EINTR;
851ba692 4698 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4699 ++vcpu->stat.signal_exits;
4700 }
4701 if (need_resched()) {
f656ce01 4702 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4703 kvm_resched(vcpu);
f656ce01 4704 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4705 }
b6c7a5dc
HB		 4706 }
4707
f656ce01 4708 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 4709
b93463aa
AK		 4710 vapic_exit(vcpu);
4711
b6c7a5dc
HB		 4712 return r;
4713}
4714
4715int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4716{
4717 int r;
4718 sigset_t sigsaved;
4719
4720 vcpu_load(vcpu);
4721
ac9f6dc0
AK		 4722 if (vcpu->sigset_active)
4723 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4724
a4535290 4725 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4726 kvm_vcpu_block(vcpu);
d7690175 4727 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4728 r = -EAGAIN;
4729 goto out;
b6c7a5dc
HB		 4730 }
4731
b6c7a5dc
HB		 4732 /* re-sync apic's tpr */
4733 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4734 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4735
92bf9748
GN		 4736 if (vcpu->arch.pio.count || vcpu->mmio_needed ||
4737 vcpu->arch.emulate_ctxt.restart) {
4738 if (vcpu->mmio_needed) {
4739 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4740 vcpu->mmio_read_completed = 1;
4741 vcpu->mmio_needed = 0;
b6c7a5dc 4742 }
f656ce01 4743 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 4744 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 4745 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 4746 if (r == EMULATE_DO_MMIO) {
b6c7a5dc
HB		 4747 r = 0;
4748 goto out;
4749 }
4750 }
5fdbf976
MT		 4751 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4752 kvm_register_write(vcpu, VCPU_REGS_RAX,
4753 kvm_run->hypercall.ret);
b6c7a5dc 4754
851ba692 4755 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4756
4757out:
f1d86e46 4758 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 4759 if (vcpu->sigset_active)
4760 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4761
4762 vcpu_put(vcpu);
4763 return r;
4764}
4765
4766int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4767{
4768 vcpu_load(vcpu);
4769
5fdbf976
MT		 4770 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4771 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4772 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4773 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4774 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4775 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4776 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4777 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4778#ifdef CONFIG_X86_64
5fdbf976
MT		 4779 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4780 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4781 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4782 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4783 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4784 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4785 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4786 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4787#endif
4788
5fdbf976 4789 regs->rip = kvm_rip_read(vcpu);
91586a3b 4790 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4791
4792 vcpu_put(vcpu);
4793
4794 return 0;
4795}
4796
4797int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4798{
4799 vcpu_load(vcpu);
4800
5fdbf976
MT		 4801 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4802 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4803 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4804 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4805 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4806 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4807 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4808 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4809#ifdef CONFIG_X86_64
5fdbf976
MT		 4810 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4811 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4812 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4813 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4814 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4815 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4816 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4817 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4818#endif
4819
5fdbf976 4820 kvm_rip_write(vcpu, regs->rip);
91586a3b 4821 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4822
b4f14abd
JK		 4823 vcpu->arch.exception.pending = false;
4824
b6c7a5dc
HB		 4825 vcpu_put(vcpu);
4826
4827 return 0;
4828}
4829
b6c7a5dc
HB		 4830void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4831{
4832 struct kvm_segment cs;
4833
3e6e0aab 4834 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4835 *db = cs.db;
4836 *l = cs.l;
4837}
4838EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4839
4840int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4841 struct kvm_sregs *sregs)
4842{
89a27f4d 4843 struct desc_ptr dt;
b6c7a5dc
HB		 4844
4845 vcpu_load(vcpu);
4846
3e6e0aab
GT		 4847 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4848 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4849 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4850 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4851 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4852 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4853
3e6e0aab
GT		 4854 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4855 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4856
4857 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 4858 sregs->idt.limit = dt.size;
4859 sregs->idt.base = dt.address;
b6c7a5dc 4860 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 4861 sregs->gdt.limit = dt.size;
4862 sregs->gdt.base = dt.address;
b6c7a5dc 4863
4d4ec087 4864 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4865 sregs->cr2 = vcpu->arch.cr2;
4866 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4867 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4868 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 4869 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 4870 sregs->apic_base = kvm_get_apic_base(vcpu);
4871
923c61bb 4872 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4873
36752c9b 4874 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4875 set_bit(vcpu->arch.interrupt.nr,
4876 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4877
b6c7a5dc
HB		 4878 vcpu_put(vcpu);
4879
4880 return 0;
4881}
4882
62d9f0db
MT		 4883int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4884 struct kvm_mp_state *mp_state)
4885{
4886 vcpu_load(vcpu);
4887 mp_state->mp_state = vcpu->arch.mp_state;
4888 vcpu_put(vcpu);
4889 return 0;
4890}
4891
4892int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4893 struct kvm_mp_state *mp_state)
4894{
4895 vcpu_load(vcpu);
4896 vcpu->arch.mp_state = mp_state->mp_state;
4897 vcpu_put(vcpu);
4898 return 0;
4899}
4900
e269fb21
JK		 4901int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
4902 bool has_error_code, u32 error_code)
b6c7a5dc 4903{
ceffb459
GN		 4904 int cs_db, cs_l, ret;
4905 cache_all_regs(vcpu);
37817f29 4906
ceffb459 4907 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
e01c2426 4908
ceffb459
GN		 4909 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4910 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4911 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4912 vcpu->arch.emulate_ctxt.mode =
4913 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4914 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4915 ? X86EMUL_MODE_VM86 : cs_l
4916 ? X86EMUL_MODE_PROT64 : cs_db
4917 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
c697518a 4918
ceffb459 4919 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt, &emulate_ops,
e269fb21
JK		 4920 tss_selector, reason, has_error_code,
4921 error_code);
c697518a 4922
c697518a 4923 if (ret)
19d04437 4924 return EMULATE_FAIL;
37817f29 4925
19d04437
GN		 4926 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4927 return EMULATE_DONE;
37817f29
IE		 4928}
4929EXPORT_SYMBOL_GPL(kvm_task_switch);
4930
b6c7a5dc
HB		 4931int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4932 struct kvm_sregs *sregs)
4933{
4934 int mmu_reset_needed = 0;
923c61bb 4935 int pending_vec, max_bits;
89a27f4d 4936 struct desc_ptr dt;
b6c7a5dc
HB		 4937
4938 vcpu_load(vcpu);
4939
89a27f4d
GN		 4940 dt.size = sregs->idt.limit;
4941 dt.address = sregs->idt.base;
b6c7a5dc 4942 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 4943 dt.size = sregs->gdt.limit;
4944 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 4945 kvm_x86_ops->set_gdt(vcpu, &dt);
4946
ad312c7c
ZX		 4947 vcpu->arch.cr2 = sregs->cr2;
4948 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4949 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4950
2d3ad1f4 4951 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4952
f6801dff 4953 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 4954 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4955 kvm_set_apic_base(vcpu, sregs->apic_base);
4956
4d4ec087 4957 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 4958 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4959 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4960
fc78f519 4961 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 4962 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 4963 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 4964 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 4965 mmu_reset_needed = 1;
4966 }
b6c7a5dc
HB		 4967
4968 if (mmu_reset_needed)
4969 kvm_mmu_reset_context(vcpu);
4970
923c61bb
GN		 4971 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4972 pending_vec = find_first_bit(
4973 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4974 if (pending_vec < max_bits) {
66fd3f7f 4975 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4976 pr_debug("Set back pending irq %d\n", pending_vec);
4977 if (irqchip_in_kernel(vcpu->kvm))
4978 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4979 }
4980
3e6e0aab
GT		 4981 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4982 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4983 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4984 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4985 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4986 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4987
3e6e0aab
GT		 4988 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4989 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4990
5f0269f5
ME		 4991 update_cr8_intercept(vcpu);
4992
9c3e4aab 4993 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4994 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 4995 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 4996 !is_protmode(vcpu))
9c3e4aab
MT		 4997 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4998
b6c7a5dc
HB		 4999 vcpu_put(vcpu);
5000
5001 return 0;
5002}
5003
d0bfb940
JK		 5004int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5005 struct kvm_guest_debug *dbg)
b6c7a5dc 5006{
355be0b9 5007 unsigned long rflags;
ae675ef0 5008 int i, r;
b6c7a5dc
HB		 5009
5010 vcpu_load(vcpu);
5011
4f926bf2
JK		 5012 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5013 r = -EBUSY;
5014 if (vcpu->arch.exception.pending)
5015 goto unlock_out;
5016 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5017 kvm_queue_exception(vcpu, DB_VECTOR);
5018 else
5019 kvm_queue_exception(vcpu, BP_VECTOR);
5020 }
5021
91586a3b
JK		 5022 /*
5023 * Read rflags as long as potentially injected trace flags are still
5024 * filtered out.
5025 */
5026 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5027
5028 vcpu->guest_debug = dbg->control;
5029 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5030 vcpu->guest_debug = 0;
5031
5032 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5033 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5034 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5035 vcpu->arch.switch_db_regs =
5036 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5037 } else {
5038 for (i = 0; i < KVM_NR_DB_REGS; i++)
5039 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5040 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5041 }
5042
f92653ee
JK		 5043 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5044 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5045 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5046
91586a3b
JK		 5047 /*
5048 * Trigger an rflags update that will inject or remove the trace
5049 * flags.
5050 */
5051 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5052
355be0b9 5053 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5054
4f926bf2 5055 r = 0;
d0bfb940 5056
4f926bf2 5057unlock_out:
b6c7a5dc
HB		 5058 vcpu_put(vcpu);
5059
5060 return r;
5061}
5062
d0752060
HB		 5063/*
5064 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
5065 * we have asm/x86/processor.h
5066 */
5067struct fxsave {
5068 u16 cwd;
5069 u16 swd;
5070 u16 twd;
5071 u16 fop;
5072 u64 rip;
5073 u64 rdp;
5074 u32 mxcsr;
5075 u32 mxcsr_mask;
5076 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
5077#ifdef CONFIG_X86_64
5078 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
5079#else
5080 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
5081#endif
5082};
5083
8b006791
ZX		 5084/*
5085 * Translate a guest virtual address to a guest physical address.
5086 */
5087int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5088 struct kvm_translation *tr)
5089{
5090 unsigned long vaddr = tr->linear_address;
5091 gpa_t gpa;
f656ce01 5092 int idx;
8b006791
ZX		 5093
5094 vcpu_load(vcpu);
f656ce01 5095 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5096 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5097 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5098 tr->physical_address = gpa;
5099 tr->valid = gpa != UNMAPPED_GVA;
5100 tr->writeable = 1;
5101 tr->usermode = 0;
8b006791
ZX		 5102 vcpu_put(vcpu);
5103
5104 return 0;
5105}
5106
d0752060
HB		 5107int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5108{
ad312c7c 5109 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5110
5111 vcpu_load(vcpu);
5112
5113 memcpy(fpu->fpr, fxsave->st_space, 128);
5114 fpu->fcw = fxsave->cwd;
5115 fpu->fsw = fxsave->swd;
5116 fpu->ftwx = fxsave->twd;
5117 fpu->last_opcode = fxsave->fop;
5118 fpu->last_ip = fxsave->rip;
5119 fpu->last_dp = fxsave->rdp;
5120 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5121
5122 vcpu_put(vcpu);
5123
5124 return 0;
5125}
5126
5127int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5128{
ad312c7c 5129 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5130
5131 vcpu_load(vcpu);
5132
5133 memcpy(fxsave->st_space, fpu->fpr, 128);
5134 fxsave->cwd = fpu->fcw;
5135 fxsave->swd = fpu->fsw;
5136 fxsave->twd = fpu->ftwx;
5137 fxsave->fop = fpu->last_opcode;
5138 fxsave->rip = fpu->last_ip;
5139 fxsave->rdp = fpu->last_dp;
5140 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5141
5142 vcpu_put(vcpu);
5143
5144 return 0;
5145}
5146
5147void fx_init(struct kvm_vcpu *vcpu)
5148{
5149 unsigned after_mxcsr_mask;
5150
bc1a34f1
AA		 5151 /*
5152 * Touch the fpu the first time in non atomic context as if
5153 * this is the first fpu instruction the exception handler
5154 * will fire before the instruction returns and it'll have to
5155 * allocate ram with GFP_KERNEL.
5156 */
5157 if (!used_math())
d6e88aec 5158 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 5159
d0752060
HB		 5160 /* Initialize guest FPU by resetting ours and saving into guest's */
5161 preempt_disable();
d6e88aec
AK		 5162 kvm_fx_save(&vcpu->arch.host_fx_image);
5163 kvm_fx_finit();
5164 kvm_fx_save(&vcpu->arch.guest_fx_image);
5165 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 5166 preempt_enable();
5167
ad312c7c 5168 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5169 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5170 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5171 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5172 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5173}
5174EXPORT_SYMBOL_GPL(fx_init);
5175
5176void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5177{
2608d7a1 5178 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5179 return;
5180
5181 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 5182 kvm_fx_save(&vcpu->arch.host_fx_image);
5183 kvm_fx_restore(&vcpu->arch.guest_fx_image);
0c04851c 5184 trace_kvm_fpu(1);
d0752060 5185}
d0752060
HB		 5186
5187void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5188{
5189 if (!vcpu->guest_fpu_loaded)
5190 return;
5191
5192 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 5193 kvm_fx_save(&vcpu->arch.guest_fx_image);
5194 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 5195 ++vcpu->stat.fpu_reload;
02daab21 5196 set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
0c04851c 5197 trace_kvm_fpu(0);
d0752060 5198}
e9b11c17
ZX		 5199
5200void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5201{
7f1ea208
JR		 5202 if (vcpu->arch.time_page) {
5203 kvm_release_page_dirty(vcpu->arch.time_page);
5204 vcpu->arch.time_page = NULL;
5205 }
5206
e9b11c17
ZX		 5207 kvm_x86_ops->vcpu_free(vcpu);
5208}
5209
5210struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5211 unsigned int id)
5212{
26e5215f
AK		 5213 return kvm_x86_ops->vcpu_create(kvm, id);
5214}
e9b11c17 5215
26e5215f
AK		 5216int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5217{
5218 int r;
e9b11c17
ZX		 5219
5220 /* We do fxsave: this must be aligned. */
ad312c7c 5221 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5222
0bed3b56 5223 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5224 vcpu_load(vcpu);
5225 r = kvm_arch_vcpu_reset(vcpu);
5226 if (r == 0)
5227 r = kvm_mmu_setup(vcpu);
5228 vcpu_put(vcpu);
5229 if (r < 0)
5230 goto free_vcpu;
5231
26e5215f 5232 return 0;
e9b11c17
ZX		 5233free_vcpu:
5234 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5235 return r;
e9b11c17
ZX		 5236}
5237
d40ccc62 5238void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5239{
5240 vcpu_load(vcpu);
5241 kvm_mmu_unload(vcpu);
5242 vcpu_put(vcpu);
5243
5244 kvm_x86_ops->vcpu_free(vcpu);
5245}
5246
5247int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5248{
448fa4a9
JK		 5249 vcpu->arch.nmi_pending = false;
5250 vcpu->arch.nmi_injected = false;
5251
42dbaa5a
JK		 5252 vcpu->arch.switch_db_regs = 0;
5253 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5254 vcpu->arch.dr6 = DR6_FIXED_1;
5255 vcpu->arch.dr7 = DR7_FIXED_1;
5256
e9b11c17
ZX		 5257 return kvm_x86_ops->vcpu_reset(vcpu);
5258}
5259
10474ae8 5260int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5261{
0cca7907
ZA		 5262 /*
5263 * Since this may be called from a hotplug notifcation,
5264 * we can't get the CPU frequency directly.
5265 */
5266 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5267 int cpu = raw_smp_processor_id();
5268 per_cpu(cpu_tsc_khz, cpu) = 0;
5269 }
18863bdd
AK		 5270
5271 kvm_shared_msr_cpu_online();
5272
10474ae8 5273 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5274}
5275
5276void kvm_arch_hardware_disable(void *garbage)
5277{
5278 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5279 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5280}
5281
5282int kvm_arch_hardware_setup(void)
5283{
5284 return kvm_x86_ops->hardware_setup();
5285}
5286
5287void kvm_arch_hardware_unsetup(void)
5288{
5289 kvm_x86_ops->hardware_unsetup();
5290}
5291
5292void kvm_arch_check_processor_compat(void *rtn)
5293{
5294 kvm_x86_ops->check_processor_compatibility(rtn);
5295}
5296
5297int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5298{
5299 struct page *page;
5300 struct kvm *kvm;
5301 int r;
5302
5303 BUG_ON(vcpu->kvm == NULL);
5304 kvm = vcpu->kvm;
5305
ad312c7c 5306 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5307 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5308 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5309 else
a4535290 5310 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5311
5312 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5313 if (!page) {
5314 r = -ENOMEM;
5315 goto fail;
5316 }
ad312c7c 5317 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5318
5319 r = kvm_mmu_create(vcpu);
5320 if (r < 0)
5321 goto fail_free_pio_data;
5322
5323 if (irqchip_in_kernel(kvm)) {
5324 r = kvm_create_lapic(vcpu);
5325 if (r < 0)
5326 goto fail_mmu_destroy;
5327 }
5328
890ca9ae
HY		 5329 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5330 GFP_KERNEL);
5331 if (!vcpu->arch.mce_banks) {
5332 r = -ENOMEM;
443c39bc 5333 goto fail_free_lapic;
890ca9ae
HY		 5334 }
5335 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5336
e9b11c17 5337 return 0;
443c39bc
WY		 5338fail_free_lapic:
5339 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5340fail_mmu_destroy:
5341 kvm_mmu_destroy(vcpu);
5342fail_free_pio_data:
ad312c7c 5343 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5344fail:
5345 return r;
5346}
5347
5348void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5349{
f656ce01
MT		 5350 int idx;
5351
36cb93fd 5352 kfree(vcpu->arch.mce_banks);
e9b11c17 5353 kvm_free_lapic(vcpu);
f656ce01 5354 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5355 kvm_mmu_destroy(vcpu);
f656ce01 5356 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5357 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5358}
d19a9cd2
ZX		 5359
5360struct kvm *kvm_arch_create_vm(void)
5361{
5362 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5363
5364 if (!kvm)
5365 return ERR_PTR(-ENOMEM);
5366
fef9cce0
MT		 5367 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5368 if (!kvm->arch.aliases) {
5369 kfree(kvm);
5370 return ERR_PTR(-ENOMEM);
5371 }
5372
f05e70ac 5373 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5374 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5375
5550af4d
SY		 5376 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5377 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5378
53f658b3
MT		 5379 rdtscll(kvm->arch.vm_init_tsc);
5380
d19a9cd2
ZX		 5381 return kvm;
5382}
5383
5384static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5385{
5386 vcpu_load(vcpu);
5387 kvm_mmu_unload(vcpu);
5388 vcpu_put(vcpu);
5389}
5390
5391static void kvm_free_vcpus(struct kvm *kvm)
5392{
5393 unsigned int i;
988a2cae 5394 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5395
5396 /*
5397 * Unpin any mmu pages first.
5398 */
988a2cae
GN		 5399 kvm_for_each_vcpu(i, vcpu, kvm)
5400 kvm_unload_vcpu_mmu(vcpu);
5401 kvm_for_each_vcpu(i, vcpu, kvm)
5402 kvm_arch_vcpu_free(vcpu);
5403
5404 mutex_lock(&kvm->lock);
5405 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5406 kvm->vcpus[i] = NULL;
d19a9cd2 5407
988a2cae
GN		 5408 atomic_set(&kvm->online_vcpus, 0);
5409 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5410}
5411
ad8ba2cd
SY		 5412void kvm_arch_sync_events(struct kvm *kvm)
5413{
ba4cef31 5414 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5415}
5416
d19a9cd2
ZX		 5417void kvm_arch_destroy_vm(struct kvm *kvm)
5418{
6eb55818 5419 kvm_iommu_unmap_guest(kvm);
7837699f 5420 kvm_free_pit(kvm);
d7deeeb0
ZX		 5421 kfree(kvm->arch.vpic);
5422 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5423 kvm_free_vcpus(kvm);
5424 kvm_free_physmem(kvm);
3d45830c
AK		 5425 if (kvm->arch.apic_access_page)
5426 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5427 if (kvm->arch.ept_identity_pagetable)
5428 put_page(kvm->arch.ept_identity_pagetable);
64749204 5429 cleanup_srcu_struct(&kvm->srcu);
fef9cce0 5430 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5431 kfree(kvm);
5432}
0de10343 5433
f7784b8e
MT		 5434int kvm_arch_prepare_memory_region(struct kvm *kvm,
5435 struct kvm_memory_slot *memslot,
0de10343 5436 struct kvm_memory_slot old,
f7784b8e 5437 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5438 int user_alloc)
5439{
f7784b8e 5440 int npages = memslot->npages;
0de10343
ZX		 5441
5442 /*To keep backward compatibility with older userspace,
5443 *x86 needs to hanlde !user_alloc case.
5444 */
5445 if (!user_alloc) {
5446 if (npages && !old.rmap) {
604b38ac
AA		 5447 unsigned long userspace_addr;
5448
72dc67a6 5449 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5450 userspace_addr = do_mmap(NULL, 0,
5451 npages * PAGE_SIZE,
5452 PROT_READ | PROT_WRITE,
acee3c04 5453 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5454 0);
72dc67a6 5455 up_write(&current->mm->mmap_sem);
0de10343 5456
604b38ac
AA		 5457 if (IS_ERR((void *)userspace_addr))
5458 return PTR_ERR((void *)userspace_addr);
5459
604b38ac 5460 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5461 }
5462 }
5463
f7784b8e
MT		 5464
5465 return 0;
5466}
5467
5468void kvm_arch_commit_memory_region(struct kvm *kvm,
5469 struct kvm_userspace_memory_region *mem,
5470 struct kvm_memory_slot old,
5471 int user_alloc)
5472{
5473
5474 int npages = mem->memory_size >> PAGE_SHIFT;
5475
5476 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5477 int ret;
5478
5479 down_write(&current->mm->mmap_sem);
5480 ret = do_munmap(current->mm, old.userspace_addr,
5481 old.npages * PAGE_SIZE);
5482 up_write(&current->mm->mmap_sem);
5483 if (ret < 0)
5484 printk(KERN_WARNING
5485 "kvm_vm_ioctl_set_memory_region: "
5486 "failed to munmap memory\n");
5487 }
5488
7c8a83b7 5489 spin_lock(&kvm->mmu_lock);
f05e70ac 5490 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5491 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5492 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5493 }
5494
5495 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5496 spin_unlock(&kvm->mmu_lock);
0de10343 5497}
1d737c8a 5498
34d4cb8f
MT		 5499void kvm_arch_flush_shadow(struct kvm *kvm)
5500{
5501 kvm_mmu_zap_all(kvm);
8986ecc0 5502 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5503}
5504
1d737c8a
ZX		 5505int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5506{
a4535290 5507 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5508 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5509 || vcpu->arch.nmi_pending ||
5510 (kvm_arch_interrupt_allowed(vcpu) &&
5511 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5512}
5736199a 5513
5736199a
ZX		 5514void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5515{
32f88400
MT		 5516 int me;
5517 int cpu = vcpu->cpu;
5736199a
ZX		 5518
5519 if (waitqueue_active(&vcpu->wq)) {
5520 wake_up_interruptible(&vcpu->wq);
5521 ++vcpu->stat.halt_wakeup;
5522 }
32f88400
MT		 5523
5524 me = get_cpu();
5525 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5526 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5527 smp_send_reschedule(cpu);
e9571ed5 5528 put_cpu();
5736199a 5529}
78646121
GN		 5530
5531int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5532{
5533 return kvm_x86_ops->interrupt_allowed(vcpu);
5534}
229456fc 5535
f92653ee
JK		 5536bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5537{
5538 unsigned long current_rip = kvm_rip_read(vcpu) +
5539 get_segment_base(vcpu, VCPU_SREG_CS);
5540
5541 return current_rip == linear_rip;
5542}
5543EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5544
94fe45da
JK		 5545unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5546{
5547 unsigned long rflags;
5548
5549 rflags = kvm_x86_ops->get_rflags(vcpu);
5550 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5551 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5552 return rflags;
5553}
5554EXPORT_SYMBOL_GPL(kvm_get_rflags);
5555
5556void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5557{
5558 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5559 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 5560 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 5561 kvm_x86_ops->set_rflags(vcpu, rflags);
5562}
5563EXPORT_SYMBOL_GPL(kvm_set_rflags);
5564
229456fc
MT		 5565EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5566EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5567EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5568EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5569EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5570EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5571EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5572EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5573EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5574EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5575EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 5576EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kernel source for telekom puls (alcatel/mediatek)