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KVM: MMU: Add infrastructure for two-level page walker
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
221d059d 9 * Copyright 2010 Red Hat, Inc. and/or its affilates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
aec51dc4 46#include <trace/events/kvm.h>
2ed152af 47
229456fc
MT		 48#define CREATE_TRACE_POINTS
49#include "trace.h"
043405e1 50
24f1e32c 51#include <asm/debugreg.h>
d825ed0a 52#include <asm/msr.h>
a5f61300 53#include <asm/desc.h>
0bed3b56 54#include <asm/mtrr.h>
890ca9ae 55#include <asm/mce.h>
7cf30855 56#include <asm/i387.h>
98918833 57#include <asm/xcr.h>
1d5f066e 58#include <asm/pvclock.h>
217fc9cf 59#include <asm/div64.h>
043405e1 60
313a3dc7 61#define MAX_IO_MSRS 256
a03490ed
CO		 62#define CR0_RESERVED_BITS \
63 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
64 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
65 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
66#define CR4_RESERVED_BITS \
67 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
68 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
69 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 70 | X86_CR4_OSXSAVE \
a03490ed
CO		 71 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
72
73#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 74
75#define KVM_MAX_MCE_BANKS 32
76#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
83static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
84#else
85static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
86#endif
313a3dc7 87
ba1389b7
AK		 88#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
89#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 90
cb142eb7 91static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 92static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
93 struct kvm_cpuid_entry2 __user *entries);
94
97896d04 95struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 96EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 97
ed85c068
AP		 98int ignore_msrs = 0;
99module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
100
18863bdd
AK		 101#define KVM_NR_SHARED_MSRS 16
102
103struct kvm_shared_msrs_global {
104 int nr;
2bf78fa7 105 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 106};
107
108struct kvm_shared_msrs {
109 struct user_return_notifier urn;
110 bool registered;
2bf78fa7
SY		 111 struct kvm_shared_msr_values {
112 u64 host;
113 u64 curr;
114 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 115};
116
117static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
118static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
119
417bc304 120struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 121 { "pf_fixed", VCPU_STAT(pf_fixed) },
122 { "pf_guest", VCPU_STAT(pf_guest) },
123 { "tlb_flush", VCPU_STAT(tlb_flush) },
124 { "invlpg", VCPU_STAT(invlpg) },
125 { "exits", VCPU_STAT(exits) },
126 { "io_exits", VCPU_STAT(io_exits) },
127 { "mmio_exits", VCPU_STAT(mmio_exits) },
128 { "signal_exits", VCPU_STAT(signal_exits) },
129 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 130 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 131 { "halt_exits", VCPU_STAT(halt_exits) },
132 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 133 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 134 { "request_irq", VCPU_STAT(request_irq_exits) },
135 { "irq_exits", VCPU_STAT(irq_exits) },
136 { "host_state_reload", VCPU_STAT(host_state_reload) },
137 { "efer_reload", VCPU_STAT(efer_reload) },
138 { "fpu_reload", VCPU_STAT(fpu_reload) },
139 { "insn_emulation", VCPU_STAT(insn_emulation) },
140 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 141 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 142 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 143 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
144 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
145 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
146 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
147 { "mmu_flooded", VM_STAT(mmu_flooded) },
148 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 149 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 150 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 151 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 152 { "largepages", VM_STAT(lpages) },
417bc304
HB		 153 { NULL }
154};
155
2acf923e
DC		 156u64 __read_mostly host_xcr0;
157
158static inline u32 bit(int bitno)
159{
160 return 1 << (bitno & 31);
161}
162
18863bdd
AK		 163static void kvm_on_user_return(struct user_return_notifier *urn)
164{
165 unsigned slot;
18863bdd
AK		 166 struct kvm_shared_msrs *locals
167 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 168 struct kvm_shared_msr_values *values;
18863bdd
AK		 169
170 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 171 values = &locals->values[slot];
172 if (values->host != values->curr) {
173 wrmsrl(shared_msrs_global.msrs[slot], values->host);
174 values->curr = values->host;
18863bdd
AK		 175 }
176 }
177 locals->registered = false;
178 user_return_notifier_unregister(urn);
179}
180
2bf78fa7 181static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 182{
2bf78fa7 183 struct kvm_shared_msrs *smsr;
18863bdd
AK		 184 u64 value;
185
2bf78fa7
SY		 186 smsr = &__get_cpu_var(shared_msrs);
187 /* only read, and nobody should modify it at this time,
188 * so don't need lock */
189 if (slot >= shared_msrs_global.nr) {
190 printk(KERN_ERR "kvm: invalid MSR slot!");
191 return;
192 }
193 rdmsrl_safe(msr, &value);
194 smsr->values[slot].host = value;
195 smsr->values[slot].curr = value;
196}
197
198void kvm_define_shared_msr(unsigned slot, u32 msr)
199{
18863bdd
AK		 200 if (slot >= shared_msrs_global.nr)
201 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 202 shared_msrs_global.msrs[slot] = msr;
203 /* we need ensured the shared_msr_global have been updated */
204 smp_wmb();
18863bdd
AK		 205}
206EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
207
208static void kvm_shared_msr_cpu_online(void)
209{
210 unsigned i;
18863bdd
AK		 211
212 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 213 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 214}
215
d5696725 216void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 217{
218 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
219
2bf78fa7 220 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 221 return;
2bf78fa7
SY		 222 smsr->values[slot].curr = value;
223 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 224 if (!smsr->registered) {
225 smsr->urn.on_user_return = kvm_on_user_return;
226 user_return_notifier_register(&smsr->urn);
227 smsr->registered = true;
228 }
229}
230EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
231
3548bab5
AK		 232static void drop_user_return_notifiers(void *ignore)
233{
234 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
235
236 if (smsr->registered)
237 kvm_on_user_return(&smsr->urn);
238}
239
6866b83e
CO		 240u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
241{
242 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 243 return vcpu->arch.apic_base;
6866b83e 244 else
ad312c7c 245 return vcpu->arch.apic_base;
6866b83e
CO		 246}
247EXPORT_SYMBOL_GPL(kvm_get_apic_base);
248
249void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
250{
251 /* TODO: reserve bits check */
252 if (irqchip_in_kernel(vcpu->kvm))
253 kvm_lapic_set_base(vcpu, data);
254 else
ad312c7c 255 vcpu->arch.apic_base = data;
6866b83e
CO		 256}
257EXPORT_SYMBOL_GPL(kvm_set_apic_base);
258
3fd28fce
ED		 259#define EXCPT_BENIGN 0
260#define EXCPT_CONTRIBUTORY 1
261#define EXCPT_PF 2
262
263static int exception_class(int vector)
264{
265 switch (vector) {
266 case PF_VECTOR:
267 return EXCPT_PF;
268 case DE_VECTOR:
269 case TS_VECTOR:
270 case NP_VECTOR:
271 case SS_VECTOR:
272 case GP_VECTOR:
273 return EXCPT_CONTRIBUTORY;
274 default:
275 break;
276 }
277 return EXCPT_BENIGN;
278}
279
280static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 281 unsigned nr, bool has_error, u32 error_code,
282 bool reinject)
3fd28fce
ED		 283{
284 u32 prev_nr;
285 int class1, class2;
286
287 if (!vcpu->arch.exception.pending) {
288 queue:
289 vcpu->arch.exception.pending = true;
290 vcpu->arch.exception.has_error_code = has_error;
291 vcpu->arch.exception.nr = nr;
292 vcpu->arch.exception.error_code = error_code;
3f0fd292 293 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 294 return;
295 }
296
297 /* to check exception */
298 prev_nr = vcpu->arch.exception.nr;
299 if (prev_nr == DF_VECTOR) {
300 /* triple fault -> shutdown */
a8eeb04a 301 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 302 return;
303 }
304 class1 = exception_class(prev_nr);
305 class2 = exception_class(nr);
306 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
307 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
308 /* generate double fault per SDM Table 5-5 */
309 vcpu->arch.exception.pending = true;
310 vcpu->arch.exception.has_error_code = true;
311 vcpu->arch.exception.nr = DF_VECTOR;
312 vcpu->arch.exception.error_code = 0;
313 } else
314 /* replace previous exception with a new one in a hope
315 that instruction re-execution will regenerate lost
316 exception */
317 goto queue;
318}
319
298101da
AK		 320void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
321{
ce7ddec4 322 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 323}
324EXPORT_SYMBOL_GPL(kvm_queue_exception);
325
ce7ddec4
JR		 326void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
327{
328 kvm_multiple_exception(vcpu, nr, false, 0, true);
329}
330EXPORT_SYMBOL_GPL(kvm_requeue_exception);
331
8df25a32 332void kvm_inject_page_fault(struct kvm_vcpu *vcpu)
c3c91fee 333{
8df25a32
JR		 334 unsigned error_code = vcpu->arch.fault.error_code;
335
c3c91fee 336 ++vcpu->stat.pf_guest;
8df25a32 337 vcpu->arch.cr2 = vcpu->arch.fault.address;
c3c91fee
AK		 338 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
339}
340
3419ffc8
SY		 341void kvm_inject_nmi(struct kvm_vcpu *vcpu)
342{
343 vcpu->arch.nmi_pending = 1;
344}
345EXPORT_SYMBOL_GPL(kvm_inject_nmi);
346
298101da
AK		 347void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
348{
ce7ddec4 349 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 350}
351EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
352
ce7ddec4
JR		 353void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
354{
355 kvm_multiple_exception(vcpu, nr, true, error_code, true);
356}
357EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
358
0a79b009
AK		 359/*
360 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
361 * a #GP and return false.
362 */
363bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 364{
0a79b009
AK		 365 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
366 return true;
367 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
368 return false;
298101da 369}
0a79b009 370EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 371
a03490ed
CO		 372/*
373 * Load the pae pdptrs. Return true is they are all valid.
374 */
375int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
376{
377 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
378 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
379 int i;
380 int ret;
ad312c7c 381 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 382
a03490ed
CO		 383 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
384 offset * sizeof(u64), sizeof(pdpte));
385 if (ret < 0) {
386 ret = 0;
387 goto out;
388 }
389 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 390 if (is_present_gpte(pdpte[i]) &&
20c466b5 391 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 392 ret = 0;
393 goto out;
394 }
395 }
396 ret = 1;
397
ad312c7c 398 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 399 __set_bit(VCPU_EXREG_PDPTR,
400 (unsigned long *)&vcpu->arch.regs_avail);
401 __set_bit(VCPU_EXREG_PDPTR,
402 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 403out:
a03490ed
CO		 404
405 return ret;
406}
cc4b6871 407EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 408
d835dfec
AK		 409static bool pdptrs_changed(struct kvm_vcpu *vcpu)
410{
ad312c7c 411 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 412 bool changed = true;
413 int r;
414
415 if (is_long_mode(vcpu) || !is_pae(vcpu))
416 return false;
417
6de4f3ad
AK		 418 if (!test_bit(VCPU_EXREG_PDPTR,
419 (unsigned long *)&vcpu->arch.regs_avail))
420 return true;
421
ad312c7c 422 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 423 if (r < 0)
424 goto out;
ad312c7c 425 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 426out:
d835dfec
AK		 427
428 return changed;
429}
430
49a9b07e 431int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 432{
aad82703
SY		 433 unsigned long old_cr0 = kvm_read_cr0(vcpu);
434 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
435 X86_CR0_CD | X86_CR0_NW;
436
f9a48e6a
AK		 437 cr0 |= X86_CR0_ET;
438
ab344828 439#ifdef CONFIG_X86_64
0f12244f
GN		 440 if (cr0 & 0xffffffff00000000UL)
441 return 1;
ab344828
GN		 442#endif
443
444 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 445
0f12244f
GN		 446 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
447 return 1;
a03490ed 448
0f12244f
GN		 449 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
450 return 1;
a03490ed
CO		 451
452 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
453#ifdef CONFIG_X86_64
f6801dff 454 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 455 int cs_db, cs_l;
456
0f12244f
GN		 457 if (!is_pae(vcpu))
458 return 1;
a03490ed 459 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 460 if (cs_l)
461 return 1;
a03490ed
CO		 462 } else
463#endif
0f12244f
GN		 464 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3))
465 return 1;
a03490ed
CO		 466 }
467
468 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 469
aad82703
SY		 470 if ((cr0 ^ old_cr0) & update_bits)
471 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 472 return 0;
473}
2d3ad1f4 474EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 475
2d3ad1f4 476void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 477{
49a9b07e 478 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 479}
2d3ad1f4 480EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 481
2acf923e
DC		 482int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
483{
484 u64 xcr0;
485
486 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
487 if (index != XCR_XFEATURE_ENABLED_MASK)
488 return 1;
489 xcr0 = xcr;
490 if (kvm_x86_ops->get_cpl(vcpu) != 0)
491 return 1;
492 if (!(xcr0 & XSTATE_FP))
493 return 1;
494 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
495 return 1;
496 if (xcr0 & ~host_xcr0)
497 return 1;
498 vcpu->arch.xcr0 = xcr0;
499 vcpu->guest_xcr0_loaded = 0;
500 return 0;
501}
502
503int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
504{
505 if (__kvm_set_xcr(vcpu, index, xcr)) {
506 kvm_inject_gp(vcpu, 0);
507 return 1;
508 }
509 return 0;
510}
511EXPORT_SYMBOL_GPL(kvm_set_xcr);
512
513static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
514{
515 struct kvm_cpuid_entry2 *best;
516
517 best = kvm_find_cpuid_entry(vcpu, 1, 0);
518 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
519}
520
521static void update_cpuid(struct kvm_vcpu *vcpu)
522{
523 struct kvm_cpuid_entry2 *best;
524
525 best = kvm_find_cpuid_entry(vcpu, 1, 0);
526 if (!best)
527 return;
528
529 /* Update OSXSAVE bit */
530 if (cpu_has_xsave && best->function == 0x1) {
531 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
532 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
533 best->ecx |= bit(X86_FEATURE_OSXSAVE);
534 }
535}
536
a83b29c6 537int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 538{
fc78f519 539 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 540 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
541
0f12244f
GN		 542 if (cr4 & CR4_RESERVED_BITS)
543 return 1;
a03490ed 544
2acf923e
DC		 545 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
546 return 1;
547
a03490ed 548 if (is_long_mode(vcpu)) {
0f12244f
GN		 549 if (!(cr4 & X86_CR4_PAE))
550 return 1;
a2edf57f
AK		 551 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
552 && ((cr4 ^ old_cr4) & pdptr_bits)
0f12244f
GN		 553 && !load_pdptrs(vcpu, vcpu->arch.cr3))
554 return 1;
555
556 if (cr4 & X86_CR4_VMXE)
557 return 1;
a03490ed 558
a03490ed 559 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 560
aad82703
SY		 561 if ((cr4 ^ old_cr4) & pdptr_bits)
562 kvm_mmu_reset_context(vcpu);
0f12244f 563
2acf923e
DC		 564 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
565 update_cpuid(vcpu);
566
0f12244f
GN		 567 return 0;
568}
2d3ad1f4 569EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 570
2390218b 571int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 572{
ad312c7c 573 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 574 kvm_mmu_sync_roots(vcpu);
d835dfec 575 kvm_mmu_flush_tlb(vcpu);
0f12244f 576 return 0;
d835dfec
AK		 577 }
578
a03490ed 579 if (is_long_mode(vcpu)) {
0f12244f
GN		 580 if (cr3 & CR3_L_MODE_RESERVED_BITS)
581 return 1;
a03490ed
CO		 582 } else {
583 if (is_pae(vcpu)) {
0f12244f
GN		 584 if (cr3 & CR3_PAE_RESERVED_BITS)
585 return 1;
586 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3))
587 return 1;
a03490ed
CO		 588 }
589 /*
590 * We don't check reserved bits in nonpae mode, because
591 * this isn't enforced, and VMware depends on this.
592 */
593 }
594
a03490ed
CO		 595 /*
596 * Does the new cr3 value map to physical memory? (Note, we
597 * catch an invalid cr3 even in real-mode, because it would
598 * cause trouble later on when we turn on paging anyway.)
599 *
600 * A real CPU would silently accept an invalid cr3 and would
601 * attempt to use it - with largely undefined (and often hard
602 * to debug) behavior on the guest side.
603 */
604 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 605 return 1;
606 vcpu->arch.cr3 = cr3;
607 vcpu->arch.mmu.new_cr3(vcpu);
608 return 0;
609}
2d3ad1f4 610EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 611
0f12244f 612int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 613{
0f12244f
GN		 614 if (cr8 & CR8_RESERVED_BITS)
615 return 1;
a03490ed
CO		 616 if (irqchip_in_kernel(vcpu->kvm))
617 kvm_lapic_set_tpr(vcpu, cr8);
618 else
ad312c7c 619 vcpu->arch.cr8 = cr8;
0f12244f
GN		 620 return 0;
621}
622
623void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
624{
625 if (__kvm_set_cr8(vcpu, cr8))
626 kvm_inject_gp(vcpu, 0);
a03490ed 627}
2d3ad1f4 628EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 629
2d3ad1f4 630unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 631{
632 if (irqchip_in_kernel(vcpu->kvm))
633 return kvm_lapic_get_cr8(vcpu);
634 else
ad312c7c 635 return vcpu->arch.cr8;
a03490ed 636}
2d3ad1f4 637EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 638
338dbc97 639static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 640{
641 switch (dr) {
642 case 0 ... 3:
643 vcpu->arch.db[dr] = val;
644 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
645 vcpu->arch.eff_db[dr] = val;
646 break;
647 case 4:
338dbc97
GN		 648 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
649 return 1; /* #UD */
020df079
GN		 650 /* fall through */
651 case 6:
338dbc97
GN		 652 if (val & 0xffffffff00000000ULL)
653 return -1; /* #GP */
020df079
GN		 654 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
655 break;
656 case 5:
338dbc97
GN		 657 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
658 return 1; /* #UD */
020df079
GN		 659 /* fall through */
660 default: /* 7 */
338dbc97
GN		 661 if (val & 0xffffffff00000000ULL)
662 return -1; /* #GP */
020df079
GN		 663 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
664 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
665 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
666 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
667 }
668 break;
669 }
670
671 return 0;
672}
338dbc97
GN		 673
674int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
675{
676 int res;
677
678 res = __kvm_set_dr(vcpu, dr, val);
679 if (res > 0)
680 kvm_queue_exception(vcpu, UD_VECTOR);
681 else if (res < 0)
682 kvm_inject_gp(vcpu, 0);
683
684 return res;
685}
020df079
GN		 686EXPORT_SYMBOL_GPL(kvm_set_dr);
687
338dbc97 688static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 689{
690 switch (dr) {
691 case 0 ... 3:
692 *val = vcpu->arch.db[dr];
693 break;
694 case 4:
338dbc97 695 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 696 return 1;
020df079
GN		 697 /* fall through */
698 case 6:
699 *val = vcpu->arch.dr6;
700 break;
701 case 5:
338dbc97 702 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 703 return 1;
020df079
GN		 704 /* fall through */
705 default: /* 7 */
706 *val = vcpu->arch.dr7;
707 break;
708 }
709
710 return 0;
711}
338dbc97
GN		 712
713int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
714{
715 if (_kvm_get_dr(vcpu, dr, val)) {
716 kvm_queue_exception(vcpu, UD_VECTOR);
717 return 1;
718 }
719 return 0;
720}
020df079
GN		 721EXPORT_SYMBOL_GPL(kvm_get_dr);
722
043405e1
CO		 723/*
724 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
725 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
726 *
727 * This list is modified at module load time to reflect the
e3267cbb
GC		 728 * capabilities of the host cpu. This capabilities test skips MSRs that are
729 * kvm-specific. Those are put in the beginning of the list.
043405e1 730 */
e3267cbb 731
11c6bffa 732#define KVM_SAVE_MSRS_BEGIN 7
043405e1 733static u32 msrs_to_save[] = {
e3267cbb 734 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 735 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 736 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 737 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1 738 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 739 MSR_STAR,
043405e1
CO		 740#ifdef CONFIG_X86_64
741 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
742#endif
e90aa41e 743 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 744};
745
746static unsigned num_msrs_to_save;
747
748static u32 emulated_msrs[] = {
749 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 750 MSR_IA32_MCG_STATUS,
751 MSR_IA32_MCG_CTL,
043405e1
CO		 752};
753
b69e8cae 754static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 755{
aad82703
SY		 756 u64 old_efer = vcpu->arch.efer;
757
b69e8cae
RJ		 758 if (efer & efer_reserved_bits)
759 return 1;
15c4a640
CO		 760
761 if (is_paging(vcpu)
b69e8cae
RJ		 762 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
763 return 1;
15c4a640 764
1b2fd70c
AG		 765 if (efer & EFER_FFXSR) {
766 struct kvm_cpuid_entry2 *feat;
767
768 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 769 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
770 return 1;
1b2fd70c
AG		 771 }
772
d8017474
AG		 773 if (efer & EFER_SVME) {
774 struct kvm_cpuid_entry2 *feat;
775
776 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 777 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
778 return 1;
d8017474
AG		 779 }
780
15c4a640 781 efer &= ~EFER_LMA;
f6801dff 782 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 783
a3d204e2
SY		 784 kvm_x86_ops->set_efer(vcpu, efer);
785
9645bb56
AK		 786 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
787 kvm_mmu_reset_context(vcpu);
b69e8cae 788
aad82703
SY		 789 /* Update reserved bits */
790 if ((efer ^ old_efer) & EFER_NX)
791 kvm_mmu_reset_context(vcpu);
792
b69e8cae 793 return 0;
15c4a640
CO		 794}
795
f2b4b7dd
JR		 796void kvm_enable_efer_bits(u64 mask)
797{
798 efer_reserved_bits &= ~mask;
799}
800EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
801
802
15c4a640
CO		 803/*
804 * Writes msr value into into the appropriate "register".
805 * Returns 0 on success, non-0 otherwise.
806 * Assumes vcpu_load() was already called.
807 */
808int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
809{
810 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
811}
812
313a3dc7
CO		 813/*
814 * Adapt set_msr() to msr_io()'s calling convention
815 */
816static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
817{
818 return kvm_set_msr(vcpu, index, *data);
819}
820
18068523
GOC		 821static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
822{
9ed3c444
AK		 823 int version;
824 int r;
50d0a0f9 825 struct pvclock_wall_clock wc;
923de3cf 826 struct timespec boot;
18068523
GOC		 827
828 if (!wall_clock)
829 return;
830
9ed3c444
AK		 831 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
832 if (r)
833 return;
834
835 if (version & 1)
836 ++version; /* first time write, random junk */
837
838 ++version;
18068523 839
18068523
GOC		 840 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
841
50d0a0f9
GH		 842 /*
843 * The guest calculates current wall clock time by adding
844 * system time (updated by kvm_write_guest_time below) to the
845 * wall clock specified here. guest system time equals host
846 * system time for us, thus we must fill in host boot time here.
847 */
923de3cf 848 getboottime(&boot);
50d0a0f9
GH		 849
850 wc.sec = boot.tv_sec;
851 wc.nsec = boot.tv_nsec;
852 wc.version = version;
18068523
GOC		 853
854 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
855
856 version++;
857 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 858}
859
50d0a0f9
GH		 860static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
861{
862 uint32_t quotient, remainder;
863
864 /* Don't try to replace with do_div(), this one calculates
865 * "(dividend << 32) / divisor" */
866 __asm__ ( "divl %4"
867 : "=a" (quotient), "=d" (remainder)
868 : "0" (0), "1" (dividend), "r" (divisor) );
869 return quotient;
870}
871
872static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
873{
874 uint64_t nsecs = 1000000000LL;
875 int32_t shift = 0;
876 uint64_t tps64;
877 uint32_t tps32;
878
879 tps64 = tsc_khz * 1000LL;
880 while (tps64 > nsecs*2) {
881 tps64 >>= 1;
882 shift--;
883 }
884
885 tps32 = (uint32_t)tps64;
886 while (tps32 <= (uint32_t)nsecs) {
887 tps32 <<= 1;
888 shift++;
889 }
890
891 hv_clock->tsc_shift = shift;
892 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
893
894 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 895 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 896 hv_clock->tsc_to_system_mul);
897}
898
759379dd
ZA		 899static inline u64 get_kernel_ns(void)
900{
901 struct timespec ts;
902
903 WARN_ON(preemptible());
904 ktime_get_ts(&ts);
905 monotonic_to_bootbased(&ts);
906 return timespec_to_ns(&ts);
907}
908
c8076604
GH		 909static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
910
8cfdc000
ZA		 911static inline int kvm_tsc_changes_freq(void)
912{
913 int cpu = get_cpu();
914 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
915 cpufreq_quick_get(cpu) != 0;
916 put_cpu();
917 return ret;
918}
919
759379dd
ZA		 920static inline u64 nsec_to_cycles(u64 nsec)
921{
217fc9cf
AK		 922 u64 ret;
923
759379dd
ZA		 924 WARN_ON(preemptible());
925 if (kvm_tsc_changes_freq())
926 printk_once(KERN_WARNING
927 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
217fc9cf
AK		 928 ret = nsec * __get_cpu_var(cpu_tsc_khz);
929 do_div(ret, USEC_PER_SEC);
930 return ret;
759379dd
ZA		 931}
932
99e3e30a
ZA		 933void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
934{
935 struct kvm *kvm = vcpu->kvm;
f38e098f 936 u64 offset, ns, elapsed;
99e3e30a 937 unsigned long flags;
46543ba4 938 s64 sdiff;
99e3e30a
ZA		 939
940 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
941 offset = data - native_read_tsc();
759379dd 942 ns = get_kernel_ns();
f38e098f 943 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 944 sdiff = data - kvm->arch.last_tsc_write;
945 if (sdiff < 0)
946 sdiff = -sdiff;
f38e098f
ZA		 947
948 /*
46543ba4 949 * Special case: close write to TSC within 5 seconds of
f38e098f 950 * another CPU is interpreted as an attempt to synchronize
46543ba4
ZA		 951 * The 5 seconds is to accomodate host load / swapping as
952 * well as any reset of TSC during the boot process.
f38e098f
ZA		 953 *
954 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 955 * or make a best guest using elapsed value.
f38e098f 956 */
46543ba4
ZA		 957 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
958 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 959 if (!check_tsc_unstable()) {
960 offset = kvm->arch.last_tsc_offset;
961 pr_debug("kvm: matched tsc offset for %llu\n", data);
962 } else {
759379dd
ZA		 963 u64 delta = nsec_to_cycles(elapsed);
964 offset += delta;
965 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 966 }
967 ns = kvm->arch.last_tsc_nsec;
968 }
969 kvm->arch.last_tsc_nsec = ns;
970 kvm->arch.last_tsc_write = data;
971 kvm->arch.last_tsc_offset = offset;
99e3e30a
ZA		 972 kvm_x86_ops->write_tsc_offset(vcpu, offset);
973 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
974
975 /* Reset of TSC must disable overshoot protection below */
976 vcpu->arch.hv_clock.tsc_timestamp = 0;
977}
978EXPORT_SYMBOL_GPL(kvm_write_tsc);
979
8cfdc000 980static int kvm_write_guest_time(struct kvm_vcpu *v)
18068523 981{
18068523
GOC		 982 unsigned long flags;
983 struct kvm_vcpu_arch *vcpu = &v->arch;
984 void *shared_kaddr;
463656c0 985 unsigned long this_tsc_khz;
1d5f066e
ZA		 986 s64 kernel_ns, max_kernel_ns;
987 u64 tsc_timestamp;
18068523
GOC		 988
989 if ((!vcpu->time_page))
8cfdc000 990 return 0;
50d0a0f9 991
18068523
GOC		 992 /* Keep irq disabled to prevent changes to the clock */
993 local_irq_save(flags);
1d5f066e 994 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 995 kernel_ns = get_kernel_ns();
8cfdc000 996 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
18068523
GOC		 997 local_irq_restore(flags);
998
8cfdc000
ZA		 999 if (unlikely(this_tsc_khz == 0)) {
1000 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
1001 return 1;
1002 }
18068523 1003
1d5f066e
ZA		 1004 /*
1005 * Time as measured by the TSC may go backwards when resetting the base
1006 * tsc_timestamp. The reason for this is that the TSC resolution is
1007 * higher than the resolution of the other clock scales. Thus, many
1008 * possible measurments of the TSC correspond to one measurement of any
1009 * other clock, and so a spread of values is possible. This is not a
1010 * problem for the computation of the nanosecond clock; with TSC rates
1011 * around 1GHZ, there can only be a few cycles which correspond to one
1012 * nanosecond value, and any path through this code will inevitably
1013 * take longer than that. However, with the kernel_ns value itself,
1014 * the precision may be much lower, down to HZ granularity. If the
1015 * first sampling of TSC against kernel_ns ends in the low part of the
1016 * range, and the second in the high end of the range, we can get:
1017 *
1018 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1019 *
1020 * As the sampling errors potentially range in the thousands of cycles,
1021 * it is possible such a time value has already been observed by the
1022 * guest. To protect against this, we must compute the system time as
1023 * observed by the guest and ensure the new system time is greater.
1024 */
1025 max_kernel_ns = 0;
1026 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1027 max_kernel_ns = vcpu->last_guest_tsc -
1028 vcpu->hv_clock.tsc_timestamp;
1029 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1030 vcpu->hv_clock.tsc_to_system_mul,
1031 vcpu->hv_clock.tsc_shift);
1032 max_kernel_ns += vcpu->last_kernel_ns;
1033 }
1034
e48672fa 1035 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
8cfdc000 1036 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
e48672fa 1037 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1038 }
1039
1d5f066e
ZA		 1040 if (max_kernel_ns > kernel_ns)
1041 kernel_ns = max_kernel_ns;
1042
8cfdc000 1043 /* With all the info we got, fill in the values */
1d5f066e 1044 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1045 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1046 vcpu->last_kernel_ns = kernel_ns;
371bcf64
GC		 1047 vcpu->hv_clock.flags = 0;
1048
18068523
GOC		 1049 /*
1050 * The interface expects us to write an even number signaling that the
1051 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1052 * state, we just increase by 2 at the end.
18068523 1053 */
50d0a0f9 1054 vcpu->hv_clock.version += 2;
18068523
GOC		 1055
1056 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1057
1058 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1059 sizeof(vcpu->hv_clock));
18068523
GOC		 1060
1061 kunmap_atomic(shared_kaddr, KM_USER0);
1062
1063 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1064 return 0;
18068523
GOC		 1065}
1066
c8076604
GH		 1067static int kvm_request_guest_time_update(struct kvm_vcpu *v)
1068{
1069 struct kvm_vcpu_arch *vcpu = &v->arch;
1070
1071 if (!vcpu->time_page)
1072 return 0;
a8eeb04a 1073 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
c8076604
GH		 1074 return 1;
1075}
1076
9ba075a6
AK		 1077static bool msr_mtrr_valid(unsigned msr)
1078{
1079 switch (msr) {
1080 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1081 case MSR_MTRRfix64K_00000:
1082 case MSR_MTRRfix16K_80000:
1083 case MSR_MTRRfix16K_A0000:
1084 case MSR_MTRRfix4K_C0000:
1085 case MSR_MTRRfix4K_C8000:
1086 case MSR_MTRRfix4K_D0000:
1087 case MSR_MTRRfix4K_D8000:
1088 case MSR_MTRRfix4K_E0000:
1089 case MSR_MTRRfix4K_E8000:
1090 case MSR_MTRRfix4K_F0000:
1091 case MSR_MTRRfix4K_F8000:
1092 case MSR_MTRRdefType:
1093 case MSR_IA32_CR_PAT:
1094 return true;
1095 case 0x2f8:
1096 return true;
1097 }
1098 return false;
1099}
1100
d6289b93
MT		 1101static bool valid_pat_type(unsigned t)
1102{
1103 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1104}
1105
1106static bool valid_mtrr_type(unsigned t)
1107{
1108 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1109}
1110
1111static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1112{
1113 int i;
1114
1115 if (!msr_mtrr_valid(msr))
1116 return false;
1117
1118 if (msr == MSR_IA32_CR_PAT) {
1119 for (i = 0; i < 8; i++)
1120 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1121 return false;
1122 return true;
1123 } else if (msr == MSR_MTRRdefType) {
1124 if (data & ~0xcff)
1125 return false;
1126 return valid_mtrr_type(data & 0xff);
1127 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1128 for (i = 0; i < 8 ; i++)
1129 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1130 return false;
1131 return true;
1132 }
1133
1134 /* variable MTRRs */
1135 return valid_mtrr_type(data & 0xff);
1136}
1137
9ba075a6
AK		 1138static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1139{
0bed3b56
SY		 1140 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1141
d6289b93 1142 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1143 return 1;
1144
0bed3b56
SY		 1145 if (msr == MSR_MTRRdefType) {
1146 vcpu->arch.mtrr_state.def_type = data;
1147 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1148 } else if (msr == MSR_MTRRfix64K_00000)
1149 p[0] = data;
1150 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1151 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1152 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1153 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1154 else if (msr == MSR_IA32_CR_PAT)
1155 vcpu->arch.pat = data;
1156 else { /* Variable MTRRs */
1157 int idx, is_mtrr_mask;
1158 u64 *pt;
1159
1160 idx = (msr - 0x200) / 2;
1161 is_mtrr_mask = msr - 0x200 - 2 * idx;
1162 if (!is_mtrr_mask)
1163 pt =
1164 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1165 else
1166 pt =
1167 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1168 *pt = data;
1169 }
1170
1171 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1172 return 0;
1173}
15c4a640 1174
890ca9ae 1175static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1176{
890ca9ae
HY		 1177 u64 mcg_cap = vcpu->arch.mcg_cap;
1178 unsigned bank_num = mcg_cap & 0xff;
1179
15c4a640 1180 switch (msr) {
15c4a640 1181 case MSR_IA32_MCG_STATUS:
890ca9ae 1182 vcpu->arch.mcg_status = data;
15c4a640 1183 break;
c7ac679c 1184 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1185 if (!(mcg_cap & MCG_CTL_P))
1186 return 1;
1187 if (data != 0 && data != ~(u64)0)
1188 return -1;
1189 vcpu->arch.mcg_ctl = data;
1190 break;
1191 default:
1192 if (msr >= MSR_IA32_MC0_CTL &&
1193 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1194 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1195 /* only 0 or all 1s can be written to IA32_MCi_CTL
1196 * some Linux kernels though clear bit 10 in bank 4 to
1197 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1198 * this to avoid an uncatched #GP in the guest
1199 */
890ca9ae 1200 if ((offset & 0x3) == 0 &&
114be429 1201 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1202 return -1;
1203 vcpu->arch.mce_banks[offset] = data;
1204 break;
1205 }
1206 return 1;
1207 }
1208 return 0;
1209}
1210
ffde22ac
ES		 1211static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1212{
1213 struct kvm *kvm = vcpu->kvm;
1214 int lm = is_long_mode(vcpu);
1215 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1216 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1217 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1218 : kvm->arch.xen_hvm_config.blob_size_32;
1219 u32 page_num = data & ~PAGE_MASK;
1220 u64 page_addr = data & PAGE_MASK;
1221 u8 *page;
1222 int r;
1223
1224 r = -E2BIG;
1225 if (page_num >= blob_size)
1226 goto out;
1227 r = -ENOMEM;
1228 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1229 if (!page)
1230 goto out;
1231 r = -EFAULT;
1232 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1233 goto out_free;
1234 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1235 goto out_free;
1236 r = 0;
1237out_free:
1238 kfree(page);
1239out:
1240 return r;
1241}
1242
55cd8e5a
GN		 1243static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1244{
1245 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1246}
1247
1248static bool kvm_hv_msr_partition_wide(u32 msr)
1249{
1250 bool r = false;
1251 switch (msr) {
1252 case HV_X64_MSR_GUEST_OS_ID:
1253 case HV_X64_MSR_HYPERCALL:
1254 r = true;
1255 break;
1256 }
1257
1258 return r;
1259}
1260
1261static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1262{
1263 struct kvm *kvm = vcpu->kvm;
1264
1265 switch (msr) {
1266 case HV_X64_MSR_GUEST_OS_ID:
1267 kvm->arch.hv_guest_os_id = data;
1268 /* setting guest os id to zero disables hypercall page */
1269 if (!kvm->arch.hv_guest_os_id)
1270 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1271 break;
1272 case HV_X64_MSR_HYPERCALL: {
1273 u64 gfn;
1274 unsigned long addr;
1275 u8 instructions[4];
1276
1277 /* if guest os id is not set hypercall should remain disabled */
1278 if (!kvm->arch.hv_guest_os_id)
1279 break;
1280 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1281 kvm->arch.hv_hypercall = data;
1282 break;
1283 }
1284 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1285 addr = gfn_to_hva(kvm, gfn);
1286 if (kvm_is_error_hva(addr))
1287 return 1;
1288 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1289 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1290 if (copy_to_user((void __user *)addr, instructions, 4))
1291 return 1;
1292 kvm->arch.hv_hypercall = data;
1293 break;
1294 }
1295 default:
1296 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1297 "data 0x%llx\n", msr, data);
1298 return 1;
1299 }
1300 return 0;
1301}
1302
1303static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1304{
10388a07
GN		 1305 switch (msr) {
1306 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1307 unsigned long addr;
55cd8e5a 1308
10388a07
GN		 1309 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1310 vcpu->arch.hv_vapic = data;
1311 break;
1312 }
1313 addr = gfn_to_hva(vcpu->kvm, data >>
1314 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1315 if (kvm_is_error_hva(addr))
1316 return 1;
1317 if (clear_user((void __user *)addr, PAGE_SIZE))
1318 return 1;
1319 vcpu->arch.hv_vapic = data;
1320 break;
1321 }
1322 case HV_X64_MSR_EOI:
1323 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1324 case HV_X64_MSR_ICR:
1325 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1326 case HV_X64_MSR_TPR:
1327 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1328 default:
1329 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1330 "data 0x%llx\n", msr, data);
1331 return 1;
1332 }
1333
1334 return 0;
55cd8e5a
GN		 1335}
1336
15c4a640
CO		 1337int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1338{
1339 switch (msr) {
15c4a640 1340 case MSR_EFER:
b69e8cae 1341 return set_efer(vcpu, data);
8f1589d9
AP		 1342 case MSR_K7_HWCR:
1343 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1344 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1345 if (data != 0) {
1346 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1347 data);
1348 return 1;
1349 }
15c4a640 1350 break;
f7c6d140
AP		 1351 case MSR_FAM10H_MMIO_CONF_BASE:
1352 if (data != 0) {
1353 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1354 "0x%llx\n", data);
1355 return 1;
1356 }
15c4a640 1357 break;
c323c0e5 1358 case MSR_AMD64_NB_CFG:
c7ac679c 1359 break;
b5e2fec0
AG		 1360 case MSR_IA32_DEBUGCTLMSR:
1361 if (!data) {
1362 /* We support the non-activated case already */
1363 break;
1364 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1365 /* Values other than LBR and BTF are vendor-specific,
1366 thus reserved and should throw a #GP */
1367 return 1;
1368 }
1369 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1370 __func__, data);
1371 break;
15c4a640
CO		 1372 case MSR_IA32_UCODE_REV:
1373 case MSR_IA32_UCODE_WRITE:
61a6bd67 1374 case MSR_VM_HSAVE_PA:
6098ca93 1375 case MSR_AMD64_PATCH_LOADER:
15c4a640 1376 break;
9ba075a6
AK		 1377 case 0x200 ... 0x2ff:
1378 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1379 case MSR_IA32_APICBASE:
1380 kvm_set_apic_base(vcpu, data);
1381 break;
0105d1a5
GN		 1382 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1383 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1384 case MSR_IA32_MISC_ENABLE:
ad312c7c 1385 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1386 break;
11c6bffa 1387 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1388 case MSR_KVM_WALL_CLOCK:
1389 vcpu->kvm->arch.wall_clock = data;
1390 kvm_write_wall_clock(vcpu->kvm, data);
1391 break;
11c6bffa 1392 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1393 case MSR_KVM_SYSTEM_TIME: {
1394 if (vcpu->arch.time_page) {
1395 kvm_release_page_dirty(vcpu->arch.time_page);
1396 vcpu->arch.time_page = NULL;
1397 }
1398
1399 vcpu->arch.time = data;
1400
1401 /* we verify if the enable bit is set... */
1402 if (!(data & 1))
1403 break;
1404
1405 /* ...but clean it before doing the actual write */
1406 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1407
18068523
GOC		 1408 vcpu->arch.time_page =
1409 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1410
1411 if (is_error_page(vcpu->arch.time_page)) {
1412 kvm_release_page_clean(vcpu->arch.time_page);
1413 vcpu->arch.time_page = NULL;
1414 }
1415
c8076604 1416 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1417 break;
1418 }
890ca9ae
HY		 1419 case MSR_IA32_MCG_CTL:
1420 case MSR_IA32_MCG_STATUS:
1421 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1422 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1423
1424 /* Performance counters are not protected by a CPUID bit,
1425 * so we should check all of them in the generic path for the sake of
1426 * cross vendor migration.
1427 * Writing a zero into the event select MSRs disables them,
1428 * which we perfectly emulate ;-). Any other value should be at least
1429 * reported, some guests depend on them.
1430 */
1431 case MSR_P6_EVNTSEL0:
1432 case MSR_P6_EVNTSEL1:
1433 case MSR_K7_EVNTSEL0:
1434 case MSR_K7_EVNTSEL1:
1435 case MSR_K7_EVNTSEL2:
1436 case MSR_K7_EVNTSEL3:
1437 if (data != 0)
1438 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1439 "0x%x data 0x%llx\n", msr, data);
1440 break;
1441 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1442 * so we ignore writes to make it happy.
1443 */
1444 case MSR_P6_PERFCTR0:
1445 case MSR_P6_PERFCTR1:
1446 case MSR_K7_PERFCTR0:
1447 case MSR_K7_PERFCTR1:
1448 case MSR_K7_PERFCTR2:
1449 case MSR_K7_PERFCTR3:
1450 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1451 "0x%x data 0x%llx\n", msr, data);
1452 break;
84e0cefa
JS		 1453 case MSR_K7_CLK_CTL:
1454 /*
1455 * Ignore all writes to this no longer documented MSR.
1456 * Writes are only relevant for old K7 processors,
1457 * all pre-dating SVM, but a recommended workaround from
1458 * AMD for these chips. It is possible to speicify the
1459 * affected processor models on the command line, hence
1460 * the need to ignore the workaround.
1461 */
1462 break;
55cd8e5a
GN		 1463 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1464 if (kvm_hv_msr_partition_wide(msr)) {
1465 int r;
1466 mutex_lock(&vcpu->kvm->lock);
1467 r = set_msr_hyperv_pw(vcpu, msr, data);
1468 mutex_unlock(&vcpu->kvm->lock);
1469 return r;
1470 } else
1471 return set_msr_hyperv(vcpu, msr, data);
1472 break;
15c4a640 1473 default:
ffde22ac
ES		 1474 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1475 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1476 if (!ignore_msrs) {
1477 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1478 msr, data);
1479 return 1;
1480 } else {
1481 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1482 msr, data);
1483 break;
1484 }
15c4a640
CO		 1485 }
1486 return 0;
1487}
1488EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1489
1490
1491/*
1492 * Reads an msr value (of 'msr_index') into 'pdata'.
1493 * Returns 0 on success, non-0 otherwise.
1494 * Assumes vcpu_load() was already called.
1495 */
1496int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1497{
1498 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1499}
1500
9ba075a6
AK		 1501static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1502{
0bed3b56
SY		 1503 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1504
9ba075a6
AK		 1505 if (!msr_mtrr_valid(msr))
1506 return 1;
1507
0bed3b56
SY		 1508 if (msr == MSR_MTRRdefType)
1509 *pdata = vcpu->arch.mtrr_state.def_type +
1510 (vcpu->arch.mtrr_state.enabled << 10);
1511 else if (msr == MSR_MTRRfix64K_00000)
1512 *pdata = p[0];
1513 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1514 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1515 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1516 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1517 else if (msr == MSR_IA32_CR_PAT)
1518 *pdata = vcpu->arch.pat;
1519 else { /* Variable MTRRs */
1520 int idx, is_mtrr_mask;
1521 u64 *pt;
1522
1523 idx = (msr - 0x200) / 2;
1524 is_mtrr_mask = msr - 0x200 - 2 * idx;
1525 if (!is_mtrr_mask)
1526 pt =
1527 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1528 else
1529 pt =
1530 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1531 *pdata = *pt;
1532 }
1533
9ba075a6
AK		 1534 return 0;
1535}
1536
890ca9ae 1537static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1538{
1539 u64 data;
890ca9ae
HY		 1540 u64 mcg_cap = vcpu->arch.mcg_cap;
1541 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1542
1543 switch (msr) {
15c4a640
CO		 1544 case MSR_IA32_P5_MC_ADDR:
1545 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1546 data = 0;
1547 break;
15c4a640 1548 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1549 data = vcpu->arch.mcg_cap;
1550 break;
c7ac679c 1551 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1552 if (!(mcg_cap & MCG_CTL_P))
1553 return 1;
1554 data = vcpu->arch.mcg_ctl;
1555 break;
1556 case MSR_IA32_MCG_STATUS:
1557 data = vcpu->arch.mcg_status;
1558 break;
1559 default:
1560 if (msr >= MSR_IA32_MC0_CTL &&
1561 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1562 u32 offset = msr - MSR_IA32_MC0_CTL;
1563 data = vcpu->arch.mce_banks[offset];
1564 break;
1565 }
1566 return 1;
1567 }
1568 *pdata = data;
1569 return 0;
1570}
1571
55cd8e5a
GN		 1572static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1573{
1574 u64 data = 0;
1575 struct kvm *kvm = vcpu->kvm;
1576
1577 switch (msr) {
1578 case HV_X64_MSR_GUEST_OS_ID:
1579 data = kvm->arch.hv_guest_os_id;
1580 break;
1581 case HV_X64_MSR_HYPERCALL:
1582 data = kvm->arch.hv_hypercall;
1583 break;
1584 default:
1585 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1586 return 1;
1587 }
1588
1589 *pdata = data;
1590 return 0;
1591}
1592
1593static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1594{
1595 u64 data = 0;
1596
1597 switch (msr) {
1598 case HV_X64_MSR_VP_INDEX: {
1599 int r;
1600 struct kvm_vcpu *v;
1601 kvm_for_each_vcpu(r, v, vcpu->kvm)
1602 if (v == vcpu)
1603 data = r;
1604 break;
1605 }
10388a07
GN		 1606 case HV_X64_MSR_EOI:
1607 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1608 case HV_X64_MSR_ICR:
1609 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1610 case HV_X64_MSR_TPR:
1611 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1612 default:
1613 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1614 return 1;
1615 }
1616 *pdata = data;
1617 return 0;
1618}
1619
890ca9ae
HY		 1620int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1621{
1622 u64 data;
1623
1624 switch (msr) {
890ca9ae 1625 case MSR_IA32_PLATFORM_ID:
15c4a640 1626 case MSR_IA32_UCODE_REV:
15c4a640 1627 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1628 case MSR_IA32_DEBUGCTLMSR:
1629 case MSR_IA32_LASTBRANCHFROMIP:
1630 case MSR_IA32_LASTBRANCHTOIP:
1631 case MSR_IA32_LASTINTFROMIP:
1632 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1633 case MSR_K8_SYSCFG:
1634 case MSR_K7_HWCR:
61a6bd67 1635 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1636 case MSR_P6_PERFCTR0:
1637 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1638 case MSR_P6_EVNTSEL0:
1639 case MSR_P6_EVNTSEL1:
9e699624 1640 case MSR_K7_EVNTSEL0:
1f3ee616 1641 case MSR_K7_PERFCTR0:
1fdbd48c 1642 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1643 case MSR_AMD64_NB_CFG:
f7c6d140 1644 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1645 data = 0;
1646 break;
9ba075a6
AK		 1647 case MSR_MTRRcap:
1648 data = 0x500 | KVM_NR_VAR_MTRR;
1649 break;
1650 case 0x200 ... 0x2ff:
1651 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1652 case 0xcd: /* fsb frequency */
1653 data = 3;
1654 break;
7b914098
JS		 1655 /*
1656 * MSR_EBC_FREQUENCY_ID
1657 * Conservative value valid for even the basic CPU models.
1658 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1659 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1660 * and 266MHz for model 3, or 4. Set Core Clock
1661 * Frequency to System Bus Frequency Ratio to 1 (bits
1662 * 31:24) even though these are only valid for CPU
1663 * models > 2, however guests may end up dividing or
1664 * multiplying by zero otherwise.
1665 */
1666 case MSR_EBC_FREQUENCY_ID:
1667 data = 1 << 24;
1668 break;
15c4a640
CO		 1669 case MSR_IA32_APICBASE:
1670 data = kvm_get_apic_base(vcpu);
1671 break;
0105d1a5
GN		 1672 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1673 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1674 break;
15c4a640 1675 case MSR_IA32_MISC_ENABLE:
ad312c7c 1676 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1677 break;
847f0ad8
AG		 1678 case MSR_IA32_PERF_STATUS:
1679 /* TSC increment by tick */
1680 data = 1000ULL;
1681 /* CPU multiplier */
1682 data |= (((uint64_t)4ULL) << 40);
1683 break;
15c4a640 1684 case MSR_EFER:
f6801dff 1685 data = vcpu->arch.efer;
15c4a640 1686 break;
18068523 1687 case MSR_KVM_WALL_CLOCK:
11c6bffa 1688 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1689 data = vcpu->kvm->arch.wall_clock;
1690 break;
1691 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1692 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1693 data = vcpu->arch.time;
1694 break;
890ca9ae
HY		 1695 case MSR_IA32_P5_MC_ADDR:
1696 case MSR_IA32_P5_MC_TYPE:
1697 case MSR_IA32_MCG_CAP:
1698 case MSR_IA32_MCG_CTL:
1699 case MSR_IA32_MCG_STATUS:
1700 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1701 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1702 case MSR_K7_CLK_CTL:
1703 /*
1704 * Provide expected ramp-up count for K7. All other
1705 * are set to zero, indicating minimum divisors for
1706 * every field.
1707 *
1708 * This prevents guest kernels on AMD host with CPU
1709 * type 6, model 8 and higher from exploding due to
1710 * the rdmsr failing.
1711 */
1712 data = 0x20000000;
1713 break;
55cd8e5a
GN		 1714 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1715 if (kvm_hv_msr_partition_wide(msr)) {
1716 int r;
1717 mutex_lock(&vcpu->kvm->lock);
1718 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1719 mutex_unlock(&vcpu->kvm->lock);
1720 return r;
1721 } else
1722 return get_msr_hyperv(vcpu, msr, pdata);
1723 break;
15c4a640 1724 default:
ed85c068
AP		 1725 if (!ignore_msrs) {
1726 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1727 return 1;
1728 } else {
1729 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1730 data = 0;
1731 }
1732 break;
15c4a640
CO		 1733 }
1734 *pdata = data;
1735 return 0;
1736}
1737EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1738
313a3dc7
CO		 1739/*
1740 * Read or write a bunch of msrs. All parameters are kernel addresses.
1741 *
1742 * @return number of msrs set successfully.
1743 */
1744static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1745 struct kvm_msr_entry *entries,
1746 int (*do_msr)(struct kvm_vcpu *vcpu,
1747 unsigned index, u64 *data))
1748{
f656ce01 1749 int i, idx;
313a3dc7 1750
f656ce01 1751 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1752 for (i = 0; i < msrs->nmsrs; ++i)
1753 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1754 break;
f656ce01 1755 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1756
313a3dc7
CO		 1757 return i;
1758}
1759
1760/*
1761 * Read or write a bunch of msrs. Parameters are user addresses.
1762 *
1763 * @return number of msrs set successfully.
1764 */
1765static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1766 int (*do_msr)(struct kvm_vcpu *vcpu,
1767 unsigned index, u64 *data),
1768 int writeback)
1769{
1770 struct kvm_msrs msrs;
1771 struct kvm_msr_entry *entries;
1772 int r, n;
1773 unsigned size;
1774
1775 r = -EFAULT;
1776 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1777 goto out;
1778
1779 r = -E2BIG;
1780 if (msrs.nmsrs >= MAX_IO_MSRS)
1781 goto out;
1782
1783 r = -ENOMEM;
1784 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1785 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1786 if (!entries)
1787 goto out;
1788
1789 r = -EFAULT;
1790 if (copy_from_user(entries, user_msrs->entries, size))
1791 goto out_free;
1792
1793 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1794 if (r < 0)
1795 goto out_free;
1796
1797 r = -EFAULT;
1798 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1799 goto out_free;
1800
1801 r = n;
1802
1803out_free:
7a73c028 1804 kfree(entries);
313a3dc7
CO		 1805out:
1806 return r;
1807}
1808
018d00d2
ZX		 1809int kvm_dev_ioctl_check_extension(long ext)
1810{
1811 int r;
1812
1813 switch (ext) {
1814 case KVM_CAP_IRQCHIP:
1815 case KVM_CAP_HLT:
1816 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1817 case KVM_CAP_SET_TSS_ADDR:
07716717 1818 case KVM_CAP_EXT_CPUID:
c8076604 1819 case KVM_CAP_CLOCKSOURCE:
7837699f 1820 case KVM_CAP_PIT:
a28e4f5a 1821 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1822 case KVM_CAP_MP_STATE:
ed848624 1823 case KVM_CAP_SYNC_MMU:
52d939a0 1824 case KVM_CAP_REINJECT_CONTROL:
4925663a 1825 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1826 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1827 case KVM_CAP_IRQFD:
d34e6b17 1828 case KVM_CAP_IOEVENTFD:
c5ff41ce 1829 case KVM_CAP_PIT2:
e9f42757 1830 case KVM_CAP_PIT_STATE2:
b927a3ce 1831 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1832 case KVM_CAP_XEN_HVM:
afbcf7ab 1833 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1834 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1835 case KVM_CAP_HYPERV:
10388a07 1836 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1837 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1838 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1839 case KVM_CAP_DEBUGREGS:
d2be1651 1840 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1841 case KVM_CAP_XSAVE:
018d00d2
ZX		 1842 r = 1;
1843 break;
542472b5
LV		 1844 case KVM_CAP_COALESCED_MMIO:
1845 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1846 break;
774ead3a
AK		 1847 case KVM_CAP_VAPIC:
1848 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1849 break;
f725230a
AK		 1850 case KVM_CAP_NR_VCPUS:
1851 r = KVM_MAX_VCPUS;
1852 break;
a988b910
AK		 1853 case KVM_CAP_NR_MEMSLOTS:
1854 r = KVM_MEMORY_SLOTS;
1855 break;
a68a6a72
MT		 1856 case KVM_CAP_PV_MMU: /* obsolete */
1857 r = 0;
2f333bcb 1858 break;
62c476c7 1859 case KVM_CAP_IOMMU:
19de40a8 1860 r = iommu_found();
62c476c7 1861 break;
890ca9ae
HY		 1862 case KVM_CAP_MCE:
1863 r = KVM_MAX_MCE_BANKS;
1864 break;
2d5b5a66
SY		 1865 case KVM_CAP_XCRS:
1866 r = cpu_has_xsave;
1867 break;
018d00d2
ZX		 1868 default:
1869 r = 0;
1870 break;
1871 }
1872 return r;
1873
1874}
1875
043405e1
CO		 1876long kvm_arch_dev_ioctl(struct file *filp,
1877 unsigned int ioctl, unsigned long arg)
1878{
1879 void __user *argp = (void __user *)arg;
1880 long r;
1881
1882 switch (ioctl) {
1883 case KVM_GET_MSR_INDEX_LIST: {
1884 struct kvm_msr_list __user *user_msr_list = argp;
1885 struct kvm_msr_list msr_list;
1886 unsigned n;
1887
1888 r = -EFAULT;
1889 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1890 goto out;
1891 n = msr_list.nmsrs;
1892 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1893 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1894 goto out;
1895 r = -E2BIG;
e125e7b6 1896 if (n < msr_list.nmsrs)
043405e1
CO		 1897 goto out;
1898 r = -EFAULT;
1899 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1900 num_msrs_to_save * sizeof(u32)))
1901 goto out;
e125e7b6 1902 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1903 &emulated_msrs,
1904 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1905 goto out;
1906 r = 0;
1907 break;
1908 }
674eea0f
AK		 1909 case KVM_GET_SUPPORTED_CPUID: {
1910 struct kvm_cpuid2 __user *cpuid_arg = argp;
1911 struct kvm_cpuid2 cpuid;
1912
1913 r = -EFAULT;
1914 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1915 goto out;
1916 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1917 cpuid_arg->entries);
674eea0f
AK		 1918 if (r)
1919 goto out;
1920
1921 r = -EFAULT;
1922 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1923 goto out;
1924 r = 0;
1925 break;
1926 }
890ca9ae
HY		 1927 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1928 u64 mce_cap;
1929
1930 mce_cap = KVM_MCE_CAP_SUPPORTED;
1931 r = -EFAULT;
1932 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1933 goto out;
1934 r = 0;
1935 break;
1936 }
043405e1
CO		 1937 default:
1938 r = -EINVAL;
1939 }
1940out:
1941 return r;
1942}
1943
f5f48ee1
SY		 1944static void wbinvd_ipi(void *garbage)
1945{
1946 wbinvd();
1947}
1948
1949static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
1950{
1951 return vcpu->kvm->arch.iommu_domain &&
1952 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
1953}
1954
313a3dc7
CO		 1955void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1956{
f5f48ee1
SY		 1957 /* Address WBINVD may be executed by guest */
1958 if (need_emulate_wbinvd(vcpu)) {
1959 if (kvm_x86_ops->has_wbinvd_exit())
1960 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
1961 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
1962 smp_call_function_single(vcpu->cpu,
1963 wbinvd_ipi, NULL, 1);
1964 }
1965
313a3dc7 1966 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 1967 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 1968 /* Make sure TSC doesn't go backwards */
1969 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
1970 native_read_tsc() - vcpu->arch.last_host_tsc;
1971 if (tsc_delta < 0)
1972 mark_tsc_unstable("KVM discovered backwards TSC");
1973 if (check_tsc_unstable())
1974 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
1975 kvm_migrate_timers(vcpu);
1976 vcpu->cpu = cpu;
1977 }
313a3dc7
CO		 1978}
1979
1980void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1981{
02daab21 1982 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 1983 kvm_put_guest_fpu(vcpu);
e48672fa 1984 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 1985}
1986
07716717 1987static int is_efer_nx(void)
313a3dc7 1988{
e286e86e 1989 unsigned long long efer = 0;
313a3dc7 1990
e286e86e 1991 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1992 return efer & EFER_NX;
1993}
1994
1995static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1996{
1997 int i;
1998 struct kvm_cpuid_entry2 *e, *entry;
1999
313a3dc7 2000 entry = NULL;
ad312c7c
ZX		 2001 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2002 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2003 if (e->function == 0x80000001) {
2004 entry = e;
2005 break;
2006 }
2007 }
07716717 2008 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2009 entry->edx &= ~(1 << 20);
2010 printk(KERN_INFO "kvm: guest NX capability removed\n");
2011 }
2012}
2013
07716717 2014/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2015static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2016 struct kvm_cpuid *cpuid,
2017 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2018{
2019 int r, i;
2020 struct kvm_cpuid_entry *cpuid_entries;
2021
2022 r = -E2BIG;
2023 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2024 goto out;
2025 r = -ENOMEM;
2026 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2027 if (!cpuid_entries)
2028 goto out;
2029 r = -EFAULT;
2030 if (copy_from_user(cpuid_entries, entries,
2031 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2032 goto out_free;
2033 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2034 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2035 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2036 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2037 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2038 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2039 vcpu->arch.cpuid_entries[i].index = 0;
2040 vcpu->arch.cpuid_entries[i].flags = 0;
2041 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2042 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2043 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2044 }
2045 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2046 cpuid_fix_nx_cap(vcpu);
2047 r = 0;
fc61b800 2048 kvm_apic_set_version(vcpu);
0e851880 2049 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2050 update_cpuid(vcpu);
07716717
DK		 2051
2052out_free:
2053 vfree(cpuid_entries);
2054out:
2055 return r;
2056}
2057
2058static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2059 struct kvm_cpuid2 *cpuid,
2060 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2061{
2062 int r;
2063
2064 r = -E2BIG;
2065 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2066 goto out;
2067 r = -EFAULT;
ad312c7c 2068 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2069 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2070 goto out;
ad312c7c 2071 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2072 kvm_apic_set_version(vcpu);
0e851880 2073 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2074 update_cpuid(vcpu);
313a3dc7
CO		 2075 return 0;
2076
2077out:
2078 return r;
2079}
2080
07716717 2081static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2082 struct kvm_cpuid2 *cpuid,
2083 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2084{
2085 int r;
2086
2087 r = -E2BIG;
ad312c7c 2088 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2089 goto out;
2090 r = -EFAULT;
ad312c7c 2091 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2092 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2093 goto out;
2094 return 0;
2095
2096out:
ad312c7c 2097 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2098 return r;
2099}
2100
07716717 2101static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2102 u32 index)
07716717
DK		 2103{
2104 entry->function = function;
2105 entry->index = index;
2106 cpuid_count(entry->function, entry->index,
19355475 2107 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2108 entry->flags = 0;
2109}
2110
7faa4ee1
AK		 2111#define F(x) bit(X86_FEATURE_##x)
2112
07716717
DK		 2113static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2114 u32 index, int *nent, int maxnent)
2115{
7faa4ee1 2116 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2117#ifdef CONFIG_X86_64
17cc3935
SY		 2118 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2119 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2120 unsigned f_lm = F(LM);
2121#else
17cc3935 2122 unsigned f_gbpages = 0;
7faa4ee1 2123 unsigned f_lm = 0;
07716717 2124#endif
4e47c7a6 2125 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2126
2127 /* cpuid 1.edx */
2128 const u32 kvm_supported_word0_x86_features =
2129 F(FPU) | F(VME) | F(DE) | F(PSE) |
2130 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2131 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2132 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2133 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2134 0 /* Reserved, DS, ACPI */ | F(MMX) |
2135 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2136 0 /* HTT, TM, Reserved, PBE */;
2137 /* cpuid 0x80000001.edx */
2138 const u32 kvm_supported_word1_x86_features =
2139 F(FPU) | F(VME) | F(DE) | F(PSE) |
2140 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2141 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2142 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2143 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2144 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2145 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2146 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2147 /* cpuid 1.ecx */
2148 const u32 kvm_supported_word4_x86_features =
6c3f6041 2149 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2150 0 /* DS-CPL, VMX, SMX, EST */ |
2151 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2152 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2153 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2154 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6c3f6041 2155 0 /* Reserved, AES */ | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX);
7faa4ee1 2156 /* cpuid 0x80000001.ecx */
07716717 2157 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 2158 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
2159 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
2160 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
2161 0 /* SKINIT */ | 0 /* WDT */;
07716717 2162
19355475 2163 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2164 get_cpu();
2165 do_cpuid_1_ent(entry, function, index);
2166 ++*nent;
2167
2168 switch (function) {
2169 case 0:
2acf923e 2170 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2171 break;
2172 case 1:
2173 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 2174 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 2175 /* we support x2apic emulation even if host does not support
2176 * it since we emulate x2apic in software */
2177 entry->ecx |= F(X2APIC);
07716717
DK		 2178 break;
2179 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2180 * may return different values. This forces us to get_cpu() before
2181 * issuing the first command, and also to emulate this annoying behavior
2182 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2183 case 2: {
2184 int t, times = entry->eax & 0xff;
2185
2186 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2187 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2188 for (t = 1; t < times && *nent < maxnent; ++t) {
2189 do_cpuid_1_ent(&entry[t], function, 0);
2190 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2191 ++*nent;
2192 }
2193 break;
2194 }
2195 /* function 4 and 0xb have additional index. */
2196 case 4: {
14af3f3c 2197 int i, cache_type;
07716717
DK		 2198
2199 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2200 /* read more entries until cache_type is zero */
14af3f3c
HH		 2201 for (i = 1; *nent < maxnent; ++i) {
2202 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2203 if (!cache_type)
2204 break;
14af3f3c
HH		 2205 do_cpuid_1_ent(&entry[i], function, i);
2206 entry[i].flags |=
07716717
DK		 2207 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2208 ++*nent;
2209 }
2210 break;
2211 }
2212 case 0xb: {
14af3f3c 2213 int i, level_type;
07716717
DK		 2214
2215 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2216 /* read more entries until level_type is zero */
14af3f3c 2217 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2218 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2219 if (!level_type)
2220 break;
14af3f3c
HH		 2221 do_cpuid_1_ent(&entry[i], function, i);
2222 entry[i].flags |=
07716717
DK		 2223 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2224 ++*nent;
2225 }
2226 break;
2227 }
2acf923e
DC		 2228 case 0xd: {
2229 int i;
2230
2231 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2232 for (i = 1; *nent < maxnent; ++i) {
2233 if (entry[i - 1].eax == 0 && i != 2)
2234 break;
2235 do_cpuid_1_ent(&entry[i], function, i);
2236 entry[i].flags |=
2237 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2238 ++*nent;
2239 }
2240 break;
2241 }
84478c82
GC		 2242 case KVM_CPUID_SIGNATURE: {
2243 char signature[12] = "KVMKVMKVM\0\0";
2244 u32 *sigptr = (u32 *)signature;
2245 entry->eax = 0;
2246 entry->ebx = sigptr[0];
2247 entry->ecx = sigptr[1];
2248 entry->edx = sigptr[2];
2249 break;
2250 }
2251 case KVM_CPUID_FEATURES:
2252 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2253 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2254 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2255 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2256 entry->ebx = 0;
2257 entry->ecx = 0;
2258 entry->edx = 0;
2259 break;
07716717
DK		 2260 case 0x80000000:
2261 entry->eax = min(entry->eax, 0x8000001a);
2262 break;
2263 case 0x80000001:
2264 entry->edx &= kvm_supported_word1_x86_features;
2265 entry->ecx &= kvm_supported_word6_x86_features;
2266 break;
2267 }
d4330ef2
JR		 2268
2269 kvm_x86_ops->set_supported_cpuid(function, entry);
2270
07716717
DK		 2271 put_cpu();
2272}
2273
7faa4ee1
AK		 2274#undef F
2275
674eea0f 2276static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2277 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2278{
2279 struct kvm_cpuid_entry2 *cpuid_entries;
2280 int limit, nent = 0, r = -E2BIG;
2281 u32 func;
2282
2283 if (cpuid->nent < 1)
2284 goto out;
6a544355
AK		 2285 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2286 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2287 r = -ENOMEM;
2288 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2289 if (!cpuid_entries)
2290 goto out;
2291
2292 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2293 limit = cpuid_entries[0].eax;
2294 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2295 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2296 &nent, cpuid->nent);
07716717
DK		 2297 r = -E2BIG;
2298 if (nent >= cpuid->nent)
2299 goto out_free;
2300
2301 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2302 limit = cpuid_entries[nent - 1].eax;
2303 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2304 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2305 &nent, cpuid->nent);
84478c82
GC		 2306
2307
2308
2309 r = -E2BIG;
2310 if (nent >= cpuid->nent)
2311 goto out_free;
2312
2313 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2314 cpuid->nent);
2315
2316 r = -E2BIG;
2317 if (nent >= cpuid->nent)
2318 goto out_free;
2319
2320 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2321 cpuid->nent);
2322
cb007648
MM		 2323 r = -E2BIG;
2324 if (nent >= cpuid->nent)
2325 goto out_free;
2326
07716717
DK		 2327 r = -EFAULT;
2328 if (copy_to_user(entries, cpuid_entries,
19355475 2329 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2330 goto out_free;
2331 cpuid->nent = nent;
2332 r = 0;
2333
2334out_free:
2335 vfree(cpuid_entries);
2336out:
2337 return r;
2338}
2339
313a3dc7
CO		 2340static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2341 struct kvm_lapic_state *s)
2342{
ad312c7c 2343 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2344
2345 return 0;
2346}
2347
2348static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2349 struct kvm_lapic_state *s)
2350{
ad312c7c 2351 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2352 kvm_apic_post_state_restore(vcpu);
cb142eb7 2353 update_cr8_intercept(vcpu);
313a3dc7
CO		 2354
2355 return 0;
2356}
2357
f77bc6a4
ZX		 2358static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2359 struct kvm_interrupt *irq)
2360{
2361 if (irq->irq < 0 || irq->irq >= 256)
2362 return -EINVAL;
2363 if (irqchip_in_kernel(vcpu->kvm))
2364 return -ENXIO;
f77bc6a4 2365
66fd3f7f 2366 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4 2367
f77bc6a4
ZX		 2368 return 0;
2369}
2370
c4abb7c9
JK		 2371static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2372{
c4abb7c9 2373 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2374
2375 return 0;
2376}
2377
b209749f
AK		 2378static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2379 struct kvm_tpr_access_ctl *tac)
2380{
2381 if (tac->flags)
2382 return -EINVAL;
2383 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2384 return 0;
2385}
2386
890ca9ae
HY		 2387static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2388 u64 mcg_cap)
2389{
2390 int r;
2391 unsigned bank_num = mcg_cap & 0xff, bank;
2392
2393 r = -EINVAL;
a9e38c3e 2394 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2395 goto out;
2396 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2397 goto out;
2398 r = 0;
2399 vcpu->arch.mcg_cap = mcg_cap;
2400 /* Init IA32_MCG_CTL to all 1s */
2401 if (mcg_cap & MCG_CTL_P)
2402 vcpu->arch.mcg_ctl = ~(u64)0;
2403 /* Init IA32_MCi_CTL to all 1s */
2404 for (bank = 0; bank < bank_num; bank++)
2405 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2406out:
2407 return r;
2408}
2409
2410static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2411 struct kvm_x86_mce *mce)
2412{
2413 u64 mcg_cap = vcpu->arch.mcg_cap;
2414 unsigned bank_num = mcg_cap & 0xff;
2415 u64 *banks = vcpu->arch.mce_banks;
2416
2417 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2418 return -EINVAL;
2419 /*
2420 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2421 * reporting is disabled
2422 */
2423 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2424 vcpu->arch.mcg_ctl != ~(u64)0)
2425 return 0;
2426 banks += 4 * mce->bank;
2427 /*
2428 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2429 * reporting is disabled for the bank
2430 */
2431 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2432 return 0;
2433 if (mce->status & MCI_STATUS_UC) {
2434 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2435 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2436 printk(KERN_DEBUG "kvm: set_mce: "
2437 "injects mce exception while "
2438 "previous one is in progress!\n");
a8eeb04a 2439 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2440 return 0;
2441 }
2442 if (banks[1] & MCI_STATUS_VAL)
2443 mce->status |= MCI_STATUS_OVER;
2444 banks[2] = mce->addr;
2445 banks[3] = mce->misc;
2446 vcpu->arch.mcg_status = mce->mcg_status;
2447 banks[1] = mce->status;
2448 kvm_queue_exception(vcpu, MC_VECTOR);
2449 } else if (!(banks[1] & MCI_STATUS_VAL)
2450 || !(banks[1] & MCI_STATUS_UC)) {
2451 if (banks[1] & MCI_STATUS_VAL)
2452 mce->status |= MCI_STATUS_OVER;
2453 banks[2] = mce->addr;
2454 banks[3] = mce->misc;
2455 banks[1] = mce->status;
2456 } else
2457 banks[1] |= MCI_STATUS_OVER;
2458 return 0;
2459}
2460
3cfc3092
JK		 2461static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2462 struct kvm_vcpu_events *events)
2463{
03b82a30
JK		 2464 events->exception.injected =
2465 vcpu->arch.exception.pending &&
2466 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2467 events->exception.nr = vcpu->arch.exception.nr;
2468 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2469 events->exception.error_code = vcpu->arch.exception.error_code;
2470
03b82a30
JK		 2471 events->interrupt.injected =
2472 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2473 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2474 events->interrupt.soft = 0;
48005f64
JK		 2475 events->interrupt.shadow =
2476 kvm_x86_ops->get_interrupt_shadow(vcpu,
2477 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2478
2479 events->nmi.injected = vcpu->arch.nmi_injected;
2480 events->nmi.pending = vcpu->arch.nmi_pending;
2481 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2482
2483 events->sipi_vector = vcpu->arch.sipi_vector;
2484
dab4b911 2485 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2486 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2487 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2488}
2489
2490static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2491 struct kvm_vcpu_events *events)
2492{
dab4b911 2493 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2494 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2495 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2496 return -EINVAL;
2497
3cfc3092
JK		 2498 vcpu->arch.exception.pending = events->exception.injected;
2499 vcpu->arch.exception.nr = events->exception.nr;
2500 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2501 vcpu->arch.exception.error_code = events->exception.error_code;
2502
2503 vcpu->arch.interrupt.pending = events->interrupt.injected;
2504 vcpu->arch.interrupt.nr = events->interrupt.nr;
2505 vcpu->arch.interrupt.soft = events->interrupt.soft;
2506 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2507 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2508 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2509 kvm_x86_ops->set_interrupt_shadow(vcpu,
2510 events->interrupt.shadow);
3cfc3092
JK		 2511
2512 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2513 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2514 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2515 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2516
dab4b911
JK		 2517 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2518 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2519
3cfc3092
JK		 2520 return 0;
2521}
2522
a1efbe77
JK		 2523static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2524 struct kvm_debugregs *dbgregs)
2525{
a1efbe77
JK		 2526 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2527 dbgregs->dr6 = vcpu->arch.dr6;
2528 dbgregs->dr7 = vcpu->arch.dr7;
2529 dbgregs->flags = 0;
a1efbe77
JK		 2530}
2531
2532static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2533 struct kvm_debugregs *dbgregs)
2534{
2535 if (dbgregs->flags)
2536 return -EINVAL;
2537
a1efbe77
JK		 2538 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2539 vcpu->arch.dr6 = dbgregs->dr6;
2540 vcpu->arch.dr7 = dbgregs->dr7;
2541
a1efbe77
JK		 2542 return 0;
2543}
2544
2d5b5a66
SY		 2545static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2546 struct kvm_xsave *guest_xsave)
2547{
2548 if (cpu_has_xsave)
2549 memcpy(guest_xsave->region,
2550 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2551 xstate_size);
2d5b5a66
SY		 2552 else {
2553 memcpy(guest_xsave->region,
2554 &vcpu->arch.guest_fpu.state->fxsave,
2555 sizeof(struct i387_fxsave_struct));
2556 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2557 XSTATE_FPSSE;
2558 }
2559}
2560
2561static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2562 struct kvm_xsave *guest_xsave)
2563{
2564 u64 xstate_bv =
2565 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2566
2567 if (cpu_has_xsave)
2568 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2569 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2570 else {
2571 if (xstate_bv & ~XSTATE_FPSSE)
2572 return -EINVAL;
2573 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2574 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2575 }
2576 return 0;
2577}
2578
2579static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2580 struct kvm_xcrs *guest_xcrs)
2581{
2582 if (!cpu_has_xsave) {
2583 guest_xcrs->nr_xcrs = 0;
2584 return;
2585 }
2586
2587 guest_xcrs->nr_xcrs = 1;
2588 guest_xcrs->flags = 0;
2589 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2590 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2591}
2592
2593static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2594 struct kvm_xcrs *guest_xcrs)
2595{
2596 int i, r = 0;
2597
2598 if (!cpu_has_xsave)
2599 return -EINVAL;
2600
2601 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2602 return -EINVAL;
2603
2604 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2605 /* Only support XCR0 currently */
2606 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2607 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2608 guest_xcrs->xcrs[0].value);
2609 break;
2610 }
2611 if (r)
2612 r = -EINVAL;
2613 return r;
2614}
2615
313a3dc7
CO		 2616long kvm_arch_vcpu_ioctl(struct file *filp,
2617 unsigned int ioctl, unsigned long arg)
2618{
2619 struct kvm_vcpu *vcpu = filp->private_data;
2620 void __user *argp = (void __user *)arg;
2621 int r;
d1ac91d8
AK		 2622 union {
2623 struct kvm_lapic_state *lapic;
2624 struct kvm_xsave *xsave;
2625 struct kvm_xcrs *xcrs;
2626 void *buffer;
2627 } u;
2628
2629 u.buffer = NULL;
313a3dc7
CO		 2630 switch (ioctl) {
2631 case KVM_GET_LAPIC: {
2204ae3c
MT		 2632 r = -EINVAL;
2633 if (!vcpu->arch.apic)
2634 goto out;
d1ac91d8 2635 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2636
b772ff36 2637 r = -ENOMEM;
d1ac91d8 2638 if (!u.lapic)
b772ff36 2639 goto out;
d1ac91d8 2640 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2641 if (r)
2642 goto out;
2643 r = -EFAULT;
d1ac91d8 2644 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2645 goto out;
2646 r = 0;
2647 break;
2648 }
2649 case KVM_SET_LAPIC: {
2204ae3c
MT		 2650 r = -EINVAL;
2651 if (!vcpu->arch.apic)
2652 goto out;
d1ac91d8 2653 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2654 r = -ENOMEM;
d1ac91d8 2655 if (!u.lapic)
b772ff36 2656 goto out;
313a3dc7 2657 r = -EFAULT;
d1ac91d8 2658 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2659 goto out;
d1ac91d8 2660 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2661 if (r)
2662 goto out;
2663 r = 0;
2664 break;
2665 }
f77bc6a4
ZX		 2666 case KVM_INTERRUPT: {
2667 struct kvm_interrupt irq;
2668
2669 r = -EFAULT;
2670 if (copy_from_user(&irq, argp, sizeof irq))
2671 goto out;
2672 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2673 if (r)
2674 goto out;
2675 r = 0;
2676 break;
2677 }
c4abb7c9
JK		 2678 case KVM_NMI: {
2679 r = kvm_vcpu_ioctl_nmi(vcpu);
2680 if (r)
2681 goto out;
2682 r = 0;
2683 break;
2684 }
313a3dc7
CO		 2685 case KVM_SET_CPUID: {
2686 struct kvm_cpuid __user *cpuid_arg = argp;
2687 struct kvm_cpuid cpuid;
2688
2689 r = -EFAULT;
2690 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2691 goto out;
2692 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2693 if (r)
2694 goto out;
2695 break;
2696 }
07716717
DK		 2697 case KVM_SET_CPUID2: {
2698 struct kvm_cpuid2 __user *cpuid_arg = argp;
2699 struct kvm_cpuid2 cpuid;
2700
2701 r = -EFAULT;
2702 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2703 goto out;
2704 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2705 cpuid_arg->entries);
07716717
DK		 2706 if (r)
2707 goto out;
2708 break;
2709 }
2710 case KVM_GET_CPUID2: {
2711 struct kvm_cpuid2 __user *cpuid_arg = argp;
2712 struct kvm_cpuid2 cpuid;
2713
2714 r = -EFAULT;
2715 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2716 goto out;
2717 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2718 cpuid_arg->entries);
07716717
DK		 2719 if (r)
2720 goto out;
2721 r = -EFAULT;
2722 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2723 goto out;
2724 r = 0;
2725 break;
2726 }
313a3dc7
CO		 2727 case KVM_GET_MSRS:
2728 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2729 break;
2730 case KVM_SET_MSRS:
2731 r = msr_io(vcpu, argp, do_set_msr, 0);
2732 break;
b209749f
AK		 2733 case KVM_TPR_ACCESS_REPORTING: {
2734 struct kvm_tpr_access_ctl tac;
2735
2736 r = -EFAULT;
2737 if (copy_from_user(&tac, argp, sizeof tac))
2738 goto out;
2739 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2740 if (r)
2741 goto out;
2742 r = -EFAULT;
2743 if (copy_to_user(argp, &tac, sizeof tac))
2744 goto out;
2745 r = 0;
2746 break;
2747 };
b93463aa
AK		 2748 case KVM_SET_VAPIC_ADDR: {
2749 struct kvm_vapic_addr va;
2750
2751 r = -EINVAL;
2752 if (!irqchip_in_kernel(vcpu->kvm))
2753 goto out;
2754 r = -EFAULT;
2755 if (copy_from_user(&va, argp, sizeof va))
2756 goto out;
2757 r = 0;
2758 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2759 break;
2760 }
890ca9ae
HY		 2761 case KVM_X86_SETUP_MCE: {
2762 u64 mcg_cap;
2763
2764 r = -EFAULT;
2765 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2766 goto out;
2767 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2768 break;
2769 }
2770 case KVM_X86_SET_MCE: {
2771 struct kvm_x86_mce mce;
2772
2773 r = -EFAULT;
2774 if (copy_from_user(&mce, argp, sizeof mce))
2775 goto out;
2776 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2777 break;
2778 }
3cfc3092
JK		 2779 case KVM_GET_VCPU_EVENTS: {
2780 struct kvm_vcpu_events events;
2781
2782 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2783
2784 r = -EFAULT;
2785 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2786 break;
2787 r = 0;
2788 break;
2789 }
2790 case KVM_SET_VCPU_EVENTS: {
2791 struct kvm_vcpu_events events;
2792
2793 r = -EFAULT;
2794 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2795 break;
2796
2797 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2798 break;
2799 }
a1efbe77
JK		 2800 case KVM_GET_DEBUGREGS: {
2801 struct kvm_debugregs dbgregs;
2802
2803 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2804
2805 r = -EFAULT;
2806 if (copy_to_user(argp, &dbgregs,
2807 sizeof(struct kvm_debugregs)))
2808 break;
2809 r = 0;
2810 break;
2811 }
2812 case KVM_SET_DEBUGREGS: {
2813 struct kvm_debugregs dbgregs;
2814
2815 r = -EFAULT;
2816 if (copy_from_user(&dbgregs, argp,
2817 sizeof(struct kvm_debugregs)))
2818 break;
2819
2820 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2821 break;
2822 }
2d5b5a66 2823 case KVM_GET_XSAVE: {
d1ac91d8 2824 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2825 r = -ENOMEM;
d1ac91d8 2826 if (!u.xsave)
2d5b5a66
SY		 2827 break;
2828
d1ac91d8 2829 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2830
2831 r = -EFAULT;
d1ac91d8 2832 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2833 break;
2834 r = 0;
2835 break;
2836 }
2837 case KVM_SET_XSAVE: {
d1ac91d8 2838 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2839 r = -ENOMEM;
d1ac91d8 2840 if (!u.xsave)
2d5b5a66
SY		 2841 break;
2842
2843 r = -EFAULT;
d1ac91d8 2844 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2845 break;
2846
d1ac91d8 2847 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2848 break;
2849 }
2850 case KVM_GET_XCRS: {
d1ac91d8 2851 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2852 r = -ENOMEM;
d1ac91d8 2853 if (!u.xcrs)
2d5b5a66
SY		 2854 break;
2855
d1ac91d8 2856 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2857
2858 r = -EFAULT;
d1ac91d8 2859 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2860 sizeof(struct kvm_xcrs)))
2861 break;
2862 r = 0;
2863 break;
2864 }
2865 case KVM_SET_XCRS: {
d1ac91d8 2866 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2867 r = -ENOMEM;
d1ac91d8 2868 if (!u.xcrs)
2d5b5a66
SY		 2869 break;
2870
2871 r = -EFAULT;
d1ac91d8 2872 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 2873 sizeof(struct kvm_xcrs)))
2874 break;
2875
d1ac91d8 2876 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2877 break;
2878 }
313a3dc7
CO		 2879 default:
2880 r = -EINVAL;
2881 }
2882out:
d1ac91d8 2883 kfree(u.buffer);
313a3dc7
CO		 2884 return r;
2885}
2886
1fe779f8
CO		 2887static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2888{
2889 int ret;
2890
2891 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2892 return -1;
2893 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2894 return ret;
2895}
2896
b927a3ce
SY		 2897static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2898 u64 ident_addr)
2899{
2900 kvm->arch.ept_identity_map_addr = ident_addr;
2901 return 0;
2902}
2903
1fe779f8
CO		 2904static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2905 u32 kvm_nr_mmu_pages)
2906{
2907 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2908 return -EINVAL;
2909
79fac95e 2910 mutex_lock(&kvm->slots_lock);
7c8a83b7 2911 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2912
2913 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2914 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2915
7c8a83b7 2916 spin_unlock(&kvm->mmu_lock);
79fac95e 2917 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2918 return 0;
2919}
2920
2921static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2922{
39de71ec 2923 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2924}
2925
1fe779f8
CO		 2926static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2927{
2928 int r;
2929
2930 r = 0;
2931 switch (chip->chip_id) {
2932 case KVM_IRQCHIP_PIC_MASTER:
2933 memcpy(&chip->chip.pic,
2934 &pic_irqchip(kvm)->pics[0],
2935 sizeof(struct kvm_pic_state));
2936 break;
2937 case KVM_IRQCHIP_PIC_SLAVE:
2938 memcpy(&chip->chip.pic,
2939 &pic_irqchip(kvm)->pics[1],
2940 sizeof(struct kvm_pic_state));
2941 break;
2942 case KVM_IRQCHIP_IOAPIC:
eba0226b 2943 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2944 break;
2945 default:
2946 r = -EINVAL;
2947 break;
2948 }
2949 return r;
2950}
2951
2952static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2953{
2954 int r;
2955
2956 r = 0;
2957 switch (chip->chip_id) {
2958 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2959 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2960 memcpy(&pic_irqchip(kvm)->pics[0],
2961 &chip->chip.pic,
2962 sizeof(struct kvm_pic_state));
fa8273e9 2963 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2964 break;
2965 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2966 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2967 memcpy(&pic_irqchip(kvm)->pics[1],
2968 &chip->chip.pic,
2969 sizeof(struct kvm_pic_state));
fa8273e9 2970 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2971 break;
2972 case KVM_IRQCHIP_IOAPIC:
eba0226b 2973 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2974 break;
2975 default:
2976 r = -EINVAL;
2977 break;
2978 }
2979 kvm_pic_update_irq(pic_irqchip(kvm));
2980 return r;
2981}
2982
e0f63cb9
SY		 2983static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2984{
2985 int r = 0;
2986
894a9c55 2987 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2988 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2989 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2990 return r;
2991}
2992
2993static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2994{
2995 int r = 0;
2996
894a9c55 2997 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2998 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2999 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3000 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3001 return r;
3002}
3003
3004static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3005{
3006 int r = 0;
3007
3008 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3009 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3010 sizeof(ps->channels));
3011 ps->flags = kvm->arch.vpit->pit_state.flags;
3012 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3013 return r;
3014}
3015
3016static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3017{
3018 int r = 0, start = 0;
3019 u32 prev_legacy, cur_legacy;
3020 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3021 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3022 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3023 if (!prev_legacy && cur_legacy)
3024 start = 1;
3025 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3026 sizeof(kvm->arch.vpit->pit_state.channels));
3027 kvm->arch.vpit->pit_state.flags = ps->flags;
3028 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3029 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3030 return r;
3031}
3032
52d939a0
MT		 3033static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3034 struct kvm_reinject_control *control)
3035{
3036 if (!kvm->arch.vpit)
3037 return -ENXIO;
894a9c55 3038 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3039 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3040 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3041 return 0;
3042}
3043
5bb064dc
ZX		 3044/*
3045 * Get (and clear) the dirty memory log for a memory slot.
3046 */
3047int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3048 struct kvm_dirty_log *log)
3049{
87bf6e7d 3050 int r, i;
5bb064dc 3051 struct kvm_memory_slot *memslot;
87bf6e7d 3052 unsigned long n;
b050b015 3053 unsigned long is_dirty = 0;
5bb064dc 3054
79fac95e 3055 mutex_lock(&kvm->slots_lock);
5bb064dc 3056
b050b015
MT		 3057 r = -EINVAL;
3058 if (log->slot >= KVM_MEMORY_SLOTS)
3059 goto out;
3060
3061 memslot = &kvm->memslots->memslots[log->slot];
3062 r = -ENOENT;
3063 if (!memslot->dirty_bitmap)
3064 goto out;
3065
87bf6e7d 3066 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3067
b050b015
MT		 3068 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3069 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3070
3071 /* If nothing is dirty, don't bother messing with page tables. */
3072 if (is_dirty) {
b050b015 3073 struct kvm_memslots *slots, *old_slots;
914ebccd 3074 unsigned long *dirty_bitmap;
b050b015 3075
7c8a83b7 3076 spin_lock(&kvm->mmu_lock);
5bb064dc 3077 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 3078 spin_unlock(&kvm->mmu_lock);
b050b015 3079
914ebccd
TY		 3080 r = -ENOMEM;
3081 dirty_bitmap = vmalloc(n);
3082 if (!dirty_bitmap)
3083 goto out;
3084 memset(dirty_bitmap, 0, n);
b050b015 3085
914ebccd
TY		 3086 r = -ENOMEM;
3087 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
3088 if (!slots) {
3089 vfree(dirty_bitmap);
3090 goto out;
3091 }
b050b015
MT		 3092 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3093 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
3094
3095 old_slots = kvm->memslots;
3096 rcu_assign_pointer(kvm->memslots, slots);
3097 synchronize_srcu_expedited(&kvm->srcu);
3098 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3099 kfree(old_slots);
914ebccd
TY		 3100
3101 r = -EFAULT;
3102 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
3103 vfree(dirty_bitmap);
3104 goto out;
3105 }
3106 vfree(dirty_bitmap);
3107 } else {
3108 r = -EFAULT;
3109 if (clear_user(log->dirty_bitmap, n))
3110 goto out;
5bb064dc 3111 }
b050b015 3112
5bb064dc
ZX		 3113 r = 0;
3114out:
79fac95e 3115 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3116 return r;
3117}
3118
1fe779f8
CO		 3119long kvm_arch_vm_ioctl(struct file *filp,
3120 unsigned int ioctl, unsigned long arg)
3121{
3122 struct kvm *kvm = filp->private_data;
3123 void __user *argp = (void __user *)arg;
367e1319 3124 int r = -ENOTTY;
f0d66275
DH		 3125 /*
3126 * This union makes it completely explicit to gcc-3.x
3127 * that these two variables' stack usage should be
3128 * combined, not added together.
3129 */
3130 union {
3131 struct kvm_pit_state ps;
e9f42757 3132 struct kvm_pit_state2 ps2;
c5ff41ce 3133 struct kvm_pit_config pit_config;
f0d66275 3134 } u;
1fe779f8
CO		 3135
3136 switch (ioctl) {
3137 case KVM_SET_TSS_ADDR:
3138 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3139 if (r < 0)
3140 goto out;
3141 break;
b927a3ce
SY		 3142 case KVM_SET_IDENTITY_MAP_ADDR: {
3143 u64 ident_addr;
3144
3145 r = -EFAULT;
3146 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3147 goto out;
3148 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3149 if (r < 0)
3150 goto out;
3151 break;
3152 }
1fe779f8
CO		 3153 case KVM_SET_NR_MMU_PAGES:
3154 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3155 if (r)
3156 goto out;
3157 break;
3158 case KVM_GET_NR_MMU_PAGES:
3159 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3160 break;
3ddea128
MT		 3161 case KVM_CREATE_IRQCHIP: {
3162 struct kvm_pic *vpic;
3163
3164 mutex_lock(&kvm->lock);
3165 r = -EEXIST;
3166 if (kvm->arch.vpic)
3167 goto create_irqchip_unlock;
1fe779f8 3168 r = -ENOMEM;
3ddea128
MT		 3169 vpic = kvm_create_pic(kvm);
3170 if (vpic) {
1fe779f8
CO		 3171 r = kvm_ioapic_init(kvm);
3172 if (r) {
72bb2fcd
WY		 3173 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3174 &vpic->dev);
3ddea128
MT		 3175 kfree(vpic);
3176 goto create_irqchip_unlock;
1fe779f8
CO		 3177 }
3178 } else
3ddea128
MT		 3179 goto create_irqchip_unlock;
3180 smp_wmb();
3181 kvm->arch.vpic = vpic;
3182 smp_wmb();
399ec807
AK		 3183 r = kvm_setup_default_irq_routing(kvm);
3184 if (r) {
3ddea128 3185 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3186 kvm_ioapic_destroy(kvm);
3187 kvm_destroy_pic(kvm);
3ddea128 3188 mutex_unlock(&kvm->irq_lock);
399ec807 3189 }
3ddea128
MT		 3190 create_irqchip_unlock:
3191 mutex_unlock(&kvm->lock);
1fe779f8 3192 break;
3ddea128 3193 }
7837699f 3194 case KVM_CREATE_PIT:
c5ff41ce
JK		 3195 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3196 goto create_pit;
3197 case KVM_CREATE_PIT2:
3198 r = -EFAULT;
3199 if (copy_from_user(&u.pit_config, argp,
3200 sizeof(struct kvm_pit_config)))
3201 goto out;
3202 create_pit:
79fac95e 3203 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3204 r = -EEXIST;
3205 if (kvm->arch.vpit)
3206 goto create_pit_unlock;
7837699f 3207 r = -ENOMEM;
c5ff41ce 3208 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3209 if (kvm->arch.vpit)
3210 r = 0;
269e05e4 3211 create_pit_unlock:
79fac95e 3212 mutex_unlock(&kvm->slots_lock);
7837699f 3213 break;
4925663a 3214 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3215 case KVM_IRQ_LINE: {
3216 struct kvm_irq_level irq_event;
3217
3218 r = -EFAULT;
3219 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3220 goto out;
160d2f6c 3221 r = -ENXIO;
1fe779f8 3222 if (irqchip_in_kernel(kvm)) {
4925663a 3223 __s32 status;
4925663a
GN		 3224 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3225 irq_event.irq, irq_event.level);
4925663a 3226 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3227 r = -EFAULT;
4925663a
GN		 3228 irq_event.status = status;
3229 if (copy_to_user(argp, &irq_event,
3230 sizeof irq_event))
3231 goto out;
3232 }
1fe779f8
CO		 3233 r = 0;
3234 }
3235 break;
3236 }
3237 case KVM_GET_IRQCHIP: {
3238 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3239 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3240
f0d66275
DH		 3241 r = -ENOMEM;
3242 if (!chip)
1fe779f8 3243 goto out;
f0d66275
DH		 3244 r = -EFAULT;
3245 if (copy_from_user(chip, argp, sizeof *chip))
3246 goto get_irqchip_out;
1fe779f8
CO		 3247 r = -ENXIO;
3248 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3249 goto get_irqchip_out;
3250 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3251 if (r)
f0d66275 3252 goto get_irqchip_out;
1fe779f8 3253 r = -EFAULT;
f0d66275
DH		 3254 if (copy_to_user(argp, chip, sizeof *chip))
3255 goto get_irqchip_out;
1fe779f8 3256 r = 0;
f0d66275
DH		 3257 get_irqchip_out:
3258 kfree(chip);
3259 if (r)
3260 goto out;
1fe779f8
CO		 3261 break;
3262 }
3263 case KVM_SET_IRQCHIP: {
3264 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3265 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3266
f0d66275
DH		 3267 r = -ENOMEM;
3268 if (!chip)
1fe779f8 3269 goto out;
f0d66275
DH		 3270 r = -EFAULT;
3271 if (copy_from_user(chip, argp, sizeof *chip))
3272 goto set_irqchip_out;
1fe779f8
CO		 3273 r = -ENXIO;
3274 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3275 goto set_irqchip_out;
3276 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3277 if (r)
f0d66275 3278 goto set_irqchip_out;
1fe779f8 3279 r = 0;
f0d66275
DH		 3280 set_irqchip_out:
3281 kfree(chip);
3282 if (r)
3283 goto out;
1fe779f8
CO		 3284 break;
3285 }
e0f63cb9 3286 case KVM_GET_PIT: {
e0f63cb9 3287 r = -EFAULT;
f0d66275 3288 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3289 goto out;
3290 r = -ENXIO;
3291 if (!kvm->arch.vpit)
3292 goto out;
f0d66275 3293 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3294 if (r)
3295 goto out;
3296 r = -EFAULT;
f0d66275 3297 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3298 goto out;
3299 r = 0;
3300 break;
3301 }
3302 case KVM_SET_PIT: {
e0f63cb9 3303 r = -EFAULT;
f0d66275 3304 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3305 goto out;
3306 r = -ENXIO;
3307 if (!kvm->arch.vpit)
3308 goto out;
f0d66275 3309 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3310 if (r)
3311 goto out;
3312 r = 0;
3313 break;
3314 }
e9f42757
BK		 3315 case KVM_GET_PIT2: {
3316 r = -ENXIO;
3317 if (!kvm->arch.vpit)
3318 goto out;
3319 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3320 if (r)
3321 goto out;
3322 r = -EFAULT;
3323 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3324 goto out;
3325 r = 0;
3326 break;
3327 }
3328 case KVM_SET_PIT2: {
3329 r = -EFAULT;
3330 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3331 goto out;
3332 r = -ENXIO;
3333 if (!kvm->arch.vpit)
3334 goto out;
3335 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3336 if (r)
3337 goto out;
3338 r = 0;
3339 break;
3340 }
52d939a0
MT		 3341 case KVM_REINJECT_CONTROL: {
3342 struct kvm_reinject_control control;
3343 r = -EFAULT;
3344 if (copy_from_user(&control, argp, sizeof(control)))
3345 goto out;
3346 r = kvm_vm_ioctl_reinject(kvm, &control);
3347 if (r)
3348 goto out;
3349 r = 0;
3350 break;
3351 }
ffde22ac
ES		 3352 case KVM_XEN_HVM_CONFIG: {
3353 r = -EFAULT;
3354 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3355 sizeof(struct kvm_xen_hvm_config)))
3356 goto out;
3357 r = -EINVAL;
3358 if (kvm->arch.xen_hvm_config.flags)
3359 goto out;
3360 r = 0;
3361 break;
3362 }
afbcf7ab 3363 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3364 struct kvm_clock_data user_ns;
3365 u64 now_ns;
3366 s64 delta;
3367
3368 r = -EFAULT;
3369 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3370 goto out;
3371
3372 r = -EINVAL;
3373 if (user_ns.flags)
3374 goto out;
3375
3376 r = 0;
759379dd 3377 now_ns = get_kernel_ns();
afbcf7ab
GC		 3378 delta = user_ns.clock - now_ns;
3379 kvm->arch.kvmclock_offset = delta;
3380 break;
3381 }
3382 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3383 struct kvm_clock_data user_ns;
3384 u64 now_ns;
3385
759379dd 3386 now_ns = get_kernel_ns();
afbcf7ab
GC		 3387 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3388 user_ns.flags = 0;
3389
3390 r = -EFAULT;
3391 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3392 goto out;
3393 r = 0;
3394 break;
3395 }
3396
1fe779f8
CO		 3397 default:
3398 ;
3399 }
3400out:
3401 return r;
3402}
3403
a16b043c 3404static void kvm_init_msr_list(void)
043405e1
CO		 3405{
3406 u32 dummy[2];
3407 unsigned i, j;
3408
e3267cbb
GC		 3409 /* skip the first msrs in the list. KVM-specific */
3410 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3411 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3412 continue;
3413 if (j < i)
3414 msrs_to_save[j] = msrs_to_save[i];
3415 j++;
3416 }
3417 num_msrs_to_save = j;
3418}
3419
bda9020e
MT		 3420static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3421 const void *v)
bbd9b64e 3422{
bda9020e
MT		 3423 if (vcpu->arch.apic &&
3424 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3425 return 0;
bbd9b64e 3426
e93f8a0f 3427 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3428}
3429
bda9020e 3430static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3431{
bda9020e
MT		 3432 if (vcpu->arch.apic &&
3433 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3434 return 0;
bbd9b64e 3435
e93f8a0f 3436 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3437}
3438
2dafc6c2
GN		 3439static void kvm_set_segment(struct kvm_vcpu *vcpu,
3440 struct kvm_segment *var, int seg)
3441{
3442 kvm_x86_ops->set_segment(vcpu, var, seg);
3443}
3444
3445void kvm_get_segment(struct kvm_vcpu *vcpu,
3446 struct kvm_segment *var, int seg)
3447{
3448 kvm_x86_ops->get_segment(vcpu, var, seg);
3449}
3450
c30a358d
JR		 3451static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3452{
3453 return gpa;
3454}
3455
1871c602
GN		 3456gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3457{
3458 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3459 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3460}
3461
3462 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3463{
3464 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3465 access |= PFERR_FETCH_MASK;
3466 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3467}
3468
3469gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3470{
3471 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3472 access |= PFERR_WRITE_MASK;
3473 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3474}
3475
3476/* uses this to access any guest's mapped memory without checking CPL */
3477gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3478{
3479 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3480}
3481
3482static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3483 struct kvm_vcpu *vcpu, u32 access,
3484 u32 *error)
bbd9b64e
CO		 3485{
3486 void *data = val;
10589a46 3487 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3488
3489 while (bytes) {
1871c602 3490 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3491 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3492 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3493 int ret;
3494
10589a46
MT		 3495 if (gpa == UNMAPPED_GVA) {
3496 r = X86EMUL_PROPAGATE_FAULT;
3497 goto out;
3498 }
77c2002e 3499 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3500 if (ret < 0) {
c3cd7ffa 3501 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3502 goto out;
3503 }
bbd9b64e 3504
77c2002e
IE		 3505 bytes -= toread;
3506 data += toread;
3507 addr += toread;
bbd9b64e 3508 }
10589a46 3509out:
10589a46 3510 return r;
bbd9b64e 3511}
77c2002e 3512
1871c602
GN		 3513/* used for instruction fetching */
3514static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3515 struct kvm_vcpu *vcpu, u32 *error)
3516{
3517 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3518 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3519 access | PFERR_FETCH_MASK, error);
3520}
3521
3522static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3523 struct kvm_vcpu *vcpu, u32 *error)
3524{
3525 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3526 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3527 error);
3528}
3529
3530static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3531 struct kvm_vcpu *vcpu, u32 *error)
3532{
3533 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3534}
3535
7972995b 3536static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3537 unsigned int bytes,
7972995b 3538 struct kvm_vcpu *vcpu,
2dafc6c2 3539 u32 *error)
77c2002e
IE		 3540{
3541 void *data = val;
3542 int r = X86EMUL_CONTINUE;
3543
3544 while (bytes) {
7972995b
GN		 3545 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr,
3546 PFERR_WRITE_MASK, error);
77c2002e
IE		 3547 unsigned offset = addr & (PAGE_SIZE-1);
3548 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3549 int ret;
3550
3551 if (gpa == UNMAPPED_GVA) {
3552 r = X86EMUL_PROPAGATE_FAULT;
3553 goto out;
3554 }
3555 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3556 if (ret < 0) {
c3cd7ffa 3557 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3558 goto out;
3559 }
3560
3561 bytes -= towrite;
3562 data += towrite;
3563 addr += towrite;
3564 }
3565out:
3566 return r;
3567}
3568
bbd9b64e
CO		 3569static int emulator_read_emulated(unsigned long addr,
3570 void *val,
3571 unsigned int bytes,
8fe681e9 3572 unsigned int *error_code,
bbd9b64e
CO		 3573 struct kvm_vcpu *vcpu)
3574{
bbd9b64e
CO		 3575 gpa_t gpa;
3576
3577 if (vcpu->mmio_read_completed) {
3578 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3579 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3580 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3581 vcpu->mmio_read_completed = 0;
3582 return X86EMUL_CONTINUE;
3583 }
3584
8fe681e9 3585 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3586
8fe681e9 3587 if (gpa == UNMAPPED_GVA)
1871c602 3588 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3589
3590 /* For APIC access vmexit */
3591 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3592 goto mmio;
3593
1871c602 3594 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3595 == X86EMUL_CONTINUE)
bbd9b64e 3596 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3597
3598mmio:
3599 /*
3600 * Is this MMIO handled locally?
3601 */
aec51dc4
AK		 3602 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3603 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3604 return X86EMUL_CONTINUE;
3605 }
aec51dc4
AK		 3606
3607 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3608
3609 vcpu->mmio_needed = 1;
411c35b7
GN		 3610 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3611 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3612 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3613 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3614
c3cd7ffa 3615 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3616}
3617
3200f405 3618int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3619 const void *val, int bytes)
bbd9b64e
CO		 3620{
3621 int ret;
3622
3623 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3624 if (ret < 0)
bbd9b64e 3625 return 0;
ad218f85 3626 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3627 return 1;
3628}
3629
3630static int emulator_write_emulated_onepage(unsigned long addr,
3631 const void *val,
3632 unsigned int bytes,
8fe681e9 3633 unsigned int *error_code,
bbd9b64e
CO		 3634 struct kvm_vcpu *vcpu)
3635{
10589a46
MT		 3636 gpa_t gpa;
3637
8fe681e9 3638 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3639
8fe681e9 3640 if (gpa == UNMAPPED_GVA)
bbd9b64e 3641 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3642
3643 /* For APIC access vmexit */
3644 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3645 goto mmio;
3646
3647 if (emulator_write_phys(vcpu, gpa, val, bytes))
3648 return X86EMUL_CONTINUE;
3649
3650mmio:
aec51dc4 3651 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3652 /*
3653 * Is this MMIO handled locally?
3654 */
bda9020e 3655 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3656 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3657
3658 vcpu->mmio_needed = 1;
411c35b7
GN		 3659 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3660 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3661 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3662 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3663 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3664
3665 return X86EMUL_CONTINUE;
3666}
3667
3668int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3669 const void *val,
3670 unsigned int bytes,
8fe681e9 3671 unsigned int *error_code,
8f6abd06 3672 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3673{
3674 /* Crossing a page boundary? */
3675 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3676 int rc, now;
3677
3678 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3679 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3680 vcpu);
bbd9b64e
CO		 3681 if (rc != X86EMUL_CONTINUE)
3682 return rc;
3683 addr += now;
3684 val += now;
3685 bytes -= now;
3686 }
8fe681e9
GN		 3687 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3688 vcpu);
bbd9b64e 3689}
bbd9b64e 3690
daea3e73
AK		 3691#define CMPXCHG_TYPE(t, ptr, old, new) \
3692 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3693
3694#ifdef CONFIG_X86_64
3695# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3696#else
3697# define CMPXCHG64(ptr, old, new) \
9749a6c0 3698 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3699#endif
3700
bbd9b64e
CO		 3701static int emulator_cmpxchg_emulated(unsigned long addr,
3702 const void *old,
3703 const void *new,
3704 unsigned int bytes,
8fe681e9 3705 unsigned int *error_code,
bbd9b64e
CO		 3706 struct kvm_vcpu *vcpu)
3707{
daea3e73
AK		 3708 gpa_t gpa;
3709 struct page *page;
3710 char *kaddr;
3711 bool exchanged;
2bacc55c 3712
daea3e73
AK		 3713 /* guests cmpxchg8b have to be emulated atomically */
3714 if (bytes > 8 || (bytes & (bytes - 1)))
3715 goto emul_write;
10589a46 3716
daea3e73 3717 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3718
daea3e73
AK		 3719 if (gpa == UNMAPPED_GVA ||
3720 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3721 goto emul_write;
2bacc55c 3722
daea3e73
AK		 3723 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3724 goto emul_write;
72dc67a6 3725
daea3e73 3726 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3727 if (is_error_page(page)) {
3728 kvm_release_page_clean(page);
3729 goto emul_write;
3730 }
72dc67a6 3731
daea3e73
AK		 3732 kaddr = kmap_atomic(page, KM_USER0);
3733 kaddr += offset_in_page(gpa);
3734 switch (bytes) {
3735 case 1:
3736 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3737 break;
3738 case 2:
3739 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3740 break;
3741 case 4:
3742 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3743 break;
3744 case 8:
3745 exchanged = CMPXCHG64(kaddr, old, new);
3746 break;
3747 default:
3748 BUG();
2bacc55c 3749 }
daea3e73
AK		 3750 kunmap_atomic(kaddr, KM_USER0);
3751 kvm_release_page_dirty(page);
3752
3753 if (!exchanged)
3754 return X86EMUL_CMPXCHG_FAILED;
3755
8f6abd06
GN		 3756 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3757
3758 return X86EMUL_CONTINUE;
4a5f48f6 3759
3200f405 3760emul_write:
daea3e73 3761 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3762
8fe681e9 3763 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3764}
3765
cf8f70bf
GN		 3766static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3767{
3768 /* TODO: String I/O for in kernel device */
3769 int r;
3770
3771 if (vcpu->arch.pio.in)
3772 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3773 vcpu->arch.pio.size, pd);
3774 else
3775 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3776 vcpu->arch.pio.port, vcpu->arch.pio.size,
3777 pd);
3778 return r;
3779}
3780
3781
3782static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3783 unsigned int count, struct kvm_vcpu *vcpu)
3784{
7972995b 3785 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3786 goto data_avail;
3787
c41a15dd 3788 trace_kvm_pio(0, port, size, 1);
cf8f70bf
GN		 3789
3790 vcpu->arch.pio.port = port;
3791 vcpu->arch.pio.in = 1;
7972995b 3792 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3793 vcpu->arch.pio.size = size;
3794
3795 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3796 data_avail:
3797 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3798 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3799 return 1;
3800 }
3801
3802 vcpu->run->exit_reason = KVM_EXIT_IO;
3803 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3804 vcpu->run->io.size = size;
3805 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3806 vcpu->run->io.count = count;
3807 vcpu->run->io.port = port;
3808
3809 return 0;
3810}
3811
3812static int emulator_pio_out_emulated(int size, unsigned short port,
3813 const void *val, unsigned int count,
3814 struct kvm_vcpu *vcpu)
3815{
c41a15dd 3816 trace_kvm_pio(1, port, size, 1);
cf8f70bf
GN		 3817
3818 vcpu->arch.pio.port = port;
3819 vcpu->arch.pio.in = 0;
7972995b 3820 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3821 vcpu->arch.pio.size = size;
3822
3823 memcpy(vcpu->arch.pio_data, val, size * count);
3824
3825 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3826 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3827 return 1;
3828 }
3829
3830 vcpu->run->exit_reason = KVM_EXIT_IO;
3831 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3832 vcpu->run->io.size = size;
3833 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3834 vcpu->run->io.count = count;
3835 vcpu->run->io.port = port;
3836
3837 return 0;
3838}
3839
bbd9b64e
CO		 3840static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3841{
3842 return kvm_x86_ops->get_segment_base(vcpu, seg);
3843}
3844
3845int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3846{
a7052897 3847 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3848 return X86EMUL_CONTINUE;
3849}
3850
f5f48ee1
SY		 3851int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3852{
3853 if (!need_emulate_wbinvd(vcpu))
3854 return X86EMUL_CONTINUE;
3855
3856 if (kvm_x86_ops->has_wbinvd_exit()) {
3857 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
3858 wbinvd_ipi, NULL, 1);
3859 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
3860 }
3861 wbinvd();
3862 return X86EMUL_CONTINUE;
3863}
3864EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
3865
bbd9b64e
CO		 3866int emulate_clts(struct kvm_vcpu *vcpu)
3867{
4d4ec087 3868 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3869 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3870 return X86EMUL_CONTINUE;
3871}
3872
35aa5375 3873int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 3874{
338dbc97 3875 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 3876}
3877
35aa5375 3878int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 3879{
338dbc97
GN		 3880
3881 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 3882}
3883
52a46617 3884static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 3885{
52a46617 3886 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 3887}
3888
52a46617 3889static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 3890{
52a46617
GN		 3891 unsigned long value;
3892
3893 switch (cr) {
3894 case 0:
3895 value = kvm_read_cr0(vcpu);
3896 break;
3897 case 2:
3898 value = vcpu->arch.cr2;
3899 break;
3900 case 3:
3901 value = vcpu->arch.cr3;
3902 break;
3903 case 4:
3904 value = kvm_read_cr4(vcpu);
3905 break;
3906 case 8:
3907 value = kvm_get_cr8(vcpu);
3908 break;
3909 default:
3910 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3911 return 0;
3912 }
3913
3914 return value;
3915}
3916
0f12244f 3917static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 3918{
0f12244f
GN		 3919 int res = 0;
3920
52a46617
GN		 3921 switch (cr) {
3922 case 0:
49a9b07e 3923 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 3924 break;
3925 case 2:
3926 vcpu->arch.cr2 = val;
3927 break;
3928 case 3:
2390218b 3929 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 3930 break;
3931 case 4:
a83b29c6 3932 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 3933 break;
3934 case 8:
0f12244f 3935 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 3936 break;
3937 default:
3938 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 3939 res = -1;
52a46617 3940 }
0f12244f
GN		 3941
3942 return res;
52a46617
GN		 3943}
3944
9c537244
GN		 3945static int emulator_get_cpl(struct kvm_vcpu *vcpu)
3946{
3947 return kvm_x86_ops->get_cpl(vcpu);
3948}
3949
2dafc6c2
GN		 3950static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3951{
3952 kvm_x86_ops->get_gdt(vcpu, dt);
3953}
3954
160ce1f1
MG		 3955static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3956{
3957 kvm_x86_ops->get_idt(vcpu, dt);
3958}
3959
5951c442
GN		 3960static unsigned long emulator_get_cached_segment_base(int seg,
3961 struct kvm_vcpu *vcpu)
3962{
3963 return get_segment_base(vcpu, seg);
3964}
3965
2dafc6c2
GN		 3966static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
3967 struct kvm_vcpu *vcpu)
3968{
3969 struct kvm_segment var;
3970
3971 kvm_get_segment(vcpu, &var, seg);
3972
3973 if (var.unusable)
3974 return false;
3975
3976 if (var.g)
3977 var.limit >>= 12;
3978 set_desc_limit(desc, var.limit);
3979 set_desc_base(desc, (unsigned long)var.base);
3980 desc->type = var.type;
3981 desc->s = var.s;
3982 desc->dpl = var.dpl;
3983 desc->p = var.present;
3984 desc->avl = var.avl;
3985 desc->l = var.l;
3986 desc->d = var.db;
3987 desc->g = var.g;
3988
3989 return true;
3990}
3991
3992static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
3993 struct kvm_vcpu *vcpu)
3994{
3995 struct kvm_segment var;
3996
3997 /* needed to preserve selector */
3998 kvm_get_segment(vcpu, &var, seg);
3999
4000 var.base = get_desc_base(desc);
4001 var.limit = get_desc_limit(desc);
4002 if (desc->g)
4003 var.limit = (var.limit << 12) | 0xfff;
4004 var.type = desc->type;
4005 var.present = desc->p;
4006 var.dpl = desc->dpl;
4007 var.db = desc->d;
4008 var.s = desc->s;
4009 var.l = desc->l;
4010 var.g = desc->g;
4011 var.avl = desc->avl;
4012 var.present = desc->p;
4013 var.unusable = !var.present;
4014 var.padding = 0;
4015
4016 kvm_set_segment(vcpu, &var, seg);
4017 return;
4018}
4019
4020static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4021{
4022 struct kvm_segment kvm_seg;
4023
4024 kvm_get_segment(vcpu, &kvm_seg, seg);
4025 return kvm_seg.selector;
4026}
4027
4028static void emulator_set_segment_selector(u16 sel, int seg,
4029 struct kvm_vcpu *vcpu)
4030{
4031 struct kvm_segment kvm_seg;
4032
4033 kvm_get_segment(vcpu, &kvm_seg, seg);
4034 kvm_seg.selector = sel;
4035 kvm_set_segment(vcpu, &kvm_seg, seg);
4036}
4037
14af3f3c 4038static struct x86_emulate_ops emulate_ops = {
1871c602 4039 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4040 .write_std = kvm_write_guest_virt_system,
1871c602 4041 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4042 .read_emulated = emulator_read_emulated,
4043 .write_emulated = emulator_write_emulated,
4044 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4045 .pio_in_emulated = emulator_pio_in_emulated,
4046 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4047 .get_cached_descriptor = emulator_get_cached_descriptor,
4048 .set_cached_descriptor = emulator_set_cached_descriptor,
4049 .get_segment_selector = emulator_get_segment_selector,
4050 .set_segment_selector = emulator_set_segment_selector,
5951c442 4051 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4052 .get_gdt = emulator_get_gdt,
160ce1f1 4053 .get_idt = emulator_get_idt,
52a46617
GN		 4054 .get_cr = emulator_get_cr,
4055 .set_cr = emulator_set_cr,
9c537244 4056 .cpl = emulator_get_cpl,
35aa5375
GN		 4057 .get_dr = emulator_get_dr,
4058 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4059 .set_msr = kvm_set_msr,
4060 .get_msr = kvm_get_msr,
bbd9b64e
CO		 4061};
4062
5fdbf976
MT		 4063static void cache_all_regs(struct kvm_vcpu *vcpu)
4064{
4065 kvm_register_read(vcpu, VCPU_REGS_RAX);
4066 kvm_register_read(vcpu, VCPU_REGS_RSP);
4067 kvm_register_read(vcpu, VCPU_REGS_RIP);
4068 vcpu->arch.regs_dirty = ~0;
4069}
4070
95cb2295
GN		 4071static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4072{
4073 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4074 /*
4075 * an sti; sti; sequence only disable interrupts for the first
4076 * instruction. So, if the last instruction, be it emulated or
4077 * not, left the system with the INT_STI flag enabled, it
4078 * means that the last instruction is an sti. We should not
4079 * leave the flag on in this case. The same goes for mov ss
4080 */
4081 if (!(int_shadow & mask))
4082 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4083}
4084
54b8486f
GN		 4085static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4086{
4087 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4088 if (ctxt->exception == PF_VECTOR)
8df25a32 4089 kvm_inject_page_fault(vcpu);
54b8486f
GN		 4090 else if (ctxt->error_code_valid)
4091 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
4092 else
4093 kvm_queue_exception(vcpu, ctxt->exception);
4094}
4095
8ec4722d
MG		 4096static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4097{
4098 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4099 int cs_db, cs_l;
4100
4101 cache_all_regs(vcpu);
4102
4103 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4104
4105 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4106 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4107 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4108 vcpu->arch.emulate_ctxt.mode =
4109 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4110 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4111 ? X86EMUL_MODE_VM86 : cs_l
4112 ? X86EMUL_MODE_PROT64 : cs_db
4113 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4114 memset(c, 0, sizeof(struct decode_cache));
4115 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4116}
4117
6d77dbfc
GN		 4118static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4119{
6d77dbfc
GN		 4120 ++vcpu->stat.insn_emulation_fail;
4121 trace_kvm_emulate_insn_failed(vcpu);
4122 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4123 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4124 vcpu->run->internal.ndata = 0;
4125 kvm_queue_exception(vcpu, UD_VECTOR);
4126 return EMULATE_FAIL;
4127}
4128
a6f177ef
GN		 4129static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4130{
4131 gpa_t gpa;
4132
68be0803
GN		 4133 if (tdp_enabled)
4134 return false;
4135
a6f177ef
GN		 4136 /*
4137 * if emulation was due to access to shadowed page table
4138 * and it failed try to unshadow page and re-entetr the
4139 * guest to let CPU execute the instruction.
4140 */
4141 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4142 return true;
4143
4144 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4145
4146 if (gpa == UNMAPPED_GVA)
4147 return true; /* let cpu generate fault */
4148
4149 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4150 return true;
4151
4152 return false;
4153}
4154
bbd9b64e 4155int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 4156 unsigned long cr2,
4157 u16 error_code,
571008da 4158 int emulation_type)
bbd9b64e 4159{
95cb2295 4160 int r;
4d2179e1 4161 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4162
26eef70c 4163 kvm_clear_exception_queue(vcpu);
ad312c7c 4164 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4165 /*
56e82318 4166 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4167 * instead of direct ->regs accesses, can save hundred cycles
4168 * on Intel for instructions that don't read/change RSP, for
4169 * for example.
4170 */
4171 cache_all_regs(vcpu);
bbd9b64e 4172
571008da 4173 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4174 init_emulate_ctxt(vcpu);
95cb2295 4175 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 4176 vcpu->arch.emulate_ctxt.exception = -1;
4fc40f07 4177 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4178
9aabc88f 4179 r = x86_decode_insn(&vcpu->arch.emulate_ctxt);
e46479f8 4180 trace_kvm_emulate_insn_start(vcpu);
571008da 4181
0cb5762e
AP		 4182 /* Only allow emulation of specific instructions on #UD
4183 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4184 if (emulation_type & EMULTYPE_TRAP_UD) {
4185 if (!c->twobyte)
4186 return EMULATE_FAIL;
4187 switch (c->b) {
4188 case 0x01: /* VMMCALL */
4189 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4190 return EMULATE_FAIL;
4191 break;
4192 case 0x34: /* sysenter */
4193 case 0x35: /* sysexit */
4194 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4195 return EMULATE_FAIL;
4196 break;
4197 case 0x05: /* syscall */
4198 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4199 return EMULATE_FAIL;
4200 break;
4201 default:
4202 return EMULATE_FAIL;
4203 }
4204
4205 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4206 return EMULATE_FAIL;
4207 }
571008da 4208
f2b5756b 4209 ++vcpu->stat.insn_emulation;
bbd9b64e 4210 if (r) {
a6f177ef 4211 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4212 return EMULATE_DONE;
6d77dbfc
GN		 4213 if (emulation_type & EMULTYPE_SKIP)
4214 return EMULATE_FAIL;
4215 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4216 }
4217 }
4218
ba8afb6b
GN		 4219 if (emulation_type & EMULTYPE_SKIP) {
4220 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4221 return EMULATE_DONE;
4222 }
4223
4d2179e1
GN		 4224 /* this is needed for vmware backdor interface to work since it
4225 changes registers values during IO operation */
4226 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4227
5cd21917 4228restart:
9aabc88f 4229 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4230
d2ddd1c4 4231 if (r == EMULATION_FAILED) {
a6f177ef 4232 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4233 return EMULATE_DONE;
4234
6d77dbfc 4235 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4236 }
4237
d2ddd1c4 4238 if (vcpu->arch.emulate_ctxt.exception >= 0) {
54b8486f 4239 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4240 r = EMULATE_DONE;
4241 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4242 if (!vcpu->arch.pio.in)
4243 vcpu->arch.pio.count = 0;
e85d28f8
GN		 4244 r = EMULATE_DO_MMIO;
4245 } else if (vcpu->mmio_needed) {
3457e419
GN		 4246 if (vcpu->mmio_is_write)
4247 vcpu->mmio_needed = 0;
e85d28f8 4248 r = EMULATE_DO_MMIO;
d2ddd1c4 4249 } else if (r == EMULATION_RESTART)
5cd21917 4250 goto restart;
d2ddd1c4
GN		 4251 else
4252 r = EMULATE_DONE;
f850e2e6 4253
e85d28f8
GN		 4254 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4255 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4256 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4257 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4258
4259 return r;
de7d789a 4260}
bbd9b64e 4261EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4262
cf8f70bf 4263int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4264{
cf8f70bf
GN		 4265 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4266 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4267 /* do not return to emulator after return from userspace */
7972995b 4268 vcpu->arch.pio.count = 0;
de7d789a
CO		 4269 return ret;
4270}
cf8f70bf 4271EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4272
8cfdc000
ZA		 4273static void tsc_bad(void *info)
4274{
4275 __get_cpu_var(cpu_tsc_khz) = 0;
4276}
4277
4278static void tsc_khz_changed(void *data)
c8076604 4279{
8cfdc000
ZA		 4280 struct cpufreq_freqs *freq = data;
4281 unsigned long khz = 0;
4282
4283 if (data)
4284 khz = freq->new;
4285 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4286 khz = cpufreq_quick_get(raw_smp_processor_id());
4287 if (!khz)
4288 khz = tsc_khz;
4289 __get_cpu_var(cpu_tsc_khz) = khz;
c8076604
GH		 4290}
4291
c8076604
GH		 4292static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4293 void *data)
4294{
4295 struct cpufreq_freqs *freq = data;
4296 struct kvm *kvm;
4297 struct kvm_vcpu *vcpu;
4298 int i, send_ipi = 0;
4299
8cfdc000
ZA		 4300 /*
4301 * We allow guests to temporarily run on slowing clocks,
4302 * provided we notify them after, or to run on accelerating
4303 * clocks, provided we notify them before. Thus time never
4304 * goes backwards.
4305 *
4306 * However, we have a problem. We can't atomically update
4307 * the frequency of a given CPU from this function; it is
4308 * merely a notifier, which can be called from any CPU.
4309 * Changing the TSC frequency at arbitrary points in time
4310 * requires a recomputation of local variables related to
4311 * the TSC for each VCPU. We must flag these local variables
4312 * to be updated and be sure the update takes place with the
4313 * new frequency before any guests proceed.
4314 *
4315 * Unfortunately, the combination of hotplug CPU and frequency
4316 * change creates an intractable locking scenario; the order
4317 * of when these callouts happen is undefined with respect to
4318 * CPU hotplug, and they can race with each other. As such,
4319 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4320 * undefined; you can actually have a CPU frequency change take
4321 * place in between the computation of X and the setting of the
4322 * variable. To protect against this problem, all updates of
4323 * the per_cpu tsc_khz variable are done in an interrupt
4324 * protected IPI, and all callers wishing to update the value
4325 * must wait for a synchronous IPI to complete (which is trivial
4326 * if the caller is on the CPU already). This establishes the
4327 * necessary total order on variable updates.
4328 *
4329 * Note that because a guest time update may take place
4330 * anytime after the setting of the VCPU's request bit, the
4331 * correct TSC value must be set before the request. However,
4332 * to ensure the update actually makes it to any guest which
4333 * starts running in hardware virtualization between the set
4334 * and the acquisition of the spinlock, we must also ping the
4335 * CPU after setting the request bit.
4336 *
4337 */
4338
c8076604
GH		 4339 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4340 return 0;
4341 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4342 return 0;
8cfdc000
ZA		 4343
4344 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4345
4346 spin_lock(&kvm_lock);
4347 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4348 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4349 if (vcpu->cpu != freq->cpu)
4350 continue;
4351 if (!kvm_request_guest_time_update(vcpu))
4352 continue;
4353 if (vcpu->cpu != smp_processor_id())
8cfdc000 4354 send_ipi = 1;
c8076604
GH		 4355 }
4356 }
4357 spin_unlock(&kvm_lock);
4358
4359 if (freq->old < freq->new && send_ipi) {
4360 /*
4361 * We upscale the frequency. Must make the guest
4362 * doesn't see old kvmclock values while running with
4363 * the new frequency, otherwise we risk the guest sees
4364 * time go backwards.
4365 *
4366 * In case we update the frequency for another cpu
4367 * (which might be in guest context) send an interrupt
4368 * to kick the cpu out of guest context. Next time
4369 * guest context is entered kvmclock will be updated,
4370 * so the guest will not see stale values.
4371 */
8cfdc000 4372 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4373 }
4374 return 0;
4375}
4376
4377static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4378 .notifier_call = kvmclock_cpufreq_notifier
4379};
4380
4381static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4382 unsigned long action, void *hcpu)
4383{
4384 unsigned int cpu = (unsigned long)hcpu;
4385
4386 switch (action) {
4387 case CPU_ONLINE:
4388 case CPU_DOWN_FAILED:
4389 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4390 break;
4391 case CPU_DOWN_PREPARE:
4392 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4393 break;
4394 }
4395 return NOTIFY_OK;
4396}
4397
4398static struct notifier_block kvmclock_cpu_notifier_block = {
4399 .notifier_call = kvmclock_cpu_notifier,
4400 .priority = -INT_MAX
c8076604
GH		 4401};
4402
b820cc0c
ZA		 4403static void kvm_timer_init(void)
4404{
4405 int cpu;
4406
8cfdc000 4407 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4408 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 4409 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4410 CPUFREQ_TRANSITION_NOTIFIER);
4411 }
8cfdc000
ZA		 4412 for_each_online_cpu(cpu)
4413 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4414}
4415
ff9d07a0
ZY		 4416static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4417
4418static int kvm_is_in_guest(void)
4419{
4420 return percpu_read(current_vcpu) != NULL;
4421}
4422
4423static int kvm_is_user_mode(void)
4424{
4425 int user_mode = 3;
dcf46b94 4426
ff9d07a0
ZY		 4427 if (percpu_read(current_vcpu))
4428 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4429
ff9d07a0
ZY		 4430 return user_mode != 0;
4431}
4432
4433static unsigned long kvm_get_guest_ip(void)
4434{
4435 unsigned long ip = 0;
dcf46b94 4436
ff9d07a0
ZY		 4437 if (percpu_read(current_vcpu))
4438 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4439
ff9d07a0
ZY		 4440 return ip;
4441}
4442
4443static struct perf_guest_info_callbacks kvm_guest_cbs = {
4444 .is_in_guest = kvm_is_in_guest,
4445 .is_user_mode = kvm_is_user_mode,
4446 .get_guest_ip = kvm_get_guest_ip,
4447};
4448
4449void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4450{
4451 percpu_write(current_vcpu, vcpu);
4452}
4453EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4454
4455void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4456{
4457 percpu_write(current_vcpu, NULL);
4458}
4459EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4460
f8c16bba 4461int kvm_arch_init(void *opaque)
043405e1 4462{
b820cc0c 4463 int r;
f8c16bba
ZX		 4464 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4465
f8c16bba
ZX		 4466 if (kvm_x86_ops) {
4467 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4468 r = -EEXIST;
4469 goto out;
f8c16bba
ZX		 4470 }
4471
4472 if (!ops->cpu_has_kvm_support()) {
4473 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4474 r = -EOPNOTSUPP;
4475 goto out;
f8c16bba
ZX		 4476 }
4477 if (ops->disabled_by_bios()) {
4478 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4479 r = -EOPNOTSUPP;
4480 goto out;
f8c16bba
ZX		 4481 }
4482
97db56ce
AK		 4483 r = kvm_mmu_module_init();
4484 if (r)
4485 goto out;
4486
4487 kvm_init_msr_list();
4488
f8c16bba 4489 kvm_x86_ops = ops;
56c6d28a 4490 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4491 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4492 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4493 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4494
b820cc0c 4495 kvm_timer_init();
c8076604 4496
ff9d07a0
ZY		 4497 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4498
2acf923e
DC		 4499 if (cpu_has_xsave)
4500 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4501
f8c16bba 4502 return 0;
56c6d28a
ZX		 4503
4504out:
56c6d28a 4505 return r;
043405e1 4506}
8776e519 4507
f8c16bba
ZX		 4508void kvm_arch_exit(void)
4509{
ff9d07a0
ZY		 4510 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4511
888d256e
JK		 4512 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4513 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4514 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4515 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4516 kvm_x86_ops = NULL;
56c6d28a
ZX		 4517 kvm_mmu_module_exit();
4518}
f8c16bba 4519
8776e519
HB		 4520int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4521{
4522 ++vcpu->stat.halt_exits;
4523 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4524 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4525 return 1;
4526 } else {
4527 vcpu->run->exit_reason = KVM_EXIT_HLT;
4528 return 0;
4529 }
4530}
4531EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4532
2f333bcb
MT		 4533static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4534 unsigned long a1)
4535{
4536 if (is_long_mode(vcpu))
4537 return a0;
4538 else
4539 return a0 | ((gpa_t)a1 << 32);
4540}
4541
55cd8e5a
GN		 4542int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4543{
4544 u64 param, ingpa, outgpa, ret;
4545 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4546 bool fast, longmode;
4547 int cs_db, cs_l;
4548
4549 /*
4550 * hypercall generates UD from non zero cpl and real mode
4551 * per HYPER-V spec
4552 */
3eeb3288 4553 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4554 kvm_queue_exception(vcpu, UD_VECTOR);
4555 return 0;
4556 }
4557
4558 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4559 longmode = is_long_mode(vcpu) && cs_l == 1;
4560
4561 if (!longmode) {
ccd46936
GN		 4562 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4563 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4564 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4565 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4566 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4567 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4568 }
4569#ifdef CONFIG_X86_64
4570 else {
4571 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4572 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4573 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4574 }
4575#endif
4576
4577 code = param & 0xffff;
4578 fast = (param >> 16) & 0x1;
4579 rep_cnt = (param >> 32) & 0xfff;
4580 rep_idx = (param >> 48) & 0xfff;
4581
4582 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4583
c25bc163
GN		 4584 switch (code) {
4585 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4586 kvm_vcpu_on_spin(vcpu);
4587 break;
4588 default:
4589 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4590 break;
4591 }
55cd8e5a
GN		 4592
4593 ret = res | (((u64)rep_done & 0xfff) << 32);
4594 if (longmode) {
4595 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4596 } else {
4597 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4598 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4599 }
4600
4601 return 1;
4602}
4603
8776e519
HB		 4604int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4605{
4606 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4607 int r = 1;
8776e519 4608
55cd8e5a
GN		 4609 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4610 return kvm_hv_hypercall(vcpu);
4611
5fdbf976
MT		 4612 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4613 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4614 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4615 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4616 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4617
229456fc 4618 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4619
8776e519
HB		 4620 if (!is_long_mode(vcpu)) {
4621 nr &= 0xFFFFFFFF;
4622 a0 &= 0xFFFFFFFF;
4623 a1 &= 0xFFFFFFFF;
4624 a2 &= 0xFFFFFFFF;
4625 a3 &= 0xFFFFFFFF;
4626 }
4627
07708c4a
JK		 4628 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4629 ret = -KVM_EPERM;
4630 goto out;
4631 }
4632
8776e519 4633 switch (nr) {
b93463aa
AK		 4634 case KVM_HC_VAPIC_POLL_IRQ:
4635 ret = 0;
4636 break;
2f333bcb
MT		 4637 case KVM_HC_MMU_OP:
4638 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4639 break;
8776e519
HB		 4640 default:
4641 ret = -KVM_ENOSYS;
4642 break;
4643 }
07708c4a 4644out:
5fdbf976 4645 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4646 ++vcpu->stat.hypercalls;
2f333bcb 4647 return r;
8776e519
HB		 4648}
4649EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4650
4651int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4652{
4653 char instruction[3];
5fdbf976 4654 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4655
8776e519
HB		 4656 /*
4657 * Blow out the MMU to ensure that no other VCPU has an active mapping
4658 * to ensure that the updated hypercall appears atomically across all
4659 * VCPUs.
4660 */
4661 kvm_mmu_zap_all(vcpu->kvm);
4662
8776e519 4663 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4664
8fe681e9 4665 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4666}
4667
8776e519
HB		 4668void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4669{
89a27f4d 4670 struct desc_ptr dt = { limit, base };
8776e519
HB		 4671
4672 kvm_x86_ops->set_gdt(vcpu, &dt);
4673}
4674
4675void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4676{
89a27f4d 4677 struct desc_ptr dt = { limit, base };
8776e519
HB		 4678
4679 kvm_x86_ops->set_idt(vcpu, &dt);
4680}
4681
07716717
DK		 4682static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4683{
ad312c7c
ZX		 4684 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4685 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4686
4687 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4688 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4689 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4690 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4691 if (ej->function == e->function) {
4692 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4693 return j;
4694 }
4695 }
4696 return 0; /* silence gcc, even though control never reaches here */
4697}
4698
4699/* find an entry with matching function, matching index (if needed), and that
4700 * should be read next (if it's stateful) */
4701static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4702 u32 function, u32 index)
4703{
4704 if (e->function != function)
4705 return 0;
4706 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4707 return 0;
4708 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4709 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4710 return 0;
4711 return 1;
4712}
4713
d8017474
AG		 4714struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4715 u32 function, u32 index)
8776e519
HB		 4716{
4717 int i;
d8017474 4718 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4719
ad312c7c 4720 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4721 struct kvm_cpuid_entry2 *e;
4722
ad312c7c 4723 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4724 if (is_matching_cpuid_entry(e, function, index)) {
4725 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4726 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4727 best = e;
4728 break;
4729 }
4730 /*
4731 * Both basic or both extended?
4732 */
4733 if (((e->function ^ function) & 0x80000000) == 0)
4734 if (!best || e->function > best->function)
4735 best = e;
4736 }
d8017474
AG		 4737 return best;
4738}
0e851880 4739EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4740
82725b20
DE		 4741int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4742{
4743 struct kvm_cpuid_entry2 *best;
4744
f7a71197
AK		 4745 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4746 if (!best || best->eax < 0x80000008)
4747 goto not_found;
82725b20
DE		 4748 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4749 if (best)
4750 return best->eax & 0xff;
f7a71197 4751not_found:
82725b20
DE		 4752 return 36;
4753}
4754
d8017474
AG		 4755void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4756{
4757 u32 function, index;
4758 struct kvm_cpuid_entry2 *best;
4759
4760 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4761 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4762 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4763 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4764 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4765 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4766 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4767 if (best) {
5fdbf976
MT		 4768 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4769 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4770 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4771 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4772 }
8776e519 4773 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4774 trace_kvm_cpuid(function,
4775 kvm_register_read(vcpu, VCPU_REGS_RAX),
4776 kvm_register_read(vcpu, VCPU_REGS_RBX),
4777 kvm_register_read(vcpu, VCPU_REGS_RCX),
4778 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4779}
4780EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4781
b6c7a5dc
HB		 4782/*
4783 * Check if userspace requested an interrupt window, and that the
4784 * interrupt window is open.
4785 *
4786 * No need to exit to userspace if we already have an interrupt queued.
4787 */
851ba692 4788static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4789{
8061823a 4790 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4791 vcpu->run->request_interrupt_window &&
5df56646 4792 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4793}
4794
851ba692 4795static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4796{
851ba692
AK		 4797 struct kvm_run *kvm_run = vcpu->run;
4798
91586a3b 4799 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4800 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4801 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4802 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4803 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4804 else
b6c7a5dc 4805 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4806 kvm_arch_interrupt_allowed(vcpu) &&
4807 !kvm_cpu_has_interrupt(vcpu) &&
4808 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4809}
4810
b93463aa
AK		 4811static void vapic_enter(struct kvm_vcpu *vcpu)
4812{
4813 struct kvm_lapic *apic = vcpu->arch.apic;
4814 struct page *page;
4815
4816 if (!apic || !apic->vapic_addr)
4817 return;
4818
4819 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4820
4821 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4822}
4823
4824static void vapic_exit(struct kvm_vcpu *vcpu)
4825{
4826 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4827 int idx;
b93463aa
AK		 4828
4829 if (!apic || !apic->vapic_addr)
4830 return;
4831
f656ce01 4832 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4833 kvm_release_page_dirty(apic->vapic_page);
4834 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4835 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4836}
4837
95ba8273
GN		 4838static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4839{
4840 int max_irr, tpr;
4841
4842 if (!kvm_x86_ops->update_cr8_intercept)
4843 return;
4844
88c808fd
AK		 4845 if (!vcpu->arch.apic)
4846 return;
4847
8db3baa2
GN		 4848 if (!vcpu->arch.apic->vapic_addr)
4849 max_irr = kvm_lapic_find_highest_irr(vcpu);
4850 else
4851 max_irr = -1;
95ba8273
GN		 4852
4853 if (max_irr != -1)
4854 max_irr >>= 4;
4855
4856 tpr = kvm_lapic_get_cr8(vcpu);
4857
4858 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4859}
4860
851ba692 4861static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4862{
4863 /* try to reinject previous events if any */
b59bb7bd 4864 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4865 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4866 vcpu->arch.exception.has_error_code,
4867 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4868 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4869 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4870 vcpu->arch.exception.error_code,
4871 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4872 return;
4873 }
4874
95ba8273
GN		 4875 if (vcpu->arch.nmi_injected) {
4876 kvm_x86_ops->set_nmi(vcpu);
4877 return;
4878 }
4879
4880 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4881 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4882 return;
4883 }
4884
4885 /* try to inject new event if pending */
4886 if (vcpu->arch.nmi_pending) {
4887 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4888 vcpu->arch.nmi_pending = false;
4889 vcpu->arch.nmi_injected = true;
4890 kvm_x86_ops->set_nmi(vcpu);
4891 }
4892 } else if (kvm_cpu_has_interrupt(vcpu)) {
4893 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4894 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4895 false);
4896 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4897 }
4898 }
4899}
4900
2acf923e
DC		 4901static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
4902{
4903 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
4904 !vcpu->guest_xcr0_loaded) {
4905 /* kvm_set_xcr() also depends on this */
4906 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
4907 vcpu->guest_xcr0_loaded = 1;
4908 }
4909}
4910
4911static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
4912{
4913 if (vcpu->guest_xcr0_loaded) {
4914 if (vcpu->arch.xcr0 != host_xcr0)
4915 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
4916 vcpu->guest_xcr0_loaded = 0;
4917 }
4918}
4919
851ba692 4920static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4921{
4922 int r;
6a8b1d13 4923 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4924 vcpu->run->request_interrupt_window;
b6c7a5dc 4925
3e007509 4926 if (vcpu->requests) {
a8eeb04a 4927 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 4928 kvm_mmu_unload(vcpu);
a8eeb04a 4929 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 4930 __kvm_migrate_timers(vcpu);
8cfdc000
ZA		 4931 if (kvm_check_request(KVM_REQ_KVMCLOCK_UPDATE, vcpu)) {
4932 r = kvm_write_guest_time(vcpu);
4933 if (unlikely(r))
4934 goto out;
4935 }
a8eeb04a 4936 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 4937 kvm_mmu_sync_roots(vcpu);
a8eeb04a 4938 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 4939 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 4940 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 4941 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4942 r = 0;
4943 goto out;
4944 }
a8eeb04a 4945 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 4946 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4947 r = 0;
4948 goto out;
4949 }
a8eeb04a 4950 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 4951 vcpu->fpu_active = 0;
4952 kvm_x86_ops->fpu_deactivate(vcpu);
4953 }
2f52d58c 4954 }
b93463aa 4955
3e007509
AK		 4956 r = kvm_mmu_reload(vcpu);
4957 if (unlikely(r))
4958 goto out;
4959
b6c7a5dc
HB		 4960 preempt_disable();
4961
4962 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4963 if (vcpu->fpu_active)
4964 kvm_load_guest_fpu(vcpu);
2acf923e 4965 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 4966
d94e1dc9
AK		 4967 atomic_set(&vcpu->guest_mode, 1);
4968 smp_wmb();
b6c7a5dc 4969
d94e1dc9 4970 local_irq_disable();
32f88400 4971
d94e1dc9
AK		 4972 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
4973 || need_resched() || signal_pending(current)) {
4974 atomic_set(&vcpu->guest_mode, 0);
4975 smp_wmb();
6c142801
AK		 4976 local_irq_enable();
4977 preempt_enable();
4978 r = 1;
4979 goto out;
4980 }
4981
851ba692 4982 inject_pending_event(vcpu);
b6c7a5dc 4983
6a8b1d13
GN		 4984 /* enable NMI/IRQ window open exits if needed */
4985 if (vcpu->arch.nmi_pending)
4986 kvm_x86_ops->enable_nmi_window(vcpu);
4987 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4988 kvm_x86_ops->enable_irq_window(vcpu);
4989
95ba8273 4990 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4991 update_cr8_intercept(vcpu);
4992 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4993 }
b93463aa 4994
f656ce01 4995 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4996
b6c7a5dc
HB		 4997 kvm_guest_enter();
4998
42dbaa5a 4999 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5000 set_debugreg(0, 7);
5001 set_debugreg(vcpu->arch.eff_db[0], 0);
5002 set_debugreg(vcpu->arch.eff_db[1], 1);
5003 set_debugreg(vcpu->arch.eff_db[2], 2);
5004 set_debugreg(vcpu->arch.eff_db[3], 3);
5005 }
b6c7a5dc 5006
229456fc 5007 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5008 kvm_x86_ops->run(vcpu);
b6c7a5dc 5009
24f1e32c
FW		 5010 /*
5011 * If the guest has used debug registers, at least dr7
5012 * will be disabled while returning to the host.
5013 * If we don't have active breakpoints in the host, we don't
5014 * care about the messed up debug address registers. But if
5015 * we have some of them active, restore the old state.
5016 */
59d8eb53 5017 if (hw_breakpoint_active())
24f1e32c 5018 hw_breakpoint_restore();
42dbaa5a 5019
1d5f066e
ZA		 5020 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5021
d94e1dc9
AK		 5022 atomic_set(&vcpu->guest_mode, 0);
5023 smp_wmb();
b6c7a5dc
HB		 5024 local_irq_enable();
5025
5026 ++vcpu->stat.exits;
5027
5028 /*
5029 * We must have an instruction between local_irq_enable() and
5030 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5031 * the interrupt shadow. The stat.exits increment will do nicely.
5032 * But we need to prevent reordering, hence this barrier():
5033 */
5034 barrier();
5035
5036 kvm_guest_exit();
5037
5038 preempt_enable();
5039
f656ce01 5040 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5041
b6c7a5dc
HB		 5042 /*
5043 * Profile KVM exit RIPs:
5044 */
5045 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5046 unsigned long rip = kvm_rip_read(vcpu);
5047 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5048 }
5049
298101da 5050
b93463aa
AK		 5051 kvm_lapic_sync_from_vapic(vcpu);
5052
851ba692 5053 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5054out:
5055 return r;
5056}
b6c7a5dc 5057
09cec754 5058
851ba692 5059static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5060{
5061 int r;
f656ce01 5062 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5063
5064 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5065 pr_debug("vcpu %d received sipi with vector # %x\n",
5066 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5067 kvm_lapic_reset(vcpu);
5f179287 5068 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5069 if (r)
5070 return r;
5071 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5072 }
5073
f656ce01 5074 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5075 vapic_enter(vcpu);
5076
5077 r = 1;
5078 while (r > 0) {
af2152f5 5079 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 5080 r = vcpu_enter_guest(vcpu);
d7690175 5081 else {
f656ce01 5082 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5083 kvm_vcpu_block(vcpu);
f656ce01 5084 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5085 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5086 {
5087 switch(vcpu->arch.mp_state) {
5088 case KVM_MP_STATE_HALTED:
d7690175 5089 vcpu->arch.mp_state =
09cec754
GN		 5090 KVM_MP_STATE_RUNNABLE;
5091 case KVM_MP_STATE_RUNNABLE:
5092 break;
5093 case KVM_MP_STATE_SIPI_RECEIVED:
5094 default:
5095 r = -EINTR;
5096 break;
5097 }
5098 }
d7690175
MT		 5099 }
5100
09cec754
GN		 5101 if (r <= 0)
5102 break;
5103
5104 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5105 if (kvm_cpu_has_pending_timer(vcpu))
5106 kvm_inject_pending_timer_irqs(vcpu);
5107
851ba692 5108 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5109 r = -EINTR;
851ba692 5110 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5111 ++vcpu->stat.request_irq_exits;
5112 }
5113 if (signal_pending(current)) {
5114 r = -EINTR;
851ba692 5115 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5116 ++vcpu->stat.signal_exits;
5117 }
5118 if (need_resched()) {
f656ce01 5119 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5120 kvm_resched(vcpu);
f656ce01 5121 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5122 }
b6c7a5dc
HB		 5123 }
5124
f656ce01 5125 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5126
b93463aa
AK		 5127 vapic_exit(vcpu);
5128
b6c7a5dc
HB		 5129 return r;
5130}
5131
5132int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5133{
5134 int r;
5135 sigset_t sigsaved;
5136
ac9f6dc0
AK		 5137 if (vcpu->sigset_active)
5138 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5139
a4535290 5140 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5141 kvm_vcpu_block(vcpu);
d7690175 5142 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5143 r = -EAGAIN;
5144 goto out;
b6c7a5dc
HB		 5145 }
5146
b6c7a5dc
HB		 5147 /* re-sync apic's tpr */
5148 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 5149 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 5150
d2ddd1c4 5151 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
92bf9748
GN		 5152 if (vcpu->mmio_needed) {
5153 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5154 vcpu->mmio_read_completed = 1;
5155 vcpu->mmio_needed = 0;
b6c7a5dc 5156 }
f656ce01 5157 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 5158 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 5159 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 5160 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 5161 r = 0;
5162 goto out;
5163 }
5164 }
5fdbf976
MT		 5165 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5166 kvm_register_write(vcpu, VCPU_REGS_RAX,
5167 kvm_run->hypercall.ret);
b6c7a5dc 5168
851ba692 5169 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5170
5171out:
f1d86e46 5172 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5173 if (vcpu->sigset_active)
5174 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5175
b6c7a5dc
HB		 5176 return r;
5177}
5178
5179int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5180{
5fdbf976
MT		 5181 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5182 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5183 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5184 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5185 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5186 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5187 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5188 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5189#ifdef CONFIG_X86_64
5fdbf976
MT		 5190 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5191 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5192 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5193 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5194 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5195 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5196 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5197 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5198#endif
5199
5fdbf976 5200 regs->rip = kvm_rip_read(vcpu);
91586a3b 5201 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5202
b6c7a5dc
HB		 5203 return 0;
5204}
5205
5206int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5207{
5fdbf976
MT		 5208 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5209 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5210 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5211 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5212 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5213 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5214 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5215 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5216#ifdef CONFIG_X86_64
5fdbf976
MT		 5217 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5218 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5219 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5220 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5221 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5222 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5223 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5224 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5225#endif
5226
5fdbf976 5227 kvm_rip_write(vcpu, regs->rip);
91586a3b 5228 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5229
b4f14abd
JK		 5230 vcpu->arch.exception.pending = false;
5231
b6c7a5dc
HB		 5232 return 0;
5233}
5234
b6c7a5dc
HB		 5235void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5236{
5237 struct kvm_segment cs;
5238
3e6e0aab 5239 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5240 *db = cs.db;
5241 *l = cs.l;
5242}
5243EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5244
5245int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5246 struct kvm_sregs *sregs)
5247{
89a27f4d 5248 struct desc_ptr dt;
b6c7a5dc 5249
3e6e0aab
GT		 5250 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5251 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5252 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5253 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5254 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5255 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5256
3e6e0aab
GT		 5257 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5258 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5259
5260 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5261 sregs->idt.limit = dt.size;
5262 sregs->idt.base = dt.address;
b6c7a5dc 5263 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5264 sregs->gdt.limit = dt.size;
5265 sregs->gdt.base = dt.address;
b6c7a5dc 5266
4d4ec087 5267 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 5268 sregs->cr2 = vcpu->arch.cr2;
5269 sregs->cr3 = vcpu->arch.cr3;
fc78f519 5270 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5271 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5272 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5273 sregs->apic_base = kvm_get_apic_base(vcpu);
5274
923c61bb 5275 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5276
36752c9b 5277 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5278 set_bit(vcpu->arch.interrupt.nr,
5279 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5280
b6c7a5dc
HB		 5281 return 0;
5282}
5283
62d9f0db
MT		 5284int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5285 struct kvm_mp_state *mp_state)
5286{
62d9f0db 5287 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5288 return 0;
5289}
5290
5291int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5292 struct kvm_mp_state *mp_state)
5293{
62d9f0db 5294 vcpu->arch.mp_state = mp_state->mp_state;
62d9f0db
MT		 5295 return 0;
5296}
5297
e269fb21
JK		 5298int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5299 bool has_error_code, u32 error_code)
b6c7a5dc 5300{
4d2179e1 5301 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5302 int ret;
e01c2426 5303
8ec4722d 5304 init_emulate_ctxt(vcpu);
c697518a 5305
9aabc88f 5306 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5307 tss_selector, reason, has_error_code,
5308 error_code);
c697518a 5309
c697518a 5310 if (ret)
19d04437 5311 return EMULATE_FAIL;
37817f29 5312
4d2179e1 5313 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5314 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437
GN		 5315 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
5316 return EMULATE_DONE;
37817f29
IE		 5317}
5318EXPORT_SYMBOL_GPL(kvm_task_switch);
5319
b6c7a5dc
HB		 5320int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5321 struct kvm_sregs *sregs)
5322{
5323 int mmu_reset_needed = 0;
923c61bb 5324 int pending_vec, max_bits;
89a27f4d 5325 struct desc_ptr dt;
b6c7a5dc 5326
89a27f4d
GN		 5327 dt.size = sregs->idt.limit;
5328 dt.address = sregs->idt.base;
b6c7a5dc 5329 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5330 dt.size = sregs->gdt.limit;
5331 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5332 kvm_x86_ops->set_gdt(vcpu, &dt);
5333
ad312c7c
ZX		 5334 vcpu->arch.cr2 = sregs->cr2;
5335 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5336 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5337
2d3ad1f4 5338 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5339
f6801dff 5340 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5341 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5342 kvm_set_apic_base(vcpu, sregs->apic_base);
5343
4d4ec087 5344 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5345 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5346 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5347
fc78f519 5348 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5349 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5350 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 5351 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 5352 mmu_reset_needed = 1;
5353 }
b6c7a5dc
HB		 5354
5355 if (mmu_reset_needed)
5356 kvm_mmu_reset_context(vcpu);
5357
923c61bb
GN		 5358 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5359 pending_vec = find_first_bit(
5360 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5361 if (pending_vec < max_bits) {
66fd3f7f 5362 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5363 pr_debug("Set back pending irq %d\n", pending_vec);
5364 if (irqchip_in_kernel(vcpu->kvm))
5365 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5366 }
5367
3e6e0aab
GT		 5368 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5369 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5370 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5371 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5372 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5373 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5374
3e6e0aab
GT		 5375 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5376 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5377
5f0269f5
ME		 5378 update_cr8_intercept(vcpu);
5379
9c3e4aab 5380 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5381 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5382 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5383 !is_protmode(vcpu))
9c3e4aab
MT		 5384 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5385
b6c7a5dc
HB		 5386 return 0;
5387}
5388
d0bfb940
JK		 5389int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5390 struct kvm_guest_debug *dbg)
b6c7a5dc 5391{
355be0b9 5392 unsigned long rflags;
ae675ef0 5393 int i, r;
b6c7a5dc 5394
4f926bf2
JK		 5395 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5396 r = -EBUSY;
5397 if (vcpu->arch.exception.pending)
2122ff5e 5398 goto out;
4f926bf2
JK		 5399 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5400 kvm_queue_exception(vcpu, DB_VECTOR);
5401 else
5402 kvm_queue_exception(vcpu, BP_VECTOR);
5403 }
5404
91586a3b
JK		 5405 /*
5406 * Read rflags as long as potentially injected trace flags are still
5407 * filtered out.
5408 */
5409 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5410
5411 vcpu->guest_debug = dbg->control;
5412 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5413 vcpu->guest_debug = 0;
5414
5415 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5416 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5417 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5418 vcpu->arch.switch_db_regs =
5419 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5420 } else {
5421 for (i = 0; i < KVM_NR_DB_REGS; i++)
5422 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5423 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5424 }
5425
f92653ee
JK		 5426 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5427 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5428 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5429
91586a3b
JK		 5430 /*
5431 * Trigger an rflags update that will inject or remove the trace
5432 * flags.
5433 */
5434 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5435
355be0b9 5436 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5437
4f926bf2 5438 r = 0;
d0bfb940 5439
2122ff5e 5440out:
b6c7a5dc
HB		 5441
5442 return r;
5443}
5444
8b006791
ZX		 5445/*
5446 * Translate a guest virtual address to a guest physical address.
5447 */
5448int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5449 struct kvm_translation *tr)
5450{
5451 unsigned long vaddr = tr->linear_address;
5452 gpa_t gpa;
f656ce01 5453 int idx;
8b006791 5454
f656ce01 5455 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5456 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5457 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5458 tr->physical_address = gpa;
5459 tr->valid = gpa != UNMAPPED_GVA;
5460 tr->writeable = 1;
5461 tr->usermode = 0;
8b006791
ZX		 5462
5463 return 0;
5464}
5465
d0752060
HB		 5466int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5467{
98918833
SY		 5468 struct i387_fxsave_struct *fxsave =
5469 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5470
d0752060
HB		 5471 memcpy(fpu->fpr, fxsave->st_space, 128);
5472 fpu->fcw = fxsave->cwd;
5473 fpu->fsw = fxsave->swd;
5474 fpu->ftwx = fxsave->twd;
5475 fpu->last_opcode = fxsave->fop;
5476 fpu->last_ip = fxsave->rip;
5477 fpu->last_dp = fxsave->rdp;
5478 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5479
d0752060
HB		 5480 return 0;
5481}
5482
5483int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5484{
98918833
SY		 5485 struct i387_fxsave_struct *fxsave =
5486 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5487
d0752060
HB		 5488 memcpy(fxsave->st_space, fpu->fpr, 128);
5489 fxsave->cwd = fpu->fcw;
5490 fxsave->swd = fpu->fsw;
5491 fxsave->twd = fpu->ftwx;
5492 fxsave->fop = fpu->last_opcode;
5493 fxsave->rip = fpu->last_ip;
5494 fxsave->rdp = fpu->last_dp;
5495 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5496
d0752060
HB		 5497 return 0;
5498}
5499
10ab25cd 5500int fx_init(struct kvm_vcpu *vcpu)
d0752060 5501{
10ab25cd
JK		 5502 int err;
5503
5504 err = fpu_alloc(&vcpu->arch.guest_fpu);
5505 if (err)
5506 return err;
5507
98918833 5508 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5509
2acf923e
DC		 5510 /*
5511 * Ensure guest xcr0 is valid for loading
5512 */
5513 vcpu->arch.xcr0 = XSTATE_FP;
5514
ad312c7c 5515 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5516
5517 return 0;
d0752060
HB		 5518}
5519EXPORT_SYMBOL_GPL(fx_init);
5520
98918833
SY		 5521static void fx_free(struct kvm_vcpu *vcpu)
5522{
5523 fpu_free(&vcpu->arch.guest_fpu);
5524}
5525
d0752060
HB		 5526void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5527{
2608d7a1 5528 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5529 return;
5530
2acf923e
DC		 5531 /*
5532 * Restore all possible states in the guest,
5533 * and assume host would use all available bits.
5534 * Guest xcr0 would be loaded later.
5535 */
5536 kvm_put_guest_xcr0(vcpu);
d0752060 5537 vcpu->guest_fpu_loaded = 1;
7cf30855 5538 unlazy_fpu(current);
98918833 5539 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5540 trace_kvm_fpu(1);
d0752060 5541}
d0752060
HB		 5542
5543void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5544{
2acf923e
DC		 5545 kvm_put_guest_xcr0(vcpu);
5546
d0752060
HB		 5547 if (!vcpu->guest_fpu_loaded)
5548 return;
5549
5550 vcpu->guest_fpu_loaded = 0;
98918833 5551 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5552 ++vcpu->stat.fpu_reload;
a8eeb04a 5553 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5554 trace_kvm_fpu(0);
d0752060 5555}
e9b11c17
ZX		 5556
5557void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5558{
7f1ea208
JR		 5559 if (vcpu->arch.time_page) {
5560 kvm_release_page_dirty(vcpu->arch.time_page);
5561 vcpu->arch.time_page = NULL;
5562 }
5563
f5f48ee1 5564 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5565 fx_free(vcpu);
e9b11c17
ZX		 5566 kvm_x86_ops->vcpu_free(vcpu);
5567}
5568
5569struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5570 unsigned int id)
5571{
6755bae8
ZA		 5572 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5573 printk_once(KERN_WARNING
5574 "kvm: SMP vm created on host with unstable TSC; "
5575 "guest TSC will not be reliable\n");
26e5215f
AK		 5576 return kvm_x86_ops->vcpu_create(kvm, id);
5577}
e9b11c17 5578
26e5215f
AK		 5579int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5580{
5581 int r;
e9b11c17 5582
0bed3b56 5583 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5584 vcpu_load(vcpu);
5585 r = kvm_arch_vcpu_reset(vcpu);
5586 if (r == 0)
5587 r = kvm_mmu_setup(vcpu);
5588 vcpu_put(vcpu);
5589 if (r < 0)
5590 goto free_vcpu;
5591
26e5215f 5592 return 0;
e9b11c17
ZX		 5593free_vcpu:
5594 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5595 return r;
e9b11c17
ZX		 5596}
5597
d40ccc62 5598void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5599{
5600 vcpu_load(vcpu);
5601 kvm_mmu_unload(vcpu);
5602 vcpu_put(vcpu);
5603
98918833 5604 fx_free(vcpu);
e9b11c17
ZX		 5605 kvm_x86_ops->vcpu_free(vcpu);
5606}
5607
5608int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5609{
448fa4a9
JK		 5610 vcpu->arch.nmi_pending = false;
5611 vcpu->arch.nmi_injected = false;
5612
42dbaa5a
JK		 5613 vcpu->arch.switch_db_regs = 0;
5614 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5615 vcpu->arch.dr6 = DR6_FIXED_1;
5616 vcpu->arch.dr7 = DR7_FIXED_1;
5617
e9b11c17
ZX		 5618 return kvm_x86_ops->vcpu_reset(vcpu);
5619}
5620
10474ae8 5621int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5622{
ca84d1a2
ZA		 5623 struct kvm *kvm;
5624 struct kvm_vcpu *vcpu;
5625 int i;
5626
18863bdd 5627 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5628 list_for_each_entry(kvm, &vm_list, vm_list)
5629 kvm_for_each_vcpu(i, vcpu, kvm)
5630 if (vcpu->cpu == smp_processor_id())
5631 kvm_request_guest_time_update(vcpu);
10474ae8 5632 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5633}
5634
5635void kvm_arch_hardware_disable(void *garbage)
5636{
5637 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5638 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5639}
5640
5641int kvm_arch_hardware_setup(void)
5642{
5643 return kvm_x86_ops->hardware_setup();
5644}
5645
5646void kvm_arch_hardware_unsetup(void)
5647{
5648 kvm_x86_ops->hardware_unsetup();
5649}
5650
5651void kvm_arch_check_processor_compat(void *rtn)
5652{
5653 kvm_x86_ops->check_processor_compatibility(rtn);
5654}
5655
5656int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5657{
5658 struct page *page;
5659 struct kvm *kvm;
5660 int r;
5661
5662 BUG_ON(vcpu->kvm == NULL);
5663 kvm = vcpu->kvm;
5664
9aabc88f 5665 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
ad312c7c 5666 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 5667 vcpu->arch.mmu.translate_gpa = translate_gpa;
c5af89b6 5668 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5669 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5670 else
a4535290 5671 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5672
5673 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5674 if (!page) {
5675 r = -ENOMEM;
5676 goto fail;
5677 }
ad312c7c 5678 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5679
5680 r = kvm_mmu_create(vcpu);
5681 if (r < 0)
5682 goto fail_free_pio_data;
5683
5684 if (irqchip_in_kernel(kvm)) {
5685 r = kvm_create_lapic(vcpu);
5686 if (r < 0)
5687 goto fail_mmu_destroy;
5688 }
5689
890ca9ae
HY		 5690 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5691 GFP_KERNEL);
5692 if (!vcpu->arch.mce_banks) {
5693 r = -ENOMEM;
443c39bc 5694 goto fail_free_lapic;
890ca9ae
HY		 5695 }
5696 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5697
f5f48ee1
SY		 5698 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5699 goto fail_free_mce_banks;
5700
e9b11c17 5701 return 0;
f5f48ee1
SY		 5702fail_free_mce_banks:
5703 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5704fail_free_lapic:
5705 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5706fail_mmu_destroy:
5707 kvm_mmu_destroy(vcpu);
5708fail_free_pio_data:
ad312c7c 5709 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5710fail:
5711 return r;
5712}
5713
5714void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5715{
f656ce01
MT		 5716 int idx;
5717
36cb93fd 5718 kfree(vcpu->arch.mce_banks);
e9b11c17 5719 kvm_free_lapic(vcpu);
f656ce01 5720 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5721 kvm_mmu_destroy(vcpu);
f656ce01 5722 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5723 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5724}
d19a9cd2
ZX		 5725
5726struct kvm *kvm_arch_create_vm(void)
5727{
5728 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5729
5730 if (!kvm)
5731 return ERR_PTR(-ENOMEM);
5732
f05e70ac 5733 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5734 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5735
5550af4d
SY		 5736 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5737 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5738
99e3e30a
ZA		 5739 spin_lock_init(&kvm->arch.tsc_write_lock);
5740
d19a9cd2
ZX		 5741 return kvm;
5742}
5743
5744static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5745{
5746 vcpu_load(vcpu);
5747 kvm_mmu_unload(vcpu);
5748 vcpu_put(vcpu);
5749}
5750
5751static void kvm_free_vcpus(struct kvm *kvm)
5752{
5753 unsigned int i;
988a2cae 5754 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5755
5756 /*
5757 * Unpin any mmu pages first.
5758 */
988a2cae
GN		 5759 kvm_for_each_vcpu(i, vcpu, kvm)
5760 kvm_unload_vcpu_mmu(vcpu);
5761 kvm_for_each_vcpu(i, vcpu, kvm)
5762 kvm_arch_vcpu_free(vcpu);
5763
5764 mutex_lock(&kvm->lock);
5765 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5766 kvm->vcpus[i] = NULL;
d19a9cd2 5767
988a2cae
GN		 5768 atomic_set(&kvm->online_vcpus, 0);
5769 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5770}
5771
ad8ba2cd
SY		 5772void kvm_arch_sync_events(struct kvm *kvm)
5773{
ba4cef31 5774 kvm_free_all_assigned_devices(kvm);
aea924f6 5775 kvm_free_pit(kvm);
ad8ba2cd
SY		 5776}
5777
d19a9cd2
ZX		 5778void kvm_arch_destroy_vm(struct kvm *kvm)
5779{
6eb55818 5780 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 5781 kfree(kvm->arch.vpic);
5782 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5783 kvm_free_vcpus(kvm);
5784 kvm_free_physmem(kvm);
3d45830c
AK		 5785 if (kvm->arch.apic_access_page)
5786 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5787 if (kvm->arch.ept_identity_pagetable)
5788 put_page(kvm->arch.ept_identity_pagetable);
64749204 5789 cleanup_srcu_struct(&kvm->srcu);
d19a9cd2
ZX		 5790 kfree(kvm);
5791}
0de10343 5792
f7784b8e
MT		 5793int kvm_arch_prepare_memory_region(struct kvm *kvm,
5794 struct kvm_memory_slot *memslot,
0de10343 5795 struct kvm_memory_slot old,
f7784b8e 5796 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5797 int user_alloc)
5798{
f7784b8e 5799 int npages = memslot->npages;
7ac77099
AK		 5800 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
5801
5802 /* Prevent internal slot pages from being moved by fork()/COW. */
5803 if (memslot->id >= KVM_MEMORY_SLOTS)
5804 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 5805
5806 /*To keep backward compatibility with older userspace,
5807 *x86 needs to hanlde !user_alloc case.
5808 */
5809 if (!user_alloc) {
5810 if (npages && !old.rmap) {
604b38ac
AA		 5811 unsigned long userspace_addr;
5812
72dc67a6 5813 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5814 userspace_addr = do_mmap(NULL, 0,
5815 npages * PAGE_SIZE,
5816 PROT_READ | PROT_WRITE,
7ac77099 5817 map_flags,
604b38ac 5818 0);
72dc67a6 5819 up_write(&current->mm->mmap_sem);
0de10343 5820
604b38ac
AA		 5821 if (IS_ERR((void *)userspace_addr))
5822 return PTR_ERR((void *)userspace_addr);
5823
604b38ac 5824 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5825 }
5826 }
5827
f7784b8e
MT		 5828
5829 return 0;
5830}
5831
5832void kvm_arch_commit_memory_region(struct kvm *kvm,
5833 struct kvm_userspace_memory_region *mem,
5834 struct kvm_memory_slot old,
5835 int user_alloc)
5836{
5837
5838 int npages = mem->memory_size >> PAGE_SHIFT;
5839
5840 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5841 int ret;
5842
5843 down_write(&current->mm->mmap_sem);
5844 ret = do_munmap(current->mm, old.userspace_addr,
5845 old.npages * PAGE_SIZE);
5846 up_write(&current->mm->mmap_sem);
5847 if (ret < 0)
5848 printk(KERN_WARNING
5849 "kvm_vm_ioctl_set_memory_region: "
5850 "failed to munmap memory\n");
5851 }
5852
7c8a83b7 5853 spin_lock(&kvm->mmu_lock);
f05e70ac 5854 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5855 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5856 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5857 }
5858
5859 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5860 spin_unlock(&kvm->mmu_lock);
0de10343 5861}
1d737c8a 5862
34d4cb8f
MT		 5863void kvm_arch_flush_shadow(struct kvm *kvm)
5864{
5865 kvm_mmu_zap_all(kvm);
8986ecc0 5866 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5867}
5868
1d737c8a
ZX		 5869int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5870{
a4535290 5871 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5872 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5873 || vcpu->arch.nmi_pending ||
5874 (kvm_arch_interrupt_allowed(vcpu) &&
5875 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5876}
5736199a 5877
5736199a
ZX		 5878void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5879{
32f88400
MT		 5880 int me;
5881 int cpu = vcpu->cpu;
5736199a
ZX		 5882
5883 if (waitqueue_active(&vcpu->wq)) {
5884 wake_up_interruptible(&vcpu->wq);
5885 ++vcpu->stat.halt_wakeup;
5886 }
32f88400
MT		 5887
5888 me = get_cpu();
5889 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 5890 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 5891 smp_send_reschedule(cpu);
e9571ed5 5892 put_cpu();
5736199a 5893}
78646121
GN		 5894
5895int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5896{
5897 return kvm_x86_ops->interrupt_allowed(vcpu);
5898}
229456fc 5899
f92653ee
JK		 5900bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5901{
5902 unsigned long current_rip = kvm_rip_read(vcpu) +
5903 get_segment_base(vcpu, VCPU_SREG_CS);
5904
5905 return current_rip == linear_rip;
5906}
5907EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5908
94fe45da
JK		 5909unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5910{
5911 unsigned long rflags;
5912
5913 rflags = kvm_x86_ops->get_rflags(vcpu);
5914 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5915 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5916 return rflags;
5917}
5918EXPORT_SYMBOL_GPL(kvm_get_rflags);
5919
5920void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5921{
5922 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5923 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 5924 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 5925 kvm_x86_ops->set_rflags(vcpu, rflags);
5926}
5927EXPORT_SYMBOL_GPL(kvm_set_rflags);
5928
229456fc
MT		 5929EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5930EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5931EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5932EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5933EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5934EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5935EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5936EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5937EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5938EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5939EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 5940EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kernel source for telekom puls (alcatel/mediatek)