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KVM: SVM: Emulate nRIP feature when reinjecting INT3
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
5a0e3ad6 42#include <linux/slab.h>
aec51dc4
AK		 43#include <trace/events/kvm.h>
44#undef TRACE_INCLUDE_FILE
229456fc
MT		 45#define CREATE_TRACE_POINTS
46#include "trace.h"
043405e1 47
24f1e32c 48#include <asm/debugreg.h>
043405e1 49#include <asm/uaccess.h>
d825ed0a 50#include <asm/msr.h>
a5f61300 51#include <asm/desc.h>
0bed3b56 52#include <asm/mtrr.h>
890ca9ae 53#include <asm/mce.h>
043405e1 54
313a3dc7 55#define MAX_IO_MSRS 256
a03490ed
CO		 56#define CR0_RESERVED_BITS \
57 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
58 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
59 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
60#define CR4_RESERVED_BITS \
61 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
62 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
63 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
64 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
65
66#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 67
68#define KVM_MAX_MCE_BANKS 32
69#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
70
50a37eb4
JR		 71/* EFER defaults:
72 * - enable syscall per default because its emulated by KVM
73 * - enable LME and LMA per default on 64 bit KVM
74 */
75#ifdef CONFIG_X86_64
76static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
77#else
78static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
79#endif
313a3dc7 80
ba1389b7
AK		 81#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
82#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 83
cb142eb7 84static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 85static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
86 struct kvm_cpuid_entry2 __user *entries);
87
97896d04 88struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 89EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 90
ed85c068
AP		 91int ignore_msrs = 0;
92module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
93
18863bdd
AK		 94#define KVM_NR_SHARED_MSRS 16
95
96struct kvm_shared_msrs_global {
97 int nr;
2bf78fa7 98 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 99};
100
101struct kvm_shared_msrs {
102 struct user_return_notifier urn;
103 bool registered;
2bf78fa7
SY		 104 struct kvm_shared_msr_values {
105 u64 host;
106 u64 curr;
107 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 108};
109
110static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
111static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
112
417bc304 113struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 114 { "pf_fixed", VCPU_STAT(pf_fixed) },
115 { "pf_guest", VCPU_STAT(pf_guest) },
116 { "tlb_flush", VCPU_STAT(tlb_flush) },
117 { "invlpg", VCPU_STAT(invlpg) },
118 { "exits", VCPU_STAT(exits) },
119 { "io_exits", VCPU_STAT(io_exits) },
120 { "mmio_exits", VCPU_STAT(mmio_exits) },
121 { "signal_exits", VCPU_STAT(signal_exits) },
122 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 123 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 124 { "halt_exits", VCPU_STAT(halt_exits) },
125 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 126 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 127 { "request_irq", VCPU_STAT(request_irq_exits) },
128 { "irq_exits", VCPU_STAT(irq_exits) },
129 { "host_state_reload", VCPU_STAT(host_state_reload) },
130 { "efer_reload", VCPU_STAT(efer_reload) },
131 { "fpu_reload", VCPU_STAT(fpu_reload) },
132 { "insn_emulation", VCPU_STAT(insn_emulation) },
133 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 134 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 135 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 136 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
137 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
138 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
139 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
140 { "mmu_flooded", VM_STAT(mmu_flooded) },
141 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 142 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 143 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 144 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 145 { "largepages", VM_STAT(lpages) },
417bc304
HB		 146 { NULL }
147};
148
18863bdd
AK		 149static void kvm_on_user_return(struct user_return_notifier *urn)
150{
151 unsigned slot;
18863bdd
AK		 152 struct kvm_shared_msrs *locals
153 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 154 struct kvm_shared_msr_values *values;
18863bdd
AK		 155
156 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 157 values = &locals->values[slot];
158 if (values->host != values->curr) {
159 wrmsrl(shared_msrs_global.msrs[slot], values->host);
160 values->curr = values->host;
18863bdd
AK		 161 }
162 }
163 locals->registered = false;
164 user_return_notifier_unregister(urn);
165}
166
2bf78fa7 167static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 168{
2bf78fa7 169 struct kvm_shared_msrs *smsr;
18863bdd
AK		 170 u64 value;
171
2bf78fa7
SY		 172 smsr = &__get_cpu_var(shared_msrs);
173 /* only read, and nobody should modify it at this time,
174 * so don't need lock */
175 if (slot >= shared_msrs_global.nr) {
176 printk(KERN_ERR "kvm: invalid MSR slot!");
177 return;
178 }
179 rdmsrl_safe(msr, &value);
180 smsr->values[slot].host = value;
181 smsr->values[slot].curr = value;
182}
183
184void kvm_define_shared_msr(unsigned slot, u32 msr)
185{
18863bdd
AK		 186 if (slot >= shared_msrs_global.nr)
187 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 188 shared_msrs_global.msrs[slot] = msr;
189 /* we need ensured the shared_msr_global have been updated */
190 smp_wmb();
18863bdd
AK		 191}
192EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
193
194static void kvm_shared_msr_cpu_online(void)
195{
196 unsigned i;
18863bdd
AK		 197
198 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 199 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 200}
201
d5696725 202void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 203{
204 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
205
2bf78fa7 206 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 207 return;
2bf78fa7
SY		 208 smsr->values[slot].curr = value;
209 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 210 if (!smsr->registered) {
211 smsr->urn.on_user_return = kvm_on_user_return;
212 user_return_notifier_register(&smsr->urn);
213 smsr->registered = true;
214 }
215}
216EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
217
3548bab5
AK		 218static void drop_user_return_notifiers(void *ignore)
219{
220 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
221
222 if (smsr->registered)
223 kvm_on_user_return(&smsr->urn);
224}
225
5fb76f9b
CO		 226unsigned long segment_base(u16 selector)
227{
89a27f4d 228 struct desc_ptr gdt;
a5f61300 229 struct desc_struct *d;
5fb76f9b
CO		 230 unsigned long table_base;
231 unsigned long v;
232
233 if (selector == 0)
234 return 0;
235
b792c344 236 kvm_get_gdt(&gdt);
89a27f4d 237 table_base = gdt.address;
5fb76f9b
CO		 238
239 if (selector & 4) { /* from ldt */
b792c344 240 u16 ldt_selector = kvm_read_ldt();
5fb76f9b 241
5fb76f9b
CO		 242 table_base = segment_base(ldt_selector);
243 }
a5f61300 244 d = (struct desc_struct *)(table_base + (selector & ~7));
46a359e7 245 v = get_desc_base(d);
5fb76f9b 246#ifdef CONFIG_X86_64
a5f61300
AK		 247 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
248 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 249#endif
250 return v;
251}
252EXPORT_SYMBOL_GPL(segment_base);
253
6866b83e
CO		 254u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255{
256 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 257 return vcpu->arch.apic_base;
6866b83e 258 else
ad312c7c 259 return vcpu->arch.apic_base;
6866b83e
CO		 260}
261EXPORT_SYMBOL_GPL(kvm_get_apic_base);
262
263void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
264{
265 /* TODO: reserve bits check */
266 if (irqchip_in_kernel(vcpu->kvm))
267 kvm_lapic_set_base(vcpu, data);
268 else
ad312c7c 269 vcpu->arch.apic_base = data;
6866b83e
CO		 270}
271EXPORT_SYMBOL_GPL(kvm_set_apic_base);
272
3fd28fce
ED		 273#define EXCPT_BENIGN 0
274#define EXCPT_CONTRIBUTORY 1
275#define EXCPT_PF 2
276
277static int exception_class(int vector)
278{
279 switch (vector) {
280 case PF_VECTOR:
281 return EXCPT_PF;
282 case DE_VECTOR:
283 case TS_VECTOR:
284 case NP_VECTOR:
285 case SS_VECTOR:
286 case GP_VECTOR:
287 return EXCPT_CONTRIBUTORY;
288 default:
289 break;
290 }
291 return EXCPT_BENIGN;
292}
293
294static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
295 unsigned nr, bool has_error, u32 error_code)
296{
297 u32 prev_nr;
298 int class1, class2;
299
300 if (!vcpu->arch.exception.pending) {
301 queue:
302 vcpu->arch.exception.pending = true;
303 vcpu->arch.exception.has_error_code = has_error;
304 vcpu->arch.exception.nr = nr;
305 vcpu->arch.exception.error_code = error_code;
306 return;
307 }
308
309 /* to check exception */
310 prev_nr = vcpu->arch.exception.nr;
311 if (prev_nr == DF_VECTOR) {
312 /* triple fault -> shutdown */
313 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
314 return;
315 }
316 class1 = exception_class(prev_nr);
317 class2 = exception_class(nr);
318 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
319 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
320 /* generate double fault per SDM Table 5-5 */
321 vcpu->arch.exception.pending = true;
322 vcpu->arch.exception.has_error_code = true;
323 vcpu->arch.exception.nr = DF_VECTOR;
324 vcpu->arch.exception.error_code = 0;
325 } else
326 /* replace previous exception with a new one in a hope
327 that instruction re-execution will regenerate lost
328 exception */
329 goto queue;
330}
331
298101da
AK		 332void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
333{
3fd28fce 334 kvm_multiple_exception(vcpu, nr, false, 0);
298101da
AK		 335}
336EXPORT_SYMBOL_GPL(kvm_queue_exception);
337
c3c91fee
AK		 338void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
339 u32 error_code)
340{
341 ++vcpu->stat.pf_guest;
ad312c7c 342 vcpu->arch.cr2 = addr;
c3c91fee
AK		 343 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
344}
345
3419ffc8
SY		 346void kvm_inject_nmi(struct kvm_vcpu *vcpu)
347{
348 vcpu->arch.nmi_pending = 1;
349}
350EXPORT_SYMBOL_GPL(kvm_inject_nmi);
351
298101da
AK		 352void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
353{
3fd28fce 354 kvm_multiple_exception(vcpu, nr, true, error_code);
298101da
AK		 355}
356EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
357
0a79b009
AK		 358/*
359 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
360 * a #GP and return false.
361 */
362bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 363{
0a79b009
AK		 364 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
365 return true;
366 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
367 return false;
298101da 368}
0a79b009 369EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 370
a03490ed
CO		 371/*
372 * Load the pae pdptrs. Return true is they are all valid.
373 */
374int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
375{
376 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
377 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
378 int i;
379 int ret;
ad312c7c 380 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 381
a03490ed
CO		 382 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
383 offset * sizeof(u64), sizeof(pdpte));
384 if (ret < 0) {
385 ret = 0;
386 goto out;
387 }
388 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 389 if (is_present_gpte(pdpte[i]) &&
20c466b5 390 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 391 ret = 0;
392 goto out;
393 }
394 }
395 ret = 1;
396
ad312c7c 397 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 398 __set_bit(VCPU_EXREG_PDPTR,
399 (unsigned long *)&vcpu->arch.regs_avail);
400 __set_bit(VCPU_EXREG_PDPTR,
401 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 402out:
a03490ed
CO		 403
404 return ret;
405}
cc4b6871 406EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 407
d835dfec
AK		 408static bool pdptrs_changed(struct kvm_vcpu *vcpu)
409{
ad312c7c 410 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 411 bool changed = true;
412 int r;
413
414 if (is_long_mode(vcpu) || !is_pae(vcpu))
415 return false;
416
6de4f3ad
AK		 417 if (!test_bit(VCPU_EXREG_PDPTR,
418 (unsigned long *)&vcpu->arch.regs_avail))
419 return true;
420
ad312c7c 421 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 422 if (r < 0)
423 goto out;
ad312c7c 424 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 425out:
d835dfec
AK		 426
427 return changed;
428}
429
2d3ad1f4 430void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 431{
f9a48e6a
AK		 432 cr0 |= X86_CR0_ET;
433
ab344828
GN		 434#ifdef CONFIG_X86_64
435 if (cr0 & 0xffffffff00000000UL) {
c1a5d4f9 436 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 437 return;
438 }
ab344828
GN		 439#endif
440
441 cr0 &= ~CR0_RESERVED_BITS;
a03490ed
CO		 442
443 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
c1a5d4f9 444 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 445 return;
446 }
447
448 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
c1a5d4f9 449 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 450 return;
451 }
452
453 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
454#ifdef CONFIG_X86_64
f6801dff 455 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 456 int cs_db, cs_l;
457
458 if (!is_pae(vcpu)) {
c1a5d4f9 459 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 460 return;
461 }
462 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
463 if (cs_l) {
c1a5d4f9 464 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 465 return;
466
467 }
468 } else
469#endif
ad312c7c 470 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 471 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 472 return;
473 }
474
475 }
476
477 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 478 vcpu->arch.cr0 = cr0;
a03490ed 479
a03490ed 480 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 481 return;
482}
2d3ad1f4 483EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 484
2d3ad1f4 485void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 486{
4d4ec087 487 kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0ful) | (msw & 0x0f));
a03490ed 488}
2d3ad1f4 489EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 490
2d3ad1f4 491void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 492{
fc78f519 493 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 494 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
495
a03490ed 496 if (cr4 & CR4_RESERVED_BITS) {
c1a5d4f9 497 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 498 return;
499 }
500
501 if (is_long_mode(vcpu)) {
502 if (!(cr4 & X86_CR4_PAE)) {
c1a5d4f9 503 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 504 return;
505 }
a2edf57f
AK		 506 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
507 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 508 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 509 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 510 return;
511 }
512
513 if (cr4 & X86_CR4_VMXE) {
c1a5d4f9 514 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 515 return;
516 }
517 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 518 vcpu->arch.cr4 = cr4;
5a41accd 519 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 520 kvm_mmu_reset_context(vcpu);
a03490ed 521}
2d3ad1f4 522EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 523
2d3ad1f4 524void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 525{
ad312c7c 526 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 527 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 528 kvm_mmu_flush_tlb(vcpu);
529 return;
530 }
531
a03490ed
CO		 532 if (is_long_mode(vcpu)) {
533 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
c1a5d4f9 534 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 535 return;
536 }
537 } else {
538 if (is_pae(vcpu)) {
539 if (cr3 & CR3_PAE_RESERVED_BITS) {
c1a5d4f9 540 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 541 return;
542 }
543 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
c1a5d4f9 544 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 545 return;
546 }
547 }
548 /*
549 * We don't check reserved bits in nonpae mode, because
550 * this isn't enforced, and VMware depends on this.
551 */
552 }
553
a03490ed
CO		 554 /*
555 * Does the new cr3 value map to physical memory? (Note, we
556 * catch an invalid cr3 even in real-mode, because it would
557 * cause trouble later on when we turn on paging anyway.)
558 *
559 * A real CPU would silently accept an invalid cr3 and would
560 * attempt to use it - with largely undefined (and often hard
561 * to debug) behavior on the guest side.
562 */
563 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 564 kvm_inject_gp(vcpu, 0);
a03490ed 565 else {
ad312c7c
ZX		 566 vcpu->arch.cr3 = cr3;
567 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 568 }
a03490ed 569}
2d3ad1f4 570EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 571
2d3ad1f4 572void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 573{
574 if (cr8 & CR8_RESERVED_BITS) {
c1a5d4f9 575 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 576 return;
577 }
578 if (irqchip_in_kernel(vcpu->kvm))
579 kvm_lapic_set_tpr(vcpu, cr8);
580 else
ad312c7c 581 vcpu->arch.cr8 = cr8;
a03490ed 582}
2d3ad1f4 583EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 584
2d3ad1f4 585unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 586{
587 if (irqchip_in_kernel(vcpu->kvm))
588 return kvm_lapic_get_cr8(vcpu);
589 else
ad312c7c 590 return vcpu->arch.cr8;
a03490ed 591}
2d3ad1f4 592EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 593
d8017474
AG		 594static inline u32 bit(int bitno)
595{
596 return 1 << (bitno & 31);
597}
598
043405e1
CO		 599/*
600 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
601 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
602 *
603 * This list is modified at module load time to reflect the
e3267cbb
GC		 604 * capabilities of the host cpu. This capabilities test skips MSRs that are
605 * kvm-specific. Those are put in the beginning of the list.
043405e1 606 */
e3267cbb 607
10388a07 608#define KVM_SAVE_MSRS_BEGIN 5
043405e1 609static u32 msrs_to_save[] = {
e3267cbb 610 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
55cd8e5a 611 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 612 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1
CO		 613 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
614 MSR_K6_STAR,
615#ifdef CONFIG_X86_64
616 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
617#endif
e3267cbb 618 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 619};
620
621static unsigned num_msrs_to_save;
622
623static u32 emulated_msrs[] = {
624 MSR_IA32_MISC_ENABLE,
625};
626
15c4a640
CO		 627static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
628{
f2b4b7dd 629 if (efer & efer_reserved_bits) {
c1a5d4f9 630 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 631 return;
632 }
633
634 if (is_paging(vcpu)
f6801dff 635 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) {
c1a5d4f9 636 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 637 return;
638 }
639
1b2fd70c
AG		 640 if (efer & EFER_FFXSR) {
641 struct kvm_cpuid_entry2 *feat;
642
643 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
644 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
1b2fd70c
AG		 645 kvm_inject_gp(vcpu, 0);
646 return;
647 }
648 }
649
d8017474
AG		 650 if (efer & EFER_SVME) {
651 struct kvm_cpuid_entry2 *feat;
652
653 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
654 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
d8017474
AG		 655 kvm_inject_gp(vcpu, 0);
656 return;
657 }
658 }
659
15c4a640
CO		 660 kvm_x86_ops->set_efer(vcpu, efer);
661
662 efer &= ~EFER_LMA;
f6801dff 663 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 664
f6801dff 665 vcpu->arch.efer = efer;
9645bb56
AK		 666
667 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
668 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 669}
670
f2b4b7dd
JR		 671void kvm_enable_efer_bits(u64 mask)
672{
673 efer_reserved_bits &= ~mask;
674}
675EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
676
677
15c4a640
CO		 678/*
679 * Writes msr value into into the appropriate "register".
680 * Returns 0 on success, non-0 otherwise.
681 * Assumes vcpu_load() was already called.
682 */
683int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
684{
685 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
686}
687
313a3dc7
CO		 688/*
689 * Adapt set_msr() to msr_io()'s calling convention
690 */
691static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
692{
693 return kvm_set_msr(vcpu, index, *data);
694}
695
18068523
GOC		 696static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
697{
698 static int version;
50d0a0f9 699 struct pvclock_wall_clock wc;
923de3cf 700 struct timespec boot;
18068523
GOC		 701
702 if (!wall_clock)
703 return;
704
705 version++;
706
18068523
GOC		 707 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
708
50d0a0f9
GH		 709 /*
710 * The guest calculates current wall clock time by adding
711 * system time (updated by kvm_write_guest_time below) to the
712 * wall clock specified here. guest system time equals host
713 * system time for us, thus we must fill in host boot time here.
714 */
923de3cf 715 getboottime(&boot);
50d0a0f9
GH		 716
717 wc.sec = boot.tv_sec;
718 wc.nsec = boot.tv_nsec;
719 wc.version = version;
18068523
GOC		 720
721 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
722
723 version++;
724 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 725}
726
50d0a0f9
GH		 727static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
728{
729 uint32_t quotient, remainder;
730
731 /* Don't try to replace with do_div(), this one calculates
732 * "(dividend << 32) / divisor" */
733 __asm__ ( "divl %4"
734 : "=a" (quotient), "=d" (remainder)
735 : "0" (0), "1" (dividend), "r" (divisor) );
736 return quotient;
737}
738
739static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
740{
741 uint64_t nsecs = 1000000000LL;
742 int32_t shift = 0;
743 uint64_t tps64;
744 uint32_t tps32;
745
746 tps64 = tsc_khz * 1000LL;
747 while (tps64 > nsecs*2) {
748 tps64 >>= 1;
749 shift--;
750 }
751
752 tps32 = (uint32_t)tps64;
753 while (tps32 <= (uint32_t)nsecs) {
754 tps32 <<= 1;
755 shift++;
756 }
757
758 hv_clock->tsc_shift = shift;
759 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
760
761 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 762 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 763 hv_clock->tsc_to_system_mul);
764}
765
c8076604
GH		 766static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
767
18068523
GOC		 768static void kvm_write_guest_time(struct kvm_vcpu *v)
769{
770 struct timespec ts;
771 unsigned long flags;
772 struct kvm_vcpu_arch *vcpu = &v->arch;
773 void *shared_kaddr;
463656c0 774 unsigned long this_tsc_khz;
18068523
GOC		 775
776 if ((!vcpu->time_page))
777 return;
778
463656c0
AK		 779 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
780 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
781 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
782 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 783 }
463656c0 784 put_cpu_var(cpu_tsc_khz);
50d0a0f9 785
18068523
GOC		 786 /* Keep irq disabled to prevent changes to the clock */
787 local_irq_save(flags);
af24a4e4 788 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 789 ktime_get_ts(&ts);
923de3cf 790 monotonic_to_bootbased(&ts);
18068523
GOC		 791 local_irq_restore(flags);
792
793 /* With all the info we got, fill in the values */
794
795 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 796 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
797
18068523
GOC		 798 /*
799 * The interface expects us to write an even number signaling that the
800 * update is finished. Since the guest won't see the intermediate
50d0a0f9 801 * state, we just increase by 2 at the end.
18068523 802 */
50d0a0f9 803 vcpu->hv_clock.version += 2;
18068523
GOC		 804
805 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
806
807 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 808 sizeof(vcpu->hv_clock));
18068523
GOC		 809
810 kunmap_atomic(shared_kaddr, KM_USER0);
811
812 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
813}
814
c8076604
GH		 815static int kvm_request_guest_time_update(struct kvm_vcpu *v)
816{
817 struct kvm_vcpu_arch *vcpu = &v->arch;
818
819 if (!vcpu->time_page)
820 return 0;
821 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
822 return 1;
823}
824
9ba075a6
AK		 825static bool msr_mtrr_valid(unsigned msr)
826{
827 switch (msr) {
828 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
829 case MSR_MTRRfix64K_00000:
830 case MSR_MTRRfix16K_80000:
831 case MSR_MTRRfix16K_A0000:
832 case MSR_MTRRfix4K_C0000:
833 case MSR_MTRRfix4K_C8000:
834 case MSR_MTRRfix4K_D0000:
835 case MSR_MTRRfix4K_D8000:
836 case MSR_MTRRfix4K_E0000:
837 case MSR_MTRRfix4K_E8000:
838 case MSR_MTRRfix4K_F0000:
839 case MSR_MTRRfix4K_F8000:
840 case MSR_MTRRdefType:
841 case MSR_IA32_CR_PAT:
842 return true;
843 case 0x2f8:
844 return true;
845 }
846 return false;
847}
848
d6289b93
MT		 849static bool valid_pat_type(unsigned t)
850{
851 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
852}
853
854static bool valid_mtrr_type(unsigned t)
855{
856 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
857}
858
859static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
860{
861 int i;
862
863 if (!msr_mtrr_valid(msr))
864 return false;
865
866 if (msr == MSR_IA32_CR_PAT) {
867 for (i = 0; i < 8; i++)
868 if (!valid_pat_type((data >> (i * 8)) & 0xff))
869 return false;
870 return true;
871 } else if (msr == MSR_MTRRdefType) {
872 if (data & ~0xcff)
873 return false;
874 return valid_mtrr_type(data & 0xff);
875 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
876 for (i = 0; i < 8 ; i++)
877 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
878 return false;
879 return true;
880 }
881
882 /* variable MTRRs */
883 return valid_mtrr_type(data & 0xff);
884}
885
9ba075a6
AK		 886static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
887{
0bed3b56
SY		 888 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
889
d6289b93 890 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 891 return 1;
892
0bed3b56
SY		 893 if (msr == MSR_MTRRdefType) {
894 vcpu->arch.mtrr_state.def_type = data;
895 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
896 } else if (msr == MSR_MTRRfix64K_00000)
897 p[0] = data;
898 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
899 p[1 + msr - MSR_MTRRfix16K_80000] = data;
900 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
901 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
902 else if (msr == MSR_IA32_CR_PAT)
903 vcpu->arch.pat = data;
904 else { /* Variable MTRRs */
905 int idx, is_mtrr_mask;
906 u64 *pt;
907
908 idx = (msr - 0x200) / 2;
909 is_mtrr_mask = msr - 0x200 - 2 * idx;
910 if (!is_mtrr_mask)
911 pt =
912 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
913 else
914 pt =
915 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
916 *pt = data;
917 }
918
919 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 920 return 0;
921}
15c4a640 922
890ca9ae 923static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 924{
890ca9ae
HY		 925 u64 mcg_cap = vcpu->arch.mcg_cap;
926 unsigned bank_num = mcg_cap & 0xff;
927
15c4a640 928 switch (msr) {
15c4a640 929 case MSR_IA32_MCG_STATUS:
890ca9ae 930 vcpu->arch.mcg_status = data;
15c4a640 931 break;
c7ac679c 932 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 933 if (!(mcg_cap & MCG_CTL_P))
934 return 1;
935 if (data != 0 && data != ~(u64)0)
936 return -1;
937 vcpu->arch.mcg_ctl = data;
938 break;
939 default:
940 if (msr >= MSR_IA32_MC0_CTL &&
941 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
942 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 943 /* only 0 or all 1s can be written to IA32_MCi_CTL
944 * some Linux kernels though clear bit 10 in bank 4 to
945 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
946 * this to avoid an uncatched #GP in the guest
947 */
890ca9ae 948 if ((offset & 0x3) == 0 &&
114be429 949 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 950 return -1;
951 vcpu->arch.mce_banks[offset] = data;
952 break;
953 }
954 return 1;
955 }
956 return 0;
957}
958
ffde22ac
ES		 959static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
960{
961 struct kvm *kvm = vcpu->kvm;
962 int lm = is_long_mode(vcpu);
963 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
964 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
965 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
966 : kvm->arch.xen_hvm_config.blob_size_32;
967 u32 page_num = data & ~PAGE_MASK;
968 u64 page_addr = data & PAGE_MASK;
969 u8 *page;
970 int r;
971
972 r = -E2BIG;
973 if (page_num >= blob_size)
974 goto out;
975 r = -ENOMEM;
976 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
977 if (!page)
978 goto out;
979 r = -EFAULT;
980 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
981 goto out_free;
982 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
983 goto out_free;
984 r = 0;
985out_free:
986 kfree(page);
987out:
988 return r;
989}
990
55cd8e5a
GN		 991static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
992{
993 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
994}
995
996static bool kvm_hv_msr_partition_wide(u32 msr)
997{
998 bool r = false;
999 switch (msr) {
1000 case HV_X64_MSR_GUEST_OS_ID:
1001 case HV_X64_MSR_HYPERCALL:
1002 r = true;
1003 break;
1004 }
1005
1006 return r;
1007}
1008
1009static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1010{
1011 struct kvm *kvm = vcpu->kvm;
1012
1013 switch (msr) {
1014 case HV_X64_MSR_GUEST_OS_ID:
1015 kvm->arch.hv_guest_os_id = data;
1016 /* setting guest os id to zero disables hypercall page */
1017 if (!kvm->arch.hv_guest_os_id)
1018 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1019 break;
1020 case HV_X64_MSR_HYPERCALL: {
1021 u64 gfn;
1022 unsigned long addr;
1023 u8 instructions[4];
1024
1025 /* if guest os id is not set hypercall should remain disabled */
1026 if (!kvm->arch.hv_guest_os_id)
1027 break;
1028 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1029 kvm->arch.hv_hypercall = data;
1030 break;
1031 }
1032 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1033 addr = gfn_to_hva(kvm, gfn);
1034 if (kvm_is_error_hva(addr))
1035 return 1;
1036 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1037 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1038 if (copy_to_user((void __user *)addr, instructions, 4))
1039 return 1;
1040 kvm->arch.hv_hypercall = data;
1041 break;
1042 }
1043 default:
1044 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1045 "data 0x%llx\n", msr, data);
1046 return 1;
1047 }
1048 return 0;
1049}
1050
1051static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1052{
10388a07
GN		 1053 switch (msr) {
1054 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1055 unsigned long addr;
55cd8e5a 1056
10388a07
GN		 1057 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1058 vcpu->arch.hv_vapic = data;
1059 break;
1060 }
1061 addr = gfn_to_hva(vcpu->kvm, data >>
1062 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1063 if (kvm_is_error_hva(addr))
1064 return 1;
1065 if (clear_user((void __user *)addr, PAGE_SIZE))
1066 return 1;
1067 vcpu->arch.hv_vapic = data;
1068 break;
1069 }
1070 case HV_X64_MSR_EOI:
1071 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1072 case HV_X64_MSR_ICR:
1073 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1074 case HV_X64_MSR_TPR:
1075 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1076 default:
1077 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1078 "data 0x%llx\n", msr, data);
1079 return 1;
1080 }
1081
1082 return 0;
55cd8e5a
GN		 1083}
1084
15c4a640
CO		 1085int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1086{
1087 switch (msr) {
15c4a640
CO		 1088 case MSR_EFER:
1089 set_efer(vcpu, data);
1090 break;
8f1589d9
AP		 1091 case MSR_K7_HWCR:
1092 data &= ~(u64)0x40; /* ignore flush filter disable */
1093 if (data != 0) {
1094 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1095 data);
1096 return 1;
1097 }
15c4a640 1098 break;
f7c6d140
AP		 1099 case MSR_FAM10H_MMIO_CONF_BASE:
1100 if (data != 0) {
1101 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1102 "0x%llx\n", data);
1103 return 1;
1104 }
15c4a640 1105 break;
c323c0e5 1106 case MSR_AMD64_NB_CFG:
c7ac679c 1107 break;
b5e2fec0
AG		 1108 case MSR_IA32_DEBUGCTLMSR:
1109 if (!data) {
1110 /* We support the non-activated case already */
1111 break;
1112 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1113 /* Values other than LBR and BTF are vendor-specific,
1114 thus reserved and should throw a #GP */
1115 return 1;
1116 }
1117 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1118 __func__, data);
1119 break;
15c4a640
CO		 1120 case MSR_IA32_UCODE_REV:
1121 case MSR_IA32_UCODE_WRITE:
61a6bd67 1122 case MSR_VM_HSAVE_PA:
6098ca93 1123 case MSR_AMD64_PATCH_LOADER:
15c4a640 1124 break;
9ba075a6
AK		 1125 case 0x200 ... 0x2ff:
1126 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1127 case MSR_IA32_APICBASE:
1128 kvm_set_apic_base(vcpu, data);
1129 break;
0105d1a5
GN		 1130 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1131 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1132 case MSR_IA32_MISC_ENABLE:
ad312c7c 1133 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1134 break;
18068523
GOC		 1135 case MSR_KVM_WALL_CLOCK:
1136 vcpu->kvm->arch.wall_clock = data;
1137 kvm_write_wall_clock(vcpu->kvm, data);
1138 break;
1139 case MSR_KVM_SYSTEM_TIME: {
1140 if (vcpu->arch.time_page) {
1141 kvm_release_page_dirty(vcpu->arch.time_page);
1142 vcpu->arch.time_page = NULL;
1143 }
1144
1145 vcpu->arch.time = data;
1146
1147 /* we verify if the enable bit is set... */
1148 if (!(data & 1))
1149 break;
1150
1151 /* ...but clean it before doing the actual write */
1152 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1153
18068523
GOC		 1154 vcpu->arch.time_page =
1155 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1156
1157 if (is_error_page(vcpu->arch.time_page)) {
1158 kvm_release_page_clean(vcpu->arch.time_page);
1159 vcpu->arch.time_page = NULL;
1160 }
1161
c8076604 1162 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1163 break;
1164 }
890ca9ae
HY		 1165 case MSR_IA32_MCG_CTL:
1166 case MSR_IA32_MCG_STATUS:
1167 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1168 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1169
1170 /* Performance counters are not protected by a CPUID bit,
1171 * so we should check all of them in the generic path for the sake of
1172 * cross vendor migration.
1173 * Writing a zero into the event select MSRs disables them,
1174 * which we perfectly emulate ;-). Any other value should be at least
1175 * reported, some guests depend on them.
1176 */
1177 case MSR_P6_EVNTSEL0:
1178 case MSR_P6_EVNTSEL1:
1179 case MSR_K7_EVNTSEL0:
1180 case MSR_K7_EVNTSEL1:
1181 case MSR_K7_EVNTSEL2:
1182 case MSR_K7_EVNTSEL3:
1183 if (data != 0)
1184 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1185 "0x%x data 0x%llx\n", msr, data);
1186 break;
1187 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1188 * so we ignore writes to make it happy.
1189 */
1190 case MSR_P6_PERFCTR0:
1191 case MSR_P6_PERFCTR1:
1192 case MSR_K7_PERFCTR0:
1193 case MSR_K7_PERFCTR1:
1194 case MSR_K7_PERFCTR2:
1195 case MSR_K7_PERFCTR3:
1196 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1197 "0x%x data 0x%llx\n", msr, data);
1198 break;
55cd8e5a
GN		 1199 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1200 if (kvm_hv_msr_partition_wide(msr)) {
1201 int r;
1202 mutex_lock(&vcpu->kvm->lock);
1203 r = set_msr_hyperv_pw(vcpu, msr, data);
1204 mutex_unlock(&vcpu->kvm->lock);
1205 return r;
1206 } else
1207 return set_msr_hyperv(vcpu, msr, data);
1208 break;
15c4a640 1209 default:
ffde22ac
ES		 1210 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1211 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1212 if (!ignore_msrs) {
1213 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1214 msr, data);
1215 return 1;
1216 } else {
1217 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1218 msr, data);
1219 break;
1220 }
15c4a640
CO		 1221 }
1222 return 0;
1223}
1224EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1225
1226
1227/*
1228 * Reads an msr value (of 'msr_index') into 'pdata'.
1229 * Returns 0 on success, non-0 otherwise.
1230 * Assumes vcpu_load() was already called.
1231 */
1232int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1233{
1234 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1235}
1236
9ba075a6
AK		 1237static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1238{
0bed3b56
SY		 1239 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1240
9ba075a6
AK		 1241 if (!msr_mtrr_valid(msr))
1242 return 1;
1243
0bed3b56
SY		 1244 if (msr == MSR_MTRRdefType)
1245 *pdata = vcpu->arch.mtrr_state.def_type +
1246 (vcpu->arch.mtrr_state.enabled << 10);
1247 else if (msr == MSR_MTRRfix64K_00000)
1248 *pdata = p[0];
1249 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1250 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1251 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1252 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1253 else if (msr == MSR_IA32_CR_PAT)
1254 *pdata = vcpu->arch.pat;
1255 else { /* Variable MTRRs */
1256 int idx, is_mtrr_mask;
1257 u64 *pt;
1258
1259 idx = (msr - 0x200) / 2;
1260 is_mtrr_mask = msr - 0x200 - 2 * idx;
1261 if (!is_mtrr_mask)
1262 pt =
1263 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1264 else
1265 pt =
1266 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1267 *pdata = *pt;
1268 }
1269
9ba075a6
AK		 1270 return 0;
1271}
1272
890ca9ae 1273static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1274{
1275 u64 data;
890ca9ae
HY		 1276 u64 mcg_cap = vcpu->arch.mcg_cap;
1277 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1278
1279 switch (msr) {
15c4a640
CO		 1280 case MSR_IA32_P5_MC_ADDR:
1281 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1282 data = 0;
1283 break;
15c4a640 1284 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1285 data = vcpu->arch.mcg_cap;
1286 break;
c7ac679c 1287 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1288 if (!(mcg_cap & MCG_CTL_P))
1289 return 1;
1290 data = vcpu->arch.mcg_ctl;
1291 break;
1292 case MSR_IA32_MCG_STATUS:
1293 data = vcpu->arch.mcg_status;
1294 break;
1295 default:
1296 if (msr >= MSR_IA32_MC0_CTL &&
1297 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1298 u32 offset = msr - MSR_IA32_MC0_CTL;
1299 data = vcpu->arch.mce_banks[offset];
1300 break;
1301 }
1302 return 1;
1303 }
1304 *pdata = data;
1305 return 0;
1306}
1307
55cd8e5a
GN		 1308static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1309{
1310 u64 data = 0;
1311 struct kvm *kvm = vcpu->kvm;
1312
1313 switch (msr) {
1314 case HV_X64_MSR_GUEST_OS_ID:
1315 data = kvm->arch.hv_guest_os_id;
1316 break;
1317 case HV_X64_MSR_HYPERCALL:
1318 data = kvm->arch.hv_hypercall;
1319 break;
1320 default:
1321 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1322 return 1;
1323 }
1324
1325 *pdata = data;
1326 return 0;
1327}
1328
1329static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1330{
1331 u64 data = 0;
1332
1333 switch (msr) {
1334 case HV_X64_MSR_VP_INDEX: {
1335 int r;
1336 struct kvm_vcpu *v;
1337 kvm_for_each_vcpu(r, v, vcpu->kvm)
1338 if (v == vcpu)
1339 data = r;
1340 break;
1341 }
10388a07
GN		 1342 case HV_X64_MSR_EOI:
1343 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1344 case HV_X64_MSR_ICR:
1345 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1346 case HV_X64_MSR_TPR:
1347 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1348 default:
1349 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1350 return 1;
1351 }
1352 *pdata = data;
1353 return 0;
1354}
1355
890ca9ae
HY		 1356int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1357{
1358 u64 data;
1359
1360 switch (msr) {
890ca9ae 1361 case MSR_IA32_PLATFORM_ID:
15c4a640 1362 case MSR_IA32_UCODE_REV:
15c4a640 1363 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1364 case MSR_IA32_DEBUGCTLMSR:
1365 case MSR_IA32_LASTBRANCHFROMIP:
1366 case MSR_IA32_LASTBRANCHTOIP:
1367 case MSR_IA32_LASTINTFROMIP:
1368 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1369 case MSR_K8_SYSCFG:
1370 case MSR_K7_HWCR:
61a6bd67 1371 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1372 case MSR_P6_PERFCTR0:
1373 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1374 case MSR_P6_EVNTSEL0:
1375 case MSR_P6_EVNTSEL1:
9e699624 1376 case MSR_K7_EVNTSEL0:
1f3ee616 1377 case MSR_K7_PERFCTR0:
1fdbd48c 1378 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1379 case MSR_AMD64_NB_CFG:
f7c6d140 1380 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1381 data = 0;
1382 break;
9ba075a6
AK		 1383 case MSR_MTRRcap:
1384 data = 0x500 | KVM_NR_VAR_MTRR;
1385 break;
1386 case 0x200 ... 0x2ff:
1387 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1388 case 0xcd: /* fsb frequency */
1389 data = 3;
1390 break;
1391 case MSR_IA32_APICBASE:
1392 data = kvm_get_apic_base(vcpu);
1393 break;
0105d1a5
GN		 1394 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1395 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1396 break;
15c4a640 1397 case MSR_IA32_MISC_ENABLE:
ad312c7c 1398 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1399 break;
847f0ad8
AG		 1400 case MSR_IA32_PERF_STATUS:
1401 /* TSC increment by tick */
1402 data = 1000ULL;
1403 /* CPU multiplier */
1404 data |= (((uint64_t)4ULL) << 40);
1405 break;
15c4a640 1406 case MSR_EFER:
f6801dff 1407 data = vcpu->arch.efer;
15c4a640 1408 break;
18068523
GOC		 1409 case MSR_KVM_WALL_CLOCK:
1410 data = vcpu->kvm->arch.wall_clock;
1411 break;
1412 case MSR_KVM_SYSTEM_TIME:
1413 data = vcpu->arch.time;
1414 break;
890ca9ae
HY		 1415 case MSR_IA32_P5_MC_ADDR:
1416 case MSR_IA32_P5_MC_TYPE:
1417 case MSR_IA32_MCG_CAP:
1418 case MSR_IA32_MCG_CTL:
1419 case MSR_IA32_MCG_STATUS:
1420 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1421 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1422 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1423 if (kvm_hv_msr_partition_wide(msr)) {
1424 int r;
1425 mutex_lock(&vcpu->kvm->lock);
1426 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1427 mutex_unlock(&vcpu->kvm->lock);
1428 return r;
1429 } else
1430 return get_msr_hyperv(vcpu, msr, pdata);
1431 break;
15c4a640 1432 default:
ed85c068
AP		 1433 if (!ignore_msrs) {
1434 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1435 return 1;
1436 } else {
1437 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1438 data = 0;
1439 }
1440 break;
15c4a640
CO		 1441 }
1442 *pdata = data;
1443 return 0;
1444}
1445EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1446
313a3dc7
CO		 1447/*
1448 * Read or write a bunch of msrs. All parameters are kernel addresses.
1449 *
1450 * @return number of msrs set successfully.
1451 */
1452static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1453 struct kvm_msr_entry *entries,
1454 int (*do_msr)(struct kvm_vcpu *vcpu,
1455 unsigned index, u64 *data))
1456{
f656ce01 1457 int i, idx;
313a3dc7
CO		 1458
1459 vcpu_load(vcpu);
1460
f656ce01 1461 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1462 for (i = 0; i < msrs->nmsrs; ++i)
1463 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1464 break;
f656ce01 1465 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7
CO		 1466
1467 vcpu_put(vcpu);
1468
1469 return i;
1470}
1471
1472/*
1473 * Read or write a bunch of msrs. Parameters are user addresses.
1474 *
1475 * @return number of msrs set successfully.
1476 */
1477static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1478 int (*do_msr)(struct kvm_vcpu *vcpu,
1479 unsigned index, u64 *data),
1480 int writeback)
1481{
1482 struct kvm_msrs msrs;
1483 struct kvm_msr_entry *entries;
1484 int r, n;
1485 unsigned size;
1486
1487 r = -EFAULT;
1488 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1489 goto out;
1490
1491 r = -E2BIG;
1492 if (msrs.nmsrs >= MAX_IO_MSRS)
1493 goto out;
1494
1495 r = -ENOMEM;
1496 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1497 entries = vmalloc(size);
1498 if (!entries)
1499 goto out;
1500
1501 r = -EFAULT;
1502 if (copy_from_user(entries, user_msrs->entries, size))
1503 goto out_free;
1504
1505 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1506 if (r < 0)
1507 goto out_free;
1508
1509 r = -EFAULT;
1510 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1511 goto out_free;
1512
1513 r = n;
1514
1515out_free:
1516 vfree(entries);
1517out:
1518 return r;
1519}
1520
018d00d2
ZX		 1521int kvm_dev_ioctl_check_extension(long ext)
1522{
1523 int r;
1524
1525 switch (ext) {
1526 case KVM_CAP_IRQCHIP:
1527 case KVM_CAP_HLT:
1528 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1529 case KVM_CAP_SET_TSS_ADDR:
07716717 1530 case KVM_CAP_EXT_CPUID:
c8076604 1531 case KVM_CAP_CLOCKSOURCE:
7837699f 1532 case KVM_CAP_PIT:
a28e4f5a 1533 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1534 case KVM_CAP_MP_STATE:
ed848624 1535 case KVM_CAP_SYNC_MMU:
52d939a0 1536 case KVM_CAP_REINJECT_CONTROL:
4925663a 1537 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1538 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1539 case KVM_CAP_IRQFD:
d34e6b17 1540 case KVM_CAP_IOEVENTFD:
c5ff41ce 1541 case KVM_CAP_PIT2:
e9f42757 1542 case KVM_CAP_PIT_STATE2:
b927a3ce 1543 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1544 case KVM_CAP_XEN_HVM:
afbcf7ab 1545 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1546 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1547 case KVM_CAP_HYPERV:
10388a07 1548 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1549 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1550 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1551 case KVM_CAP_DEBUGREGS:
d2be1651 1552 case KVM_CAP_X86_ROBUST_SINGLESTEP:
018d00d2
ZX		 1553 r = 1;
1554 break;
542472b5
LV		 1555 case KVM_CAP_COALESCED_MMIO:
1556 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1557 break;
774ead3a
AK		 1558 case KVM_CAP_VAPIC:
1559 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1560 break;
f725230a
AK		 1561 case KVM_CAP_NR_VCPUS:
1562 r = KVM_MAX_VCPUS;
1563 break;
a988b910
AK		 1564 case KVM_CAP_NR_MEMSLOTS:
1565 r = KVM_MEMORY_SLOTS;
1566 break;
a68a6a72
MT		 1567 case KVM_CAP_PV_MMU: /* obsolete */
1568 r = 0;
2f333bcb 1569 break;
62c476c7 1570 case KVM_CAP_IOMMU:
19de40a8 1571 r = iommu_found();
62c476c7 1572 break;
890ca9ae
HY		 1573 case KVM_CAP_MCE:
1574 r = KVM_MAX_MCE_BANKS;
1575 break;
018d00d2
ZX		 1576 default:
1577 r = 0;
1578 break;
1579 }
1580 return r;
1581
1582}
1583
043405e1
CO		 1584long kvm_arch_dev_ioctl(struct file *filp,
1585 unsigned int ioctl, unsigned long arg)
1586{
1587 void __user *argp = (void __user *)arg;
1588 long r;
1589
1590 switch (ioctl) {
1591 case KVM_GET_MSR_INDEX_LIST: {
1592 struct kvm_msr_list __user *user_msr_list = argp;
1593 struct kvm_msr_list msr_list;
1594 unsigned n;
1595
1596 r = -EFAULT;
1597 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1598 goto out;
1599 n = msr_list.nmsrs;
1600 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1601 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1602 goto out;
1603 r = -E2BIG;
e125e7b6 1604 if (n < msr_list.nmsrs)
043405e1
CO		 1605 goto out;
1606 r = -EFAULT;
1607 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1608 num_msrs_to_save * sizeof(u32)))
1609 goto out;
e125e7b6 1610 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1611 &emulated_msrs,
1612 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1613 goto out;
1614 r = 0;
1615 break;
1616 }
674eea0f
AK		 1617 case KVM_GET_SUPPORTED_CPUID: {
1618 struct kvm_cpuid2 __user *cpuid_arg = argp;
1619 struct kvm_cpuid2 cpuid;
1620
1621 r = -EFAULT;
1622 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1623 goto out;
1624 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1625 cpuid_arg->entries);
674eea0f
AK		 1626 if (r)
1627 goto out;
1628
1629 r = -EFAULT;
1630 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1631 goto out;
1632 r = 0;
1633 break;
1634 }
890ca9ae
HY		 1635 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1636 u64 mce_cap;
1637
1638 mce_cap = KVM_MCE_CAP_SUPPORTED;
1639 r = -EFAULT;
1640 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1641 goto out;
1642 r = 0;
1643 break;
1644 }
043405e1
CO		 1645 default:
1646 r = -EINVAL;
1647 }
1648out:
1649 return r;
1650}
1651
313a3dc7
CO		 1652void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1653{
1654 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1655 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1656 unsigned long khz = cpufreq_quick_get(cpu);
1657 if (!khz)
1658 khz = tsc_khz;
1659 per_cpu(cpu_tsc_khz, cpu) = khz;
1660 }
c8076604 1661 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1662}
1663
1664void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1665{
9327fd11 1666 kvm_put_guest_fpu(vcpu);
02daab21 1667 kvm_x86_ops->vcpu_put(vcpu);
313a3dc7
CO		 1668}
1669
07716717 1670static int is_efer_nx(void)
313a3dc7 1671{
e286e86e 1672 unsigned long long efer = 0;
313a3dc7 1673
e286e86e 1674 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1675 return efer & EFER_NX;
1676}
1677
1678static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1679{
1680 int i;
1681 struct kvm_cpuid_entry2 *e, *entry;
1682
313a3dc7 1683 entry = NULL;
ad312c7c
ZX		 1684 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1685 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1686 if (e->function == 0x80000001) {
1687 entry = e;
1688 break;
1689 }
1690 }
07716717 1691 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1692 entry->edx &= ~(1 << 20);
1693 printk(KERN_INFO "kvm: guest NX capability removed\n");
1694 }
1695}
1696
07716717 1697/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1698static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1699 struct kvm_cpuid *cpuid,
1700 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1701{
1702 int r, i;
1703 struct kvm_cpuid_entry *cpuid_entries;
1704
1705 r = -E2BIG;
1706 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1707 goto out;
1708 r = -ENOMEM;
1709 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1710 if (!cpuid_entries)
1711 goto out;
1712 r = -EFAULT;
1713 if (copy_from_user(cpuid_entries, entries,
1714 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1715 goto out_free;
1716 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1717 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1718 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1719 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1720 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1721 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1722 vcpu->arch.cpuid_entries[i].index = 0;
1723 vcpu->arch.cpuid_entries[i].flags = 0;
1724 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1725 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1726 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1727 }
1728 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1729 cpuid_fix_nx_cap(vcpu);
1730 r = 0;
fc61b800 1731 kvm_apic_set_version(vcpu);
0e851880 1732 kvm_x86_ops->cpuid_update(vcpu);
07716717
DK		 1733
1734out_free:
1735 vfree(cpuid_entries);
1736out:
1737 return r;
1738}
1739
1740static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1741 struct kvm_cpuid2 *cpuid,
1742 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1743{
1744 int r;
1745
1746 r = -E2BIG;
1747 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1748 goto out;
1749 r = -EFAULT;
ad312c7c 1750 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1751 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1752 goto out;
ad312c7c 1753 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1754 kvm_apic_set_version(vcpu);
0e851880 1755 kvm_x86_ops->cpuid_update(vcpu);
313a3dc7
CO		 1756 return 0;
1757
1758out:
1759 return r;
1760}
1761
07716717 1762static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1763 struct kvm_cpuid2 *cpuid,
1764 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1765{
1766 int r;
1767
1768 r = -E2BIG;
ad312c7c 1769 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1770 goto out;
1771 r = -EFAULT;
ad312c7c 1772 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1773 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1774 goto out;
1775 return 0;
1776
1777out:
ad312c7c 1778 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1779 return r;
1780}
1781
07716717 1782static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1783 u32 index)
07716717
DK		 1784{
1785 entry->function = function;
1786 entry->index = index;
1787 cpuid_count(entry->function, entry->index,
19355475 1788 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1789 entry->flags = 0;
1790}
1791
7faa4ee1
AK		 1792#define F(x) bit(X86_FEATURE_##x)
1793
07716717
DK		 1794static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1795 u32 index, int *nent, int maxnent)
1796{
7faa4ee1 1797 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1798#ifdef CONFIG_X86_64
17cc3935
SY		 1799 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1800 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1801 unsigned f_lm = F(LM);
1802#else
17cc3935 1803 unsigned f_gbpages = 0;
7faa4ee1 1804 unsigned f_lm = 0;
07716717 1805#endif
4e47c7a6 1806 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1807
1808 /* cpuid 1.edx */
1809 const u32 kvm_supported_word0_x86_features =
1810 F(FPU) | F(VME) | F(DE) | F(PSE) |
1811 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1812 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1813 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1814 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1815 0 /* Reserved, DS, ACPI */ | F(MMX) |
1816 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1817 0 /* HTT, TM, Reserved, PBE */;
1818 /* cpuid 0x80000001.edx */
1819 const u32 kvm_supported_word1_x86_features =
1820 F(FPU) | F(VME) | F(DE) | F(PSE) |
1821 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1822 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1823 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1824 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1825 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1826 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1827 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1828 /* cpuid 1.ecx */
1829 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1830 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1831 0 /* DS-CPL, VMX, SMX, EST */ |
1832 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1833 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1834 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1835 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1836 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1837 /* cpuid 0x80000001.ecx */
07716717 1838 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1839 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1840 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1841 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1842 0 /* SKINIT */ | 0 /* WDT */;
07716717 1843
19355475 1844 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1845 get_cpu();
1846 do_cpuid_1_ent(entry, function, index);
1847 ++*nent;
1848
1849 switch (function) {
1850 case 0:
1851 entry->eax = min(entry->eax, (u32)0xb);
1852 break;
1853 case 1:
1854 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1855 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1856 /* we support x2apic emulation even if host does not support
1857 * it since we emulate x2apic in software */
1858 entry->ecx |= F(X2APIC);
07716717
DK		 1859 break;
1860 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1861 * may return different values. This forces us to get_cpu() before
1862 * issuing the first command, and also to emulate this annoying behavior
1863 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1864 case 2: {
1865 int t, times = entry->eax & 0xff;
1866
1867 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1868 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1869 for (t = 1; t < times && *nent < maxnent; ++t) {
1870 do_cpuid_1_ent(&entry[t], function, 0);
1871 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1872 ++*nent;
1873 }
1874 break;
1875 }
1876 /* function 4 and 0xb have additional index. */
1877 case 4: {
14af3f3c 1878 int i, cache_type;
07716717
DK		 1879
1880 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1881 /* read more entries until cache_type is zero */
14af3f3c
HH		 1882 for (i = 1; *nent < maxnent; ++i) {
1883 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1884 if (!cache_type)
1885 break;
14af3f3c
HH		 1886 do_cpuid_1_ent(&entry[i], function, i);
1887 entry[i].flags |=
07716717
DK		 1888 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1889 ++*nent;
1890 }
1891 break;
1892 }
1893 case 0xb: {
14af3f3c 1894 int i, level_type;
07716717
DK		 1895
1896 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1897 /* read more entries until level_type is zero */
14af3f3c 1898 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1899 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1900 if (!level_type)
1901 break;
14af3f3c
HH		 1902 do_cpuid_1_ent(&entry[i], function, i);
1903 entry[i].flags |=
07716717
DK		 1904 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1905 ++*nent;
1906 }
1907 break;
1908 }
1909 case 0x80000000:
1910 entry->eax = min(entry->eax, 0x8000001a);
1911 break;
1912 case 0x80000001:
1913 entry->edx &= kvm_supported_word1_x86_features;
1914 entry->ecx &= kvm_supported_word6_x86_features;
1915 break;
1916 }
1917 put_cpu();
1918}
1919
7faa4ee1
AK		 1920#undef F
1921
674eea0f 1922static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1923 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1924{
1925 struct kvm_cpuid_entry2 *cpuid_entries;
1926 int limit, nent = 0, r = -E2BIG;
1927 u32 func;
1928
1929 if (cpuid->nent < 1)
1930 goto out;
6a544355
AK		 1931 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1932 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 1933 r = -ENOMEM;
1934 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1935 if (!cpuid_entries)
1936 goto out;
1937
1938 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1939 limit = cpuid_entries[0].eax;
1940 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1941 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1942 &nent, cpuid->nent);
07716717
DK		 1943 r = -E2BIG;
1944 if (nent >= cpuid->nent)
1945 goto out_free;
1946
1947 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1948 limit = cpuid_entries[nent - 1].eax;
1949 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1950 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1951 &nent, cpuid->nent);
cb007648
MM		 1952 r = -E2BIG;
1953 if (nent >= cpuid->nent)
1954 goto out_free;
1955
07716717
DK		 1956 r = -EFAULT;
1957 if (copy_to_user(entries, cpuid_entries,
19355475 1958 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1959 goto out_free;
1960 cpuid->nent = nent;
1961 r = 0;
1962
1963out_free:
1964 vfree(cpuid_entries);
1965out:
1966 return r;
1967}
1968
313a3dc7
CO		 1969static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1970 struct kvm_lapic_state *s)
1971{
1972 vcpu_load(vcpu);
ad312c7c 1973 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1974 vcpu_put(vcpu);
1975
1976 return 0;
1977}
1978
1979static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1980 struct kvm_lapic_state *s)
1981{
1982 vcpu_load(vcpu);
ad312c7c 1983 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 1984 kvm_apic_post_state_restore(vcpu);
cb142eb7 1985 update_cr8_intercept(vcpu);
313a3dc7
CO		 1986 vcpu_put(vcpu);
1987
1988 return 0;
1989}
1990
f77bc6a4
ZX		 1991static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1992 struct kvm_interrupt *irq)
1993{
1994 if (irq->irq < 0 || irq->irq >= 256)
1995 return -EINVAL;
1996 if (irqchip_in_kernel(vcpu->kvm))
1997 return -ENXIO;
1998 vcpu_load(vcpu);
1999
66fd3f7f 2000 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 2001
2002 vcpu_put(vcpu);
2003
2004 return 0;
2005}
2006
c4abb7c9
JK		 2007static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2008{
2009 vcpu_load(vcpu);
2010 kvm_inject_nmi(vcpu);
2011 vcpu_put(vcpu);
2012
2013 return 0;
2014}
2015
b209749f
AK		 2016static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2017 struct kvm_tpr_access_ctl *tac)
2018{
2019 if (tac->flags)
2020 return -EINVAL;
2021 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2022 return 0;
2023}
2024
890ca9ae
HY		 2025static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2026 u64 mcg_cap)
2027{
2028 int r;
2029 unsigned bank_num = mcg_cap & 0xff, bank;
2030
2031 r = -EINVAL;
a9e38c3e 2032 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2033 goto out;
2034 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2035 goto out;
2036 r = 0;
2037 vcpu->arch.mcg_cap = mcg_cap;
2038 /* Init IA32_MCG_CTL to all 1s */
2039 if (mcg_cap & MCG_CTL_P)
2040 vcpu->arch.mcg_ctl = ~(u64)0;
2041 /* Init IA32_MCi_CTL to all 1s */
2042 for (bank = 0; bank < bank_num; bank++)
2043 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2044out:
2045 return r;
2046}
2047
2048static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2049 struct kvm_x86_mce *mce)
2050{
2051 u64 mcg_cap = vcpu->arch.mcg_cap;
2052 unsigned bank_num = mcg_cap & 0xff;
2053 u64 *banks = vcpu->arch.mce_banks;
2054
2055 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2056 return -EINVAL;
2057 /*
2058 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2059 * reporting is disabled
2060 */
2061 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2062 vcpu->arch.mcg_ctl != ~(u64)0)
2063 return 0;
2064 banks += 4 * mce->bank;
2065 /*
2066 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2067 * reporting is disabled for the bank
2068 */
2069 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2070 return 0;
2071 if (mce->status & MCI_STATUS_UC) {
2072 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2073 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2074 printk(KERN_DEBUG "kvm: set_mce: "
2075 "injects mce exception while "
2076 "previous one is in progress!\n");
2077 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2078 return 0;
2079 }
2080 if (banks[1] & MCI_STATUS_VAL)
2081 mce->status |= MCI_STATUS_OVER;
2082 banks[2] = mce->addr;
2083 banks[3] = mce->misc;
2084 vcpu->arch.mcg_status = mce->mcg_status;
2085 banks[1] = mce->status;
2086 kvm_queue_exception(vcpu, MC_VECTOR);
2087 } else if (!(banks[1] & MCI_STATUS_VAL)
2088 || !(banks[1] & MCI_STATUS_UC)) {
2089 if (banks[1] & MCI_STATUS_VAL)
2090 mce->status |= MCI_STATUS_OVER;
2091 banks[2] = mce->addr;
2092 banks[3] = mce->misc;
2093 banks[1] = mce->status;
2094 } else
2095 banks[1] |= MCI_STATUS_OVER;
2096 return 0;
2097}
2098
3cfc3092
JK		 2099static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2100 struct kvm_vcpu_events *events)
2101{
2102 vcpu_load(vcpu);
2103
03b82a30
JK		 2104 events->exception.injected =
2105 vcpu->arch.exception.pending &&
2106 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2107 events->exception.nr = vcpu->arch.exception.nr;
2108 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2109 events->exception.error_code = vcpu->arch.exception.error_code;
2110
03b82a30
JK		 2111 events->interrupt.injected =
2112 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2113 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2114 events->interrupt.soft = 0;
48005f64
JK		 2115 events->interrupt.shadow =
2116 kvm_x86_ops->get_interrupt_shadow(vcpu,
2117 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2118
2119 events->nmi.injected = vcpu->arch.nmi_injected;
2120 events->nmi.pending = vcpu->arch.nmi_pending;
2121 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2122
2123 events->sipi_vector = vcpu->arch.sipi_vector;
2124
dab4b911 2125 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2126 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2127 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2128
2129 vcpu_put(vcpu);
2130}
2131
2132static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2133 struct kvm_vcpu_events *events)
2134{
dab4b911 2135 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2136 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2137 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2138 return -EINVAL;
2139
2140 vcpu_load(vcpu);
2141
2142 vcpu->arch.exception.pending = events->exception.injected;
2143 vcpu->arch.exception.nr = events->exception.nr;
2144 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2145 vcpu->arch.exception.error_code = events->exception.error_code;
2146
2147 vcpu->arch.interrupt.pending = events->interrupt.injected;
2148 vcpu->arch.interrupt.nr = events->interrupt.nr;
2149 vcpu->arch.interrupt.soft = events->interrupt.soft;
2150 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2151 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2152 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2153 kvm_x86_ops->set_interrupt_shadow(vcpu,
2154 events->interrupt.shadow);
3cfc3092
JK		 2155
2156 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2157 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2158 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2159 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2160
dab4b911
JK		 2161 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2162 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 2163
2164 vcpu_put(vcpu);
2165
2166 return 0;
2167}
2168
a1efbe77
JK		 2169static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2170 struct kvm_debugregs *dbgregs)
2171{
2172 vcpu_load(vcpu);
2173
2174 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2175 dbgregs->dr6 = vcpu->arch.dr6;
2176 dbgregs->dr7 = vcpu->arch.dr7;
2177 dbgregs->flags = 0;
2178
2179 vcpu_put(vcpu);
2180}
2181
2182static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2183 struct kvm_debugregs *dbgregs)
2184{
2185 if (dbgregs->flags)
2186 return -EINVAL;
2187
2188 vcpu_load(vcpu);
2189
2190 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2191 vcpu->arch.dr6 = dbgregs->dr6;
2192 vcpu->arch.dr7 = dbgregs->dr7;
2193
2194 vcpu_put(vcpu);
2195
2196 return 0;
2197}
2198
313a3dc7
CO		 2199long kvm_arch_vcpu_ioctl(struct file *filp,
2200 unsigned int ioctl, unsigned long arg)
2201{
2202 struct kvm_vcpu *vcpu = filp->private_data;
2203 void __user *argp = (void __user *)arg;
2204 int r;
b772ff36 2205 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2206
2207 switch (ioctl) {
2208 case KVM_GET_LAPIC: {
2204ae3c
MT		 2209 r = -EINVAL;
2210 if (!vcpu->arch.apic)
2211 goto out;
b772ff36 2212 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2213
b772ff36
DH		 2214 r = -ENOMEM;
2215 if (!lapic)
2216 goto out;
2217 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2218 if (r)
2219 goto out;
2220 r = -EFAULT;
b772ff36 2221 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2222 goto out;
2223 r = 0;
2224 break;
2225 }
2226 case KVM_SET_LAPIC: {
2204ae3c
MT		 2227 r = -EINVAL;
2228 if (!vcpu->arch.apic)
2229 goto out;
b772ff36
DH		 2230 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2231 r = -ENOMEM;
2232 if (!lapic)
2233 goto out;
313a3dc7 2234 r = -EFAULT;
b772ff36 2235 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2236 goto out;
b772ff36 2237 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2238 if (r)
2239 goto out;
2240 r = 0;
2241 break;
2242 }
f77bc6a4
ZX		 2243 case KVM_INTERRUPT: {
2244 struct kvm_interrupt irq;
2245
2246 r = -EFAULT;
2247 if (copy_from_user(&irq, argp, sizeof irq))
2248 goto out;
2249 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2250 if (r)
2251 goto out;
2252 r = 0;
2253 break;
2254 }
c4abb7c9
JK		 2255 case KVM_NMI: {
2256 r = kvm_vcpu_ioctl_nmi(vcpu);
2257 if (r)
2258 goto out;
2259 r = 0;
2260 break;
2261 }
313a3dc7
CO		 2262 case KVM_SET_CPUID: {
2263 struct kvm_cpuid __user *cpuid_arg = argp;
2264 struct kvm_cpuid cpuid;
2265
2266 r = -EFAULT;
2267 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2268 goto out;
2269 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2270 if (r)
2271 goto out;
2272 break;
2273 }
07716717
DK		 2274 case KVM_SET_CPUID2: {
2275 struct kvm_cpuid2 __user *cpuid_arg = argp;
2276 struct kvm_cpuid2 cpuid;
2277
2278 r = -EFAULT;
2279 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2280 goto out;
2281 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2282 cpuid_arg->entries);
07716717
DK		 2283 if (r)
2284 goto out;
2285 break;
2286 }
2287 case KVM_GET_CPUID2: {
2288 struct kvm_cpuid2 __user *cpuid_arg = argp;
2289 struct kvm_cpuid2 cpuid;
2290
2291 r = -EFAULT;
2292 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2293 goto out;
2294 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2295 cpuid_arg->entries);
07716717
DK		 2296 if (r)
2297 goto out;
2298 r = -EFAULT;
2299 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2300 goto out;
2301 r = 0;
2302 break;
2303 }
313a3dc7
CO		 2304 case KVM_GET_MSRS:
2305 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2306 break;
2307 case KVM_SET_MSRS:
2308 r = msr_io(vcpu, argp, do_set_msr, 0);
2309 break;
b209749f
AK		 2310 case KVM_TPR_ACCESS_REPORTING: {
2311 struct kvm_tpr_access_ctl tac;
2312
2313 r = -EFAULT;
2314 if (copy_from_user(&tac, argp, sizeof tac))
2315 goto out;
2316 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2317 if (r)
2318 goto out;
2319 r = -EFAULT;
2320 if (copy_to_user(argp, &tac, sizeof tac))
2321 goto out;
2322 r = 0;
2323 break;
2324 };
b93463aa
AK		 2325 case KVM_SET_VAPIC_ADDR: {
2326 struct kvm_vapic_addr va;
2327
2328 r = -EINVAL;
2329 if (!irqchip_in_kernel(vcpu->kvm))
2330 goto out;
2331 r = -EFAULT;
2332 if (copy_from_user(&va, argp, sizeof va))
2333 goto out;
2334 r = 0;
2335 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2336 break;
2337 }
890ca9ae
HY		 2338 case KVM_X86_SETUP_MCE: {
2339 u64 mcg_cap;
2340
2341 r = -EFAULT;
2342 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2343 goto out;
2344 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2345 break;
2346 }
2347 case KVM_X86_SET_MCE: {
2348 struct kvm_x86_mce mce;
2349
2350 r = -EFAULT;
2351 if (copy_from_user(&mce, argp, sizeof mce))
2352 goto out;
2353 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2354 break;
2355 }
3cfc3092
JK		 2356 case KVM_GET_VCPU_EVENTS: {
2357 struct kvm_vcpu_events events;
2358
2359 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2360
2361 r = -EFAULT;
2362 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2363 break;
2364 r = 0;
2365 break;
2366 }
2367 case KVM_SET_VCPU_EVENTS: {
2368 struct kvm_vcpu_events events;
2369
2370 r = -EFAULT;
2371 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2372 break;
2373
2374 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2375 break;
2376 }
a1efbe77
JK		 2377 case KVM_GET_DEBUGREGS: {
2378 struct kvm_debugregs dbgregs;
2379
2380 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2381
2382 r = -EFAULT;
2383 if (copy_to_user(argp, &dbgregs,
2384 sizeof(struct kvm_debugregs)))
2385 break;
2386 r = 0;
2387 break;
2388 }
2389 case KVM_SET_DEBUGREGS: {
2390 struct kvm_debugregs dbgregs;
2391
2392 r = -EFAULT;
2393 if (copy_from_user(&dbgregs, argp,
2394 sizeof(struct kvm_debugregs)))
2395 break;
2396
2397 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2398 break;
2399 }
313a3dc7
CO		 2400 default:
2401 r = -EINVAL;
2402 }
2403out:
7a6ce84c 2404 kfree(lapic);
313a3dc7
CO		 2405 return r;
2406}
2407
1fe779f8
CO		 2408static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2409{
2410 int ret;
2411
2412 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2413 return -1;
2414 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2415 return ret;
2416}
2417
b927a3ce
SY		 2418static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2419 u64 ident_addr)
2420{
2421 kvm->arch.ept_identity_map_addr = ident_addr;
2422 return 0;
2423}
2424
1fe779f8
CO		 2425static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2426 u32 kvm_nr_mmu_pages)
2427{
2428 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2429 return -EINVAL;
2430
79fac95e 2431 mutex_lock(&kvm->slots_lock);
7c8a83b7 2432 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2433
2434 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2435 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2436
7c8a83b7 2437 spin_unlock(&kvm->mmu_lock);
79fac95e 2438 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2439 return 0;
2440}
2441
2442static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2443{
f05e70ac 2444 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2445}
2446
a983fb23
MT		 2447gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2448{
2449 int i;
2450 struct kvm_mem_alias *alias;
2451 struct kvm_mem_aliases *aliases;
2452
2453 aliases = rcu_dereference(kvm->arch.aliases);
2454
2455 for (i = 0; i < aliases->naliases; ++i) {
2456 alias = &aliases->aliases[i];
2457 if (alias->flags & KVM_ALIAS_INVALID)
2458 continue;
2459 if (gfn >= alias->base_gfn
2460 && gfn < alias->base_gfn + alias->npages)
2461 return alias->target_gfn + gfn - alias->base_gfn;
2462 }
2463 return gfn;
2464}
2465
e9f85cde
ZX		 2466gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2467{
2468 int i;
2469 struct kvm_mem_alias *alias;
a983fb23
MT		 2470 struct kvm_mem_aliases *aliases;
2471
2472 aliases = rcu_dereference(kvm->arch.aliases);
e9f85cde 2473
fef9cce0
MT		 2474 for (i = 0; i < aliases->naliases; ++i) {
2475 alias = &aliases->aliases[i];
e9f85cde
ZX		 2476 if (gfn >= alias->base_gfn
2477 && gfn < alias->base_gfn + alias->npages)
2478 return alias->target_gfn + gfn - alias->base_gfn;
2479 }
2480 return gfn;
2481}
2482
1fe779f8
CO		 2483/*
2484 * Set a new alias region. Aliases map a portion of physical memory into
2485 * another portion. This is useful for memory windows, for example the PC
2486 * VGA region.
2487 */
2488static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2489 struct kvm_memory_alias *alias)
2490{
2491 int r, n;
2492 struct kvm_mem_alias *p;
a983fb23 2493 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2494
2495 r = -EINVAL;
2496 /* General sanity checks */
2497 if (alias->memory_size & (PAGE_SIZE - 1))
2498 goto out;
2499 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2500 goto out;
2501 if (alias->slot >= KVM_ALIAS_SLOTS)
2502 goto out;
2503 if (alias->guest_phys_addr + alias->memory_size
2504 < alias->guest_phys_addr)
2505 goto out;
2506 if (alias->target_phys_addr + alias->memory_size
2507 < alias->target_phys_addr)
2508 goto out;
2509
a983fb23
MT		 2510 r = -ENOMEM;
2511 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2512 if (!aliases)
2513 goto out;
2514
79fac95e 2515 mutex_lock(&kvm->slots_lock);
1fe779f8 2516
a983fb23
MT		 2517 /* invalidate any gfn reference in case of deletion/shrinking */
2518 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2519 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2520 old_aliases = kvm->arch.aliases;
2521 rcu_assign_pointer(kvm->arch.aliases, aliases);
2522 synchronize_srcu_expedited(&kvm->srcu);
2523 kvm_mmu_zap_all(kvm);
2524 kfree(old_aliases);
2525
2526 r = -ENOMEM;
2527 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2528 if (!aliases)
2529 goto out_unlock;
2530
2531 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2532
2533 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2534 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2535 p->npages = alias->memory_size >> PAGE_SHIFT;
2536 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2537 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2538
2539 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2540 if (aliases->aliases[n - 1].npages)
1fe779f8 2541 break;
fef9cce0 2542 aliases->naliases = n;
1fe779f8 2543
a983fb23
MT		 2544 old_aliases = kvm->arch.aliases;
2545 rcu_assign_pointer(kvm->arch.aliases, aliases);
2546 synchronize_srcu_expedited(&kvm->srcu);
2547 kfree(old_aliases);
2548 r = 0;
1fe779f8 2549
a983fb23 2550out_unlock:
79fac95e 2551 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2552out:
2553 return r;
2554}
2555
2556static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2557{
2558 int r;
2559
2560 r = 0;
2561 switch (chip->chip_id) {
2562 case KVM_IRQCHIP_PIC_MASTER:
2563 memcpy(&chip->chip.pic,
2564 &pic_irqchip(kvm)->pics[0],
2565 sizeof(struct kvm_pic_state));
2566 break;
2567 case KVM_IRQCHIP_PIC_SLAVE:
2568 memcpy(&chip->chip.pic,
2569 &pic_irqchip(kvm)->pics[1],
2570 sizeof(struct kvm_pic_state));
2571 break;
2572 case KVM_IRQCHIP_IOAPIC:
eba0226b 2573 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2574 break;
2575 default:
2576 r = -EINVAL;
2577 break;
2578 }
2579 return r;
2580}
2581
2582static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2583{
2584 int r;
2585
2586 r = 0;
2587 switch (chip->chip_id) {
2588 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2589 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2590 memcpy(&pic_irqchip(kvm)->pics[0],
2591 &chip->chip.pic,
2592 sizeof(struct kvm_pic_state));
fa8273e9 2593 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2594 break;
2595 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2596 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2597 memcpy(&pic_irqchip(kvm)->pics[1],
2598 &chip->chip.pic,
2599 sizeof(struct kvm_pic_state));
fa8273e9 2600 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2601 break;
2602 case KVM_IRQCHIP_IOAPIC:
eba0226b 2603 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2604 break;
2605 default:
2606 r = -EINVAL;
2607 break;
2608 }
2609 kvm_pic_update_irq(pic_irqchip(kvm));
2610 return r;
2611}
2612
e0f63cb9
SY		 2613static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2614{
2615 int r = 0;
2616
894a9c55 2617 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2618 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2619 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2620 return r;
2621}
2622
2623static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2624{
2625 int r = 0;
2626
894a9c55 2627 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2628 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2629 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2630 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2631 return r;
2632}
2633
2634static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2635{
2636 int r = 0;
2637
2638 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2639 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2640 sizeof(ps->channels));
2641 ps->flags = kvm->arch.vpit->pit_state.flags;
2642 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2643 return r;
2644}
2645
2646static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2647{
2648 int r = 0, start = 0;
2649 u32 prev_legacy, cur_legacy;
2650 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2651 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2652 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2653 if (!prev_legacy && cur_legacy)
2654 start = 1;
2655 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2656 sizeof(kvm->arch.vpit->pit_state.channels));
2657 kvm->arch.vpit->pit_state.flags = ps->flags;
2658 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2659 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2660 return r;
2661}
2662
52d939a0
MT		 2663static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2664 struct kvm_reinject_control *control)
2665{
2666 if (!kvm->arch.vpit)
2667 return -ENXIO;
894a9c55 2668 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2669 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2670 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2671 return 0;
2672}
2673
5bb064dc
ZX		 2674/*
2675 * Get (and clear) the dirty memory log for a memory slot.
2676 */
2677int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2678 struct kvm_dirty_log *log)
2679{
87bf6e7d 2680 int r, i;
5bb064dc 2681 struct kvm_memory_slot *memslot;
87bf6e7d 2682 unsigned long n;
b050b015
MT		 2683 unsigned long is_dirty = 0;
2684 unsigned long *dirty_bitmap = NULL;
5bb064dc 2685
79fac95e 2686 mutex_lock(&kvm->slots_lock);
5bb064dc 2687
b050b015
MT		 2688 r = -EINVAL;
2689 if (log->slot >= KVM_MEMORY_SLOTS)
2690 goto out;
2691
2692 memslot = &kvm->memslots->memslots[log->slot];
2693 r = -ENOENT;
2694 if (!memslot->dirty_bitmap)
2695 goto out;
2696
87bf6e7d 2697 n = kvm_dirty_bitmap_bytes(memslot);
b050b015
MT		 2698
2699 r = -ENOMEM;
2700 dirty_bitmap = vmalloc(n);
2701 if (!dirty_bitmap)
5bb064dc 2702 goto out;
b050b015
MT		 2703 memset(dirty_bitmap, 0, n);
2704
2705 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2706 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2707
2708 /* If nothing is dirty, don't bother messing with page tables. */
2709 if (is_dirty) {
b050b015
MT		 2710 struct kvm_memslots *slots, *old_slots;
2711
7c8a83b7 2712 spin_lock(&kvm->mmu_lock);
5bb064dc 2713 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2714 spin_unlock(&kvm->mmu_lock);
b050b015
MT		 2715
2716 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2717 if (!slots)
2718 goto out_free;
2719
2720 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2721 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2722
2723 old_slots = kvm->memslots;
2724 rcu_assign_pointer(kvm->memslots, slots);
2725 synchronize_srcu_expedited(&kvm->srcu);
2726 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2727 kfree(old_slots);
5bb064dc 2728 }
b050b015 2729
5bb064dc 2730 r = 0;
b050b015
MT		 2731 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
2732 r = -EFAULT;
2733out_free:
2734 vfree(dirty_bitmap);
5bb064dc 2735out:
79fac95e 2736 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2737 return r;
2738}
2739
1fe779f8
CO		 2740long kvm_arch_vm_ioctl(struct file *filp,
2741 unsigned int ioctl, unsigned long arg)
2742{
2743 struct kvm *kvm = filp->private_data;
2744 void __user *argp = (void __user *)arg;
367e1319 2745 int r = -ENOTTY;
f0d66275
DH		 2746 /*
2747 * This union makes it completely explicit to gcc-3.x
2748 * that these two variables' stack usage should be
2749 * combined, not added together.
2750 */
2751 union {
2752 struct kvm_pit_state ps;
e9f42757 2753 struct kvm_pit_state2 ps2;
f0d66275 2754 struct kvm_memory_alias alias;
c5ff41ce 2755 struct kvm_pit_config pit_config;
f0d66275 2756 } u;
1fe779f8
CO		 2757
2758 switch (ioctl) {
2759 case KVM_SET_TSS_ADDR:
2760 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2761 if (r < 0)
2762 goto out;
2763 break;
b927a3ce
SY		 2764 case KVM_SET_IDENTITY_MAP_ADDR: {
2765 u64 ident_addr;
2766
2767 r = -EFAULT;
2768 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2769 goto out;
2770 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2771 if (r < 0)
2772 goto out;
2773 break;
2774 }
1fe779f8
CO		 2775 case KVM_SET_MEMORY_REGION: {
2776 struct kvm_memory_region kvm_mem;
2777 struct kvm_userspace_memory_region kvm_userspace_mem;
2778
2779 r = -EFAULT;
2780 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2781 goto out;
2782 kvm_userspace_mem.slot = kvm_mem.slot;
2783 kvm_userspace_mem.flags = kvm_mem.flags;
2784 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2785 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2786 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2787 if (r)
2788 goto out;
2789 break;
2790 }
2791 case KVM_SET_NR_MMU_PAGES:
2792 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2793 if (r)
2794 goto out;
2795 break;
2796 case KVM_GET_NR_MMU_PAGES:
2797 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2798 break;
f0d66275 2799 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2800 r = -EFAULT;
f0d66275 2801 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2802 goto out;
f0d66275 2803 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2804 if (r)
2805 goto out;
2806 break;
3ddea128
MT		 2807 case KVM_CREATE_IRQCHIP: {
2808 struct kvm_pic *vpic;
2809
2810 mutex_lock(&kvm->lock);
2811 r = -EEXIST;
2812 if (kvm->arch.vpic)
2813 goto create_irqchip_unlock;
1fe779f8 2814 r = -ENOMEM;
3ddea128
MT		 2815 vpic = kvm_create_pic(kvm);
2816 if (vpic) {
1fe779f8
CO		 2817 r = kvm_ioapic_init(kvm);
2818 if (r) {
72bb2fcd
WY		 2819 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
2820 &vpic->dev);
3ddea128
MT		 2821 kfree(vpic);
2822 goto create_irqchip_unlock;
1fe779f8
CO		 2823 }
2824 } else
3ddea128
MT		 2825 goto create_irqchip_unlock;
2826 smp_wmb();
2827 kvm->arch.vpic = vpic;
2828 smp_wmb();
399ec807
AK		 2829 r = kvm_setup_default_irq_routing(kvm);
2830 if (r) {
3ddea128 2831 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 2832 kvm_ioapic_destroy(kvm);
2833 kvm_destroy_pic(kvm);
3ddea128 2834 mutex_unlock(&kvm->irq_lock);
399ec807 2835 }
3ddea128
MT		 2836 create_irqchip_unlock:
2837 mutex_unlock(&kvm->lock);
1fe779f8 2838 break;
3ddea128 2839 }
7837699f 2840 case KVM_CREATE_PIT:
c5ff41ce
JK		 2841 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2842 goto create_pit;
2843 case KVM_CREATE_PIT2:
2844 r = -EFAULT;
2845 if (copy_from_user(&u.pit_config, argp,
2846 sizeof(struct kvm_pit_config)))
2847 goto out;
2848 create_pit:
79fac95e 2849 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 2850 r = -EEXIST;
2851 if (kvm->arch.vpit)
2852 goto create_pit_unlock;
7837699f 2853 r = -ENOMEM;
c5ff41ce 2854 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2855 if (kvm->arch.vpit)
2856 r = 0;
269e05e4 2857 create_pit_unlock:
79fac95e 2858 mutex_unlock(&kvm->slots_lock);
7837699f 2859 break;
4925663a 2860 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2861 case KVM_IRQ_LINE: {
2862 struct kvm_irq_level irq_event;
2863
2864 r = -EFAULT;
2865 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2866 goto out;
2867 if (irqchip_in_kernel(kvm)) {
4925663a 2868 __s32 status;
4925663a
GN		 2869 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2870 irq_event.irq, irq_event.level);
4925663a
GN		 2871 if (ioctl == KVM_IRQ_LINE_STATUS) {
2872 irq_event.status = status;
2873 if (copy_to_user(argp, &irq_event,
2874 sizeof irq_event))
2875 goto out;
2876 }
1fe779f8
CO		 2877 r = 0;
2878 }
2879 break;
2880 }
2881 case KVM_GET_IRQCHIP: {
2882 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2883 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2884
f0d66275
DH		 2885 r = -ENOMEM;
2886 if (!chip)
1fe779f8 2887 goto out;
f0d66275
DH		 2888 r = -EFAULT;
2889 if (copy_from_user(chip, argp, sizeof *chip))
2890 goto get_irqchip_out;
1fe779f8
CO		 2891 r = -ENXIO;
2892 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2893 goto get_irqchip_out;
2894 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2895 if (r)
f0d66275 2896 goto get_irqchip_out;
1fe779f8 2897 r = -EFAULT;
f0d66275
DH		 2898 if (copy_to_user(argp, chip, sizeof *chip))
2899 goto get_irqchip_out;
1fe779f8 2900 r = 0;
f0d66275
DH		 2901 get_irqchip_out:
2902 kfree(chip);
2903 if (r)
2904 goto out;
1fe779f8
CO		 2905 break;
2906 }
2907 case KVM_SET_IRQCHIP: {
2908 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2909 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2910
f0d66275
DH		 2911 r = -ENOMEM;
2912 if (!chip)
1fe779f8 2913 goto out;
f0d66275
DH		 2914 r = -EFAULT;
2915 if (copy_from_user(chip, argp, sizeof *chip))
2916 goto set_irqchip_out;
1fe779f8
CO		 2917 r = -ENXIO;
2918 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2919 goto set_irqchip_out;
2920 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2921 if (r)
f0d66275 2922 goto set_irqchip_out;
1fe779f8 2923 r = 0;
f0d66275
DH		 2924 set_irqchip_out:
2925 kfree(chip);
2926 if (r)
2927 goto out;
1fe779f8
CO		 2928 break;
2929 }
e0f63cb9 2930 case KVM_GET_PIT: {
e0f63cb9 2931 r = -EFAULT;
f0d66275 2932 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2933 goto out;
2934 r = -ENXIO;
2935 if (!kvm->arch.vpit)
2936 goto out;
f0d66275 2937 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2938 if (r)
2939 goto out;
2940 r = -EFAULT;
f0d66275 2941 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2942 goto out;
2943 r = 0;
2944 break;
2945 }
2946 case KVM_SET_PIT: {
e0f63cb9 2947 r = -EFAULT;
f0d66275 2948 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2949 goto out;
2950 r = -ENXIO;
2951 if (!kvm->arch.vpit)
2952 goto out;
f0d66275 2953 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2954 if (r)
2955 goto out;
2956 r = 0;
2957 break;
2958 }
e9f42757
BK		 2959 case KVM_GET_PIT2: {
2960 r = -ENXIO;
2961 if (!kvm->arch.vpit)
2962 goto out;
2963 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2964 if (r)
2965 goto out;
2966 r = -EFAULT;
2967 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2968 goto out;
2969 r = 0;
2970 break;
2971 }
2972 case KVM_SET_PIT2: {
2973 r = -EFAULT;
2974 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2975 goto out;
2976 r = -ENXIO;
2977 if (!kvm->arch.vpit)
2978 goto out;
2979 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2980 if (r)
2981 goto out;
2982 r = 0;
2983 break;
2984 }
52d939a0
MT		 2985 case KVM_REINJECT_CONTROL: {
2986 struct kvm_reinject_control control;
2987 r = -EFAULT;
2988 if (copy_from_user(&control, argp, sizeof(control)))
2989 goto out;
2990 r = kvm_vm_ioctl_reinject(kvm, &control);
2991 if (r)
2992 goto out;
2993 r = 0;
2994 break;
2995 }
ffde22ac
ES		 2996 case KVM_XEN_HVM_CONFIG: {
2997 r = -EFAULT;
2998 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
2999 sizeof(struct kvm_xen_hvm_config)))
3000 goto out;
3001 r = -EINVAL;
3002 if (kvm->arch.xen_hvm_config.flags)
3003 goto out;
3004 r = 0;
3005 break;
3006 }
afbcf7ab
GC		 3007 case KVM_SET_CLOCK: {
3008 struct timespec now;
3009 struct kvm_clock_data user_ns;
3010 u64 now_ns;
3011 s64 delta;
3012
3013 r = -EFAULT;
3014 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3015 goto out;
3016
3017 r = -EINVAL;
3018 if (user_ns.flags)
3019 goto out;
3020
3021 r = 0;
3022 ktime_get_ts(&now);
3023 now_ns = timespec_to_ns(&now);
3024 delta = user_ns.clock - now_ns;
3025 kvm->arch.kvmclock_offset = delta;
3026 break;
3027 }
3028 case KVM_GET_CLOCK: {
3029 struct timespec now;
3030 struct kvm_clock_data user_ns;
3031 u64 now_ns;
3032
3033 ktime_get_ts(&now);
3034 now_ns = timespec_to_ns(&now);
3035 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3036 user_ns.flags = 0;
3037
3038 r = -EFAULT;
3039 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3040 goto out;
3041 r = 0;
3042 break;
3043 }
3044
1fe779f8
CO		 3045 default:
3046 ;
3047 }
3048out:
3049 return r;
3050}
3051
a16b043c 3052static void kvm_init_msr_list(void)
043405e1
CO		 3053{
3054 u32 dummy[2];
3055 unsigned i, j;
3056
e3267cbb
GC		 3057 /* skip the first msrs in the list. KVM-specific */
3058 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3059 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3060 continue;
3061 if (j < i)
3062 msrs_to_save[j] = msrs_to_save[i];
3063 j++;
3064 }
3065 num_msrs_to_save = j;
3066}
3067
bda9020e
MT		 3068static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3069 const void *v)
bbd9b64e 3070{
bda9020e
MT		 3071 if (vcpu->arch.apic &&
3072 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3073 return 0;
bbd9b64e 3074
e93f8a0f 3075 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3076}
3077
bda9020e 3078static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3079{
bda9020e
MT		 3080 if (vcpu->arch.apic &&
3081 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3082 return 0;
bbd9b64e 3083
e93f8a0f 3084 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3085}
3086
1871c602
GN		 3087gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3088{
3089 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3090 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3091}
3092
3093 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3094{
3095 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3096 access |= PFERR_FETCH_MASK;
3097 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3098}
3099
3100gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3101{
3102 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3103 access |= PFERR_WRITE_MASK;
3104 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3105}
3106
3107/* uses this to access any guest's mapped memory without checking CPL */
3108gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3109{
3110 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3111}
3112
3113static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3114 struct kvm_vcpu *vcpu, u32 access,
3115 u32 *error)
bbd9b64e
CO		 3116{
3117 void *data = val;
10589a46 3118 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3119
3120 while (bytes) {
1871c602 3121 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3122 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3123 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3124 int ret;
3125
10589a46
MT		 3126 if (gpa == UNMAPPED_GVA) {
3127 r = X86EMUL_PROPAGATE_FAULT;
3128 goto out;
3129 }
77c2002e 3130 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 3131 if (ret < 0) {
3132 r = X86EMUL_UNHANDLEABLE;
3133 goto out;
3134 }
bbd9b64e 3135
77c2002e
IE		 3136 bytes -= toread;
3137 data += toread;
3138 addr += toread;
bbd9b64e 3139 }
10589a46 3140out:
10589a46 3141 return r;
bbd9b64e 3142}
77c2002e 3143
1871c602
GN		 3144/* used for instruction fetching */
3145static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3146 struct kvm_vcpu *vcpu, u32 *error)
3147{
3148 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3149 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3150 access | PFERR_FETCH_MASK, error);
3151}
3152
3153static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3154 struct kvm_vcpu *vcpu, u32 *error)
3155{
3156 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3157 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3158 error);
3159}
3160
3161static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3162 struct kvm_vcpu *vcpu, u32 *error)
3163{
3164 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3165}
3166
cded19f3 3167static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
1871c602 3168 struct kvm_vcpu *vcpu, u32 *error)
77c2002e
IE		 3169{
3170 void *data = val;
3171 int r = X86EMUL_CONTINUE;
3172
3173 while (bytes) {
1871c602 3174 gpa_t gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error);
77c2002e
IE		 3175 unsigned offset = addr & (PAGE_SIZE-1);
3176 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3177 int ret;
3178
3179 if (gpa == UNMAPPED_GVA) {
3180 r = X86EMUL_PROPAGATE_FAULT;
3181 goto out;
3182 }
3183 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3184 if (ret < 0) {
3185 r = X86EMUL_UNHANDLEABLE;
3186 goto out;
3187 }
3188
3189 bytes -= towrite;
3190 data += towrite;
3191 addr += towrite;
3192 }
3193out:
3194 return r;
3195}
3196
bbd9b64e 3197
bbd9b64e
CO		 3198static int emulator_read_emulated(unsigned long addr,
3199 void *val,
3200 unsigned int bytes,
3201 struct kvm_vcpu *vcpu)
3202{
bbd9b64e 3203 gpa_t gpa;
1871c602 3204 u32 error_code;
bbd9b64e
CO		 3205
3206 if (vcpu->mmio_read_completed) {
3207 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3208 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3209 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3210 vcpu->mmio_read_completed = 0;
3211 return X86EMUL_CONTINUE;
3212 }
3213
1871c602
GN		 3214 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, &error_code);
3215
3216 if (gpa == UNMAPPED_GVA) {
3217 kvm_inject_page_fault(vcpu, addr, error_code);
3218 return X86EMUL_PROPAGATE_FAULT;
3219 }
bbd9b64e
CO		 3220
3221 /* For APIC access vmexit */
3222 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3223 goto mmio;
3224
1871c602 3225 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3226 == X86EMUL_CONTINUE)
bbd9b64e 3227 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3228
3229mmio:
3230 /*
3231 * Is this MMIO handled locally?
3232 */
aec51dc4
AK		 3233 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3234 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3235 return X86EMUL_CONTINUE;
3236 }
aec51dc4
AK		 3237
3238 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3239
3240 vcpu->mmio_needed = 1;
3241 vcpu->mmio_phys_addr = gpa;
3242 vcpu->mmio_size = bytes;
3243 vcpu->mmio_is_write = 0;
3244
3245 return X86EMUL_UNHANDLEABLE;
3246}
3247
3200f405 3248int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3249 const void *val, int bytes)
bbd9b64e
CO		 3250{
3251 int ret;
3252
3253 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3254 if (ret < 0)
bbd9b64e 3255 return 0;
ad218f85 3256 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3257 return 1;
3258}
3259
3260static int emulator_write_emulated_onepage(unsigned long addr,
3261 const void *val,
3262 unsigned int bytes,
3263 struct kvm_vcpu *vcpu)
3264{
10589a46 3265 gpa_t gpa;
1871c602 3266 u32 error_code;
10589a46 3267
1871c602 3268 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, &error_code);
bbd9b64e
CO		 3269
3270 if (gpa == UNMAPPED_GVA) {
1871c602 3271 kvm_inject_page_fault(vcpu, addr, error_code);
bbd9b64e
CO		 3272 return X86EMUL_PROPAGATE_FAULT;
3273 }
3274
3275 /* For APIC access vmexit */
3276 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3277 goto mmio;
3278
3279 if (emulator_write_phys(vcpu, gpa, val, bytes))
3280 return X86EMUL_CONTINUE;
3281
3282mmio:
aec51dc4 3283 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3284 /*
3285 * Is this MMIO handled locally?
3286 */
bda9020e 3287 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3288 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3289
3290 vcpu->mmio_needed = 1;
3291 vcpu->mmio_phys_addr = gpa;
3292 vcpu->mmio_size = bytes;
3293 vcpu->mmio_is_write = 1;
3294 memcpy(vcpu->mmio_data, val, bytes);
3295
3296 return X86EMUL_CONTINUE;
3297}
3298
3299int emulator_write_emulated(unsigned long addr,
3300 const void *val,
3301 unsigned int bytes,
3302 struct kvm_vcpu *vcpu)
3303{
3304 /* Crossing a page boundary? */
3305 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3306 int rc, now;
3307
3308 now = -addr & ~PAGE_MASK;
3309 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
3310 if (rc != X86EMUL_CONTINUE)
3311 return rc;
3312 addr += now;
3313 val += now;
3314 bytes -= now;
3315 }
3316 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
3317}
3318EXPORT_SYMBOL_GPL(emulator_write_emulated);
3319
3320static int emulator_cmpxchg_emulated(unsigned long addr,
3321 const void *old,
3322 const void *new,
3323 unsigned int bytes,
3324 struct kvm_vcpu *vcpu)
3325{
9f51e24e 3326 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c
MT		 3327#ifndef CONFIG_X86_64
3328 /* guests cmpxchg8b have to be emulated atomically */
3329 if (bytes == 8) {
10589a46 3330 gpa_t gpa;
2bacc55c 3331 struct page *page;
c0b49b0d 3332 char *kaddr;
2bacc55c
MT		 3333 u64 val;
3334
1871c602 3335 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
10589a46 3336
2bacc55c
MT		 3337 if (gpa == UNMAPPED_GVA ||
3338 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3339 goto emul_write;
3340
3341 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3342 goto emul_write;
3343
3344 val = *(u64 *)new;
72dc67a6 3345
2bacc55c 3346 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3347
c0b49b0d
AM		 3348 kaddr = kmap_atomic(page, KM_USER0);
3349 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
3350 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 3351 kvm_release_page_dirty(page);
3352 }
3200f405 3353emul_write:
2bacc55c
MT		 3354#endif
3355
bbd9b64e
CO		 3356 return emulator_write_emulated(addr, new, bytes, vcpu);
3357}
3358
3359static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3360{
3361 return kvm_x86_ops->get_segment_base(vcpu, seg);
3362}
3363
3364int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3365{
a7052897 3366 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3367 return X86EMUL_CONTINUE;
3368}
3369
3370int emulate_clts(struct kvm_vcpu *vcpu)
3371{
4d4ec087 3372 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3373 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3374 return X86EMUL_CONTINUE;
3375}
3376
3377int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
3378{
c76de350 3379 return kvm_x86_ops->get_dr(ctxt->vcpu, dr, dest);
bbd9b64e
CO		 3380}
3381
3382int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
3383{
3384 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
bbd9b64e 3385
c76de350 3386 return kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask);
bbd9b64e
CO		 3387}
3388
3389void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
3390{
bbd9b64e 3391 u8 opcodes[4];
5fdbf976 3392 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 3393 unsigned long rip_linear;
3394
f76c710d 3395 if (!printk_ratelimit())
bbd9b64e
CO		 3396 return;
3397
25be4608
GC		 3398 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
3399
1871c602 3400 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu, NULL);
bbd9b64e
CO		 3401
3402 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
3403 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 3404}
3405EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
3406
14af3f3c 3407static struct x86_emulate_ops emulate_ops = {
1871c602
GN		 3408 .read_std = kvm_read_guest_virt_system,
3409 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3410 .read_emulated = emulator_read_emulated,
3411 .write_emulated = emulator_write_emulated,
3412 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3413};
3414
5fdbf976
MT		 3415static void cache_all_regs(struct kvm_vcpu *vcpu)
3416{
3417 kvm_register_read(vcpu, VCPU_REGS_RAX);
3418 kvm_register_read(vcpu, VCPU_REGS_RSP);
3419 kvm_register_read(vcpu, VCPU_REGS_RIP);
3420 vcpu->arch.regs_dirty = ~0;
3421}
3422
bbd9b64e 3423int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3424 unsigned long cr2,
3425 u16 error_code,
571008da 3426 int emulation_type)
bbd9b64e 3427{
310b5d30 3428 int r, shadow_mask;
571008da 3429 struct decode_cache *c;
851ba692 3430 struct kvm_run *run = vcpu->run;
bbd9b64e 3431
26eef70c 3432 kvm_clear_exception_queue(vcpu);
ad312c7c 3433 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3434 /*
56e82318 3435 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3436 * instead of direct ->regs accesses, can save hundred cycles
3437 * on Intel for instructions that don't read/change RSP, for
3438 * for example.
3439 */
3440 cache_all_regs(vcpu);
bbd9b64e
CO		 3441
3442 vcpu->mmio_is_write = 0;
ad312c7c 3443 vcpu->arch.pio.string = 0;
bbd9b64e 3444
571008da 3445 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3446 int cs_db, cs_l;
3447 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3448
ad312c7c 3449 vcpu->arch.emulate_ctxt.vcpu = vcpu;
91586a3b 3450 vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu);
ad312c7c 3451 vcpu->arch.emulate_ctxt.mode =
a0044755 3452 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3453 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3454 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3455 ? X86EMUL_MODE_PROT64 : cs_db
3456 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3457
ad312c7c 3458 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 3459
0cb5762e
AP		 3460 /* Only allow emulation of specific instructions on #UD
3461 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 3462 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 3463 if (emulation_type & EMULTYPE_TRAP_UD) {
3464 if (!c->twobyte)
3465 return EMULATE_FAIL;
3466 switch (c->b) {
3467 case 0x01: /* VMMCALL */
3468 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3469 return EMULATE_FAIL;
3470 break;
3471 case 0x34: /* sysenter */
3472 case 0x35: /* sysexit */
3473 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3474 return EMULATE_FAIL;
3475 break;
3476 case 0x05: /* syscall */
3477 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3478 return EMULATE_FAIL;
3479 break;
3480 default:
3481 return EMULATE_FAIL;
3482 }
3483
3484 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3485 return EMULATE_FAIL;
3486 }
571008da 3487
f2b5756b 3488 ++vcpu->stat.insn_emulation;
bbd9b64e 3489 if (r) {
f2b5756b 3490 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 3491 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3492 return EMULATE_DONE;
3493 return EMULATE_FAIL;
3494 }
3495 }
3496
ba8afb6b
GN		 3497 if (emulation_type & EMULTYPE_SKIP) {
3498 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3499 return EMULATE_DONE;
3500 }
3501
ad312c7c 3502 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 3503 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3504
3505 if (r == 0)
3506 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 3507
ad312c7c 3508 if (vcpu->arch.pio.string)
bbd9b64e
CO		 3509 return EMULATE_DO_MMIO;
3510
112592da 3511 if (r || vcpu->mmio_is_write) {
bbd9b64e
CO		 3512 run->exit_reason = KVM_EXIT_MMIO;
3513 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3514 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3515 run->mmio.len = vcpu->mmio_size;
3516 run->mmio.is_write = vcpu->mmio_is_write;
3517 }
3518
3519 if (r) {
3520 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3521 return EMULATE_DONE;
3522 if (!vcpu->mmio_needed) {
3523 kvm_report_emulation_failure(vcpu, "mmio");
3524 return EMULATE_FAIL;
3525 }
3526 return EMULATE_DO_MMIO;
3527 }
3528
91586a3b 3529 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 3530
3531 if (vcpu->mmio_is_write) {
3532 vcpu->mmio_needed = 0;
3533 return EMULATE_DO_MMIO;
3534 }
3535
3536 return EMULATE_DONE;
3537}
3538EXPORT_SYMBOL_GPL(emulate_instruction);
3539
de7d789a
CO		 3540static int pio_copy_data(struct kvm_vcpu *vcpu)
3541{
ad312c7c 3542 void *p = vcpu->arch.pio_data;
0f346074 3543 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 3544 unsigned bytes;
0f346074 3545 int ret;
1871c602 3546 u32 error_code;
de7d789a 3547
ad312c7c
ZX		 3548 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
3549 if (vcpu->arch.pio.in)
1871c602 3550 ret = kvm_write_guest_virt(q, p, bytes, vcpu, &error_code);
de7d789a 3551 else
1871c602
GN		 3552 ret = kvm_read_guest_virt(q, p, bytes, vcpu, &error_code);
3553
3554 if (ret == X86EMUL_PROPAGATE_FAULT)
3555 kvm_inject_page_fault(vcpu, q, error_code);
3556
0f346074 3557 return ret;
de7d789a
CO		 3558}
3559
3560int complete_pio(struct kvm_vcpu *vcpu)
3561{
ad312c7c 3562 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 3563 long delta;
3564 int r;
5fdbf976 3565 unsigned long val;
de7d789a
CO		 3566
3567 if (!io->string) {
5fdbf976
MT		 3568 if (io->in) {
3569 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3570 memcpy(&val, vcpu->arch.pio_data, io->size);
3571 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
3572 }
de7d789a
CO		 3573 } else {
3574 if (io->in) {
3575 r = pio_copy_data(vcpu);
5fdbf976 3576 if (r)
1871c602 3577 goto out;
de7d789a
CO		 3578 }
3579
3580 delta = 1;
3581 if (io->rep) {
3582 delta *= io->cur_count;
3583 /*
3584 * The size of the register should really depend on
3585 * current address size.
3586 */
5fdbf976
MT		 3587 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
3588 val -= delta;
3589 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 3590 }
3591 if (io->down)
3592 delta = -delta;
3593 delta *= io->size;
5fdbf976
MT		 3594 if (io->in) {
3595 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
3596 val += delta;
3597 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
3598 } else {
3599 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
3600 val += delta;
3601 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
3602 }
de7d789a 3603 }
1871c602 3604out:
de7d789a
CO		 3605 io->count -= io->cur_count;
3606 io->cur_count = 0;
3607
3608 return 0;
3609}
3610
bda9020e 3611static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 3612{
3613 /* TODO: String I/O for in kernel device */
bda9020e 3614 int r;
de7d789a 3615
ad312c7c 3616 if (vcpu->arch.pio.in)
e93f8a0f 3617 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
bda9020e 3618 vcpu->arch.pio.size, pd);
de7d789a 3619 else
e93f8a0f
MT		 3620 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3621 vcpu->arch.pio.port, vcpu->arch.pio.size,
3622 pd);
bda9020e 3623 return r;
de7d789a
CO		 3624}
3625
bda9020e 3626static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 3627{
ad312c7c
ZX		 3628 struct kvm_pio_request *io = &vcpu->arch.pio;
3629 void *pd = vcpu->arch.pio_data;
bda9020e 3630 int i, r = 0;
de7d789a 3631
de7d789a 3632 for (i = 0; i < io->cur_count; i++) {
e93f8a0f 3633 if (kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
bda9020e
MT		 3634 io->port, io->size, pd)) {
3635 r = -EOPNOTSUPP;
3636 break;
3637 }
de7d789a
CO		 3638 pd += io->size;
3639 }
bda9020e 3640 return r;
de7d789a
CO		 3641}
3642
851ba692 3643int kvm_emulate_pio(struct kvm_vcpu *vcpu, int in, int size, unsigned port)
de7d789a 3644{
5fdbf976 3645 unsigned long val;
de7d789a 3646
f850e2e6
GN		 3647 trace_kvm_pio(!in, port, size, 1);
3648
de7d789a
CO		 3649 vcpu->run->exit_reason = KVM_EXIT_IO;
3650 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3651 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3652 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3653 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
3654 vcpu->run->io.port = vcpu->arch.pio.port = port;
3655 vcpu->arch.pio.in = in;
3656 vcpu->arch.pio.string = 0;
3657 vcpu->arch.pio.down = 0;
ad312c7c 3658 vcpu->arch.pio.rep = 0;
de7d789a 3659
1976d2d2
TY		 3660 if (!vcpu->arch.pio.in) {
3661 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3662 memcpy(vcpu->arch.pio_data, &val, 4);
3663 }
de7d789a 3664
bda9020e 3665 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 3666 complete_pio(vcpu);
3667 return 1;
3668 }
3669 return 0;
3670}
3671EXPORT_SYMBOL_GPL(kvm_emulate_pio);
3672
851ba692 3673int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, int in,
de7d789a
CO		 3674 int size, unsigned long count, int down,
3675 gva_t address, int rep, unsigned port)
3676{
3677 unsigned now, in_page;
0f346074 3678 int ret = 0;
de7d789a 3679
f850e2e6
GN		 3680 trace_kvm_pio(!in, port, size, count);
3681
de7d789a
CO		 3682 vcpu->run->exit_reason = KVM_EXIT_IO;
3683 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3684 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3685 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3686 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
3687 vcpu->run->io.port = vcpu->arch.pio.port = port;
3688 vcpu->arch.pio.in = in;
3689 vcpu->arch.pio.string = 1;
3690 vcpu->arch.pio.down = down;
ad312c7c 3691 vcpu->arch.pio.rep = rep;
de7d789a
CO		 3692
3693 if (!count) {
3694 kvm_x86_ops->skip_emulated_instruction(vcpu);
3695 return 1;
3696 }
3697
3698 if (!down)
3699 in_page = PAGE_SIZE - offset_in_page(address);
3700 else
3701 in_page = offset_in_page(address) + size;
3702 now = min(count, (unsigned long)in_page / size);
0f346074 3703 if (!now)
de7d789a 3704 now = 1;
de7d789a
CO		 3705 if (down) {
3706 /*
3707 * String I/O in reverse. Yuck. Kill the guest, fix later.
3708 */
3709 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 3710 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 3711 return 1;
3712 }
3713 vcpu->run->io.count = now;
ad312c7c 3714 vcpu->arch.pio.cur_count = now;
de7d789a 3715
ad312c7c 3716 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 3717 kvm_x86_ops->skip_emulated_instruction(vcpu);
3718
0f346074 3719 vcpu->arch.pio.guest_gva = address;
de7d789a 3720
ad312c7c 3721 if (!vcpu->arch.pio.in) {
de7d789a
CO		 3722 /* string PIO write */
3723 ret = pio_copy_data(vcpu);
1871c602 3724 if (ret == X86EMUL_PROPAGATE_FAULT)
0f346074 3725 return 1;
bda9020e 3726 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 3727 complete_pio(vcpu);
ad312c7c 3728 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 3729 ret = 1;
3730 }
bda9020e
MT		 3731 }
3732 /* no string PIO read support yet */
de7d789a
CO		 3733
3734 return ret;
3735}
3736EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3737
c8076604
GH		 3738static void bounce_off(void *info)
3739{
3740 /* nothing */
3741}
3742
c8076604
GH		 3743static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3744 void *data)
3745{
3746 struct cpufreq_freqs *freq = data;
3747 struct kvm *kvm;
3748 struct kvm_vcpu *vcpu;
3749 int i, send_ipi = 0;
3750
c8076604
GH		 3751 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3752 return 0;
3753 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3754 return 0;
0cca7907 3755 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3756
3757 spin_lock(&kvm_lock);
3758 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3759 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3760 if (vcpu->cpu != freq->cpu)
3761 continue;
3762 if (!kvm_request_guest_time_update(vcpu))
3763 continue;
3764 if (vcpu->cpu != smp_processor_id())
3765 send_ipi++;
3766 }
3767 }
3768 spin_unlock(&kvm_lock);
3769
3770 if (freq->old < freq->new && send_ipi) {
3771 /*
3772 * We upscale the frequency. Must make the guest
3773 * doesn't see old kvmclock values while running with
3774 * the new frequency, otherwise we risk the guest sees
3775 * time go backwards.
3776 *
3777 * In case we update the frequency for another cpu
3778 * (which might be in guest context) send an interrupt
3779 * to kick the cpu out of guest context. Next time
3780 * guest context is entered kvmclock will be updated,
3781 * so the guest will not see stale values.
3782 */
3783 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3784 }
3785 return 0;
3786}
3787
3788static struct notifier_block kvmclock_cpufreq_notifier_block = {
3789 .notifier_call = kvmclock_cpufreq_notifier
3790};
3791
b820cc0c
ZA		 3792static void kvm_timer_init(void)
3793{
3794 int cpu;
3795
b820cc0c 3796 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 3797 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3798 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 3799 for_each_online_cpu(cpu) {
3800 unsigned long khz = cpufreq_get(cpu);
3801 if (!khz)
3802 khz = tsc_khz;
3803 per_cpu(cpu_tsc_khz, cpu) = khz;
3804 }
0cca7907
ZA		 3805 } else {
3806 for_each_possible_cpu(cpu)
3807 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 3808 }
3809}
3810
f8c16bba 3811int kvm_arch_init(void *opaque)
043405e1 3812{
b820cc0c 3813 int r;
f8c16bba
ZX		 3814 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3815
f8c16bba
ZX		 3816 if (kvm_x86_ops) {
3817 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3818 r = -EEXIST;
3819 goto out;
f8c16bba
ZX		 3820 }
3821
3822 if (!ops->cpu_has_kvm_support()) {
3823 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3824 r = -EOPNOTSUPP;
3825 goto out;
f8c16bba
ZX		 3826 }
3827 if (ops->disabled_by_bios()) {
3828 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3829 r = -EOPNOTSUPP;
3830 goto out;
f8c16bba
ZX		 3831 }
3832
97db56ce
AK		 3833 r = kvm_mmu_module_init();
3834 if (r)
3835 goto out;
3836
3837 kvm_init_msr_list();
3838
f8c16bba 3839 kvm_x86_ops = ops;
56c6d28a 3840 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3841 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3842 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3843 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 3844
b820cc0c 3845 kvm_timer_init();
c8076604 3846
f8c16bba 3847 return 0;
56c6d28a
ZX		 3848
3849out:
56c6d28a 3850 return r;
043405e1 3851}
8776e519 3852
f8c16bba
ZX		 3853void kvm_arch_exit(void)
3854{
888d256e
JK		 3855 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3856 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3857 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3858 kvm_x86_ops = NULL;
56c6d28a
ZX		 3859 kvm_mmu_module_exit();
3860}
f8c16bba 3861
8776e519
HB		 3862int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3863{
3864 ++vcpu->stat.halt_exits;
3865 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3866 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3867 return 1;
3868 } else {
3869 vcpu->run->exit_reason = KVM_EXIT_HLT;
3870 return 0;
3871 }
3872}
3873EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3874
2f333bcb
MT		 3875static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3876 unsigned long a1)
3877{
3878 if (is_long_mode(vcpu))
3879 return a0;
3880 else
3881 return a0 | ((gpa_t)a1 << 32);
3882}
3883
55cd8e5a
GN		 3884int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
3885{
3886 u64 param, ingpa, outgpa, ret;
3887 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
3888 bool fast, longmode;
3889 int cs_db, cs_l;
3890
3891 /*
3892 * hypercall generates UD from non zero cpl and real mode
3893 * per HYPER-V spec
3894 */
3eeb3288 3895 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 3896 kvm_queue_exception(vcpu, UD_VECTOR);
3897 return 0;
3898 }
3899
3900 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3901 longmode = is_long_mode(vcpu) && cs_l == 1;
3902
3903 if (!longmode) {
ccd46936
GN		 3904 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
3905 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
3906 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
3907 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
3908 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
3909 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 3910 }
3911#ifdef CONFIG_X86_64
3912 else {
3913 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
3914 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
3915 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
3916 }
3917#endif
3918
3919 code = param & 0xffff;
3920 fast = (param >> 16) & 0x1;
3921 rep_cnt = (param >> 32) & 0xfff;
3922 rep_idx = (param >> 48) & 0xfff;
3923
3924 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
3925
c25bc163
GN		 3926 switch (code) {
3927 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
3928 kvm_vcpu_on_spin(vcpu);
3929 break;
3930 default:
3931 res = HV_STATUS_INVALID_HYPERCALL_CODE;
3932 break;
3933 }
55cd8e5a
GN		 3934
3935 ret = res | (((u64)rep_done & 0xfff) << 32);
3936 if (longmode) {
3937 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
3938 } else {
3939 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
3940 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
3941 }
3942
3943 return 1;
3944}
3945
8776e519
HB		 3946int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3947{
3948 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3949 int r = 1;
8776e519 3950
55cd8e5a
GN		 3951 if (kvm_hv_hypercall_enabled(vcpu->kvm))
3952 return kvm_hv_hypercall(vcpu);
3953
5fdbf976
MT		 3954 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3955 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3956 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3957 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3958 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3959
229456fc 3960 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3961
8776e519
HB		 3962 if (!is_long_mode(vcpu)) {
3963 nr &= 0xFFFFFFFF;
3964 a0 &= 0xFFFFFFFF;
3965 a1 &= 0xFFFFFFFF;
3966 a2 &= 0xFFFFFFFF;
3967 a3 &= 0xFFFFFFFF;
3968 }
3969
07708c4a
JK		 3970 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
3971 ret = -KVM_EPERM;
3972 goto out;
3973 }
3974
8776e519 3975 switch (nr) {
b93463aa
AK		 3976 case KVM_HC_VAPIC_POLL_IRQ:
3977 ret = 0;
3978 break;
2f333bcb
MT		 3979 case KVM_HC_MMU_OP:
3980 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3981 break;
8776e519
HB		 3982 default:
3983 ret = -KVM_ENOSYS;
3984 break;
3985 }
07708c4a 3986out:
5fdbf976 3987 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3988 ++vcpu->stat.hypercalls;
2f333bcb 3989 return r;
8776e519
HB		 3990}
3991EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3992
3993int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3994{
3995 char instruction[3];
5fdbf976 3996 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3997
8776e519
HB		 3998 /*
3999 * Blow out the MMU to ensure that no other VCPU has an active mapping
4000 * to ensure that the updated hypercall appears atomically across all
4001 * VCPUs.
4002 */
4003 kvm_mmu_zap_all(vcpu->kvm);
4004
8776e519 4005 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4006
7edcface 4007 return emulator_write_emulated(rip, instruction, 3, vcpu);
8776e519
HB		 4008}
4009
4010static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4011{
4012 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4013}
4014
4015void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4016{
89a27f4d 4017 struct desc_ptr dt = { limit, base };
8776e519
HB		 4018
4019 kvm_x86_ops->set_gdt(vcpu, &dt);
4020}
4021
4022void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4023{
89a27f4d 4024 struct desc_ptr dt = { limit, base };
8776e519
HB		 4025
4026 kvm_x86_ops->set_idt(vcpu, &dt);
4027}
4028
4029void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
4030 unsigned long *rflags)
4031{
2d3ad1f4 4032 kvm_lmsw(vcpu, msw);
91586a3b 4033 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 4034}
4035
4036unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
4037{
54e445ca
JR		 4038 unsigned long value;
4039
8776e519
HB		 4040 switch (cr) {
4041 case 0:
4d4ec087 4042 value = kvm_read_cr0(vcpu);
54e445ca 4043 break;
8776e519 4044 case 2:
54e445ca
JR		 4045 value = vcpu->arch.cr2;
4046 break;
8776e519 4047 case 3:
54e445ca
JR		 4048 value = vcpu->arch.cr3;
4049 break;
8776e519 4050 case 4:
fc78f519 4051 value = kvm_read_cr4(vcpu);
54e445ca 4052 break;
152ff9be 4053 case 8:
54e445ca
JR		 4054 value = kvm_get_cr8(vcpu);
4055 break;
8776e519 4056 default:
b8688d51 4057 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 4058 return 0;
4059 }
54e445ca
JR		 4060
4061 return value;
8776e519
HB		 4062}
4063
4064void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
4065 unsigned long *rflags)
4066{
4067 switch (cr) {
4068 case 0:
4d4ec087 4069 kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
91586a3b 4070 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 4071 break;
4072 case 2:
ad312c7c 4073 vcpu->arch.cr2 = val;
8776e519
HB		 4074 break;
4075 case 3:
2d3ad1f4 4076 kvm_set_cr3(vcpu, val);
8776e519
HB		 4077 break;
4078 case 4:
fc78f519 4079 kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
8776e519 4080 break;
152ff9be 4081 case 8:
2d3ad1f4 4082 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 4083 break;
8776e519 4084 default:
b8688d51 4085 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 4086 }
4087}
4088
07716717
DK		 4089static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4090{
ad312c7c
ZX		 4091 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4092 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4093
4094 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4095 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4096 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4097 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4098 if (ej->function == e->function) {
4099 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4100 return j;
4101 }
4102 }
4103 return 0; /* silence gcc, even though control never reaches here */
4104}
4105
4106/* find an entry with matching function, matching index (if needed), and that
4107 * should be read next (if it's stateful) */
4108static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4109 u32 function, u32 index)
4110{
4111 if (e->function != function)
4112 return 0;
4113 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4114 return 0;
4115 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4116 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4117 return 0;
4118 return 1;
4119}
4120
d8017474
AG		 4121struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4122 u32 function, u32 index)
8776e519
HB		 4123{
4124 int i;
d8017474 4125 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4126
ad312c7c 4127 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4128 struct kvm_cpuid_entry2 *e;
4129
ad312c7c 4130 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4131 if (is_matching_cpuid_entry(e, function, index)) {
4132 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4133 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4134 best = e;
4135 break;
4136 }
4137 /*
4138 * Both basic or both extended?
4139 */
4140 if (((e->function ^ function) & 0x80000000) == 0)
4141 if (!best || e->function > best->function)
4142 best = e;
4143 }
d8017474
AG		 4144 return best;
4145}
0e851880 4146EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4147
82725b20
DE		 4148int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4149{
4150 struct kvm_cpuid_entry2 *best;
4151
4152 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4153 if (best)
4154 return best->eax & 0xff;
4155 return 36;
4156}
4157
d8017474
AG		 4158void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4159{
4160 u32 function, index;
4161 struct kvm_cpuid_entry2 *best;
4162
4163 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4164 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4165 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4166 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4167 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4168 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4169 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4170 if (best) {
5fdbf976
MT		 4171 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4172 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4173 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4174 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4175 }
8776e519 4176 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4177 trace_kvm_cpuid(function,
4178 kvm_register_read(vcpu, VCPU_REGS_RAX),
4179 kvm_register_read(vcpu, VCPU_REGS_RBX),
4180 kvm_register_read(vcpu, VCPU_REGS_RCX),
4181 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4182}
4183EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4184
b6c7a5dc
HB		 4185/*
4186 * Check if userspace requested an interrupt window, and that the
4187 * interrupt window is open.
4188 *
4189 * No need to exit to userspace if we already have an interrupt queued.
4190 */
851ba692 4191static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4192{
8061823a 4193 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4194 vcpu->run->request_interrupt_window &&
5df56646 4195 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4196}
4197
851ba692 4198static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4199{
851ba692
AK		 4200 struct kvm_run *kvm_run = vcpu->run;
4201
91586a3b 4202 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4203 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4204 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4205 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4206 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4207 else
b6c7a5dc 4208 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4209 kvm_arch_interrupt_allowed(vcpu) &&
4210 !kvm_cpu_has_interrupt(vcpu) &&
4211 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4212}
4213
b93463aa
AK		 4214static void vapic_enter(struct kvm_vcpu *vcpu)
4215{
4216 struct kvm_lapic *apic = vcpu->arch.apic;
4217 struct page *page;
4218
4219 if (!apic || !apic->vapic_addr)
4220 return;
4221
4222 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4223
4224 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4225}
4226
4227static void vapic_exit(struct kvm_vcpu *vcpu)
4228{
4229 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4230 int idx;
b93463aa
AK		 4231
4232 if (!apic || !apic->vapic_addr)
4233 return;
4234
f656ce01 4235 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4236 kvm_release_page_dirty(apic->vapic_page);
4237 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4238 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4239}
4240
95ba8273
GN		 4241static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4242{
4243 int max_irr, tpr;
4244
4245 if (!kvm_x86_ops->update_cr8_intercept)
4246 return;
4247
88c808fd
AK		 4248 if (!vcpu->arch.apic)
4249 return;
4250
8db3baa2
GN		 4251 if (!vcpu->arch.apic->vapic_addr)
4252 max_irr = kvm_lapic_find_highest_irr(vcpu);
4253 else
4254 max_irr = -1;
95ba8273
GN		 4255
4256 if (max_irr != -1)
4257 max_irr >>= 4;
4258
4259 tpr = kvm_lapic_get_cr8(vcpu);
4260
4261 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4262}
4263
851ba692 4264static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4265{
4266 /* try to reinject previous events if any */
b59bb7bd
GN		 4267 if (vcpu->arch.exception.pending) {
4268 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4269 vcpu->arch.exception.has_error_code,
4270 vcpu->arch.exception.error_code);
4271 return;
4272 }
4273
95ba8273
GN		 4274 if (vcpu->arch.nmi_injected) {
4275 kvm_x86_ops->set_nmi(vcpu);
4276 return;
4277 }
4278
4279 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4280 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4281 return;
4282 }
4283
4284 /* try to inject new event if pending */
4285 if (vcpu->arch.nmi_pending) {
4286 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4287 vcpu->arch.nmi_pending = false;
4288 vcpu->arch.nmi_injected = true;
4289 kvm_x86_ops->set_nmi(vcpu);
4290 }
4291 } else if (kvm_cpu_has_interrupt(vcpu)) {
4292 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4293 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4294 false);
4295 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4296 }
4297 }
4298}
4299
851ba692 4300static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4301{
4302 int r;
6a8b1d13 4303 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4304 vcpu->run->request_interrupt_window;
b6c7a5dc 4305
2e53d63a
MT		 4306 if (vcpu->requests)
4307 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
4308 kvm_mmu_unload(vcpu);
4309
b6c7a5dc
HB		 4310 r = kvm_mmu_reload(vcpu);
4311 if (unlikely(r))
4312 goto out;
4313
2f52d58c
AK		 4314 if (vcpu->requests) {
4315 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 4316 __kvm_migrate_timers(vcpu);
c8076604
GH		 4317 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
4318 kvm_write_guest_time(vcpu);
4731d4c7
MT		 4319 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
4320 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 4321 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
4322 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 4323 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
4324 &vcpu->requests)) {
851ba692 4325 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4326 r = 0;
4327 goto out;
4328 }
71c4dfaf 4329 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4330 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4331 r = 0;
4332 goto out;
4333 }
02daab21
AK		 4334 if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
4335 vcpu->fpu_active = 0;
4336 kvm_x86_ops->fpu_deactivate(vcpu);
4337 }
2f52d58c 4338 }
b93463aa 4339
b6c7a5dc
HB		 4340 preempt_disable();
4341
4342 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4343 if (vcpu->fpu_active)
4344 kvm_load_guest_fpu(vcpu);
b6c7a5dc
HB		 4345
4346 local_irq_disable();
4347
32f88400
MT		 4348 clear_bit(KVM_REQ_KICK, &vcpu->requests);
4349 smp_mb__after_clear_bit();
4350
d7690175 4351 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 4352 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 4353 local_irq_enable();
4354 preempt_enable();
4355 r = 1;
4356 goto out;
4357 }
4358
851ba692 4359 inject_pending_event(vcpu);
b6c7a5dc 4360
6a8b1d13
GN		 4361 /* enable NMI/IRQ window open exits if needed */
4362 if (vcpu->arch.nmi_pending)
4363 kvm_x86_ops->enable_nmi_window(vcpu);
4364 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4365 kvm_x86_ops->enable_irq_window(vcpu);
4366
95ba8273 4367 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4368 update_cr8_intercept(vcpu);
4369 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4370 }
b93463aa 4371
f656ce01 4372 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4373
b6c7a5dc
HB		 4374 kvm_guest_enter();
4375
42dbaa5a 4376 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4377 set_debugreg(0, 7);
4378 set_debugreg(vcpu->arch.eff_db[0], 0);
4379 set_debugreg(vcpu->arch.eff_db[1], 1);
4380 set_debugreg(vcpu->arch.eff_db[2], 2);
4381 set_debugreg(vcpu->arch.eff_db[3], 3);
4382 }
b6c7a5dc 4383
229456fc 4384 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4385 kvm_x86_ops->run(vcpu);
b6c7a5dc 4386
24f1e32c
FW		 4387 /*
4388 * If the guest has used debug registers, at least dr7
4389 * will be disabled while returning to the host.
4390 * If we don't have active breakpoints in the host, we don't
4391 * care about the messed up debug address registers. But if
4392 * we have some of them active, restore the old state.
4393 */
59d8eb53 4394 if (hw_breakpoint_active())
24f1e32c 4395 hw_breakpoint_restore();
42dbaa5a 4396
32f88400 4397 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 4398 local_irq_enable();
4399
4400 ++vcpu->stat.exits;
4401
4402 /*
4403 * We must have an instruction between local_irq_enable() and
4404 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4405 * the interrupt shadow. The stat.exits increment will do nicely.
4406 * But we need to prevent reordering, hence this barrier():
4407 */
4408 barrier();
4409
4410 kvm_guest_exit();
4411
4412 preempt_enable();
4413
f656ce01 4414 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4415
b6c7a5dc
HB		 4416 /*
4417 * Profile KVM exit RIPs:
4418 */
4419 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4420 unsigned long rip = kvm_rip_read(vcpu);
4421 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4422 }
4423
298101da 4424
b93463aa
AK		 4425 kvm_lapic_sync_from_vapic(vcpu);
4426
851ba692 4427 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4428out:
4429 return r;
4430}
b6c7a5dc 4431
09cec754 4432
851ba692 4433static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4434{
4435 int r;
f656ce01 4436 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4437
4438 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4439 pr_debug("vcpu %d received sipi with vector # %x\n",
4440 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4441 kvm_lapic_reset(vcpu);
5f179287 4442 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4443 if (r)
4444 return r;
4445 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4446 }
4447
f656ce01 4448 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4449 vapic_enter(vcpu);
4450
4451 r = 1;
4452 while (r > 0) {
af2152f5 4453 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4454 r = vcpu_enter_guest(vcpu);
d7690175 4455 else {
f656ce01 4456 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4457 kvm_vcpu_block(vcpu);
f656ce01 4458 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4459 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4460 {
4461 switch(vcpu->arch.mp_state) {
4462 case KVM_MP_STATE_HALTED:
d7690175 4463 vcpu->arch.mp_state =
09cec754
GN		 4464 KVM_MP_STATE_RUNNABLE;
4465 case KVM_MP_STATE_RUNNABLE:
4466 break;
4467 case KVM_MP_STATE_SIPI_RECEIVED:
4468 default:
4469 r = -EINTR;
4470 break;
4471 }
4472 }
d7690175
MT		 4473 }
4474
09cec754
GN		 4475 if (r <= 0)
4476 break;
4477
4478 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4479 if (kvm_cpu_has_pending_timer(vcpu))
4480 kvm_inject_pending_timer_irqs(vcpu);
4481
851ba692 4482 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4483 r = -EINTR;
851ba692 4484 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4485 ++vcpu->stat.request_irq_exits;
4486 }
4487 if (signal_pending(current)) {
4488 r = -EINTR;
851ba692 4489 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4490 ++vcpu->stat.signal_exits;
4491 }
4492 if (need_resched()) {
f656ce01 4493 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4494 kvm_resched(vcpu);
f656ce01 4495 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4496 }
b6c7a5dc
HB		 4497 }
4498
f656ce01 4499 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
851ba692 4500 post_kvm_run_save(vcpu);
b6c7a5dc 4501
b93463aa
AK		 4502 vapic_exit(vcpu);
4503
b6c7a5dc
HB		 4504 return r;
4505}
4506
4507int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4508{
4509 int r;
4510 sigset_t sigsaved;
4511
4512 vcpu_load(vcpu);
4513
ac9f6dc0
AK		 4514 if (vcpu->sigset_active)
4515 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4516
a4535290 4517 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4518 kvm_vcpu_block(vcpu);
d7690175 4519 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4520 r = -EAGAIN;
4521 goto out;
b6c7a5dc
HB		 4522 }
4523
b6c7a5dc
HB		 4524 /* re-sync apic's tpr */
4525 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4526 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4527
ad312c7c 4528 if (vcpu->arch.pio.cur_count) {
7567cae1 4529 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
b6c7a5dc 4530 r = complete_pio(vcpu);
7567cae1 4531 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 4532 if (r)
4533 goto out;
4534 }
b6c7a5dc
HB		 4535 if (vcpu->mmio_needed) {
4536 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4537 vcpu->mmio_read_completed = 1;
4538 vcpu->mmio_needed = 0;
3200f405 4539
f656ce01 4540 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
851ba692 4541 r = emulate_instruction(vcpu, vcpu->arch.mmio_fault_cr2, 0,
571008da 4542 EMULTYPE_NO_DECODE);
f656ce01 4543 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 4544 if (r == EMULATE_DO_MMIO) {
4545 /*
4546 * Read-modify-write. Back to userspace.
4547 */
4548 r = 0;
4549 goto out;
4550 }
4551 }
5fdbf976
MT		 4552 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4553 kvm_register_write(vcpu, VCPU_REGS_RAX,
4554 kvm_run->hypercall.ret);
b6c7a5dc 4555
851ba692 4556 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4557
4558out:
4559 if (vcpu->sigset_active)
4560 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4561
4562 vcpu_put(vcpu);
4563 return r;
4564}
4565
4566int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4567{
4568 vcpu_load(vcpu);
4569
5fdbf976
MT		 4570 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4571 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4572 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4573 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4574 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4575 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4576 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4577 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4578#ifdef CONFIG_X86_64
5fdbf976
MT		 4579 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4580 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4581 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4582 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4583 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4584 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4585 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4586 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4587#endif
4588
5fdbf976 4589 regs->rip = kvm_rip_read(vcpu);
91586a3b 4590 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4591
4592 vcpu_put(vcpu);
4593
4594 return 0;
4595}
4596
4597int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4598{
4599 vcpu_load(vcpu);
4600
5fdbf976
MT		 4601 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4602 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4603 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4604 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4605 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4606 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4607 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4608 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4609#ifdef CONFIG_X86_64
5fdbf976
MT		 4610 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4611 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4612 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4613 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4614 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4615 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4616 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4617 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4618#endif
4619
5fdbf976 4620 kvm_rip_write(vcpu, regs->rip);
91586a3b 4621 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4622
b4f14abd
JK		 4623 vcpu->arch.exception.pending = false;
4624
b6c7a5dc
HB		 4625 vcpu_put(vcpu);
4626
4627 return 0;
4628}
4629
3e6e0aab
GT		 4630void kvm_get_segment(struct kvm_vcpu *vcpu,
4631 struct kvm_segment *var, int seg)
b6c7a5dc 4632{
14af3f3c 4633 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 4634}
4635
4636void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4637{
4638 struct kvm_segment cs;
4639
3e6e0aab 4640 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4641 *db = cs.db;
4642 *l = cs.l;
4643}
4644EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4645
4646int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4647 struct kvm_sregs *sregs)
4648{
89a27f4d 4649 struct desc_ptr dt;
b6c7a5dc
HB		 4650
4651 vcpu_load(vcpu);
4652
3e6e0aab
GT		 4653 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4654 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4655 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4656 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4657 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4658 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4659
3e6e0aab
GT		 4660 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4661 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4662
4663 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 4664 sregs->idt.limit = dt.size;
4665 sregs->idt.base = dt.address;
b6c7a5dc 4666 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 4667 sregs->gdt.limit = dt.size;
4668 sregs->gdt.base = dt.address;
b6c7a5dc 4669
4d4ec087 4670 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4671 sregs->cr2 = vcpu->arch.cr2;
4672 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4673 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4674 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 4675 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 4676 sregs->apic_base = kvm_get_apic_base(vcpu);
4677
923c61bb 4678 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4679
36752c9b 4680 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4681 set_bit(vcpu->arch.interrupt.nr,
4682 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4683
b6c7a5dc
HB		 4684 vcpu_put(vcpu);
4685
4686 return 0;
4687}
4688
62d9f0db
MT		 4689int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4690 struct kvm_mp_state *mp_state)
4691{
4692 vcpu_load(vcpu);
4693 mp_state->mp_state = vcpu->arch.mp_state;
4694 vcpu_put(vcpu);
4695 return 0;
4696}
4697
4698int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4699 struct kvm_mp_state *mp_state)
4700{
4701 vcpu_load(vcpu);
4702 vcpu->arch.mp_state = mp_state->mp_state;
4703 vcpu_put(vcpu);
4704 return 0;
4705}
4706
3e6e0aab 4707static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 4708 struct kvm_segment *var, int seg)
4709{
14af3f3c 4710 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 4711}
4712
37817f29
IE		 4713static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
4714 struct kvm_segment *kvm_desct)
4715{
46a359e7
AM		 4716 kvm_desct->base = get_desc_base(seg_desc);
4717 kvm_desct->limit = get_desc_limit(seg_desc);
c93cd3a5
MT		 4718 if (seg_desc->g) {
4719 kvm_desct->limit <<= 12;
4720 kvm_desct->limit |= 0xfff;
4721 }
37817f29
IE		 4722 kvm_desct->selector = selector;
4723 kvm_desct->type = seg_desc->type;
4724 kvm_desct->present = seg_desc->p;
4725 kvm_desct->dpl = seg_desc->dpl;
4726 kvm_desct->db = seg_desc->d;
4727 kvm_desct->s = seg_desc->s;
4728 kvm_desct->l = seg_desc->l;
4729 kvm_desct->g = seg_desc->g;
4730 kvm_desct->avl = seg_desc->avl;
4731 if (!selector)
4732 kvm_desct->unusable = 1;
4733 else
4734 kvm_desct->unusable = 0;
4735 kvm_desct->padding = 0;
4736}
4737
b8222ad2
AS		 4738static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
4739 u16 selector,
89a27f4d 4740 struct desc_ptr *dtable)
37817f29
IE		 4741{
4742 if (selector & 1 << 2) {
4743 struct kvm_segment kvm_seg;
4744
3e6e0aab 4745 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 4746
4747 if (kvm_seg.unusable)
89a27f4d 4748 dtable->size = 0;
37817f29 4749 else
89a27f4d
GN		 4750 dtable->size = kvm_seg.limit;
4751 dtable->address = kvm_seg.base;
37817f29
IE		 4752 }
4753 else
4754 kvm_x86_ops->get_gdt(vcpu, dtable);
4755}
4756
4757/* allowed just for 8 bytes segments */
4758static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4759 struct desc_struct *seg_desc)
4760{
89a27f4d 4761 struct desc_ptr dtable;
37817f29 4762 u16 index = selector >> 3;
6f550484
TY		 4763 int ret;
4764 u32 err;
4765 gva_t addr;
37817f29 4766
b8222ad2 4767 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29 4768
89a27f4d 4769 if (dtable.size < index * 8 + 7) {
37817f29 4770 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
c125c607 4771 return X86EMUL_PROPAGATE_FAULT;
37817f29 4772 }
6f550484
TY		 4773 addr = dtable.base + index * 8;
4774 ret = kvm_read_guest_virt_system(addr, seg_desc, sizeof(*seg_desc),
4775 vcpu, &err);
4776 if (ret == X86EMUL_PROPAGATE_FAULT)
4777 kvm_inject_page_fault(vcpu, addr, err);
4778
4779 return ret;
37817f29
IE		 4780}
4781
4782/* allowed just for 8 bytes segments */
4783static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4784 struct desc_struct *seg_desc)
4785{
89a27f4d 4786 struct desc_ptr dtable;
37817f29
IE		 4787 u16 index = selector >> 3;
4788
b8222ad2 4789 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29 4790
89a27f4d 4791 if (dtable.size < index * 8 + 7)
37817f29 4792 return 1;
89a27f4d 4793 return kvm_write_guest_virt(dtable.address + index*8, seg_desc, sizeof(*seg_desc), vcpu, NULL);
1871c602
GN		 4794}
4795
4796static gpa_t get_tss_base_addr_write(struct kvm_vcpu *vcpu,
4797 struct desc_struct *seg_desc)
4798{
4799 u32 base_addr = get_desc_base(seg_desc);
4800
4801 return kvm_mmu_gva_to_gpa_write(vcpu, base_addr, NULL);
37817f29
IE		 4802}
4803
1871c602 4804static gpa_t get_tss_base_addr_read(struct kvm_vcpu *vcpu,
37817f29
IE		 4805 struct desc_struct *seg_desc)
4806{
46a359e7 4807 u32 base_addr = get_desc_base(seg_desc);
37817f29 4808
1871c602 4809 return kvm_mmu_gva_to_gpa_read(vcpu, base_addr, NULL);
37817f29
IE		 4810}
4811
37817f29
IE		 4812static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4813{
4814 struct kvm_segment kvm_seg;
4815
3e6e0aab 4816 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4817 return kvm_seg.selector;
4818}
4819
2259e3a7 4820static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4821{
4822 struct kvm_segment segvar = {
4823 .base = selector << 4,
4824 .limit = 0xffff,
4825 .selector = selector,
4826 .type = 3,
4827 .present = 1,
4828 .dpl = 3,
4829 .db = 0,
4830 .s = 1,
4831 .l = 0,
4832 .g = 0,
4833 .avl = 0,
4834 .unusable = 0,
4835 };
4836 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
c697518a 4837 return X86EMUL_CONTINUE;
f4bbd9aa
AK		 4838}
4839
c0c7c04b
AL		 4840static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg)
4841{
4842 return (seg != VCPU_SREG_LDTR) &&
4843 (seg != VCPU_SREG_TR) &&
91586a3b 4844 (kvm_get_rflags(vcpu) & X86_EFLAGS_VM);
c0c7c04b
AL		 4845}
4846
c697518a 4847int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg)
37817f29
IE		 4848{
4849 struct kvm_segment kvm_seg;
e01c2426 4850 struct desc_struct seg_desc;
c697518a
GN		 4851 u8 dpl, rpl, cpl;
4852 unsigned err_vec = GP_VECTOR;
4853 u32 err_code = 0;
4854 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
4855 int ret;
37817f29 4856
3eeb3288 4857 if (is_vm86_segment(vcpu, seg) || !is_protmode(vcpu))
f4bbd9aa 4858 return kvm_load_realmode_segment(vcpu, selector, seg);
e01c2426 4859
c697518a
GN		 4860 /* NULL selector is not valid for TR, CS and SS */
4861 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
4862 && null_selector)
4863 goto exception;
4864
4865 /* TR should be in GDT only */
4866 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
4867 goto exception;
4868
4869 ret = load_guest_segment_descriptor(vcpu, selector, &seg_desc);
4870 if (ret)
4871 return ret;
4872
e01c2426 4873 seg_desct_to_kvm_desct(&seg_desc, selector, &kvm_seg);
cb84b55f 4874
c697518a
GN		 4875 if (null_selector) { /* for NULL selector skip all following checks */
4876 kvm_seg.unusable = 1;
4877 goto load;
4878 }
37817f29 4879
c697518a
GN		 4880 err_code = selector & 0xfffc;
4881 err_vec = GP_VECTOR;
37817f29 4882
c697518a
GN		 4883 /* can't load system descriptor into segment selecor */
4884 if (seg <= VCPU_SREG_GS && !kvm_seg.s)
4885 goto exception;
4886
4887 if (!kvm_seg.present) {
4888 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
4889 goto exception;
4890 }
4891
4892 rpl = selector & 3;
4893 dpl = kvm_seg.dpl;
4894 cpl = kvm_x86_ops->get_cpl(vcpu);
4895
4896 switch (seg) {
4897 case VCPU_SREG_SS:
4898 /*
4899 * segment is not a writable data segment or segment
4900 * selector's RPL != CPL or segment selector's RPL != CPL
4901 */
4902 if (rpl != cpl || (kvm_seg.type & 0xa) != 0x2 || dpl != cpl)
4903 goto exception;
4904 break;
4905 case VCPU_SREG_CS:
4906 if (!(kvm_seg.type & 8))
4907 goto exception;
4908
4909 if (kvm_seg.type & 4) {
4910 /* conforming */
4911 if (dpl > cpl)
4912 goto exception;
4913 } else {
4914 /* nonconforming */
4915 if (rpl > cpl || dpl != cpl)
4916 goto exception;
4917 }
4918 /* CS(RPL) <- CPL */
4919 selector = (selector & 0xfffc) | cpl;
4920 break;
4921 case VCPU_SREG_TR:
4922 if (kvm_seg.s || (kvm_seg.type != 1 && kvm_seg.type != 9))
4923 goto exception;
4924 break;
4925 case VCPU_SREG_LDTR:
4926 if (kvm_seg.s || kvm_seg.type != 2)
4927 goto exception;
4928 break;
4929 default: /* DS, ES, FS, or GS */
4930 /*
4931 * segment is not a data or readable code segment or
4932 * ((segment is a data or nonconforming code segment)
4933 * and (both RPL and CPL > DPL))
4934 */
4935 if ((kvm_seg.type & 0xa) == 0x8 ||
4936 (((kvm_seg.type & 0xc) != 0xc) && (rpl > dpl && cpl > dpl)))
4937 goto exception;
4938 break;
4939 }
4940
4941 if (!kvm_seg.unusable && kvm_seg.s) {
e01c2426 4942 /* mark segment as accessed */
c697518a 4943 kvm_seg.type |= 1;
e01c2426
GN		 4944 seg_desc.type |= 1;
4945 save_guest_segment_descriptor(vcpu, selector, &seg_desc);
4946 }
c697518a
GN		 4947load:
4948 kvm_set_segment(vcpu, &kvm_seg, seg);
4949 return X86EMUL_CONTINUE;
4950exception:
4951 kvm_queue_exception_e(vcpu, err_vec, err_code);
4952 return X86EMUL_PROPAGATE_FAULT;
37817f29
IE		 4953}
4954
4955static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4956 struct tss_segment_32 *tss)
4957{
4958 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4959 tss->eip = kvm_rip_read(vcpu);
91586a3b 4960 tss->eflags = kvm_get_rflags(vcpu);
5fdbf976
MT		 4961 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4962 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4963 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4964 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4965 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4966 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4967 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4968 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4969 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4970 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4971 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4972 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4973 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4974 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4975 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4976}
4977
c697518a
GN		 4978static void kvm_load_segment_selector(struct kvm_vcpu *vcpu, u16 sel, int seg)
4979{
4980 struct kvm_segment kvm_seg;
4981 kvm_get_segment(vcpu, &kvm_seg, seg);
4982 kvm_seg.selector = sel;
4983 kvm_set_segment(vcpu, &kvm_seg, seg);
4984}
4985
37817f29
IE		 4986static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4987 struct tss_segment_32 *tss)
4988{
4989 kvm_set_cr3(vcpu, tss->cr3);
4990
5fdbf976 4991 kvm_rip_write(vcpu, tss->eip);
91586a3b 4992 kvm_set_rflags(vcpu, tss->eflags | 2);
37817f29 4993
5fdbf976
MT		 4994 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4995 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4996 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4997 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4998 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4999 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
5000 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
5001 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 5002
c697518a
GN		 5003 /*
5004 * SDM says that segment selectors are loaded before segment
5005 * descriptors
5006 */
5007 kvm_load_segment_selector(vcpu, tss->ldt_selector, VCPU_SREG_LDTR);
5008 kvm_load_segment_selector(vcpu, tss->es, VCPU_SREG_ES);
5009 kvm_load_segment_selector(vcpu, tss->cs, VCPU_SREG_CS);
5010 kvm_load_segment_selector(vcpu, tss->ss, VCPU_SREG_SS);
5011 kvm_load_segment_selector(vcpu, tss->ds, VCPU_SREG_DS);
5012 kvm_load_segment_selector(vcpu, tss->fs, VCPU_SREG_FS);
5013 kvm_load_segment_selector(vcpu, tss->gs, VCPU_SREG_GS);
5014
5015 /*
5016 * Now load segment descriptors. If fault happenes at this stage
5017 * it is handled in a context of new task
5018 */
5019 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, VCPU_SREG_LDTR))
37817f29
IE		 5020 return 1;
5021
c697518a 5022 if (kvm_load_segment_descriptor(vcpu, tss->es, VCPU_SREG_ES))
37817f29
IE		 5023 return 1;
5024
c697518a 5025 if (kvm_load_segment_descriptor(vcpu, tss->cs, VCPU_SREG_CS))
37817f29
IE		 5026 return 1;
5027
c697518a 5028 if (kvm_load_segment_descriptor(vcpu, tss->ss, VCPU_SREG_SS))
37817f29
IE		 5029 return 1;
5030
c697518a 5031 if (kvm_load_segment_descriptor(vcpu, tss->ds, VCPU_SREG_DS))
37817f29
IE		 5032 return 1;
5033
c697518a 5034 if (kvm_load_segment_descriptor(vcpu, tss->fs, VCPU_SREG_FS))
37817f29
IE		 5035 return 1;
5036
c697518a 5037 if (kvm_load_segment_descriptor(vcpu, tss->gs, VCPU_SREG_GS))
37817f29
IE		 5038 return 1;
5039 return 0;
5040}
5041
5042static void save_state_to_tss16(struct kvm_vcpu *vcpu,
5043 struct tss_segment_16 *tss)
5044{
5fdbf976 5045 tss->ip = kvm_rip_read(vcpu);
91586a3b 5046 tss->flag = kvm_get_rflags(vcpu);
5fdbf976
MT		 5047 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5048 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5049 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5050 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5051 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5052 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5053 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
5054 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 5055
5056 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
5057 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
5058 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
5059 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
5060 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 5061}
5062
5063static int load_state_from_tss16(struct kvm_vcpu *vcpu,
5064 struct tss_segment_16 *tss)
5065{
5fdbf976 5066 kvm_rip_write(vcpu, tss->ip);
91586a3b 5067 kvm_set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 5068 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
5069 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
5070 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
5071 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
5072 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
5073 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
5074 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
5075 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 5076
c697518a
GN		 5077 /*
5078 * SDM says that segment selectors are loaded before segment
5079 * descriptors
5080 */
5081 kvm_load_segment_selector(vcpu, tss->ldt, VCPU_SREG_LDTR);
5082 kvm_load_segment_selector(vcpu, tss->es, VCPU_SREG_ES);
5083 kvm_load_segment_selector(vcpu, tss->cs, VCPU_SREG_CS);
5084 kvm_load_segment_selector(vcpu, tss->ss, VCPU_SREG_SS);
5085 kvm_load_segment_selector(vcpu, tss->ds, VCPU_SREG_DS);
5086
5087 /*
5088 * Now load segment descriptors. If fault happenes at this stage
5089 * it is handled in a context of new task
5090 */
5091 if (kvm_load_segment_descriptor(vcpu, tss->ldt, VCPU_SREG_LDTR))
37817f29
IE		 5092 return 1;
5093
c697518a 5094 if (kvm_load_segment_descriptor(vcpu, tss->es, VCPU_SREG_ES))
37817f29
IE		 5095 return 1;
5096
c697518a 5097 if (kvm_load_segment_descriptor(vcpu, tss->cs, VCPU_SREG_CS))
37817f29
IE		 5098 return 1;
5099
c697518a 5100 if (kvm_load_segment_descriptor(vcpu, tss->ss, VCPU_SREG_SS))
37817f29
IE		 5101 return 1;
5102
c697518a 5103 if (kvm_load_segment_descriptor(vcpu, tss->ds, VCPU_SREG_DS))
37817f29
IE		 5104 return 1;
5105 return 0;
5106}
5107
8b2cf73c 5108static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 5109 u16 old_tss_sel, u32 old_tss_base,
5110 struct desc_struct *nseg_desc)
37817f29
IE		 5111{
5112 struct tss_segment_16 tss_segment_16;
5113 int ret = 0;
5114
34198bf8
MT		 5115 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
5116 sizeof tss_segment_16))
37817f29
IE		 5117 goto out;
5118
5119 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 5120
34198bf8
MT		 5121 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
5122 sizeof tss_segment_16))
37817f29 5123 goto out;
34198bf8 5124
1871c602 5125 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr_read(vcpu, nseg_desc),
34198bf8
MT		 5126 &tss_segment_16, sizeof tss_segment_16))
5127 goto out;
5128
b237ac37
GN		 5129 if (old_tss_sel != 0xffff) {
5130 tss_segment_16.prev_task_link = old_tss_sel;
5131
5132 if (kvm_write_guest(vcpu->kvm,
1871c602 5133 get_tss_base_addr_write(vcpu, nseg_desc),
b237ac37
GN		 5134 &tss_segment_16.prev_task_link,
5135 sizeof tss_segment_16.prev_task_link))
5136 goto out;
5137 }
5138
37817f29
IE		 5139 if (load_state_from_tss16(vcpu, &tss_segment_16))
5140 goto out;
5141
5142 ret = 1;
5143out:
5144 return ret;
5145}
5146
8b2cf73c 5147static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 5148 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 5149 struct desc_struct *nseg_desc)
5150{
5151 struct tss_segment_32 tss_segment_32;
5152 int ret = 0;
5153
34198bf8
MT		 5154 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
5155 sizeof tss_segment_32))
37817f29
IE		 5156 goto out;
5157
5158 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 5159
34198bf8
MT		 5160 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
5161 sizeof tss_segment_32))
5162 goto out;
5163
1871c602 5164 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr_read(vcpu, nseg_desc),
34198bf8 5165 &tss_segment_32, sizeof tss_segment_32))
37817f29 5166 goto out;
34198bf8 5167
b237ac37
GN		 5168 if (old_tss_sel != 0xffff) {
5169 tss_segment_32.prev_task_link = old_tss_sel;
5170
5171 if (kvm_write_guest(vcpu->kvm,
1871c602 5172 get_tss_base_addr_write(vcpu, nseg_desc),
b237ac37
GN		 5173 &tss_segment_32.prev_task_link,
5174 sizeof tss_segment_32.prev_task_link))
5175 goto out;
5176 }
5177
37817f29
IE		 5178 if (load_state_from_tss32(vcpu, &tss_segment_32))
5179 goto out;
5180
5181 ret = 1;
5182out:
5183 return ret;
5184}
5185
5186int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
5187{
5188 struct kvm_segment tr_seg;
5189 struct desc_struct cseg_desc;
5190 struct desc_struct nseg_desc;
5191 int ret = 0;
34198bf8
MT		 5192 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
5193 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
e8861cfe 5194 u32 desc_limit;
37817f29 5195
1871c602 5196 old_tss_base = kvm_mmu_gva_to_gpa_write(vcpu, old_tss_base, NULL);
37817f29 5197
34198bf8
MT		 5198 /* FIXME: Handle errors. Failure to read either TSS or their
5199 * descriptors should generate a pagefault.
5200 */
37817f29
IE		 5201 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
5202 goto out;
5203
34198bf8 5204 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 5205 goto out;
5206
37817f29
IE		 5207 if (reason != TASK_SWITCH_IRET) {
5208 int cpl;
5209
5210 cpl = kvm_x86_ops->get_cpl(vcpu);
5211 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
5212 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
5213 return 1;
5214 }
5215 }
5216
e8861cfe
JK		 5217 desc_limit = get_desc_limit(&nseg_desc);
5218 if (!nseg_desc.p ||
5219 ((desc_limit < 0x67 && (nseg_desc.type & 8)) ||
5220 desc_limit < 0x2b)) {
37817f29
IE		 5221 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
5222 return 1;
5223 }
5224
5225 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 5226 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 5227 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 5228 }
5229
5230 if (reason == TASK_SWITCH_IRET) {
91586a3b
JK		 5231 u32 eflags = kvm_get_rflags(vcpu);
5232 kvm_set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
37817f29
IE		 5233 }
5234
b237ac37
GN		 5235 /* set back link to prev task only if NT bit is set in eflags
5236 note that old_tss_sel is not used afetr this point */
5237 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
5238 old_tss_sel = 0xffff;
5239
37817f29 5240 if (nseg_desc.type & 8)
b237ac37
GN		 5241 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
5242 old_tss_base, &nseg_desc);
37817f29 5243 else
b237ac37
GN		 5244 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
5245 old_tss_base, &nseg_desc);
37817f29
IE		 5246
5247 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
91586a3b
JK		 5248 u32 eflags = kvm_get_rflags(vcpu);
5249 kvm_set_rflags(vcpu, eflags | X86_EFLAGS_NT);
37817f29
IE		 5250 }
5251
5252 if (reason != TASK_SWITCH_IRET) {
3fe913e7 5253 nseg_desc.type |= (1 << 1);
37817f29
IE		 5254 save_guest_segment_descriptor(vcpu, tss_selector,
5255 &nseg_desc);
5256 }
5257
4d4ec087 5258 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0(vcpu) | X86_CR0_TS);
37817f29
IE		 5259 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
5260 tr_seg.type = 11;
3e6e0aab 5261 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 5262out:
37817f29
IE		 5263 return ret;
5264}
5265EXPORT_SYMBOL_GPL(kvm_task_switch);
5266
b6c7a5dc
HB		 5267int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5268 struct kvm_sregs *sregs)
5269{
5270 int mmu_reset_needed = 0;
923c61bb 5271 int pending_vec, max_bits;
89a27f4d 5272 struct desc_ptr dt;
b6c7a5dc
HB		 5273
5274 vcpu_load(vcpu);
5275
89a27f4d
GN		 5276 dt.size = sregs->idt.limit;
5277 dt.address = sregs->idt.base;
b6c7a5dc 5278 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5279 dt.size = sregs->gdt.limit;
5280 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5281 kvm_x86_ops->set_gdt(vcpu, &dt);
5282
ad312c7c
ZX		 5283 vcpu->arch.cr2 = sregs->cr2;
5284 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5285 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5286
2d3ad1f4 5287 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5288
f6801dff 5289 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5290 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5291 kvm_set_apic_base(vcpu, sregs->apic_base);
5292
4d4ec087 5293 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5294 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5295 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5296
fc78f519 5297 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5298 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5299 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 5300 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 5301 mmu_reset_needed = 1;
5302 }
b6c7a5dc
HB		 5303
5304 if (mmu_reset_needed)
5305 kvm_mmu_reset_context(vcpu);
5306
923c61bb
GN		 5307 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5308 pending_vec = find_first_bit(
5309 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5310 if (pending_vec < max_bits) {
66fd3f7f 5311 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5312 pr_debug("Set back pending irq %d\n", pending_vec);
5313 if (irqchip_in_kernel(vcpu->kvm))
5314 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5315 }
5316
3e6e0aab
GT		 5317 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5318 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5319 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5320 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5321 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5322 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5323
3e6e0aab
GT		 5324 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5325 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5326
5f0269f5
ME		 5327 update_cr8_intercept(vcpu);
5328
9c3e4aab 5329 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5330 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5331 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5332 !is_protmode(vcpu))
9c3e4aab
MT		 5333 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5334
b6c7a5dc
HB		 5335 vcpu_put(vcpu);
5336
5337 return 0;
5338}
5339
d0bfb940
JK		 5340int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5341 struct kvm_guest_debug *dbg)
b6c7a5dc 5342{
355be0b9 5343 unsigned long rflags;
ae675ef0 5344 int i, r;
b6c7a5dc
HB		 5345
5346 vcpu_load(vcpu);
5347
4f926bf2
JK		 5348 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5349 r = -EBUSY;
5350 if (vcpu->arch.exception.pending)
5351 goto unlock_out;
5352 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5353 kvm_queue_exception(vcpu, DB_VECTOR);
5354 else
5355 kvm_queue_exception(vcpu, BP_VECTOR);
5356 }
5357
91586a3b
JK		 5358 /*
5359 * Read rflags as long as potentially injected trace flags are still
5360 * filtered out.
5361 */
5362 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5363
5364 vcpu->guest_debug = dbg->control;
5365 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5366 vcpu->guest_debug = 0;
5367
5368 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5369 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5370 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5371 vcpu->arch.switch_db_regs =
5372 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5373 } else {
5374 for (i = 0; i < KVM_NR_DB_REGS; i++)
5375 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5376 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5377 }
5378
f92653ee
JK		 5379 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5380 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5381 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5382
91586a3b
JK		 5383 /*
5384 * Trigger an rflags update that will inject or remove the trace
5385 * flags.
5386 */
5387 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5388
355be0b9 5389 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5390
4f926bf2 5391 r = 0;
d0bfb940 5392
4f926bf2 5393unlock_out:
b6c7a5dc
HB		 5394 vcpu_put(vcpu);
5395
5396 return r;
5397}
5398
d0752060
HB		 5399/*
5400 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
5401 * we have asm/x86/processor.h
5402 */
5403struct fxsave {
5404 u16 cwd;
5405 u16 swd;
5406 u16 twd;
5407 u16 fop;
5408 u64 rip;
5409 u64 rdp;
5410 u32 mxcsr;
5411 u32 mxcsr_mask;
5412 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
5413#ifdef CONFIG_X86_64
5414 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
5415#else
5416 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
5417#endif
5418};
5419
8b006791
ZX		 5420/*
5421 * Translate a guest virtual address to a guest physical address.
5422 */
5423int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5424 struct kvm_translation *tr)
5425{
5426 unsigned long vaddr = tr->linear_address;
5427 gpa_t gpa;
f656ce01 5428 int idx;
8b006791
ZX		 5429
5430 vcpu_load(vcpu);
f656ce01 5431 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5432 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5433 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5434 tr->physical_address = gpa;
5435 tr->valid = gpa != UNMAPPED_GVA;
5436 tr->writeable = 1;
5437 tr->usermode = 0;
8b006791
ZX		 5438 vcpu_put(vcpu);
5439
5440 return 0;
5441}
5442
d0752060
HB		 5443int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5444{
ad312c7c 5445 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5446
5447 vcpu_load(vcpu);
5448
5449 memcpy(fpu->fpr, fxsave->st_space, 128);
5450 fpu->fcw = fxsave->cwd;
5451 fpu->fsw = fxsave->swd;
5452 fpu->ftwx = fxsave->twd;
5453 fpu->last_opcode = fxsave->fop;
5454 fpu->last_ip = fxsave->rip;
5455 fpu->last_dp = fxsave->rdp;
5456 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5457
5458 vcpu_put(vcpu);
5459
5460 return 0;
5461}
5462
5463int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5464{
ad312c7c 5465 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5466
5467 vcpu_load(vcpu);
5468
5469 memcpy(fxsave->st_space, fpu->fpr, 128);
5470 fxsave->cwd = fpu->fcw;
5471 fxsave->swd = fpu->fsw;
5472 fxsave->twd = fpu->ftwx;
5473 fxsave->fop = fpu->last_opcode;
5474 fxsave->rip = fpu->last_ip;
5475 fxsave->rdp = fpu->last_dp;
5476 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5477
5478 vcpu_put(vcpu);
5479
5480 return 0;
5481}
5482
5483void fx_init(struct kvm_vcpu *vcpu)
5484{
5485 unsigned after_mxcsr_mask;
5486
bc1a34f1
AA		 5487 /*
5488 * Touch the fpu the first time in non atomic context as if
5489 * this is the first fpu instruction the exception handler
5490 * will fire before the instruction returns and it'll have to
5491 * allocate ram with GFP_KERNEL.
5492 */
5493 if (!used_math())
d6e88aec 5494 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 5495
d0752060
HB		 5496 /* Initialize guest FPU by resetting ours and saving into guest's */
5497 preempt_disable();
d6e88aec
AK		 5498 kvm_fx_save(&vcpu->arch.host_fx_image);
5499 kvm_fx_finit();
5500 kvm_fx_save(&vcpu->arch.guest_fx_image);
5501 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 5502 preempt_enable();
5503
ad312c7c 5504 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5505 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5506 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5507 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5508 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5509}
5510EXPORT_SYMBOL_GPL(fx_init);
5511
5512void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5513{
2608d7a1 5514 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5515 return;
5516
5517 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 5518 kvm_fx_save(&vcpu->arch.host_fx_image);
5519 kvm_fx_restore(&vcpu->arch.guest_fx_image);
0c04851c 5520 trace_kvm_fpu(1);
d0752060 5521}
d0752060
HB		 5522
5523void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5524{
5525 if (!vcpu->guest_fpu_loaded)
5526 return;
5527
5528 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 5529 kvm_fx_save(&vcpu->arch.guest_fx_image);
5530 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 5531 ++vcpu->stat.fpu_reload;
02daab21 5532 set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
0c04851c 5533 trace_kvm_fpu(0);
d0752060 5534}
e9b11c17
ZX		 5535
5536void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5537{
7f1ea208
JR		 5538 if (vcpu->arch.time_page) {
5539 kvm_release_page_dirty(vcpu->arch.time_page);
5540 vcpu->arch.time_page = NULL;
5541 }
5542
e9b11c17
ZX		 5543 kvm_x86_ops->vcpu_free(vcpu);
5544}
5545
5546struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5547 unsigned int id)
5548{
26e5215f
AK		 5549 return kvm_x86_ops->vcpu_create(kvm, id);
5550}
e9b11c17 5551
26e5215f
AK		 5552int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5553{
5554 int r;
e9b11c17
ZX		 5555
5556 /* We do fxsave: this must be aligned. */
ad312c7c 5557 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5558
0bed3b56 5559 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5560 vcpu_load(vcpu);
5561 r = kvm_arch_vcpu_reset(vcpu);
5562 if (r == 0)
5563 r = kvm_mmu_setup(vcpu);
5564 vcpu_put(vcpu);
5565 if (r < 0)
5566 goto free_vcpu;
5567
26e5215f 5568 return 0;
e9b11c17
ZX		 5569free_vcpu:
5570 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5571 return r;
e9b11c17
ZX		 5572}
5573
d40ccc62 5574void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5575{
5576 vcpu_load(vcpu);
5577 kvm_mmu_unload(vcpu);
5578 vcpu_put(vcpu);
5579
5580 kvm_x86_ops->vcpu_free(vcpu);
5581}
5582
5583int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5584{
448fa4a9
JK		 5585 vcpu->arch.nmi_pending = false;
5586 vcpu->arch.nmi_injected = false;
5587
42dbaa5a
JK		 5588 vcpu->arch.switch_db_regs = 0;
5589 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5590 vcpu->arch.dr6 = DR6_FIXED_1;
5591 vcpu->arch.dr7 = DR7_FIXED_1;
5592
e9b11c17
ZX		 5593 return kvm_x86_ops->vcpu_reset(vcpu);
5594}
5595
10474ae8 5596int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5597{
0cca7907
ZA		 5598 /*
5599 * Since this may be called from a hotplug notifcation,
5600 * we can't get the CPU frequency directly.
5601 */
5602 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5603 int cpu = raw_smp_processor_id();
5604 per_cpu(cpu_tsc_khz, cpu) = 0;
5605 }
18863bdd
AK		 5606
5607 kvm_shared_msr_cpu_online();
5608
10474ae8 5609 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5610}
5611
5612void kvm_arch_hardware_disable(void *garbage)
5613{
5614 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5615 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5616}
5617
5618int kvm_arch_hardware_setup(void)
5619{
5620 return kvm_x86_ops->hardware_setup();
5621}
5622
5623void kvm_arch_hardware_unsetup(void)
5624{
5625 kvm_x86_ops->hardware_unsetup();
5626}
5627
5628void kvm_arch_check_processor_compat(void *rtn)
5629{
5630 kvm_x86_ops->check_processor_compatibility(rtn);
5631}
5632
5633int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5634{
5635 struct page *page;
5636 struct kvm *kvm;
5637 int r;
5638
5639 BUG_ON(vcpu->kvm == NULL);
5640 kvm = vcpu->kvm;
5641
ad312c7c 5642 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5643 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5644 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5645 else
a4535290 5646 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5647
5648 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5649 if (!page) {
5650 r = -ENOMEM;
5651 goto fail;
5652 }
ad312c7c 5653 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5654
5655 r = kvm_mmu_create(vcpu);
5656 if (r < 0)
5657 goto fail_free_pio_data;
5658
5659 if (irqchip_in_kernel(kvm)) {
5660 r = kvm_create_lapic(vcpu);
5661 if (r < 0)
5662 goto fail_mmu_destroy;
5663 }
5664
890ca9ae
HY		 5665 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5666 GFP_KERNEL);
5667 if (!vcpu->arch.mce_banks) {
5668 r = -ENOMEM;
443c39bc 5669 goto fail_free_lapic;
890ca9ae
HY		 5670 }
5671 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5672
e9b11c17 5673 return 0;
443c39bc
WY		 5674fail_free_lapic:
5675 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5676fail_mmu_destroy:
5677 kvm_mmu_destroy(vcpu);
5678fail_free_pio_data:
ad312c7c 5679 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5680fail:
5681 return r;
5682}
5683
5684void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5685{
f656ce01
MT		 5686 int idx;
5687
36cb93fd 5688 kfree(vcpu->arch.mce_banks);
e9b11c17 5689 kvm_free_lapic(vcpu);
f656ce01 5690 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5691 kvm_mmu_destroy(vcpu);
f656ce01 5692 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5693 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5694}
d19a9cd2
ZX		 5695
5696struct kvm *kvm_arch_create_vm(void)
5697{
5698 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5699
5700 if (!kvm)
5701 return ERR_PTR(-ENOMEM);
5702
fef9cce0
MT		 5703 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5704 if (!kvm->arch.aliases) {
5705 kfree(kvm);
5706 return ERR_PTR(-ENOMEM);
5707 }
5708
f05e70ac 5709 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5710 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5711
5550af4d
SY		 5712 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5713 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5714
53f658b3
MT		 5715 rdtscll(kvm->arch.vm_init_tsc);
5716
d19a9cd2
ZX		 5717 return kvm;
5718}
5719
5720static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5721{
5722 vcpu_load(vcpu);
5723 kvm_mmu_unload(vcpu);
5724 vcpu_put(vcpu);
5725}
5726
5727static void kvm_free_vcpus(struct kvm *kvm)
5728{
5729 unsigned int i;
988a2cae 5730 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5731
5732 /*
5733 * Unpin any mmu pages first.
5734 */
988a2cae
GN		 5735 kvm_for_each_vcpu(i, vcpu, kvm)
5736 kvm_unload_vcpu_mmu(vcpu);
5737 kvm_for_each_vcpu(i, vcpu, kvm)
5738 kvm_arch_vcpu_free(vcpu);
5739
5740 mutex_lock(&kvm->lock);
5741 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5742 kvm->vcpus[i] = NULL;
d19a9cd2 5743
988a2cae
GN		 5744 atomic_set(&kvm->online_vcpus, 0);
5745 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5746}
5747
ad8ba2cd
SY		 5748void kvm_arch_sync_events(struct kvm *kvm)
5749{
ba4cef31 5750 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5751}
5752
d19a9cd2
ZX		 5753void kvm_arch_destroy_vm(struct kvm *kvm)
5754{
6eb55818 5755 kvm_iommu_unmap_guest(kvm);
7837699f 5756 kvm_free_pit(kvm);
d7deeeb0
ZX		 5757 kfree(kvm->arch.vpic);
5758 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5759 kvm_free_vcpus(kvm);
5760 kvm_free_physmem(kvm);
3d45830c
AK		 5761 if (kvm->arch.apic_access_page)
5762 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5763 if (kvm->arch.ept_identity_pagetable)
5764 put_page(kvm->arch.ept_identity_pagetable);
64749204 5765 cleanup_srcu_struct(&kvm->srcu);
fef9cce0 5766 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5767 kfree(kvm);
5768}
0de10343 5769
f7784b8e
MT		 5770int kvm_arch_prepare_memory_region(struct kvm *kvm,
5771 struct kvm_memory_slot *memslot,
0de10343 5772 struct kvm_memory_slot old,
f7784b8e 5773 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5774 int user_alloc)
5775{
f7784b8e 5776 int npages = memslot->npages;
0de10343
ZX		 5777
5778 /*To keep backward compatibility with older userspace,
5779 *x86 needs to hanlde !user_alloc case.
5780 */
5781 if (!user_alloc) {
5782 if (npages && !old.rmap) {
604b38ac
AA		 5783 unsigned long userspace_addr;
5784
72dc67a6 5785 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5786 userspace_addr = do_mmap(NULL, 0,
5787 npages * PAGE_SIZE,
5788 PROT_READ | PROT_WRITE,
acee3c04 5789 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5790 0);
72dc67a6 5791 up_write(&current->mm->mmap_sem);
0de10343 5792
604b38ac
AA		 5793 if (IS_ERR((void *)userspace_addr))
5794 return PTR_ERR((void *)userspace_addr);
5795
604b38ac 5796 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5797 }
5798 }
5799
f7784b8e
MT		 5800
5801 return 0;
5802}
5803
5804void kvm_arch_commit_memory_region(struct kvm *kvm,
5805 struct kvm_userspace_memory_region *mem,
5806 struct kvm_memory_slot old,
5807 int user_alloc)
5808{
5809
5810 int npages = mem->memory_size >> PAGE_SHIFT;
5811
5812 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5813 int ret;
5814
5815 down_write(&current->mm->mmap_sem);
5816 ret = do_munmap(current->mm, old.userspace_addr,
5817 old.npages * PAGE_SIZE);
5818 up_write(&current->mm->mmap_sem);
5819 if (ret < 0)
5820 printk(KERN_WARNING
5821 "kvm_vm_ioctl_set_memory_region: "
5822 "failed to munmap memory\n");
5823 }
5824
7c8a83b7 5825 spin_lock(&kvm->mmu_lock);
f05e70ac 5826 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5827 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5828 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5829 }
5830
5831 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5832 spin_unlock(&kvm->mmu_lock);
0de10343 5833}
1d737c8a 5834
34d4cb8f
MT		 5835void kvm_arch_flush_shadow(struct kvm *kvm)
5836{
5837 kvm_mmu_zap_all(kvm);
8986ecc0 5838 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5839}
5840
1d737c8a
ZX		 5841int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5842{
a4535290 5843 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5844 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5845 || vcpu->arch.nmi_pending ||
5846 (kvm_arch_interrupt_allowed(vcpu) &&
5847 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5848}
5736199a 5849
5736199a
ZX		 5850void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5851{
32f88400
MT		 5852 int me;
5853 int cpu = vcpu->cpu;
5736199a
ZX		 5854
5855 if (waitqueue_active(&vcpu->wq)) {
5856 wake_up_interruptible(&vcpu->wq);
5857 ++vcpu->stat.halt_wakeup;
5858 }
32f88400
MT		 5859
5860 me = get_cpu();
5861 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5862 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5863 smp_send_reschedule(cpu);
e9571ed5 5864 put_cpu();
5736199a 5865}
78646121
GN		 5866
5867int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5868{
5869 return kvm_x86_ops->interrupt_allowed(vcpu);
5870}
229456fc 5871
f92653ee
JK		 5872bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5873{
5874 unsigned long current_rip = kvm_rip_read(vcpu) +
5875 get_segment_base(vcpu, VCPU_SREG_CS);
5876
5877 return current_rip == linear_rip;
5878}
5879EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5880
94fe45da
JK		 5881unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5882{
5883 unsigned long rflags;
5884
5885 rflags = kvm_x86_ops->get_rflags(vcpu);
5886 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5887 rflags &= ~(unsigned long)(X86_EFLAGS_TF | X86_EFLAGS_RF);
5888 return rflags;
5889}
5890EXPORT_SYMBOL_GPL(kvm_get_rflags);
5891
5892void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5893{
5894 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5895 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
94fe45da
JK		 5896 rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
5897 kvm_x86_ops->set_rflags(vcpu, rflags);
5898}
5899EXPORT_SYMBOL_GPL(kvm_set_rflags);
5900
229456fc
MT		 5901EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5902EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5903EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5904EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5905EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5906EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5907EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5908EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5909EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5910EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5911EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
kernel source for telekom puls (alcatel/mediatek)