Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
39928722 | 26 | #include <linux/ioport.h> |
773763df | 27 | #include <linux/cpu.h> |
ba7eda4c | 28 | #include <linux/clockchips.h> |
70a20025 | 29 | #include <linux/acpi_pmtmr.h> |
e83a5fdc | 30 | #include <linux/module.h> |
773763df | 31 | #include <linux/dmi.h> |
6e1cb38a | 32 | #include <linux/dmar.h> |
bcbc4f20 | 33 | #include <linux/ftrace.h> |
e423e33e JSR |
34 | #include <linux/smp.h> |
35 | #include <linux/nmi.h> | |
36 | #include <linux/timex.h> | |
1da177e4 LT |
37 | |
38 | #include <asm/atomic.h> | |
1da177e4 LT |
39 | #include <asm/mtrr.h> |
40 | #include <asm/mpspec.h> | |
efa2559f | 41 | #include <asm/desc.h> |
773763df | 42 | #include <asm/arch_hooks.h> |
e83a5fdc | 43 | #include <asm/hpet.h> |
1da177e4 | 44 | #include <asm/pgalloc.h> |
773763df | 45 | #include <asm/i8253.h> |
95833c83 | 46 | #include <asm/idle.h> |
73dea47f | 47 | #include <asm/proto.h> |
2c8c0e6b | 48 | #include <asm/apic.h> |
6e1cb38a | 49 | #include <asm/i8259.h> |
2bc13797 | 50 | #include <asm/smp.h> |
1da177e4 | 51 | |
dd46e3ca | 52 | #include <mach_apic.h> |
773763df | 53 | #include <mach_ipi.h> |
5af5573e | 54 | |
80e5609c CG |
55 | /* |
56 | * Sanity check | |
57 | */ | |
58 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) | |
59 | # error SPURIOUS_APIC_VECTOR definition error | |
60 | #endif | |
61 | ||
ec70de8b BG |
62 | unsigned int num_processors; |
63 | unsigned disabled_cpus __cpuinitdata; | |
64 | /* Processor that is doing the boot up */ | |
65 | unsigned int boot_cpu_physical_apicid = -1U; | |
66 | EXPORT_SYMBOL(boot_cpu_physical_apicid); | |
67 | unsigned int max_physical_apicid; | |
68 | ||
69 | /* Bitmask of physically existing CPUs */ | |
70 | physid_mask_t phys_cpu_present_map; | |
71 | ||
72 | /* | |
73 | * Map cpu index to physical APIC ID | |
74 | */ | |
75 | DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID); | |
76 | DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID); | |
77 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); | |
78 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); | |
79 | ||
b3c51170 YL |
80 | #ifdef CONFIG_X86_32 |
81 | /* | |
82 | * Knob to control our willingness to enable the local APIC. | |
83 | * | |
84 | * +1=force-enable | |
85 | */ | |
86 | static int force_enable_local_apic; | |
87 | /* | |
88 | * APIC command line parameters | |
89 | */ | |
90 | static int __init parse_lapic(char *arg) | |
91 | { | |
92 | force_enable_local_apic = 1; | |
93 | return 0; | |
94 | } | |
95 | early_param("lapic", parse_lapic); | |
f28c0ae2 YL |
96 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
97 | static int enabled_via_apicbase; | |
98 | ||
b3c51170 YL |
99 | #endif |
100 | ||
101 | #ifdef CONFIG_X86_64 | |
bc1d99c1 | 102 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
103 | static __init int setup_apicpmtimer(char *s) |
104 | { | |
105 | apic_calibrate_pmtmr = 1; | |
106 | notsc_setup(NULL); | |
107 | return 0; | |
108 | } | |
109 | __setup("apicpmtimer", setup_apicpmtimer); | |
110 | #endif | |
111 | ||
49899eac YL |
112 | #ifdef CONFIG_X86_64 |
113 | #define HAVE_X2APIC | |
114 | #endif | |
115 | ||
116 | #ifdef HAVE_X2APIC | |
89027d35 | 117 | int x2apic; |
6e1cb38a | 118 | /* x2apic enabled before OS handover */ |
b6b301aa JS |
119 | static int x2apic_preenabled; |
120 | static int disable_x2apic; | |
49899eac YL |
121 | static __init int setup_nox2apic(char *str) |
122 | { | |
123 | disable_x2apic = 1; | |
124 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
125 | return 0; | |
126 | } | |
127 | early_param("nox2apic", setup_nox2apic); | |
128 | #endif | |
1da177e4 | 129 | |
b3c51170 YL |
130 | unsigned long mp_lapic_addr; |
131 | int disable_apic; | |
132 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ | |
133 | static int disable_apic_timer __cpuinitdata; | |
e83a5fdc | 134 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
135 | int local_apic_timer_c2_ok; |
136 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
137 | ||
efa2559f YL |
138 | int first_system_vector = 0xfe; |
139 | ||
e83a5fdc HS |
140 | /* |
141 | * Debug level, exported for io_apic.c | |
142 | */ | |
baa13188 | 143 | unsigned int apic_verbosity; |
e83a5fdc | 144 | |
89c38c28 CG |
145 | int pic_mode; |
146 | ||
bab4b27c AS |
147 | /* Have we found an MP table */ |
148 | int smp_found_config; | |
149 | ||
39928722 AD |
150 | static struct resource lapic_resource = { |
151 | .name = "Local APIC", | |
152 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
153 | }; | |
154 | ||
d03030e9 TG |
155 | static unsigned int calibration_result; |
156 | ||
ba7eda4c TG |
157 | static int lapic_next_event(unsigned long delta, |
158 | struct clock_event_device *evt); | |
159 | static void lapic_timer_setup(enum clock_event_mode mode, | |
160 | struct clock_event_device *evt); | |
9628937d | 161 | static void lapic_timer_broadcast(const struct cpumask *mask); |
0e078e2f | 162 | static void apic_pm_activate(void); |
ba7eda4c | 163 | |
274cfe59 CG |
164 | /* |
165 | * The local apic timer can be used for any function which is CPU local. | |
166 | */ | |
ba7eda4c TG |
167 | static struct clock_event_device lapic_clockevent = { |
168 | .name = "lapic", | |
169 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
170 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
171 | .shift = 32, | |
172 | .set_mode = lapic_timer_setup, | |
173 | .set_next_event = lapic_next_event, | |
174 | .broadcast = lapic_timer_broadcast, | |
175 | .rating = 100, | |
176 | .irq = -1, | |
177 | }; | |
178 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
179 | ||
d3432896 AK |
180 | static unsigned long apic_phys; |
181 | ||
0e078e2f TG |
182 | /* |
183 | * Get the LAPIC version | |
184 | */ | |
185 | static inline int lapic_get_version(void) | |
ba7eda4c | 186 | { |
0e078e2f | 187 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
188 | } |
189 | ||
0e078e2f | 190 | /* |
9c803869 | 191 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
192 | */ |
193 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 194 | { |
9c803869 | 195 | #ifdef CONFIG_X86_64 |
0e078e2f | 196 | return 1; |
9c803869 CG |
197 | #else |
198 | return APIC_INTEGRATED(lapic_get_version()); | |
199 | #endif | |
ba7eda4c TG |
200 | } |
201 | ||
202 | /* | |
0e078e2f | 203 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 204 | */ |
0e078e2f | 205 | static int modern_apic(void) |
ba7eda4c | 206 | { |
0e078e2f TG |
207 | /* AMD systems use old APIC versions, so check the CPU */ |
208 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
209 | boot_cpu_data.x86 >= 0xf) | |
210 | return 1; | |
211 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
212 | } |
213 | ||
274cfe59 CG |
214 | /* |
215 | * Paravirt kernels also might be using these below ops. So we still | |
216 | * use generic apic_read()/apic_write(), which might be pointing to different | |
217 | * ops in PARAVIRT case. | |
218 | */ | |
1b374e4d | 219 | void xapic_wait_icr_idle(void) |
8339e9fb FLV |
220 | { |
221 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
222 | cpu_relax(); | |
223 | } | |
224 | ||
1b374e4d | 225 | u32 safe_xapic_wait_icr_idle(void) |
8339e9fb | 226 | { |
3c6bb07a | 227 | u32 send_status; |
8339e9fb FLV |
228 | int timeout; |
229 | ||
230 | timeout = 0; | |
231 | do { | |
232 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
233 | if (!send_status) | |
234 | break; | |
235 | udelay(100); | |
236 | } while (timeout++ < 1000); | |
237 | ||
238 | return send_status; | |
239 | } | |
240 | ||
1b374e4d SS |
241 | void xapic_icr_write(u32 low, u32 id) |
242 | { | |
ed4e5ec1 | 243 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
244 | apic_write(APIC_ICR, low); |
245 | } | |
246 | ||
ec8c842a | 247 | static u64 xapic_icr_read(void) |
1b374e4d SS |
248 | { |
249 | u32 icr1, icr2; | |
250 | ||
251 | icr2 = apic_read(APIC_ICR2); | |
252 | icr1 = apic_read(APIC_ICR); | |
253 | ||
cf9768d7 | 254 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
255 | } |
256 | ||
257 | static struct apic_ops xapic_ops = { | |
258 | .read = native_apic_mem_read, | |
259 | .write = native_apic_mem_write, | |
1b374e4d SS |
260 | .icr_read = xapic_icr_read, |
261 | .icr_write = xapic_icr_write, | |
262 | .wait_icr_idle = xapic_wait_icr_idle, | |
263 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
264 | }; | |
265 | ||
266 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
1b374e4d SS |
267 | EXPORT_SYMBOL_GPL(apic_ops); |
268 | ||
49899eac | 269 | #ifdef HAVE_X2APIC |
13c88fb5 SS |
270 | static void x2apic_wait_icr_idle(void) |
271 | { | |
272 | /* no need to wait for icr idle in x2apic */ | |
273 | return; | |
274 | } | |
275 | ||
276 | static u32 safe_x2apic_wait_icr_idle(void) | |
277 | { | |
278 | /* no need to wait for icr idle in x2apic */ | |
279 | return 0; | |
280 | } | |
281 | ||
282 | void x2apic_icr_write(u32 low, u32 id) | |
283 | { | |
284 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
285 | } | |
286 | ||
ec8c842a | 287 | static u64 x2apic_icr_read(void) |
13c88fb5 SS |
288 | { |
289 | unsigned long val; | |
290 | ||
291 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
292 | return val; | |
293 | } | |
294 | ||
295 | static struct apic_ops x2apic_ops = { | |
296 | .read = native_apic_msr_read, | |
297 | .write = native_apic_msr_write, | |
13c88fb5 SS |
298 | .icr_read = x2apic_icr_read, |
299 | .icr_write = x2apic_icr_write, | |
300 | .wait_icr_idle = x2apic_wait_icr_idle, | |
301 | .safe_wait_icr_idle = safe_x2apic_wait_icr_idle, | |
302 | }; | |
49899eac | 303 | #endif |
13c88fb5 | 304 | |
0e078e2f TG |
305 | /** |
306 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
307 | */ | |
e9427101 | 308 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 309 | { |
11a8e778 | 310 | unsigned int v; |
6935d1f9 TG |
311 | |
312 | /* unmask and set to NMI */ | |
313 | v = APIC_DM_NMI; | |
d4c63ec0 CG |
314 | |
315 | /* Level triggered for 82489DX (32bit mode) */ | |
316 | if (!lapic_is_integrated()) | |
317 | v |= APIC_LVT_LEVEL_TRIGGER; | |
318 | ||
11a8e778 | 319 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
320 | } |
321 | ||
7c37e48b CG |
322 | #ifdef CONFIG_X86_32 |
323 | /** | |
324 | * get_physical_broadcast - Get number of physical broadcast IDs | |
325 | */ | |
326 | int get_physical_broadcast(void) | |
327 | { | |
328 | return modern_apic() ? 0xff : 0xf; | |
329 | } | |
330 | #endif | |
331 | ||
0e078e2f TG |
332 | /** |
333 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
334 | */ | |
37e650c7 | 335 | int lapic_get_maxlvt(void) |
1da177e4 | 336 | { |
36a028de | 337 | unsigned int v; |
1da177e4 LT |
338 | |
339 | v = apic_read(APIC_LVR); | |
36a028de CG |
340 | /* |
341 | * - we always have APIC integrated on 64bit mode | |
342 | * - 82489DXs do not report # of LVT entries | |
343 | */ | |
344 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
345 | } |
346 | ||
274cfe59 CG |
347 | /* |
348 | * Local APIC timer | |
349 | */ | |
350 | ||
c40aaec6 | 351 | /* Clock divisor */ |
c40aaec6 | 352 | #define APIC_DIVISOR 16 |
f07f4f90 | 353 | |
0e078e2f TG |
354 | /* |
355 | * This function sets up the local APIC timer, with a timeout of | |
356 | * 'clocks' APIC bus clock. During calibration we actually call | |
357 | * this function twice on the boot CPU, once with a bogus timeout | |
358 | * value, second time for real. The other (noncalibrating) CPUs | |
359 | * call this function only once, with the real, calibrated value. | |
360 | * | |
361 | * We do reads before writes even if unnecessary, to get around the | |
362 | * P5 APIC double write bug. | |
363 | */ | |
0e078e2f | 364 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 365 | { |
0e078e2f | 366 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 367 | |
0e078e2f TG |
368 | lvtt_value = LOCAL_TIMER_VECTOR; |
369 | if (!oneshot) | |
370 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
f07f4f90 CG |
371 | if (!lapic_is_integrated()) |
372 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
373 | ||
0e078e2f TG |
374 | if (!irqen) |
375 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 376 | |
0e078e2f | 377 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
378 | |
379 | /* | |
0e078e2f | 380 | * Divide PICLK by 16 |
1da177e4 | 381 | */ |
0e078e2f | 382 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
383 | apic_write(APIC_TDCR, |
384 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
385 | APIC_TDR_DIV_16); | |
0e078e2f TG |
386 | |
387 | if (!oneshot) | |
f07f4f90 | 388 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
389 | } |
390 | ||
0e078e2f | 391 | /* |
7b83dae7 RR |
392 | * Setup extended LVT, AMD specific (K8, family 10h) |
393 | * | |
394 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
395 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
286f5718 RR |
396 | * |
397 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
398 | * enables the vector. See also the BKDGs. | |
0e078e2f | 399 | */ |
7b83dae7 RR |
400 | |
401 | #define APIC_EILVT_LVTOFF_MCE 0 | |
402 | #define APIC_EILVT_LVTOFF_IBS 1 | |
403 | ||
404 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 405 | { |
7b83dae7 | 406 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 407 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 408 | |
0e078e2f | 409 | apic_write(reg, v); |
1da177e4 LT |
410 | } |
411 | ||
7b83dae7 RR |
412 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
413 | { | |
414 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
415 | return APIC_EILVT_LVTOFF_MCE; | |
416 | } | |
417 | ||
418 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
419 | { | |
420 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
421 | return APIC_EILVT_LVTOFF_IBS; | |
422 | } | |
6aa360e6 | 423 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); |
7b83dae7 | 424 | |
0e078e2f TG |
425 | /* |
426 | * Program the next event, relative to now | |
427 | */ | |
428 | static int lapic_next_event(unsigned long delta, | |
429 | struct clock_event_device *evt) | |
1da177e4 | 430 | { |
0e078e2f TG |
431 | apic_write(APIC_TMICT, delta); |
432 | return 0; | |
1da177e4 LT |
433 | } |
434 | ||
0e078e2f TG |
435 | /* |
436 | * Setup the lapic timer in periodic or oneshot mode | |
437 | */ | |
438 | static void lapic_timer_setup(enum clock_event_mode mode, | |
439 | struct clock_event_device *evt) | |
9b7711f0 HS |
440 | { |
441 | unsigned long flags; | |
0e078e2f | 442 | unsigned int v; |
9b7711f0 | 443 | |
0e078e2f TG |
444 | /* Lapic used as dummy for broadcast ? */ |
445 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
446 | return; |
447 | ||
448 | local_irq_save(flags); | |
449 | ||
0e078e2f TG |
450 | switch (mode) { |
451 | case CLOCK_EVT_MODE_PERIODIC: | |
452 | case CLOCK_EVT_MODE_ONESHOT: | |
453 | __setup_APIC_LVTT(calibration_result, | |
454 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
455 | break; | |
456 | case CLOCK_EVT_MODE_UNUSED: | |
457 | case CLOCK_EVT_MODE_SHUTDOWN: | |
458 | v = apic_read(APIC_LVTT); | |
459 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
460 | apic_write(APIC_LVTT, v); | |
a98f8fd2 | 461 | apic_write(APIC_TMICT, 0xffffffff); |
0e078e2f TG |
462 | break; |
463 | case CLOCK_EVT_MODE_RESUME: | |
464 | /* Nothing to do here */ | |
465 | break; | |
466 | } | |
9b7711f0 HS |
467 | |
468 | local_irq_restore(flags); | |
469 | } | |
470 | ||
1da177e4 | 471 | /* |
0e078e2f | 472 | * Local APIC timer broadcast function |
1da177e4 | 473 | */ |
9628937d | 474 | static void lapic_timer_broadcast(const struct cpumask *mask) |
1da177e4 | 475 | { |
0e078e2f | 476 | #ifdef CONFIG_SMP |
dac5f412 | 477 | apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
0e078e2f TG |
478 | #endif |
479 | } | |
1da177e4 | 480 | |
0e078e2f TG |
481 | /* |
482 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
483 | * of the boot CPU and register the clock event in the framework. | |
484 | */ | |
db4b5525 | 485 | static void __cpuinit setup_APIC_timer(void) |
0e078e2f TG |
486 | { |
487 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 488 | |
0e078e2f | 489 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
320ab2b0 | 490 | levt->cpumask = cpumask_of(smp_processor_id()); |
1da177e4 | 491 | |
0e078e2f TG |
492 | clockevents_register_device(levt); |
493 | } | |
1da177e4 | 494 | |
2f04fa88 YL |
495 | /* |
496 | * In this functions we calibrate APIC bus clocks to the external timer. | |
497 | * | |
498 | * We want to do the calibration only once since we want to have local timer | |
499 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
500 | * frequency. | |
501 | * | |
502 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
503 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
504 | * readout is broken, so it never gets out of the wait loop again. This was | |
505 | * also reported by others. | |
506 | * | |
507 | * Monitoring the jiffies value is inaccurate and the clockevents | |
508 | * infrastructure allows us to do a simple substitution of the interrupt | |
509 | * handler. | |
510 | * | |
511 | * The calibration routine also uses the pm_timer when possible, as the PIT | |
512 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
513 | * back to normal later in the boot process). | |
514 | */ | |
515 | ||
516 | #define LAPIC_CAL_LOOPS (HZ/10) | |
517 | ||
518 | static __initdata int lapic_cal_loops = -1; | |
519 | static __initdata long lapic_cal_t1, lapic_cal_t2; | |
520 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
521 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
522 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
523 | ||
524 | /* | |
525 | * Temporary interrupt handler. | |
526 | */ | |
527 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
528 | { | |
529 | unsigned long long tsc = 0; | |
530 | long tapic = apic_read(APIC_TMCCT); | |
531 | unsigned long pm = acpi_pm_read_early(); | |
532 | ||
533 | if (cpu_has_tsc) | |
534 | rdtscll(tsc); | |
535 | ||
536 | switch (lapic_cal_loops++) { | |
537 | case 0: | |
538 | lapic_cal_t1 = tapic; | |
539 | lapic_cal_tsc1 = tsc; | |
540 | lapic_cal_pm1 = pm; | |
541 | lapic_cal_j1 = jiffies; | |
542 | break; | |
543 | ||
544 | case LAPIC_CAL_LOOPS: | |
545 | lapic_cal_t2 = tapic; | |
546 | lapic_cal_tsc2 = tsc; | |
547 | if (pm < lapic_cal_pm1) | |
548 | pm += ACPI_PM_OVRRUN; | |
549 | lapic_cal_pm2 = pm; | |
550 | lapic_cal_j2 = jiffies; | |
551 | break; | |
552 | } | |
553 | } | |
554 | ||
b189892d CG |
555 | static int __init calibrate_by_pmtimer(long deltapm, long *delta) |
556 | { | |
557 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; | |
558 | const long pm_thresh = pm_100ms / 100; | |
559 | unsigned long mult; | |
560 | u64 res; | |
561 | ||
562 | #ifndef CONFIG_X86_PM_TIMER | |
563 | return -1; | |
564 | #endif | |
565 | ||
566 | apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm); | |
567 | ||
568 | /* Check, if the PM timer is available */ | |
569 | if (!deltapm) | |
570 | return -1; | |
571 | ||
572 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
573 | ||
574 | if (deltapm > (pm_100ms - pm_thresh) && | |
575 | deltapm < (pm_100ms + pm_thresh)) { | |
576 | apic_printk(APIC_VERBOSE, "... PM timer result ok\n"); | |
577 | } else { | |
578 | res = (((u64)deltapm) * mult) >> 22; | |
579 | do_div(res, 1000000); | |
ba21ebb6 | 580 | pr_warning("APIC calibration not consistent " |
b189892d CG |
581 | "with PM Timer: %ldms instead of 100ms\n", |
582 | (long)res); | |
583 | /* Correct the lapic counter value */ | |
584 | res = (((u64)(*delta)) * pm_100ms); | |
585 | do_div(res, deltapm); | |
ba21ebb6 | 586 | pr_info("APIC delta adjusted to PM-Timer: " |
b189892d CG |
587 | "%lu (%ld)\n", (unsigned long)res, *delta); |
588 | *delta = (long)res; | |
589 | } | |
590 | ||
591 | return 0; | |
592 | } | |
593 | ||
2f04fa88 YL |
594 | static int __init calibrate_APIC_clock(void) |
595 | { | |
596 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
2f04fa88 YL |
597 | void (*real_handler)(struct clock_event_device *dev); |
598 | unsigned long deltaj; | |
b189892d | 599 | long delta; |
2f04fa88 YL |
600 | int pm_referenced = 0; |
601 | ||
602 | local_irq_disable(); | |
603 | ||
604 | /* Replace the global interrupt handler */ | |
605 | real_handler = global_clock_event->event_handler; | |
606 | global_clock_event->event_handler = lapic_cal_handler; | |
607 | ||
608 | /* | |
81608f3c | 609 | * Setup the APIC counter to maximum. There is no way the lapic |
2f04fa88 YL |
610 | * can underflow in the 100ms detection time frame |
611 | */ | |
81608f3c | 612 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
2f04fa88 YL |
613 | |
614 | /* Let the interrupts run */ | |
615 | local_irq_enable(); | |
616 | ||
617 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
618 | cpu_relax(); | |
619 | ||
620 | local_irq_disable(); | |
621 | ||
622 | /* Restore the real event handler */ | |
623 | global_clock_event->event_handler = real_handler; | |
624 | ||
625 | /* Build delta t1-t2 as apic timer counts down */ | |
626 | delta = lapic_cal_t1 - lapic_cal_t2; | |
627 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
628 | ||
b189892d CG |
629 | /* we trust the PM based calibration if possible */ |
630 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, | |
631 | &delta); | |
2f04fa88 YL |
632 | |
633 | /* Calculate the scaled math multiplication factor */ | |
634 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, | |
635 | lapic_clockevent.shift); | |
636 | lapic_clockevent.max_delta_ns = | |
637 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
638 | lapic_clockevent.min_delta_ns = | |
639 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
640 | ||
641 | calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; | |
642 | ||
643 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
644 | apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); | |
645 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", | |
646 | calibration_result); | |
647 | ||
648 | if (cpu_has_tsc) { | |
649 | delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); | |
650 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " | |
651 | "%ld.%04ld MHz.\n", | |
652 | (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ), | |
653 | (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
654 | } | |
655 | ||
656 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
657 | "%u.%04u MHz.\n", | |
658 | calibration_result / (1000000 / HZ), | |
659 | calibration_result % (1000000 / HZ)); | |
660 | ||
661 | /* | |
662 | * Do a sanity check on the APIC calibration result | |
663 | */ | |
664 | if (calibration_result < (1000000 / HZ)) { | |
665 | local_irq_enable(); | |
ba21ebb6 | 666 | pr_warning("APIC frequency too slow, disabling apic timer\n"); |
2f04fa88 YL |
667 | return -1; |
668 | } | |
669 | ||
670 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; | |
671 | ||
b189892d CG |
672 | /* |
673 | * PM timer calibration failed or not turned on | |
674 | * so lets try APIC timer based calibration | |
675 | */ | |
2f04fa88 YL |
676 | if (!pm_referenced) { |
677 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
678 | ||
679 | /* | |
680 | * Setup the apic timer manually | |
681 | */ | |
682 | levt->event_handler = lapic_cal_handler; | |
683 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
684 | lapic_cal_loops = -1; | |
685 | ||
686 | /* Let the interrupts run */ | |
687 | local_irq_enable(); | |
688 | ||
689 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
690 | cpu_relax(); | |
691 | ||
2f04fa88 YL |
692 | /* Stop the lapic timer */ |
693 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
694 | ||
2f04fa88 YL |
695 | /* Jiffies delta */ |
696 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
697 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
698 | ||
699 | /* Check, if the jiffies result is consistent */ | |
700 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) | |
701 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); | |
702 | else | |
703 | levt->features |= CLOCK_EVT_FEAT_DUMMY; | |
704 | } else | |
705 | local_irq_enable(); | |
706 | ||
707 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { | |
e423e33e | 708 | pr_warning("APIC timer disabled due to verification failure\n"); |
2f04fa88 YL |
709 | return -1; |
710 | } | |
711 | ||
712 | return 0; | |
713 | } | |
714 | ||
e83a5fdc HS |
715 | /* |
716 | * Setup the boot APIC | |
717 | * | |
718 | * Calibrate and verify the result. | |
719 | */ | |
0e078e2f TG |
720 | void __init setup_boot_APIC_clock(void) |
721 | { | |
722 | /* | |
274cfe59 CG |
723 | * The local apic timer can be disabled via the kernel |
724 | * commandline or from the CPU detection code. Register the lapic | |
725 | * timer as a dummy clock event source on SMP systems, so the | |
726 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
727 | */ |
728 | if (disable_apic_timer) { | |
ba21ebb6 | 729 | pr_info("Disabling APIC timer\n"); |
0e078e2f | 730 | /* No broadcast on UP ! */ |
9d09951d TG |
731 | if (num_possible_cpus() > 1) { |
732 | lapic_clockevent.mult = 1; | |
0e078e2f | 733 | setup_APIC_timer(); |
9d09951d | 734 | } |
0e078e2f TG |
735 | return; |
736 | } | |
737 | ||
274cfe59 CG |
738 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
739 | "calibrating APIC timer ...\n"); | |
740 | ||
89b3b1f4 | 741 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
742 | /* No broadcast on UP ! */ |
743 | if (num_possible_cpus() > 1) | |
744 | setup_APIC_timer(); | |
745 | return; | |
746 | } | |
747 | ||
0e078e2f TG |
748 | /* |
749 | * If nmi_watchdog is set to IO_APIC, we need the | |
750 | * PIT/HPET going. Otherwise register lapic as a dummy | |
751 | * device. | |
752 | */ | |
753 | if (nmi_watchdog != NMI_IO_APIC) | |
754 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
755 | else | |
ba21ebb6 | 756 | pr_warning("APIC timer registered as dummy," |
116f570e | 757 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
0e078e2f | 758 | |
274cfe59 | 759 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
760 | setup_APIC_timer(); |
761 | } | |
762 | ||
0e078e2f TG |
763 | void __cpuinit setup_secondary_APIC_clock(void) |
764 | { | |
0e078e2f TG |
765 | setup_APIC_timer(); |
766 | } | |
767 | ||
768 | /* | |
769 | * The guts of the apic timer interrupt | |
770 | */ | |
771 | static void local_apic_timer_interrupt(void) | |
772 | { | |
773 | int cpu = smp_processor_id(); | |
774 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
775 | ||
776 | /* | |
777 | * Normally we should not be here till LAPIC has been initialized but | |
778 | * in some cases like kdump, its possible that there is a pending LAPIC | |
779 | * timer interrupt from previous kernel's context and is delivered in | |
780 | * new kernel the moment interrupts are enabled. | |
781 | * | |
782 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
783 | * its possible that when we get here evt->event_handler is NULL. | |
784 | * Check for event_handler being NULL and discard the interrupt as | |
785 | * spurious. | |
786 | */ | |
787 | if (!evt->event_handler) { | |
ba21ebb6 | 788 | pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); |
0e078e2f TG |
789 | /* Switch it off */ |
790 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
791 | return; | |
792 | } | |
793 | ||
794 | /* | |
795 | * the NMI deadlock-detector uses this. | |
796 | */ | |
915b0d01 | 797 | inc_irq_stat(apic_timer_irqs); |
0e078e2f TG |
798 | |
799 | evt->event_handler(evt); | |
800 | } | |
801 | ||
802 | /* | |
803 | * Local APIC timer interrupt. This is the most natural way for doing | |
804 | * local interrupts, but local timer interrupts can be emulated by | |
805 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
806 | * | |
807 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
808 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
809 | */ | |
bcbc4f20 | 810 | void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) |
0e078e2f TG |
811 | { |
812 | struct pt_regs *old_regs = set_irq_regs(regs); | |
813 | ||
814 | /* | |
815 | * NOTE! We'd better ACK the irq immediately, | |
816 | * because timer handling can be slow. | |
817 | */ | |
818 | ack_APIC_irq(); | |
819 | /* | |
820 | * update_process_times() expects us to have done irq_enter(). | |
821 | * Besides, if we don't timer interrupts ignore the global | |
822 | * interrupt lock, which is the WrongThing (tm) to do. | |
823 | */ | |
824 | exit_idle(); | |
825 | irq_enter(); | |
826 | local_apic_timer_interrupt(); | |
827 | irq_exit(); | |
274cfe59 | 828 | |
0e078e2f TG |
829 | set_irq_regs(old_regs); |
830 | } | |
831 | ||
832 | int setup_profiling_timer(unsigned int multiplier) | |
833 | { | |
834 | return -EINVAL; | |
835 | } | |
836 | ||
0e078e2f TG |
837 | /* |
838 | * Local APIC start and shutdown | |
839 | */ | |
840 | ||
841 | /** | |
842 | * clear_local_APIC - shutdown the local APIC | |
843 | * | |
844 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
845 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
846 | * leftovers during boot. | |
847 | */ | |
848 | void clear_local_APIC(void) | |
849 | { | |
2584a82d | 850 | int maxlvt; |
0e078e2f TG |
851 | u32 v; |
852 | ||
d3432896 AK |
853 | /* APIC hasn't been mapped yet */ |
854 | if (!apic_phys) | |
855 | return; | |
856 | ||
857 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
858 | /* |
859 | * Masking an LVT entry can trigger a local APIC error | |
860 | * if the vector is zero. Mask LVTERR first to prevent this. | |
861 | */ | |
862 | if (maxlvt >= 3) { | |
863 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
864 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
865 | } | |
866 | /* | |
867 | * Careful: we have to set masks only first to deassert | |
868 | * any level-triggered sources. | |
869 | */ | |
870 | v = apic_read(APIC_LVTT); | |
871 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
872 | v = apic_read(APIC_LVT0); | |
873 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
874 | v = apic_read(APIC_LVT1); | |
875 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
876 | if (maxlvt >= 4) { | |
877 | v = apic_read(APIC_LVTPC); | |
878 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
879 | } | |
880 | ||
6764014b CG |
881 | /* lets not touch this if we didn't frob it */ |
882 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) | |
883 | if (maxlvt >= 5) { | |
884 | v = apic_read(APIC_LVTTHMR); | |
885 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
886 | } | |
887 | #endif | |
0e078e2f TG |
888 | /* |
889 | * Clean APIC state for other OSs: | |
890 | */ | |
891 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
892 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
893 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
894 | if (maxlvt >= 3) | |
895 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
896 | if (maxlvt >= 4) | |
897 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
898 | |
899 | /* Integrated APIC (!82489DX) ? */ | |
900 | if (lapic_is_integrated()) { | |
901 | if (maxlvt > 3) | |
902 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
903 | apic_write(APIC_ESR, 0); | |
904 | apic_read(APIC_ESR); | |
905 | } | |
0e078e2f TG |
906 | } |
907 | ||
908 | /** | |
909 | * disable_local_APIC - clear and disable the local APIC | |
910 | */ | |
911 | void disable_local_APIC(void) | |
912 | { | |
913 | unsigned int value; | |
914 | ||
a08c4743 JB |
915 | /* APIC hasn't been mapped yet */ |
916 | if (!apic_phys) | |
917 | return; | |
918 | ||
0e078e2f TG |
919 | clear_local_APIC(); |
920 | ||
921 | /* | |
922 | * Disable APIC (implies clearing of registers | |
923 | * for 82489DX!). | |
924 | */ | |
925 | value = apic_read(APIC_SPIV); | |
926 | value &= ~APIC_SPIV_APIC_ENABLED; | |
927 | apic_write(APIC_SPIV, value); | |
990b183e CG |
928 | |
929 | #ifdef CONFIG_X86_32 | |
930 | /* | |
931 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
932 | * restore the disabled state. | |
933 | */ | |
934 | if (enabled_via_apicbase) { | |
935 | unsigned int l, h; | |
936 | ||
937 | rdmsr(MSR_IA32_APICBASE, l, h); | |
938 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
939 | wrmsr(MSR_IA32_APICBASE, l, h); | |
940 | } | |
941 | #endif | |
0e078e2f TG |
942 | } |
943 | ||
fe4024dc CG |
944 | /* |
945 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
946 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
947 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
948 | * for the case where Linux didn't enable the LAPIC. | |
949 | */ | |
0e078e2f TG |
950 | void lapic_shutdown(void) |
951 | { | |
952 | unsigned long flags; | |
953 | ||
954 | if (!cpu_has_apic) | |
955 | return; | |
956 | ||
957 | local_irq_save(flags); | |
958 | ||
fe4024dc CG |
959 | #ifdef CONFIG_X86_32 |
960 | if (!enabled_via_apicbase) | |
961 | clear_local_APIC(); | |
962 | else | |
963 | #endif | |
964 | disable_local_APIC(); | |
965 | ||
0e078e2f TG |
966 | |
967 | local_irq_restore(flags); | |
968 | } | |
969 | ||
970 | /* | |
971 | * This is to verify that we're looking at a real local APIC. | |
972 | * Check these against your board if the CPUs aren't getting | |
973 | * started for no apparent reason. | |
974 | */ | |
975 | int __init verify_local_APIC(void) | |
976 | { | |
977 | unsigned int reg0, reg1; | |
978 | ||
979 | /* | |
980 | * The version register is read-only in a real APIC. | |
981 | */ | |
982 | reg0 = apic_read(APIC_LVR); | |
983 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
984 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
985 | reg1 = apic_read(APIC_LVR); | |
986 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
987 | ||
988 | /* | |
989 | * The two version reads above should print the same | |
990 | * numbers. If the second one is different, then we | |
991 | * poke at a non-APIC. | |
992 | */ | |
993 | if (reg1 != reg0) | |
994 | return 0; | |
995 | ||
996 | /* | |
997 | * Check if the version looks reasonably. | |
998 | */ | |
999 | reg1 = GET_APIC_VERSION(reg0); | |
1000 | if (reg1 == 0x00 || reg1 == 0xff) | |
1001 | return 0; | |
1002 | reg1 = lapic_get_maxlvt(); | |
1003 | if (reg1 < 0x02 || reg1 == 0xff) | |
1004 | return 0; | |
1005 | ||
1006 | /* | |
1007 | * The ID register is read/write in a real APIC. | |
1008 | */ | |
2d7a66d0 | 1009 | reg0 = apic_read(APIC_ID); |
0e078e2f | 1010 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
5b812727 | 1011 | apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); |
2d7a66d0 | 1012 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
1013 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
1014 | apic_write(APIC_ID, reg0); | |
5b812727 | 1015 | if (reg1 != (reg0 ^ apic->apic_id_mask)) |
0e078e2f TG |
1016 | return 0; |
1017 | ||
1018 | /* | |
1da177e4 LT |
1019 | * The next two are just to see if we have sane values. |
1020 | * They're only really relevant if we're in Virtual Wire | |
1021 | * compatibility mode, but most boxes are anymore. | |
1022 | */ | |
1023 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 1024 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
1025 | reg1 = apic_read(APIC_LVT1); |
1026 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
1027 | ||
1028 | return 1; | |
1029 | } | |
1030 | ||
0e078e2f TG |
1031 | /** |
1032 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
1033 | */ | |
1da177e4 LT |
1034 | void __init sync_Arb_IDs(void) |
1035 | { | |
296cb951 CG |
1036 | /* |
1037 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
1038 | * needed on AMD. | |
1039 | */ | |
1040 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
1041 | return; |
1042 | ||
1043 | /* | |
1044 | * Wait for idle. | |
1045 | */ | |
1046 | apic_wait_icr_idle(); | |
1047 | ||
1048 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
1049 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
1050 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
1051 | } |
1052 | ||
1da177e4 LT |
1053 | /* |
1054 | * An initial setup of the virtual wire mode. | |
1055 | */ | |
1056 | void __init init_bsp_APIC(void) | |
1057 | { | |
11a8e778 | 1058 | unsigned int value; |
1da177e4 LT |
1059 | |
1060 | /* | |
1061 | * Don't do the setup now if we have a SMP BIOS as the | |
1062 | * through-I/O-APIC virtual wire mode might be active. | |
1063 | */ | |
1064 | if (smp_found_config || !cpu_has_apic) | |
1065 | return; | |
1066 | ||
1da177e4 LT |
1067 | /* |
1068 | * Do not trust the local APIC being empty at bootup. | |
1069 | */ | |
1070 | clear_local_APIC(); | |
1071 | ||
1072 | /* | |
1073 | * Enable APIC. | |
1074 | */ | |
1075 | value = apic_read(APIC_SPIV); | |
1076 | value &= ~APIC_VECTOR_MASK; | |
1077 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
1078 | |
1079 | #ifdef CONFIG_X86_32 | |
1080 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
1081 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
1082 | (boot_cpu_data.x86 == 15)) | |
1083 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1084 | else | |
1085 | #endif | |
1086 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1087 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 1088 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1089 | |
1090 | /* | |
1091 | * Set up the virtual wire mode. | |
1092 | */ | |
11a8e778 | 1093 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 1094 | value = APIC_DM_NMI; |
638c0411 CG |
1095 | if (!lapic_is_integrated()) /* 82489DX */ |
1096 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1097 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
1098 | } |
1099 | ||
c43da2f5 CG |
1100 | static void __cpuinit lapic_setup_esr(void) |
1101 | { | |
9df08f10 CG |
1102 | unsigned int oldvalue, value, maxlvt; |
1103 | ||
1104 | if (!lapic_is_integrated()) { | |
ba21ebb6 | 1105 | pr_info("No ESR for 82489DX.\n"); |
9df08f10 CG |
1106 | return; |
1107 | } | |
c43da2f5 | 1108 | |
08125d3e | 1109 | if (apic->disable_esr) { |
c43da2f5 | 1110 | /* |
9df08f10 CG |
1111 | * Something untraceable is creating bad interrupts on |
1112 | * secondary quads ... for the moment, just leave the | |
1113 | * ESR disabled - we can't do anything useful with the | |
1114 | * errors anyway - mbligh | |
c43da2f5 | 1115 | */ |
ba21ebb6 | 1116 | pr_info("Leaving ESR disabled.\n"); |
9df08f10 | 1117 | return; |
c43da2f5 | 1118 | } |
9df08f10 CG |
1119 | |
1120 | maxlvt = lapic_get_maxlvt(); | |
1121 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1122 | apic_write(APIC_ESR, 0); | |
1123 | oldvalue = apic_read(APIC_ESR); | |
1124 | ||
1125 | /* enables sending errors */ | |
1126 | value = ERROR_APIC_VECTOR; | |
1127 | apic_write(APIC_LVTERR, value); | |
1128 | ||
1129 | /* | |
1130 | * spec says clear errors after enabling vector. | |
1131 | */ | |
1132 | if (maxlvt > 3) | |
1133 | apic_write(APIC_ESR, 0); | |
1134 | value = apic_read(APIC_ESR); | |
1135 | if (value != oldvalue) | |
1136 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1137 | "vector: 0x%08x after: 0x%08x\n", | |
1138 | oldvalue, value); | |
c43da2f5 CG |
1139 | } |
1140 | ||
1141 | ||
0e078e2f TG |
1142 | /** |
1143 | * setup_local_APIC - setup the local APIC | |
1144 | */ | |
1145 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 1146 | { |
739f33b3 | 1147 | unsigned int value; |
da7ed9f9 | 1148 | int i, j; |
1da177e4 | 1149 | |
f1182638 | 1150 | if (disable_apic) { |
5cdc5e9e | 1151 | #ifdef CONFIG_X86_IO_APIC |
f1182638 | 1152 | disable_ioapic_setup(); |
5cdc5e9e | 1153 | #endif |
f1182638 JB |
1154 | return; |
1155 | } | |
1156 | ||
89c38c28 CG |
1157 | #ifdef CONFIG_X86_32 |
1158 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
08125d3e | 1159 | if (lapic_is_integrated() && apic->disable_esr) { |
89c38c28 CG |
1160 | apic_write(APIC_ESR, 0); |
1161 | apic_write(APIC_ESR, 0); | |
1162 | apic_write(APIC_ESR, 0); | |
1163 | apic_write(APIC_ESR, 0); | |
1164 | } | |
1165 | #endif | |
1166 | ||
ac23d4ee | 1167 | preempt_disable(); |
1da177e4 | 1168 | |
1da177e4 LT |
1169 | /* |
1170 | * Double-check whether this APIC is really registered. | |
1171 | * This is meaningless in clustered apic mode, so we skip it. | |
1172 | */ | |
7ed248da | 1173 | if (!apic->apic_id_registered()) |
1da177e4 LT |
1174 | BUG(); |
1175 | ||
1176 | /* | |
1177 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1178 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1179 | * document number 292116). So here it goes... | |
1180 | */ | |
a5c43296 | 1181 | apic->init_apic_ldr(); |
1da177e4 LT |
1182 | |
1183 | /* | |
1184 | * Set Task Priority to 'accept all'. We never change this | |
1185 | * later on. | |
1186 | */ | |
1187 | value = apic_read(APIC_TASKPRI); | |
1188 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 1189 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1190 | |
da7ed9f9 VG |
1191 | /* |
1192 | * After a crash, we no longer service the interrupts and a pending | |
1193 | * interrupt from previous kernel might still have ISR bit set. | |
1194 | * | |
1195 | * Most probably by now CPU has serviced that pending interrupt and | |
1196 | * it might not have done the ack_APIC_irq() because it thought, | |
1197 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1198 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1199 | * the interrupt. Hence a vector might get locked. It was noticed | |
1200 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1201 | */ | |
1202 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1203 | value = apic_read(APIC_ISR + i*0x10); | |
1204 | for (j = 31; j >= 0; j--) { | |
1205 | if (value & (1<<j)) | |
1206 | ack_APIC_irq(); | |
1207 | } | |
1208 | } | |
1209 | ||
1da177e4 LT |
1210 | /* |
1211 | * Now that we are all set up, enable the APIC | |
1212 | */ | |
1213 | value = apic_read(APIC_SPIV); | |
1214 | value &= ~APIC_VECTOR_MASK; | |
1215 | /* | |
1216 | * Enable APIC | |
1217 | */ | |
1218 | value |= APIC_SPIV_APIC_ENABLED; | |
1219 | ||
89c38c28 CG |
1220 | #ifdef CONFIG_X86_32 |
1221 | /* | |
1222 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1223 | * certain networking cards. If high frequency interrupts are | |
1224 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1225 | * entry is masked/unmasked at a high rate as well then sooner or | |
1226 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1227 | * from the device. If focus CPU is disabled then the hang goes | |
1228 | * away, oh well :-( | |
1229 | * | |
1230 | * [ This bug can be reproduced easily with a level-triggered | |
1231 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1232 | * BX chipset. ] | |
1233 | */ | |
1234 | /* | |
1235 | * Actually disabling the focus CPU check just makes the hang less | |
1236 | * frequent as it makes the interrupt distributon model be more | |
1237 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1238 | * See also the comment in end_level_ioapic_irq(). --macro | |
1239 | */ | |
1240 | ||
1241 | /* | |
1242 | * - enable focus processor (bit==0) | |
1243 | * - 64bit mode always use processor focus | |
1244 | * so no need to set it | |
1245 | */ | |
1246 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1247 | #endif | |
3f14c746 | 1248 | |
1da177e4 LT |
1249 | /* |
1250 | * Set spurious IRQ vector | |
1251 | */ | |
1252 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1253 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1254 | |
1255 | /* | |
1256 | * Set up LVT0, LVT1: | |
1257 | * | |
1258 | * set up through-local-APIC on the BP's LINT0. This is not | |
1259 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1260 | * we delegate interrupts to the 8259A. | |
1261 | */ | |
1262 | /* | |
1263 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1264 | */ | |
1265 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
89c38c28 | 1266 | if (!smp_processor_id() && (pic_mode || !value)) { |
1da177e4 | 1267 | value = APIC_DM_EXTINT; |
bc1d99c1 | 1268 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
89c38c28 | 1269 | smp_processor_id()); |
1da177e4 LT |
1270 | } else { |
1271 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 | 1272 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
89c38c28 | 1273 | smp_processor_id()); |
1da177e4 | 1274 | } |
11a8e778 | 1275 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1276 | |
1277 | /* | |
1278 | * only the BP should see the LINT1 NMI signal, obviously. | |
1279 | */ | |
1280 | if (!smp_processor_id()) | |
1281 | value = APIC_DM_NMI; | |
1282 | else | |
1283 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1284 | if (!lapic_is_integrated()) /* 82489DX */ |
1285 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1286 | apic_write(APIC_LVT1, value); |
89c38c28 | 1287 | |
ac23d4ee | 1288 | preempt_enable(); |
739f33b3 | 1289 | } |
1da177e4 | 1290 | |
739f33b3 AK |
1291 | void __cpuinit end_local_APIC_setup(void) |
1292 | { | |
1293 | lapic_setup_esr(); | |
fa6b95fc CG |
1294 | |
1295 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1296 | { |
1297 | unsigned int value; | |
1298 | /* Disable the local apic timer */ | |
1299 | value = apic_read(APIC_LVTT); | |
1300 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1301 | apic_write(APIC_LVTT, value); | |
1302 | } | |
fa6b95fc CG |
1303 | #endif |
1304 | ||
f2802e7f | 1305 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 1306 | apic_pm_activate(); |
1da177e4 | 1307 | } |
1da177e4 | 1308 | |
49899eac | 1309 | #ifdef HAVE_X2APIC |
6e1cb38a SS |
1310 | void check_x2apic(void) |
1311 | { | |
1312 | int msr, msr2; | |
1313 | ||
1314 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1315 | ||
1316 | if (msr & X2APIC_ENABLE) { | |
ba21ebb6 | 1317 | pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); |
6e1cb38a SS |
1318 | x2apic_preenabled = x2apic = 1; |
1319 | apic_ops = &x2apic_ops; | |
1320 | } | |
1321 | } | |
1322 | ||
1323 | void enable_x2apic(void) | |
1324 | { | |
1325 | int msr, msr2; | |
1326 | ||
1327 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1328 | if (!(msr & X2APIC_ENABLE)) { | |
ba21ebb6 | 1329 | pr_info("Enabling x2apic\n"); |
6e1cb38a SS |
1330 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); |
1331 | } | |
1332 | } | |
1333 | ||
2236d252 | 1334 | void __init enable_IR_x2apic(void) |
6e1cb38a SS |
1335 | { |
1336 | #ifdef CONFIG_INTR_REMAP | |
1337 | int ret; | |
1338 | unsigned long flags; | |
1339 | ||
1340 | if (!cpu_has_x2apic) | |
1341 | return; | |
1342 | ||
1343 | if (!x2apic_preenabled && disable_x2apic) { | |
ba21ebb6 CG |
1344 | pr_info("Skipped enabling x2apic and Interrupt-remapping " |
1345 | "because of nox2apic\n"); | |
6e1cb38a SS |
1346 | return; |
1347 | } | |
1348 | ||
1349 | if (x2apic_preenabled && disable_x2apic) | |
1350 | panic("Bios already enabled x2apic, can't enforce nox2apic"); | |
1351 | ||
1352 | if (!x2apic_preenabled && skip_ioapic_setup) { | |
ba21ebb6 CG |
1353 | pr_info("Skipped enabling x2apic and Interrupt-remapping " |
1354 | "because of skipping io-apic setup\n"); | |
6e1cb38a SS |
1355 | return; |
1356 | } | |
1357 | ||
1358 | ret = dmar_table_init(); | |
1359 | if (ret) { | |
ba21ebb6 | 1360 | pr_info("dmar_table_init() failed with %d:\n", ret); |
6e1cb38a SS |
1361 | |
1362 | if (x2apic_preenabled) | |
1363 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1364 | else | |
ba21ebb6 | 1365 | pr_info("Not enabling x2apic,Intr-remapping\n"); |
6e1cb38a SS |
1366 | return; |
1367 | } | |
1368 | ||
1369 | local_irq_save(flags); | |
1370 | mask_8259A(); | |
5ffa4eb2 CG |
1371 | |
1372 | ret = save_mask_IO_APIC_setup(); | |
1373 | if (ret) { | |
ba21ebb6 | 1374 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
5ffa4eb2 CG |
1375 | goto end; |
1376 | } | |
6e1cb38a SS |
1377 | |
1378 | ret = enable_intr_remapping(1); | |
1379 | ||
1380 | if (ret && x2apic_preenabled) { | |
1381 | local_irq_restore(flags); | |
1382 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1383 | } | |
1384 | ||
1385 | if (ret) | |
5ffa4eb2 | 1386 | goto end_restore; |
6e1cb38a SS |
1387 | |
1388 | if (!x2apic) { | |
1389 | x2apic = 1; | |
1390 | apic_ops = &x2apic_ops; | |
1391 | enable_x2apic(); | |
1392 | } | |
5ffa4eb2 CG |
1393 | |
1394 | end_restore: | |
6e1cb38a SS |
1395 | if (ret) |
1396 | /* | |
1397 | * IR enabling failed | |
1398 | */ | |
1399 | restore_IO_APIC_setup(); | |
1400 | else | |
1401 | reinit_intr_remapped_IO_APIC(x2apic_preenabled); | |
1402 | ||
5ffa4eb2 | 1403 | end: |
6e1cb38a SS |
1404 | unmask_8259A(); |
1405 | local_irq_restore(flags); | |
1406 | ||
1407 | if (!ret) { | |
1408 | if (!x2apic_preenabled) | |
ba21ebb6 | 1409 | pr_info("Enabled x2apic and interrupt-remapping\n"); |
6e1cb38a | 1410 | else |
ba21ebb6 | 1411 | pr_info("Enabled Interrupt-remapping\n"); |
6e1cb38a | 1412 | } else |
ba21ebb6 | 1413 | pr_err("Failed to enable Interrupt-remapping and x2apic\n"); |
6e1cb38a SS |
1414 | #else |
1415 | if (!cpu_has_x2apic) | |
1416 | return; | |
1417 | ||
1418 | if (x2apic_preenabled) | |
1419 | panic("x2apic enabled prior OS handover," | |
1420 | " enable CONFIG_INTR_REMAP"); | |
1421 | ||
ba21ebb6 CG |
1422 | pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping " |
1423 | " and x2apic\n"); | |
6e1cb38a SS |
1424 | #endif |
1425 | ||
1426 | return; | |
1427 | } | |
49899eac | 1428 | #endif /* HAVE_X2APIC */ |
6e1cb38a | 1429 | |
be7a656f | 1430 | #ifdef CONFIG_X86_64 |
1da177e4 LT |
1431 | /* |
1432 | * Detect and enable local APICs on non-SMP boards. | |
1433 | * Original code written by Keir Fraser. | |
1434 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1435 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1436 | */ |
0e078e2f | 1437 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1438 | { |
1439 | if (!cpu_has_apic) { | |
ba21ebb6 | 1440 | pr_info("No local APIC present\n"); |
1da177e4 LT |
1441 | return -1; |
1442 | } | |
1443 | ||
1444 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 1445 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
1446 | return 0; |
1447 | } | |
be7a656f YL |
1448 | #else |
1449 | /* | |
1450 | * Detect and initialize APIC | |
1451 | */ | |
1452 | static int __init detect_init_APIC(void) | |
1453 | { | |
1454 | u32 h, l, features; | |
1455 | ||
1456 | /* Disabled by kernel option? */ | |
1457 | if (disable_apic) | |
1458 | return -1; | |
1459 | ||
1460 | switch (boot_cpu_data.x86_vendor) { | |
1461 | case X86_VENDOR_AMD: | |
1462 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
1463 | (boot_cpu_data.x86 == 15)) | |
1464 | break; | |
1465 | goto no_apic; | |
1466 | case X86_VENDOR_INTEL: | |
1467 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1468 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1469 | break; | |
1470 | goto no_apic; | |
1471 | default: | |
1472 | goto no_apic; | |
1473 | } | |
1474 | ||
1475 | if (!cpu_has_apic) { | |
1476 | /* | |
1477 | * Over-ride BIOS and try to enable the local APIC only if | |
1478 | * "lapic" specified. | |
1479 | */ | |
1480 | if (!force_enable_local_apic) { | |
ba21ebb6 CG |
1481 | pr_info("Local APIC disabled by BIOS -- " |
1482 | "you can enable it with \"lapic\"\n"); | |
be7a656f YL |
1483 | return -1; |
1484 | } | |
1485 | /* | |
1486 | * Some BIOSes disable the local APIC in the APIC_BASE | |
1487 | * MSR. This can only be done in software for Intel P6 or later | |
1488 | * and AMD K7 (Model > 1) or later. | |
1489 | */ | |
1490 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1491 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
ba21ebb6 | 1492 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); |
be7a656f YL |
1493 | l &= ~MSR_IA32_APICBASE_BASE; |
1494 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
1495 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1496 | enabled_via_apicbase = 1; | |
1497 | } | |
1498 | } | |
1499 | /* | |
1500 | * The APIC feature bit should now be enabled | |
1501 | * in `cpuid' | |
1502 | */ | |
1503 | features = cpuid_edx(1); | |
1504 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
ba21ebb6 | 1505 | pr_warning("Could not enable APIC!\n"); |
be7a656f YL |
1506 | return -1; |
1507 | } | |
1508 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
1509 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1510 | ||
1511 | /* The BIOS may have set up the APIC at some other address */ | |
1512 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1513 | if (l & MSR_IA32_APICBASE_ENABLE) | |
1514 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1515 | ||
ba21ebb6 | 1516 | pr_info("Found and enabled local APIC!\n"); |
be7a656f YL |
1517 | |
1518 | apic_pm_activate(); | |
1519 | ||
1520 | return 0; | |
1521 | ||
1522 | no_apic: | |
ba21ebb6 | 1523 | pr_info("No local APIC present or hardware disabled\n"); |
be7a656f YL |
1524 | return -1; |
1525 | } | |
1526 | #endif | |
1da177e4 | 1527 | |
f28c0ae2 | 1528 | #ifdef CONFIG_X86_64 |
8643f9d0 YL |
1529 | void __init early_init_lapic_mapping(void) |
1530 | { | |
431ee79d | 1531 | unsigned long phys_addr; |
8643f9d0 YL |
1532 | |
1533 | /* | |
1534 | * If no local APIC can be found then go out | |
1535 | * : it means there is no mpatable and MADT | |
1536 | */ | |
1537 | if (!smp_found_config) | |
1538 | return; | |
1539 | ||
431ee79d | 1540 | phys_addr = mp_lapic_addr; |
8643f9d0 | 1541 | |
431ee79d | 1542 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
8643f9d0 | 1543 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
431ee79d | 1544 | APIC_BASE, phys_addr); |
8643f9d0 YL |
1545 | |
1546 | /* | |
1547 | * Fetch the APIC ID of the BSP in case we have a | |
1548 | * default configuration (or the MP table is broken). | |
1549 | */ | |
4c9961d5 | 1550 | boot_cpu_physical_apicid = read_apic_id(); |
8643f9d0 | 1551 | } |
f28c0ae2 | 1552 | #endif |
8643f9d0 | 1553 | |
0e078e2f TG |
1554 | /** |
1555 | * init_apic_mappings - initialize APIC mappings | |
1556 | */ | |
1da177e4 LT |
1557 | void __init init_apic_mappings(void) |
1558 | { | |
49899eac | 1559 | #ifdef HAVE_X2APIC |
6e1cb38a | 1560 | if (x2apic) { |
4c9961d5 | 1561 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1562 | return; |
1563 | } | |
49899eac | 1564 | #endif |
6e1cb38a | 1565 | |
1da177e4 LT |
1566 | /* |
1567 | * If no local APIC can be found then set up a fake all | |
1568 | * zeroes page to simulate the local APIC and another | |
1569 | * one for the IO-APIC. | |
1570 | */ | |
1571 | if (!smp_found_config && detect_init_APIC()) { | |
1572 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1573 | apic_phys = __pa(apic_phys); | |
1574 | } else | |
1575 | apic_phys = mp_lapic_addr; | |
1576 | ||
1577 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
79c09698 | 1578 | apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", |
7ffeeb1e | 1579 | APIC_BASE, apic_phys); |
1da177e4 LT |
1580 | |
1581 | /* | |
1582 | * Fetch the APIC ID of the BSP in case we have a | |
1583 | * default configuration (or the MP table is broken). | |
1584 | */ | |
f28c0ae2 YL |
1585 | if (boot_cpu_physical_apicid == -1U) |
1586 | boot_cpu_physical_apicid = read_apic_id(); | |
1da177e4 LT |
1587 | } |
1588 | ||
1589 | /* | |
0e078e2f TG |
1590 | * This initializes the IO-APIC and APIC hardware if this is |
1591 | * a UP kernel. | |
1da177e4 | 1592 | */ |
1b313f4a CG |
1593 | int apic_version[MAX_APICS]; |
1594 | ||
0e078e2f | 1595 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1596 | { |
0e078e2f | 1597 | if (disable_apic) { |
ba21ebb6 | 1598 | pr_info("Apic disabled\n"); |
0e078e2f TG |
1599 | return -1; |
1600 | } | |
f1182638 | 1601 | #ifdef CONFIG_X86_64 |
0e078e2f TG |
1602 | if (!cpu_has_apic) { |
1603 | disable_apic = 1; | |
ba21ebb6 | 1604 | pr_info("Apic disabled by BIOS\n"); |
0e078e2f TG |
1605 | return -1; |
1606 | } | |
fa2bd35a YL |
1607 | #else |
1608 | if (!smp_found_config && !cpu_has_apic) | |
1609 | return -1; | |
1610 | ||
1611 | /* | |
1612 | * Complain if the BIOS pretends there is one. | |
1613 | */ | |
1614 | if (!cpu_has_apic && | |
1615 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
ba21ebb6 CG |
1616 | pr_err("BIOS bug, local APIC 0x%x not detected!...\n", |
1617 | boot_cpu_physical_apicid); | |
fa2bd35a YL |
1618 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
1619 | return -1; | |
1620 | } | |
1621 | #endif | |
1622 | ||
49899eac | 1623 | #ifdef HAVE_X2APIC |
6e1cb38a | 1624 | enable_IR_x2apic(); |
49899eac | 1625 | #endif |
fa2bd35a | 1626 | #ifdef CONFIG_X86_64 |
72ce0165 | 1627 | default_setup_apic_routing(); |
fa2bd35a | 1628 | #endif |
6e1cb38a | 1629 | |
0e078e2f | 1630 | verify_local_APIC(); |
b5841765 GC |
1631 | connect_bsp_APIC(); |
1632 | ||
fa2bd35a | 1633 | #ifdef CONFIG_X86_64 |
c70dcb74 | 1634 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
fa2bd35a YL |
1635 | #else |
1636 | /* | |
1637 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1638 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1639 | * might be zero if read from MP tables. Get it from LAPIC. | |
1640 | */ | |
1641 | # ifdef CONFIG_CRASH_DUMP | |
1642 | boot_cpu_physical_apicid = read_apic_id(); | |
1643 | # endif | |
1644 | #endif | |
1645 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); | |
0e078e2f | 1646 | setup_local_APIC(); |
1da177e4 | 1647 | |
fa2bd35a | 1648 | #ifdef CONFIG_X86_64 |
739f33b3 AK |
1649 | /* |
1650 | * Now enable IO-APICs, actually call clear_IO_APIC | |
1651 | * We need clear_IO_APIC before enabling vector on BP | |
1652 | */ | |
1653 | if (!skip_ioapic_setup && nr_ioapics) | |
1654 | enable_IO_APIC(); | |
fa2bd35a | 1655 | #endif |
739f33b3 | 1656 | |
fa2bd35a | 1657 | #ifdef CONFIG_X86_IO_APIC |
acae7d90 | 1658 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) |
fa2bd35a | 1659 | #endif |
acae7d90 | 1660 | localise_nmi_watchdog(); |
739f33b3 AK |
1661 | end_local_APIC_setup(); |
1662 | ||
fa2bd35a | 1663 | #ifdef CONFIG_X86_IO_APIC |
0e078e2f TG |
1664 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1665 | setup_IO_APIC(); | |
fa2bd35a | 1666 | # ifdef CONFIG_X86_64 |
0e078e2f TG |
1667 | else |
1668 | nr_ioapics = 0; | |
fa2bd35a YL |
1669 | # endif |
1670 | #endif | |
1671 | ||
1672 | #ifdef CONFIG_X86_64 | |
0e078e2f TG |
1673 | setup_boot_APIC_clock(); |
1674 | check_nmi_watchdog(); | |
fa2bd35a YL |
1675 | #else |
1676 | setup_boot_clock(); | |
1677 | #endif | |
1678 | ||
0e078e2f | 1679 | return 0; |
1da177e4 LT |
1680 | } |
1681 | ||
1682 | /* | |
0e078e2f | 1683 | * Local APIC interrupts |
1da177e4 LT |
1684 | */ |
1685 | ||
0e078e2f TG |
1686 | /* |
1687 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1688 | */ | |
dc1528dd | 1689 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 | 1690 | { |
dc1528dd YL |
1691 | u32 v; |
1692 | ||
0e078e2f TG |
1693 | exit_idle(); |
1694 | irq_enter(); | |
1da177e4 | 1695 | /* |
0e078e2f TG |
1696 | * Check if this really is a spurious interrupt and ACK it |
1697 | * if it is a vectored one. Just in case... | |
1698 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1699 | */ |
0e078e2f TG |
1700 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1701 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1702 | ack_APIC_irq(); | |
c4d58cbd | 1703 | |
915b0d01 HS |
1704 | inc_irq_stat(irq_spurious_count); |
1705 | ||
dc1528dd | 1706 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ |
ba21ebb6 CG |
1707 | pr_info("spurious APIC interrupt on CPU#%d, " |
1708 | "should never happen.\n", smp_processor_id()); | |
0e078e2f TG |
1709 | irq_exit(); |
1710 | } | |
1da177e4 | 1711 | |
0e078e2f TG |
1712 | /* |
1713 | * This interrupt should never happen with our APIC/SMP architecture | |
1714 | */ | |
dc1528dd | 1715 | void smp_error_interrupt(struct pt_regs *regs) |
0e078e2f | 1716 | { |
dc1528dd | 1717 | u32 v, v1; |
1da177e4 | 1718 | |
0e078e2f TG |
1719 | exit_idle(); |
1720 | irq_enter(); | |
1721 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1722 | v = apic_read(APIC_ESR); | |
1723 | apic_write(APIC_ESR, 0); | |
1724 | v1 = apic_read(APIC_ESR); | |
1725 | ack_APIC_irq(); | |
1726 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1727 | |
ba21ebb6 CG |
1728 | /* |
1729 | * Here is what the APIC error bits mean: | |
1730 | * 0: Send CS error | |
1731 | * 1: Receive CS error | |
1732 | * 2: Send accept error | |
1733 | * 3: Receive accept error | |
1734 | * 4: Reserved | |
1735 | * 5: Send illegal vector | |
1736 | * 6: Received illegal vector | |
1737 | * 7: Illegal register address | |
1738 | */ | |
1739 | pr_debug("APIC error on CPU%d: %02x(%02x)\n", | |
0e078e2f TG |
1740 | smp_processor_id(), v , v1); |
1741 | irq_exit(); | |
1da177e4 LT |
1742 | } |
1743 | ||
b5841765 | 1744 | /** |
36c9d674 CG |
1745 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1746 | */ | |
b5841765 GC |
1747 | void __init connect_bsp_APIC(void) |
1748 | { | |
36c9d674 CG |
1749 | #ifdef CONFIG_X86_32 |
1750 | if (pic_mode) { | |
1751 | /* | |
1752 | * Do not trust the local APIC being empty at bootup. | |
1753 | */ | |
1754 | clear_local_APIC(); | |
1755 | /* | |
1756 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1757 | * local APIC to INT and NMI lines. | |
1758 | */ | |
1759 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1760 | "enabling APIC mode.\n"); | |
1761 | outb(0x70, 0x22); | |
1762 | outb(0x01, 0x23); | |
1763 | } | |
1764 | #endif | |
49040333 IM |
1765 | if (apic->enable_apic_mode) |
1766 | apic->enable_apic_mode(); | |
b5841765 GC |
1767 | } |
1768 | ||
274cfe59 CG |
1769 | /** |
1770 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1771 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1772 | * | |
1773 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1774 | * APIC is disabled. | |
1775 | */ | |
0e078e2f | 1776 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1777 | { |
1b4ee4e4 CG |
1778 | unsigned int value; |
1779 | ||
c177b0bc CG |
1780 | #ifdef CONFIG_X86_32 |
1781 | if (pic_mode) { | |
1782 | /* | |
1783 | * Put the board back into PIC mode (has an effect only on | |
1784 | * certain older boards). Note that APIC interrupts, including | |
1785 | * IPIs, won't work beyond this point! The only exception are | |
1786 | * INIT IPIs. | |
1787 | */ | |
1788 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1789 | "entering PIC mode.\n"); | |
1790 | outb(0x70, 0x22); | |
1791 | outb(0x00, 0x23); | |
1792 | return; | |
1793 | } | |
1794 | #endif | |
1795 | ||
0e078e2f | 1796 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1797 | |
0e078e2f TG |
1798 | /* For the spurious interrupt use vector F, and enable it */ |
1799 | value = apic_read(APIC_SPIV); | |
1800 | value &= ~APIC_VECTOR_MASK; | |
1801 | value |= APIC_SPIV_APIC_ENABLED; | |
1802 | value |= 0xf; | |
1803 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1804 | |
0e078e2f TG |
1805 | if (!virt_wire_setup) { |
1806 | /* | |
1807 | * For LVT0 make it edge triggered, active high, | |
1808 | * external and enabled | |
1809 | */ | |
1810 | value = apic_read(APIC_LVT0); | |
1811 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1812 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1813 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1814 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1815 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1816 | apic_write(APIC_LVT0, value); | |
1817 | } else { | |
1818 | /* Disable LVT0 */ | |
1819 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1820 | } | |
b8ce3359 | 1821 | |
c177b0bc CG |
1822 | /* |
1823 | * For LVT1 make it edge triggered, active high, | |
1824 | * nmi and enabled | |
1825 | */ | |
0e078e2f TG |
1826 | value = apic_read(APIC_LVT1); |
1827 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1828 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1829 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1830 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1831 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1832 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1833 | } |
1834 | ||
be8a5685 AS |
1835 | void __cpuinit generic_processor_info(int apicid, int version) |
1836 | { | |
1837 | int cpu; | |
be8a5685 | 1838 | |
1b313f4a CG |
1839 | /* |
1840 | * Validate version | |
1841 | */ | |
1842 | if (version == 0x0) { | |
ba21ebb6 | 1843 | pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " |
3b11ce7f MT |
1844 | "fixing up to 0x10. (tell your hw vendor)\n", |
1845 | version); | |
1b313f4a | 1846 | version = 0x10; |
be8a5685 | 1847 | } |
1b313f4a | 1848 | apic_version[apicid] = version; |
be8a5685 | 1849 | |
3b11ce7f MT |
1850 | if (num_processors >= nr_cpu_ids) { |
1851 | int max = nr_cpu_ids; | |
1852 | int thiscpu = max + disabled_cpus; | |
1853 | ||
1854 | pr_warning( | |
1855 | "ACPI: NR_CPUS/possible_cpus limit of %i reached." | |
1856 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
1857 | ||
1858 | disabled_cpus++; | |
be8a5685 AS |
1859 | return; |
1860 | } | |
1861 | ||
1862 | num_processors++; | |
3b11ce7f | 1863 | cpu = cpumask_next_zero(-1, cpu_present_mask); |
be8a5685 | 1864 | |
cef30b3a MT |
1865 | if (version != apic_version[boot_cpu_physical_apicid]) |
1866 | WARN_ONCE(1, | |
1867 | "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n", | |
1868 | apic_version[boot_cpu_physical_apicid], cpu, version); | |
1869 | ||
be8a5685 AS |
1870 | physid_set(apicid, phys_cpu_present_map); |
1871 | if (apicid == boot_cpu_physical_apicid) { | |
1872 | /* | |
1873 | * x86_bios_cpu_apicid is required to have processors listed | |
1874 | * in same order as logical cpu numbers. Hence the first | |
1875 | * entry is BSP, and so on. | |
1876 | */ | |
1877 | cpu = 0; | |
1878 | } | |
e0da3364 YL |
1879 | if (apicid > max_physical_apicid) |
1880 | max_physical_apicid = apicid; | |
1881 | ||
1b313f4a CG |
1882 | #ifdef CONFIG_X86_32 |
1883 | /* | |
1884 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1885 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1886 | * before this can be done without some confusion. | |
1887 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1888 | * - Ashok Raj <ashok.raj@intel.com> | |
1889 | */ | |
1890 | if (max_physical_apicid >= 8) { | |
1891 | switch (boot_cpu_data.x86_vendor) { | |
1892 | case X86_VENDOR_INTEL: | |
1893 | if (!APIC_XAPIC(version)) { | |
1894 | def_to_bigsmp = 0; | |
1895 | break; | |
1896 | } | |
1897 | /* If P4 and above fall through */ | |
1898 | case X86_VENDOR_AMD: | |
1899 | def_to_bigsmp = 1; | |
1900 | } | |
1901 | } | |
1902 | #endif | |
1903 | ||
1904 | #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64) | |
f10fcd47 TH |
1905 | early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; |
1906 | early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1b313f4a | 1907 | #endif |
be8a5685 | 1908 | |
1de88cd4 MT |
1909 | set_cpu_possible(cpu, true); |
1910 | set_cpu_present(cpu, true); | |
be8a5685 AS |
1911 | } |
1912 | ||
3491998d | 1913 | #ifdef CONFIG_X86_64 |
0c81c746 SS |
1914 | int hard_smp_processor_id(void) |
1915 | { | |
1916 | return read_apic_id(); | |
1917 | } | |
3491998d | 1918 | #endif |
0c81c746 | 1919 | |
89039b37 | 1920 | /* |
0e078e2f | 1921 | * Power management |
89039b37 | 1922 | */ |
0e078e2f TG |
1923 | #ifdef CONFIG_PM |
1924 | ||
1925 | static struct { | |
274cfe59 CG |
1926 | /* |
1927 | * 'active' is true if the local APIC was enabled by us and | |
1928 | * not the BIOS; this signifies that we are also responsible | |
1929 | * for disabling it before entering apm/acpi suspend | |
1930 | */ | |
0e078e2f TG |
1931 | int active; |
1932 | /* r/w apic fields */ | |
1933 | unsigned int apic_id; | |
1934 | unsigned int apic_taskpri; | |
1935 | unsigned int apic_ldr; | |
1936 | unsigned int apic_dfr; | |
1937 | unsigned int apic_spiv; | |
1938 | unsigned int apic_lvtt; | |
1939 | unsigned int apic_lvtpc; | |
1940 | unsigned int apic_lvt0; | |
1941 | unsigned int apic_lvt1; | |
1942 | unsigned int apic_lvterr; | |
1943 | unsigned int apic_tmict; | |
1944 | unsigned int apic_tdcr; | |
1945 | unsigned int apic_thmr; | |
1946 | } apic_pm_state; | |
1947 | ||
1948 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1949 | { | |
1950 | unsigned long flags; | |
1951 | int maxlvt; | |
89039b37 | 1952 | |
0e078e2f TG |
1953 | if (!apic_pm_state.active) |
1954 | return 0; | |
89039b37 | 1955 | |
0e078e2f | 1956 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1957 | |
2d7a66d0 | 1958 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
1959 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1960 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1961 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1962 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1963 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1964 | if (maxlvt >= 4) | |
1965 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1966 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1967 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1968 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1969 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1970 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
24968cfd | 1971 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1972 | if (maxlvt >= 5) |
1973 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1974 | #endif | |
24968cfd | 1975 | |
0e078e2f TG |
1976 | local_irq_save(flags); |
1977 | disable_local_APIC(); | |
1978 | local_irq_restore(flags); | |
1979 | return 0; | |
1da177e4 LT |
1980 | } |
1981 | ||
0e078e2f | 1982 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1983 | { |
0e078e2f TG |
1984 | unsigned int l, h; |
1985 | unsigned long flags; | |
1986 | int maxlvt; | |
1da177e4 | 1987 | |
0e078e2f TG |
1988 | if (!apic_pm_state.active) |
1989 | return 0; | |
89b831ef | 1990 | |
0e078e2f | 1991 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 1992 | |
0e078e2f | 1993 | local_irq_save(flags); |
92206c90 | 1994 | |
49899eac | 1995 | #ifdef HAVE_X2APIC |
92206c90 CG |
1996 | if (x2apic) |
1997 | enable_x2apic(); | |
1998 | else | |
1999 | #endif | |
d5e629a6 | 2000 | { |
92206c90 CG |
2001 | /* |
2002 | * Make sure the APICBASE points to the right address | |
2003 | * | |
2004 | * FIXME! This will be wrong if we ever support suspend on | |
2005 | * SMP! We'll need to do this as part of the CPU restore! | |
2006 | */ | |
6e1cb38a SS |
2007 | rdmsr(MSR_IA32_APICBASE, l, h); |
2008 | l &= ~MSR_IA32_APICBASE_BASE; | |
2009 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
2010 | wrmsr(MSR_IA32_APICBASE, l, h); | |
d5e629a6 | 2011 | } |
6e1cb38a | 2012 | |
0e078e2f TG |
2013 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
2014 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
2015 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
2016 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
2017 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
2018 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
2019 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
2020 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 2021 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
2022 | if (maxlvt >= 5) |
2023 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
2024 | #endif | |
2025 | if (maxlvt >= 4) | |
2026 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
2027 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
2028 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
2029 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
2030 | apic_write(APIC_ESR, 0); | |
2031 | apic_read(APIC_ESR); | |
2032 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
2033 | apic_write(APIC_ESR, 0); | |
2034 | apic_read(APIC_ESR); | |
92206c90 | 2035 | |
0e078e2f | 2036 | local_irq_restore(flags); |
92206c90 | 2037 | |
0e078e2f TG |
2038 | return 0; |
2039 | } | |
b8ce3359 | 2040 | |
274cfe59 CG |
2041 | /* |
2042 | * This device has no shutdown method - fully functioning local APICs | |
2043 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
2044 | */ | |
2045 | ||
0e078e2f TG |
2046 | static struct sysdev_class lapic_sysclass = { |
2047 | .name = "lapic", | |
2048 | .resume = lapic_resume, | |
2049 | .suspend = lapic_suspend, | |
2050 | }; | |
b8ce3359 | 2051 | |
0e078e2f | 2052 | static struct sys_device device_lapic = { |
e83a5fdc HS |
2053 | .id = 0, |
2054 | .cls = &lapic_sysclass, | |
0e078e2f | 2055 | }; |
b8ce3359 | 2056 | |
0e078e2f TG |
2057 | static void __cpuinit apic_pm_activate(void) |
2058 | { | |
2059 | apic_pm_state.active = 1; | |
1da177e4 LT |
2060 | } |
2061 | ||
0e078e2f | 2062 | static int __init init_lapic_sysfs(void) |
1da177e4 | 2063 | { |
0e078e2f | 2064 | int error; |
e83a5fdc | 2065 | |
0e078e2f TG |
2066 | if (!cpu_has_apic) |
2067 | return 0; | |
2068 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 2069 | |
0e078e2f TG |
2070 | error = sysdev_class_register(&lapic_sysclass); |
2071 | if (!error) | |
2072 | error = sysdev_register(&device_lapic); | |
2073 | return error; | |
1da177e4 | 2074 | } |
0e078e2f TG |
2075 | device_initcall(init_lapic_sysfs); |
2076 | ||
2077 | #else /* CONFIG_PM */ | |
2078 | ||
2079 | static void apic_pm_activate(void) { } | |
2080 | ||
2081 | #endif /* CONFIG_PM */ | |
1da177e4 | 2082 | |
f28c0ae2 | 2083 | #ifdef CONFIG_X86_64 |
1da177e4 | 2084 | /* |
f8bf3c65 | 2085 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
2086 | * |
2087 | * Thus far, the major user of this is IBM's Summit2 series: | |
2088 | * | |
637029c6 | 2089 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
2090 | * multi-chassis. Use available data to take a good guess. |
2091 | * If in doubt, go HPET. | |
2092 | */ | |
f8bf3c65 | 2093 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
2094 | { |
2095 | int i, clusters, zeros; | |
2096 | unsigned id; | |
322850af | 2097 | u16 *bios_cpu_apicid; |
1da177e4 LT |
2098 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
2099 | ||
322850af YL |
2100 | /* |
2101 | * there is not this kind of box with AMD CPU yet. | |
2102 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
2103 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 2104 | * vsmp box still need checking... |
322850af | 2105 | */ |
1cb68487 | 2106 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
2107 | return 0; |
2108 | ||
23ca4bba | 2109 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 2110 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 | 2111 | |
168ef543 | 2112 | for (i = 0; i < nr_cpu_ids; i++) { |
e8c10ef9 | 2113 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
2114 | if (bios_cpu_apicid) { |
2115 | id = bios_cpu_apicid[i]; | |
e423e33e | 2116 | } else if (i < nr_cpu_ids) { |
e8c10ef9 | 2117 | if (cpu_present(i)) |
2118 | id = per_cpu(x86_bios_cpu_apicid, i); | |
2119 | else | |
2120 | continue; | |
e423e33e | 2121 | } else |
e8c10ef9 | 2122 | break; |
2123 | ||
1da177e4 LT |
2124 | if (id != BAD_APICID) |
2125 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
2126 | } | |
2127 | ||
2128 | /* Problem: Partially populated chassis may not have CPUs in some of | |
2129 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 2130 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
2131 | * Since clusters are allocated sequentially, count zeros only if | |
2132 | * they are bounded by ones. | |
1da177e4 LT |
2133 | */ |
2134 | clusters = 0; | |
2135 | zeros = 0; | |
2136 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
2137 | if (test_bit(i, clustermap)) { | |
2138 | clusters += 1 + zeros; | |
2139 | zeros = 0; | |
2140 | } else | |
2141 | ++zeros; | |
2142 | } | |
2143 | ||
1cb68487 RT |
2144 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
2145 | * not guaranteed to be synced between boards | |
2146 | */ | |
2147 | if (is_vsmp_box() && clusters > 1) | |
2148 | return 1; | |
2149 | ||
1da177e4 | 2150 | /* |
f8bf3c65 | 2151 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
2152 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
2153 | * out, but AFAIK this will work even for them. | |
2154 | */ | |
2155 | return (clusters > 2); | |
2156 | } | |
f28c0ae2 | 2157 | #endif |
1da177e4 LT |
2158 | |
2159 | /* | |
0e078e2f | 2160 | * APIC command line parameters |
1da177e4 | 2161 | */ |
789fa735 | 2162 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 2163 | { |
1da177e4 | 2164 | disable_apic = 1; |
9175fc06 | 2165 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
2166 | return 0; |
2167 | } | |
2168 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 2169 | |
2c8c0e6b | 2170 | /* same as disableapic, for compatibility */ |
789fa735 | 2171 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 2172 | { |
789fa735 | 2173 | return setup_disableapic(arg); |
6935d1f9 | 2174 | } |
2c8c0e6b | 2175 | early_param("nolapic", setup_nolapic); |
1da177e4 | 2176 | |
2e7c2838 LT |
2177 | static int __init parse_lapic_timer_c2_ok(char *arg) |
2178 | { | |
2179 | local_apic_timer_c2_ok = 1; | |
2180 | return 0; | |
2181 | } | |
2182 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
2183 | ||
36fef094 | 2184 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 2185 | { |
1da177e4 | 2186 | disable_apic_timer = 1; |
36fef094 | 2187 | return 0; |
6935d1f9 | 2188 | } |
36fef094 CG |
2189 | early_param("noapictimer", parse_disable_apic_timer); |
2190 | ||
2191 | static int __init parse_nolapic_timer(char *arg) | |
2192 | { | |
2193 | disable_apic_timer = 1; | |
2194 | return 0; | |
6935d1f9 | 2195 | } |
36fef094 | 2196 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 2197 | |
79af9bec CG |
2198 | static int __init apic_set_verbosity(char *arg) |
2199 | { | |
2200 | if (!arg) { | |
2201 | #ifdef CONFIG_X86_64 | |
2202 | skip_ioapic_setup = 0; | |
79af9bec CG |
2203 | return 0; |
2204 | #endif | |
2205 | return -EINVAL; | |
2206 | } | |
2207 | ||
2208 | if (strcmp("debug", arg) == 0) | |
2209 | apic_verbosity = APIC_DEBUG; | |
2210 | else if (strcmp("verbose", arg) == 0) | |
2211 | apic_verbosity = APIC_VERBOSE; | |
2212 | else { | |
ba21ebb6 | 2213 | pr_warning("APIC Verbosity level %s not recognised" |
79af9bec CG |
2214 | " use apic=verbose or apic=debug\n", arg); |
2215 | return -EINVAL; | |
2216 | } | |
2217 | ||
2218 | return 0; | |
2219 | } | |
2220 | early_param("apic", apic_set_verbosity); | |
2221 | ||
1e934dda YL |
2222 | static int __init lapic_insert_resource(void) |
2223 | { | |
2224 | if (!apic_phys) | |
2225 | return -1; | |
2226 | ||
2227 | /* Put local APIC into the resource map. */ | |
2228 | lapic_resource.start = apic_phys; | |
2229 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
2230 | insert_resource(&iomem_resource, &lapic_resource); | |
2231 | ||
2232 | return 0; | |
2233 | } | |
2234 | ||
2235 | /* | |
2236 | * need call insert after e820_reserve_resources() | |
2237 | * that is using request_resource | |
2238 | */ | |
2239 | late_initcall(lapic_insert_resource); |