Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
39928722 | 26 | #include <linux/ioport.h> |
ba7eda4c | 27 | #include <linux/clockchips.h> |
70a20025 | 28 | #include <linux/acpi_pmtmr.h> |
e83a5fdc | 29 | #include <linux/module.h> |
1da177e4 LT |
30 | |
31 | #include <asm/atomic.h> | |
32 | #include <asm/smp.h> | |
33 | #include <asm/mtrr.h> | |
34 | #include <asm/mpspec.h> | |
e83a5fdc | 35 | #include <asm/hpet.h> |
1da177e4 LT |
36 | #include <asm/pgalloc.h> |
37 | #include <asm/mach_apic.h> | |
75152114 | 38 | #include <asm/nmi.h> |
95833c83 | 39 | #include <asm/idle.h> |
73dea47f AK |
40 | #include <asm/proto.h> |
41 | #include <asm/timex.h> | |
2c8c0e6b | 42 | #include <asm/apic.h> |
1da177e4 | 43 | |
fb79d22e | 44 | int disable_apic_timer __cpuinitdata; |
bc1d99c1 | 45 | static int apic_calibrate_pmtmr __initdata; |
0e078e2f | 46 | int disable_apic; |
1da177e4 | 47 | |
e83a5fdc | 48 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
49 | int local_apic_timer_c2_ok; |
50 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
51 | ||
e83a5fdc HS |
52 | /* |
53 | * Debug level, exported for io_apic.c | |
54 | */ | |
55 | int apic_verbosity; | |
56 | ||
39928722 AD |
57 | static struct resource lapic_resource = { |
58 | .name = "Local APIC", | |
59 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
60 | }; | |
61 | ||
d03030e9 TG |
62 | static unsigned int calibration_result; |
63 | ||
ba7eda4c TG |
64 | static int lapic_next_event(unsigned long delta, |
65 | struct clock_event_device *evt); | |
66 | static void lapic_timer_setup(enum clock_event_mode mode, | |
67 | struct clock_event_device *evt); | |
ba7eda4c | 68 | static void lapic_timer_broadcast(cpumask_t mask); |
0e078e2f | 69 | static void apic_pm_activate(void); |
ba7eda4c TG |
70 | |
71 | static struct clock_event_device lapic_clockevent = { | |
72 | .name = "lapic", | |
73 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
74 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
75 | .shift = 32, | |
76 | .set_mode = lapic_timer_setup, | |
77 | .set_next_event = lapic_next_event, | |
78 | .broadcast = lapic_timer_broadcast, | |
79 | .rating = 100, | |
80 | .irq = -1, | |
81 | }; | |
82 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
83 | ||
0e078e2f TG |
84 | /* |
85 | * Get the LAPIC version | |
86 | */ | |
87 | static inline int lapic_get_version(void) | |
ba7eda4c | 88 | { |
0e078e2f | 89 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
90 | } |
91 | ||
0e078e2f TG |
92 | /* |
93 | * Check, if the APIC is integrated or a seperate chip | |
94 | */ | |
95 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 96 | { |
0e078e2f | 97 | return 1; |
ba7eda4c TG |
98 | } |
99 | ||
100 | /* | |
0e078e2f | 101 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 102 | */ |
0e078e2f | 103 | static int modern_apic(void) |
ba7eda4c | 104 | { |
0e078e2f TG |
105 | /* AMD systems use old APIC versions, so check the CPU */ |
106 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
107 | boot_cpu_data.x86 >= 0xf) | |
108 | return 1; | |
109 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
110 | } |
111 | ||
8339e9fb FLV |
112 | void apic_wait_icr_idle(void) |
113 | { | |
114 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
115 | cpu_relax(); | |
116 | } | |
117 | ||
3c6bb07a | 118 | u32 safe_apic_wait_icr_idle(void) |
8339e9fb | 119 | { |
3c6bb07a | 120 | u32 send_status; |
8339e9fb FLV |
121 | int timeout; |
122 | ||
123 | timeout = 0; | |
124 | do { | |
125 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
126 | if (!send_status) | |
127 | break; | |
128 | udelay(100); | |
129 | } while (timeout++ < 1000); | |
130 | ||
131 | return send_status; | |
132 | } | |
133 | ||
0e078e2f TG |
134 | /** |
135 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
136 | */ | |
e9427101 | 137 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 138 | { |
11a8e778 | 139 | unsigned int v; |
6935d1f9 TG |
140 | |
141 | /* unmask and set to NMI */ | |
142 | v = APIC_DM_NMI; | |
11a8e778 | 143 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
144 | } |
145 | ||
0e078e2f TG |
146 | /** |
147 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
148 | */ | |
37e650c7 | 149 | int lapic_get_maxlvt(void) |
1da177e4 | 150 | { |
11a8e778 | 151 | unsigned int v, maxlvt; |
1da177e4 LT |
152 | |
153 | v = apic_read(APIC_LVR); | |
1da177e4 LT |
154 | maxlvt = GET_APIC_MAXLVT(v); |
155 | return maxlvt; | |
156 | } | |
157 | ||
0e078e2f TG |
158 | /* |
159 | * This function sets up the local APIC timer, with a timeout of | |
160 | * 'clocks' APIC bus clock. During calibration we actually call | |
161 | * this function twice on the boot CPU, once with a bogus timeout | |
162 | * value, second time for real. The other (noncalibrating) CPUs | |
163 | * call this function only once, with the real, calibrated value. | |
164 | * | |
165 | * We do reads before writes even if unnecessary, to get around the | |
166 | * P5 APIC double write bug. | |
167 | */ | |
168 | ||
169 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) | |
1da177e4 | 170 | { |
0e078e2f | 171 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 172 | |
0e078e2f TG |
173 | lvtt_value = LOCAL_TIMER_VECTOR; |
174 | if (!oneshot) | |
175 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
176 | if (!irqen) | |
177 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 178 | |
0e078e2f | 179 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
180 | |
181 | /* | |
0e078e2f | 182 | * Divide PICLK by 16 |
1da177e4 | 183 | */ |
0e078e2f TG |
184 | tmp_value = apic_read(APIC_TDCR); |
185 | apic_write(APIC_TDCR, (tmp_value | |
186 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
187 | | APIC_TDR_DIV_16); | |
188 | ||
189 | if (!oneshot) | |
190 | apic_write(APIC_TMICT, clocks); | |
1da177e4 LT |
191 | } |
192 | ||
0e078e2f | 193 | /* |
7b83dae7 RR |
194 | * Setup extended LVT, AMD specific (K8, family 10h) |
195 | * | |
196 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
197 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
0e078e2f | 198 | */ |
7b83dae7 RR |
199 | |
200 | #define APIC_EILVT_LVTOFF_MCE 0 | |
201 | #define APIC_EILVT_LVTOFF_IBS 1 | |
202 | ||
203 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 204 | { |
7b83dae7 | 205 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 206 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 207 | |
0e078e2f | 208 | apic_write(reg, v); |
1da177e4 LT |
209 | } |
210 | ||
7b83dae7 RR |
211 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
212 | { | |
213 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
214 | return APIC_EILVT_LVTOFF_MCE; | |
215 | } | |
216 | ||
217 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
218 | { | |
219 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
220 | return APIC_EILVT_LVTOFF_IBS; | |
221 | } | |
222 | ||
0e078e2f TG |
223 | /* |
224 | * Program the next event, relative to now | |
225 | */ | |
226 | static int lapic_next_event(unsigned long delta, | |
227 | struct clock_event_device *evt) | |
1da177e4 | 228 | { |
0e078e2f TG |
229 | apic_write(APIC_TMICT, delta); |
230 | return 0; | |
1da177e4 LT |
231 | } |
232 | ||
0e078e2f TG |
233 | /* |
234 | * Setup the lapic timer in periodic or oneshot mode | |
235 | */ | |
236 | static void lapic_timer_setup(enum clock_event_mode mode, | |
237 | struct clock_event_device *evt) | |
9b7711f0 HS |
238 | { |
239 | unsigned long flags; | |
0e078e2f | 240 | unsigned int v; |
9b7711f0 | 241 | |
0e078e2f TG |
242 | /* Lapic used as dummy for broadcast ? */ |
243 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
244 | return; |
245 | ||
246 | local_irq_save(flags); | |
247 | ||
0e078e2f TG |
248 | switch (mode) { |
249 | case CLOCK_EVT_MODE_PERIODIC: | |
250 | case CLOCK_EVT_MODE_ONESHOT: | |
251 | __setup_APIC_LVTT(calibration_result, | |
252 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
253 | break; | |
254 | case CLOCK_EVT_MODE_UNUSED: | |
255 | case CLOCK_EVT_MODE_SHUTDOWN: | |
256 | v = apic_read(APIC_LVTT); | |
257 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
258 | apic_write(APIC_LVTT, v); | |
259 | break; | |
260 | case CLOCK_EVT_MODE_RESUME: | |
261 | /* Nothing to do here */ | |
262 | break; | |
263 | } | |
9b7711f0 HS |
264 | |
265 | local_irq_restore(flags); | |
266 | } | |
267 | ||
1da177e4 | 268 | /* |
0e078e2f | 269 | * Local APIC timer broadcast function |
1da177e4 | 270 | */ |
0e078e2f | 271 | static void lapic_timer_broadcast(cpumask_t mask) |
1da177e4 | 272 | { |
0e078e2f TG |
273 | #ifdef CONFIG_SMP |
274 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
275 | #endif | |
276 | } | |
1da177e4 | 277 | |
0e078e2f TG |
278 | /* |
279 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
280 | * of the boot CPU and register the clock event in the framework. | |
281 | */ | |
282 | static void setup_APIC_timer(void) | |
283 | { | |
284 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 285 | |
0e078e2f TG |
286 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
287 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
1da177e4 | 288 | |
0e078e2f TG |
289 | clockevents_register_device(levt); |
290 | } | |
1da177e4 | 291 | |
0e078e2f TG |
292 | /* |
293 | * In this function we calibrate APIC bus clocks to the external | |
294 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
295 | * to calibrate, since some later bootup code depends on getting | |
296 | * the first irq? Ugh. | |
297 | * | |
298 | * We want to do the calibration only once since we | |
299 | * want to have local timer irqs syncron. CPUs connected | |
300 | * by the same APIC bus have the very same bus frequency. | |
301 | * And we want to have irqs off anyways, no accidental | |
302 | * APIC irq that way. | |
303 | */ | |
304 | ||
305 | #define TICK_COUNT 100000000 | |
306 | ||
307 | static void __init calibrate_APIC_clock(void) | |
308 | { | |
309 | unsigned apic, apic_start; | |
310 | unsigned long tsc, tsc_start; | |
311 | int result; | |
312 | ||
313 | local_irq_disable(); | |
314 | ||
315 | /* | |
316 | * Put whatever arbitrary (but long enough) timeout | |
317 | * value into the APIC clock, we just want to get the | |
318 | * counter running for calibration. | |
319 | * | |
320 | * No interrupt enable ! | |
321 | */ | |
322 | __setup_APIC_LVTT(250000000, 0, 0); | |
323 | ||
324 | apic_start = apic_read(APIC_TMCCT); | |
325 | #ifdef CONFIG_X86_PM_TIMER | |
326 | if (apic_calibrate_pmtmr && pmtmr_ioport) { | |
327 | pmtimer_wait(5000); /* 5ms wait */ | |
328 | apic = apic_read(APIC_TMCCT); | |
329 | result = (apic_start - apic) * 1000L / 5; | |
330 | } else | |
331 | #endif | |
332 | { | |
333 | rdtscll(tsc_start); | |
334 | ||
335 | do { | |
336 | apic = apic_read(APIC_TMCCT); | |
337 | rdtscll(tsc); | |
338 | } while ((tsc - tsc_start) < TICK_COUNT && | |
339 | (apic_start - apic) < TICK_COUNT); | |
340 | ||
341 | result = (apic_start - apic) * 1000L * tsc_khz / | |
342 | (tsc - tsc_start); | |
343 | } | |
344 | ||
345 | local_irq_enable(); | |
346 | ||
347 | printk(KERN_DEBUG "APIC timer calibration result %d\n", result); | |
348 | ||
349 | printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n", | |
350 | result / 1000 / 1000, result / 1000 % 1000); | |
351 | ||
352 | /* Calculate the scaled math multiplication factor */ | |
353 | lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, 32); | |
354 | lapic_clockevent.max_delta_ns = | |
355 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
356 | lapic_clockevent.min_delta_ns = | |
357 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
358 | ||
359 | calibration_result = result / HZ; | |
360 | } | |
361 | ||
e83a5fdc HS |
362 | /* |
363 | * Setup the boot APIC | |
364 | * | |
365 | * Calibrate and verify the result. | |
366 | */ | |
0e078e2f TG |
367 | void __init setup_boot_APIC_clock(void) |
368 | { | |
369 | /* | |
370 | * The local apic timer can be disabled via the kernel commandline. | |
371 | * Register the lapic timer as a dummy clock event source on SMP | |
372 | * systems, so the broadcast mechanism is used. On UP systems simply | |
373 | * ignore it. | |
374 | */ | |
375 | if (disable_apic_timer) { | |
376 | printk(KERN_INFO "Disabling APIC timer\n"); | |
377 | /* No broadcast on UP ! */ | |
9d09951d TG |
378 | if (num_possible_cpus() > 1) { |
379 | lapic_clockevent.mult = 1; | |
0e078e2f | 380 | setup_APIC_timer(); |
9d09951d | 381 | } |
0e078e2f TG |
382 | return; |
383 | } | |
384 | ||
385 | printk(KERN_INFO "Using local APIC timer interrupts.\n"); | |
386 | calibrate_APIC_clock(); | |
387 | ||
c2b84b30 TG |
388 | /* |
389 | * Do a sanity check on the APIC calibration result | |
390 | */ | |
391 | if (calibration_result < (1000000 / HZ)) { | |
392 | printk(KERN_WARNING | |
393 | "APIC frequency too slow, disabling apic timer\n"); | |
394 | /* No broadcast on UP ! */ | |
395 | if (num_possible_cpus() > 1) | |
396 | setup_APIC_timer(); | |
397 | return; | |
398 | } | |
399 | ||
0e078e2f TG |
400 | /* |
401 | * If nmi_watchdog is set to IO_APIC, we need the | |
402 | * PIT/HPET going. Otherwise register lapic as a dummy | |
403 | * device. | |
404 | */ | |
405 | if (nmi_watchdog != NMI_IO_APIC) | |
406 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
407 | else | |
408 | printk(KERN_WARNING "APIC timer registered as dummy," | |
409 | " due to nmi_watchdog=1!\n"); | |
410 | ||
411 | setup_APIC_timer(); | |
412 | } | |
413 | ||
414 | /* | |
415 | * AMD C1E enabled CPUs have a real nasty problem: Some BIOSes set the | |
416 | * C1E flag only in the secondary CPU, so when we detect the wreckage | |
417 | * we already have enabled the boot CPU local apic timer. Check, if | |
418 | * disable_apic_timer is set and the DUMMY flag is cleared. If yes, | |
419 | * set the DUMMY flag again and force the broadcast mode in the | |
420 | * clockevents layer. | |
421 | */ | |
422 | void __cpuinit check_boot_apic_timer_broadcast(void) | |
423 | { | |
424 | if (!disable_apic_timer || | |
425 | (lapic_clockevent.features & CLOCK_EVT_FEAT_DUMMY)) | |
426 | return; | |
427 | ||
428 | printk(KERN_INFO "AMD C1E detected late. Force timer broadcast.\n"); | |
429 | lapic_clockevent.features |= CLOCK_EVT_FEAT_DUMMY; | |
430 | ||
431 | local_irq_enable(); | |
432 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, &boot_cpu_id); | |
433 | local_irq_disable(); | |
434 | } | |
435 | ||
436 | void __cpuinit setup_secondary_APIC_clock(void) | |
437 | { | |
438 | check_boot_apic_timer_broadcast(); | |
439 | setup_APIC_timer(); | |
440 | } | |
441 | ||
442 | /* | |
443 | * The guts of the apic timer interrupt | |
444 | */ | |
445 | static void local_apic_timer_interrupt(void) | |
446 | { | |
447 | int cpu = smp_processor_id(); | |
448 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
449 | ||
450 | /* | |
451 | * Normally we should not be here till LAPIC has been initialized but | |
452 | * in some cases like kdump, its possible that there is a pending LAPIC | |
453 | * timer interrupt from previous kernel's context and is delivered in | |
454 | * new kernel the moment interrupts are enabled. | |
455 | * | |
456 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
457 | * its possible that when we get here evt->event_handler is NULL. | |
458 | * Check for event_handler being NULL and discard the interrupt as | |
459 | * spurious. | |
460 | */ | |
461 | if (!evt->event_handler) { | |
462 | printk(KERN_WARNING | |
463 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
464 | /* Switch it off */ | |
465 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
466 | return; | |
467 | } | |
468 | ||
469 | /* | |
470 | * the NMI deadlock-detector uses this. | |
471 | */ | |
472 | add_pda(apic_timer_irqs, 1); | |
473 | ||
474 | evt->event_handler(evt); | |
475 | } | |
476 | ||
477 | /* | |
478 | * Local APIC timer interrupt. This is the most natural way for doing | |
479 | * local interrupts, but local timer interrupts can be emulated by | |
480 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
481 | * | |
482 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
483 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
484 | */ | |
485 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
486 | { | |
487 | struct pt_regs *old_regs = set_irq_regs(regs); | |
488 | ||
489 | /* | |
490 | * NOTE! We'd better ACK the irq immediately, | |
491 | * because timer handling can be slow. | |
492 | */ | |
493 | ack_APIC_irq(); | |
494 | /* | |
495 | * update_process_times() expects us to have done irq_enter(). | |
496 | * Besides, if we don't timer interrupts ignore the global | |
497 | * interrupt lock, which is the WrongThing (tm) to do. | |
498 | */ | |
499 | exit_idle(); | |
500 | irq_enter(); | |
501 | local_apic_timer_interrupt(); | |
502 | irq_exit(); | |
503 | set_irq_regs(old_regs); | |
504 | } | |
505 | ||
506 | int setup_profiling_timer(unsigned int multiplier) | |
507 | { | |
508 | return -EINVAL; | |
509 | } | |
510 | ||
511 | ||
512 | /* | |
513 | * Local APIC start and shutdown | |
514 | */ | |
515 | ||
516 | /** | |
517 | * clear_local_APIC - shutdown the local APIC | |
518 | * | |
519 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
520 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
521 | * leftovers during boot. | |
522 | */ | |
523 | void clear_local_APIC(void) | |
524 | { | |
525 | int maxlvt = lapic_get_maxlvt(); | |
526 | u32 v; | |
527 | ||
528 | /* | |
529 | * Masking an LVT entry can trigger a local APIC error | |
530 | * if the vector is zero. Mask LVTERR first to prevent this. | |
531 | */ | |
532 | if (maxlvt >= 3) { | |
533 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
534 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
535 | } | |
536 | /* | |
537 | * Careful: we have to set masks only first to deassert | |
538 | * any level-triggered sources. | |
539 | */ | |
540 | v = apic_read(APIC_LVTT); | |
541 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
542 | v = apic_read(APIC_LVT0); | |
543 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
544 | v = apic_read(APIC_LVT1); | |
545 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
546 | if (maxlvt >= 4) { | |
547 | v = apic_read(APIC_LVTPC); | |
548 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
549 | } | |
550 | ||
551 | /* | |
552 | * Clean APIC state for other OSs: | |
553 | */ | |
554 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
555 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
556 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
557 | if (maxlvt >= 3) | |
558 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
559 | if (maxlvt >= 4) | |
560 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
561 | apic_write(APIC_ESR, 0); | |
562 | apic_read(APIC_ESR); | |
563 | } | |
564 | ||
565 | /** | |
566 | * disable_local_APIC - clear and disable the local APIC | |
567 | */ | |
568 | void disable_local_APIC(void) | |
569 | { | |
570 | unsigned int value; | |
571 | ||
572 | clear_local_APIC(); | |
573 | ||
574 | /* | |
575 | * Disable APIC (implies clearing of registers | |
576 | * for 82489DX!). | |
577 | */ | |
578 | value = apic_read(APIC_SPIV); | |
579 | value &= ~APIC_SPIV_APIC_ENABLED; | |
580 | apic_write(APIC_SPIV, value); | |
581 | } | |
582 | ||
583 | void lapic_shutdown(void) | |
584 | { | |
585 | unsigned long flags; | |
586 | ||
587 | if (!cpu_has_apic) | |
588 | return; | |
589 | ||
590 | local_irq_save(flags); | |
591 | ||
592 | disable_local_APIC(); | |
593 | ||
594 | local_irq_restore(flags); | |
595 | } | |
596 | ||
597 | /* | |
598 | * This is to verify that we're looking at a real local APIC. | |
599 | * Check these against your board if the CPUs aren't getting | |
600 | * started for no apparent reason. | |
601 | */ | |
602 | int __init verify_local_APIC(void) | |
603 | { | |
604 | unsigned int reg0, reg1; | |
605 | ||
606 | /* | |
607 | * The version register is read-only in a real APIC. | |
608 | */ | |
609 | reg0 = apic_read(APIC_LVR); | |
610 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
611 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
612 | reg1 = apic_read(APIC_LVR); | |
613 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
614 | ||
615 | /* | |
616 | * The two version reads above should print the same | |
617 | * numbers. If the second one is different, then we | |
618 | * poke at a non-APIC. | |
619 | */ | |
620 | if (reg1 != reg0) | |
621 | return 0; | |
622 | ||
623 | /* | |
624 | * Check if the version looks reasonably. | |
625 | */ | |
626 | reg1 = GET_APIC_VERSION(reg0); | |
627 | if (reg1 == 0x00 || reg1 == 0xff) | |
628 | return 0; | |
629 | reg1 = lapic_get_maxlvt(); | |
630 | if (reg1 < 0x02 || reg1 == 0xff) | |
631 | return 0; | |
632 | ||
633 | /* | |
634 | * The ID register is read/write in a real APIC. | |
635 | */ | |
636 | reg0 = apic_read(APIC_ID); | |
637 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
638 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
639 | reg1 = apic_read(APIC_ID); | |
640 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); | |
641 | apic_write(APIC_ID, reg0); | |
642 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
643 | return 0; | |
644 | ||
645 | /* | |
1da177e4 LT |
646 | * The next two are just to see if we have sane values. |
647 | * They're only really relevant if we're in Virtual Wire | |
648 | * compatibility mode, but most boxes are anymore. | |
649 | */ | |
650 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 651 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
652 | reg1 = apic_read(APIC_LVT1); |
653 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
654 | ||
655 | return 1; | |
656 | } | |
657 | ||
0e078e2f TG |
658 | /** |
659 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
660 | */ | |
1da177e4 LT |
661 | void __init sync_Arb_IDs(void) |
662 | { | |
663 | /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */ | |
0e078e2f | 664 | if (modern_apic()) |
1da177e4 LT |
665 | return; |
666 | ||
667 | /* | |
668 | * Wait for idle. | |
669 | */ | |
670 | apic_wait_icr_idle(); | |
671 | ||
672 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
11a8e778 | 673 | apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG |
1da177e4 LT |
674 | | APIC_DM_INIT); |
675 | } | |
676 | ||
1da177e4 LT |
677 | /* |
678 | * An initial setup of the virtual wire mode. | |
679 | */ | |
680 | void __init init_bsp_APIC(void) | |
681 | { | |
11a8e778 | 682 | unsigned int value; |
1da177e4 LT |
683 | |
684 | /* | |
685 | * Don't do the setup now if we have a SMP BIOS as the | |
686 | * through-I/O-APIC virtual wire mode might be active. | |
687 | */ | |
688 | if (smp_found_config || !cpu_has_apic) | |
689 | return; | |
690 | ||
691 | value = apic_read(APIC_LVR); | |
1da177e4 LT |
692 | |
693 | /* | |
694 | * Do not trust the local APIC being empty at bootup. | |
695 | */ | |
696 | clear_local_APIC(); | |
697 | ||
698 | /* | |
699 | * Enable APIC. | |
700 | */ | |
701 | value = apic_read(APIC_SPIV); | |
702 | value &= ~APIC_VECTOR_MASK; | |
703 | value |= APIC_SPIV_APIC_ENABLED; | |
704 | value |= APIC_SPIV_FOCUS_DISABLED; | |
705 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 706 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
707 | |
708 | /* | |
709 | * Set up the virtual wire mode. | |
710 | */ | |
11a8e778 | 711 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 712 | value = APIC_DM_NMI; |
11a8e778 | 713 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
714 | } |
715 | ||
0e078e2f TG |
716 | /** |
717 | * setup_local_APIC - setup the local APIC | |
718 | */ | |
719 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 720 | { |
739f33b3 | 721 | unsigned int value; |
da7ed9f9 | 722 | int i, j; |
1da177e4 | 723 | |
1da177e4 | 724 | value = apic_read(APIC_LVR); |
1da177e4 | 725 | |
fe7414a2 | 726 | BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f); |
1da177e4 LT |
727 | |
728 | /* | |
729 | * Double-check whether this APIC is really registered. | |
730 | * This is meaningless in clustered apic mode, so we skip it. | |
731 | */ | |
732 | if (!apic_id_registered()) | |
733 | BUG(); | |
734 | ||
735 | /* | |
736 | * Intel recommends to set DFR, LDR and TPR before enabling | |
737 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
738 | * document number 292116). So here it goes... | |
739 | */ | |
740 | init_apic_ldr(); | |
741 | ||
742 | /* | |
743 | * Set Task Priority to 'accept all'. We never change this | |
744 | * later on. | |
745 | */ | |
746 | value = apic_read(APIC_TASKPRI); | |
747 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 748 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 749 | |
da7ed9f9 VG |
750 | /* |
751 | * After a crash, we no longer service the interrupts and a pending | |
752 | * interrupt from previous kernel might still have ISR bit set. | |
753 | * | |
754 | * Most probably by now CPU has serviced that pending interrupt and | |
755 | * it might not have done the ack_APIC_irq() because it thought, | |
756 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
757 | * does not clear the ISR bit and cpu thinks it has already serivced | |
758 | * the interrupt. Hence a vector might get locked. It was noticed | |
759 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
760 | */ | |
761 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
762 | value = apic_read(APIC_ISR + i*0x10); | |
763 | for (j = 31; j >= 0; j--) { | |
764 | if (value & (1<<j)) | |
765 | ack_APIC_irq(); | |
766 | } | |
767 | } | |
768 | ||
1da177e4 LT |
769 | /* |
770 | * Now that we are all set up, enable the APIC | |
771 | */ | |
772 | value = apic_read(APIC_SPIV); | |
773 | value &= ~APIC_VECTOR_MASK; | |
774 | /* | |
775 | * Enable APIC | |
776 | */ | |
777 | value |= APIC_SPIV_APIC_ENABLED; | |
778 | ||
3f14c746 AK |
779 | /* We always use processor focus */ |
780 | ||
1da177e4 LT |
781 | /* |
782 | * Set spurious IRQ vector | |
783 | */ | |
784 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 785 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
786 | |
787 | /* | |
788 | * Set up LVT0, LVT1: | |
789 | * | |
790 | * set up through-local-APIC on the BP's LINT0. This is not | |
791 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
792 | * we delegate interrupts to the 8259A. | |
793 | */ | |
794 | /* | |
795 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
796 | */ | |
797 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
a8fcf1a2 | 798 | if (!smp_processor_id() && !value) { |
1da177e4 | 799 | value = APIC_DM_EXTINT; |
bc1d99c1 CW |
800 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
801 | smp_processor_id()); | |
1da177e4 LT |
802 | } else { |
803 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 CW |
804 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
805 | smp_processor_id()); | |
1da177e4 | 806 | } |
11a8e778 | 807 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
808 | |
809 | /* | |
810 | * only the BP should see the LINT1 NMI signal, obviously. | |
811 | */ | |
812 | if (!smp_processor_id()) | |
813 | value = APIC_DM_NMI; | |
814 | else | |
815 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
11a8e778 | 816 | apic_write(APIC_LVT1, value); |
739f33b3 | 817 | } |
1da177e4 | 818 | |
739f33b3 AK |
819 | void __cpuinit lapic_setup_esr(void) |
820 | { | |
821 | unsigned maxlvt = lapic_get_maxlvt(); | |
822 | ||
823 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR); | |
1c69524c | 824 | /* |
739f33b3 | 825 | * spec says clear errors after enabling vector. |
1c69524c | 826 | */ |
739f33b3 AK |
827 | if (maxlvt > 3) |
828 | apic_write(APIC_ESR, 0); | |
829 | } | |
1da177e4 | 830 | |
739f33b3 AK |
831 | void __cpuinit end_local_APIC_setup(void) |
832 | { | |
833 | lapic_setup_esr(); | |
1da177e4 | 834 | nmi_watchdog_default(); |
f2802e7f | 835 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 836 | apic_pm_activate(); |
1da177e4 | 837 | } |
1da177e4 LT |
838 | |
839 | /* | |
840 | * Detect and enable local APICs on non-SMP boards. | |
841 | * Original code written by Keir Fraser. | |
842 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 843 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 844 | */ |
0e078e2f | 845 | static int __init detect_init_APIC(void) |
1da177e4 LT |
846 | { |
847 | if (!cpu_has_apic) { | |
848 | printk(KERN_INFO "No local APIC present\n"); | |
849 | return -1; | |
850 | } | |
851 | ||
852 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
853 | boot_cpu_id = 0; | |
854 | return 0; | |
855 | } | |
856 | ||
0e078e2f TG |
857 | /** |
858 | * init_apic_mappings - initialize APIC mappings | |
859 | */ | |
1da177e4 LT |
860 | void __init init_apic_mappings(void) |
861 | { | |
862 | unsigned long apic_phys; | |
863 | ||
864 | /* | |
865 | * If no local APIC can be found then set up a fake all | |
866 | * zeroes page to simulate the local APIC and another | |
867 | * one for the IO-APIC. | |
868 | */ | |
869 | if (!smp_found_config && detect_init_APIC()) { | |
870 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
871 | apic_phys = __pa(apic_phys); | |
872 | } else | |
873 | apic_phys = mp_lapic_addr; | |
874 | ||
875 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
7ffeeb1e YL |
876 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
877 | APIC_BASE, apic_phys); | |
1da177e4 | 878 | |
39928722 AD |
879 | /* Put local APIC into the resource map. */ |
880 | lapic_resource.start = apic_phys; | |
881 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
882 | insert_resource(&iomem_resource, &lapic_resource); | |
883 | ||
1da177e4 LT |
884 | /* |
885 | * Fetch the APIC ID of the BSP in case we have a | |
886 | * default configuration (or the MP table is broken). | |
887 | */ | |
1d3fbbf9 | 888 | boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID)); |
1da177e4 LT |
889 | } |
890 | ||
891 | /* | |
0e078e2f TG |
892 | * This initializes the IO-APIC and APIC hardware if this is |
893 | * a UP kernel. | |
1da177e4 | 894 | */ |
0e078e2f | 895 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 896 | { |
0e078e2f TG |
897 | if (disable_apic) { |
898 | printk(KERN_INFO "Apic disabled\n"); | |
899 | return -1; | |
900 | } | |
901 | if (!cpu_has_apic) { | |
902 | disable_apic = 1; | |
903 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
904 | return -1; | |
905 | } | |
1da177e4 | 906 | |
0e078e2f | 907 | verify_local_APIC(); |
1da177e4 | 908 | |
0e078e2f TG |
909 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id); |
910 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_id)); | |
1da177e4 | 911 | |
0e078e2f | 912 | setup_local_APIC(); |
1da177e4 | 913 | |
739f33b3 AK |
914 | /* |
915 | * Now enable IO-APICs, actually call clear_IO_APIC | |
916 | * We need clear_IO_APIC before enabling vector on BP | |
917 | */ | |
918 | if (!skip_ioapic_setup && nr_ioapics) | |
919 | enable_IO_APIC(); | |
920 | ||
921 | end_local_APIC_setup(); | |
922 | ||
0e078e2f TG |
923 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
924 | setup_IO_APIC(); | |
925 | else | |
926 | nr_ioapics = 0; | |
927 | setup_boot_APIC_clock(); | |
928 | check_nmi_watchdog(); | |
929 | return 0; | |
1da177e4 LT |
930 | } |
931 | ||
932 | /* | |
0e078e2f | 933 | * Local APIC interrupts |
1da177e4 LT |
934 | */ |
935 | ||
0e078e2f TG |
936 | /* |
937 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
938 | */ | |
939 | asmlinkage void smp_spurious_interrupt(void) | |
1da177e4 | 940 | { |
0e078e2f TG |
941 | unsigned int v; |
942 | exit_idle(); | |
943 | irq_enter(); | |
1da177e4 | 944 | /* |
0e078e2f TG |
945 | * Check if this really is a spurious interrupt and ACK it |
946 | * if it is a vectored one. Just in case... | |
947 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 948 | */ |
0e078e2f TG |
949 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
950 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
951 | ack_APIC_irq(); | |
c4d58cbd | 952 | |
0e078e2f TG |
953 | add_pda(irq_spurious_count, 1); |
954 | irq_exit(); | |
955 | } | |
1da177e4 | 956 | |
0e078e2f TG |
957 | /* |
958 | * This interrupt should never happen with our APIC/SMP architecture | |
959 | */ | |
960 | asmlinkage void smp_error_interrupt(void) | |
961 | { | |
962 | unsigned int v, v1; | |
1da177e4 | 963 | |
0e078e2f TG |
964 | exit_idle(); |
965 | irq_enter(); | |
966 | /* First tickle the hardware, only then report what went on. -- REW */ | |
967 | v = apic_read(APIC_ESR); | |
968 | apic_write(APIC_ESR, 0); | |
969 | v1 = apic_read(APIC_ESR); | |
970 | ack_APIC_irq(); | |
971 | atomic_inc(&irq_err_count); | |
ba7eda4c | 972 | |
0e078e2f TG |
973 | /* Here is what the APIC error bits mean: |
974 | 0: Send CS error | |
975 | 1: Receive CS error | |
976 | 2: Send accept error | |
977 | 3: Receive accept error | |
978 | 4: Reserved | |
979 | 5: Send illegal vector | |
980 | 6: Received illegal vector | |
981 | 7: Illegal register address | |
982 | */ | |
983 | printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | |
984 | smp_processor_id(), v , v1); | |
985 | irq_exit(); | |
1da177e4 LT |
986 | } |
987 | ||
0e078e2f | 988 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 989 | { |
0e078e2f TG |
990 | /* Go back to Virtual Wire compatibility mode */ |
991 | unsigned long value; | |
1da177e4 | 992 | |
0e078e2f TG |
993 | /* For the spurious interrupt use vector F, and enable it */ |
994 | value = apic_read(APIC_SPIV); | |
995 | value &= ~APIC_VECTOR_MASK; | |
996 | value |= APIC_SPIV_APIC_ENABLED; | |
997 | value |= 0xf; | |
998 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 999 | |
0e078e2f TG |
1000 | if (!virt_wire_setup) { |
1001 | /* | |
1002 | * For LVT0 make it edge triggered, active high, | |
1003 | * external and enabled | |
1004 | */ | |
1005 | value = apic_read(APIC_LVT0); | |
1006 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1007 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1008 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1009 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1010 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1011 | apic_write(APIC_LVT0, value); | |
1012 | } else { | |
1013 | /* Disable LVT0 */ | |
1014 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1015 | } | |
b8ce3359 | 1016 | |
0e078e2f TG |
1017 | /* For LVT1 make it edge triggered, active high, nmi and enabled */ |
1018 | value = apic_read(APIC_LVT1); | |
1019 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1020 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1021 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1022 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1023 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1024 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1025 | } |
1026 | ||
89039b37 | 1027 | /* |
0e078e2f | 1028 | * Power management |
89039b37 | 1029 | */ |
0e078e2f TG |
1030 | #ifdef CONFIG_PM |
1031 | ||
1032 | static struct { | |
1033 | /* 'active' is true if the local APIC was enabled by us and | |
1034 | not the BIOS; this signifies that we are also responsible | |
1035 | for disabling it before entering apm/acpi suspend */ | |
1036 | int active; | |
1037 | /* r/w apic fields */ | |
1038 | unsigned int apic_id; | |
1039 | unsigned int apic_taskpri; | |
1040 | unsigned int apic_ldr; | |
1041 | unsigned int apic_dfr; | |
1042 | unsigned int apic_spiv; | |
1043 | unsigned int apic_lvtt; | |
1044 | unsigned int apic_lvtpc; | |
1045 | unsigned int apic_lvt0; | |
1046 | unsigned int apic_lvt1; | |
1047 | unsigned int apic_lvterr; | |
1048 | unsigned int apic_tmict; | |
1049 | unsigned int apic_tdcr; | |
1050 | unsigned int apic_thmr; | |
1051 | } apic_pm_state; | |
1052 | ||
1053 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1054 | { | |
1055 | unsigned long flags; | |
1056 | int maxlvt; | |
89039b37 | 1057 | |
0e078e2f TG |
1058 | if (!apic_pm_state.active) |
1059 | return 0; | |
89039b37 | 1060 | |
0e078e2f | 1061 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1062 | |
0e078e2f TG |
1063 | apic_pm_state.apic_id = apic_read(APIC_ID); |
1064 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
1065 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1066 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1067 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1068 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1069 | if (maxlvt >= 4) | |
1070 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1071 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1072 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1073 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1074 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1075 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
1076 | #ifdef CONFIG_X86_MCE_INTEL | |
1077 | if (maxlvt >= 5) | |
1078 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1079 | #endif | |
1080 | local_irq_save(flags); | |
1081 | disable_local_APIC(); | |
1082 | local_irq_restore(flags); | |
1083 | return 0; | |
1da177e4 LT |
1084 | } |
1085 | ||
0e078e2f | 1086 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1087 | { |
0e078e2f TG |
1088 | unsigned int l, h; |
1089 | unsigned long flags; | |
1090 | int maxlvt; | |
1da177e4 | 1091 | |
0e078e2f TG |
1092 | if (!apic_pm_state.active) |
1093 | return 0; | |
89b831ef | 1094 | |
0e078e2f | 1095 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 1096 | |
0e078e2f TG |
1097 | local_irq_save(flags); |
1098 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1099 | l &= ~MSR_IA32_APICBASE_BASE; | |
1100 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1101 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1102 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
1103 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1104 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1105 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1106 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1107 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1108 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1109 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
1110 | #ifdef CONFIG_X86_MCE_INTEL | |
1111 | if (maxlvt >= 5) | |
1112 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1113 | #endif | |
1114 | if (maxlvt >= 4) | |
1115 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1116 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1117 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1118 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1119 | apic_write(APIC_ESR, 0); | |
1120 | apic_read(APIC_ESR); | |
1121 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1122 | apic_write(APIC_ESR, 0); | |
1123 | apic_read(APIC_ESR); | |
1124 | local_irq_restore(flags); | |
1125 | return 0; | |
1126 | } | |
b8ce3359 | 1127 | |
0e078e2f TG |
1128 | static struct sysdev_class lapic_sysclass = { |
1129 | .name = "lapic", | |
1130 | .resume = lapic_resume, | |
1131 | .suspend = lapic_suspend, | |
1132 | }; | |
b8ce3359 | 1133 | |
0e078e2f | 1134 | static struct sys_device device_lapic = { |
e83a5fdc HS |
1135 | .id = 0, |
1136 | .cls = &lapic_sysclass, | |
0e078e2f | 1137 | }; |
b8ce3359 | 1138 | |
0e078e2f TG |
1139 | static void __cpuinit apic_pm_activate(void) |
1140 | { | |
1141 | apic_pm_state.active = 1; | |
1da177e4 LT |
1142 | } |
1143 | ||
0e078e2f | 1144 | static int __init init_lapic_sysfs(void) |
1da177e4 | 1145 | { |
0e078e2f | 1146 | int error; |
e83a5fdc | 1147 | |
0e078e2f TG |
1148 | if (!cpu_has_apic) |
1149 | return 0; | |
1150 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 1151 | |
0e078e2f TG |
1152 | error = sysdev_class_register(&lapic_sysclass); |
1153 | if (!error) | |
1154 | error = sysdev_register(&device_lapic); | |
1155 | return error; | |
1da177e4 | 1156 | } |
0e078e2f TG |
1157 | device_initcall(init_lapic_sysfs); |
1158 | ||
1159 | #else /* CONFIG_PM */ | |
1160 | ||
1161 | static void apic_pm_activate(void) { } | |
1162 | ||
1163 | #endif /* CONFIG_PM */ | |
1da177e4 LT |
1164 | |
1165 | /* | |
f8bf3c65 | 1166 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
1167 | * |
1168 | * Thus far, the major user of this is IBM's Summit2 series: | |
1169 | * | |
637029c6 | 1170 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
1171 | * multi-chassis. Use available data to take a good guess. |
1172 | * If in doubt, go HPET. | |
1173 | */ | |
f8bf3c65 | 1174 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
1175 | { |
1176 | int i, clusters, zeros; | |
1177 | unsigned id; | |
1178 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); | |
1179 | ||
376ec33f | 1180 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 LT |
1181 | |
1182 | for (i = 0; i < NR_CPUS; i++) { | |
1183 | id = bios_cpu_apicid[i]; | |
1184 | if (id != BAD_APICID) | |
1185 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
1186 | } | |
1187 | ||
1188 | /* Problem: Partially populated chassis may not have CPUs in some of | |
1189 | * the APIC clusters they have been allocated. Only present CPUs have | |
1190 | * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since | |
1191 | * clusters are allocated sequentially, count zeros only if they are | |
1192 | * bounded by ones. | |
1193 | */ | |
1194 | clusters = 0; | |
1195 | zeros = 0; | |
1196 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
1197 | if (test_bit(i, clustermap)) { | |
1198 | clusters += 1 + zeros; | |
1199 | zeros = 0; | |
1200 | } else | |
1201 | ++zeros; | |
1202 | } | |
1203 | ||
1204 | /* | |
f8bf3c65 | 1205 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
1206 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
1207 | * out, but AFAIK this will work even for them. | |
1208 | */ | |
1209 | return (clusters > 2); | |
1210 | } | |
1211 | ||
1212 | /* | |
0e078e2f | 1213 | * APIC command line parameters |
1da177e4 | 1214 | */ |
0e078e2f | 1215 | static int __init apic_set_verbosity(char *str) |
1da177e4 | 1216 | { |
0e078e2f TG |
1217 | if (str == NULL) { |
1218 | skip_ioapic_setup = 0; | |
1219 | ioapic_force = 1; | |
1220 | return 0; | |
1da177e4 | 1221 | } |
0e078e2f TG |
1222 | if (strcmp("debug", str) == 0) |
1223 | apic_verbosity = APIC_DEBUG; | |
1224 | else if (strcmp("verbose", str) == 0) | |
1225 | apic_verbosity = APIC_VERBOSE; | |
1226 | else { | |
1227 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
1228 | " use apic=verbose or apic=debug\n", str); | |
1229 | return -EINVAL; | |
1da177e4 LT |
1230 | } |
1231 | ||
1da177e4 LT |
1232 | return 0; |
1233 | } | |
0e078e2f | 1234 | early_param("apic", apic_set_verbosity); |
1da177e4 | 1235 | |
6935d1f9 TG |
1236 | static __init int setup_disableapic(char *str) |
1237 | { | |
1da177e4 | 1238 | disable_apic = 1; |
53756d37 | 1239 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
2c8c0e6b AK |
1240 | return 0; |
1241 | } | |
1242 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 1243 | |
2c8c0e6b | 1244 | /* same as disableapic, for compatibility */ |
6935d1f9 TG |
1245 | static __init int setup_nolapic(char *str) |
1246 | { | |
2c8c0e6b | 1247 | return setup_disableapic(str); |
6935d1f9 | 1248 | } |
2c8c0e6b | 1249 | early_param("nolapic", setup_nolapic); |
1da177e4 | 1250 | |
2e7c2838 LT |
1251 | static int __init parse_lapic_timer_c2_ok(char *arg) |
1252 | { | |
1253 | local_apic_timer_c2_ok = 1; | |
1254 | return 0; | |
1255 | } | |
1256 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1257 | ||
6935d1f9 TG |
1258 | static __init int setup_noapictimer(char *str) |
1259 | { | |
73dea47f | 1260 | if (str[0] != ' ' && str[0] != 0) |
9b41046c | 1261 | return 0; |
1da177e4 | 1262 | disable_apic_timer = 1; |
9b41046c | 1263 | return 1; |
6935d1f9 | 1264 | } |
9f75e9b7 | 1265 | __setup("noapictimer", setup_noapictimer); |
73dea47f | 1266 | |
0c3749c4 AK |
1267 | static __init int setup_apicpmtimer(char *s) |
1268 | { | |
1269 | apic_calibrate_pmtmr = 1; | |
7fd67843 | 1270 | notsc_setup(NULL); |
b8ce3359 | 1271 | return 0; |
0c3749c4 AK |
1272 | } |
1273 | __setup("apicpmtimer", setup_apicpmtimer); | |
1274 |