[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-omap2 / cpuidle34xx.c

/*
 * linux/arch/arm/mach-omap2/cpuidle34xx.c
 *
 * OMAP3 CPU IDLE Routines
 *
 * Copyright (C) 2008 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Karthik Dasu <karthik-dp@ti.com>
 *
 * Copyright (C) 2006 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * Based on pm.c for omap2
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/sched.h>
#include <linux/cpuidle.h>

#include <plat/prcm.h>
#include <plat/irqs.h>
#include "powerdomain.h"
#include "clockdomain.h"
#include <plat/serial.h>

#include "pm.h"
#include "control.h"

#ifdef CONFIG_CPU_IDLE

#define OMAP3_MAX_STATES 7
#define OMAP3_STATE_C1 0 /* C1 - MPU WFI + Core active */
#define OMAP3_STATE_C2 1 /* C2 - MPU WFI + Core inactive */
#define OMAP3_STATE_C3 2 /* C3 - MPU CSWR + Core inactive */
#define OMAP3_STATE_C4 3 /* C4 - MPU OFF + Core iactive */
#define OMAP3_STATE_C5 4 /* C5 - MPU RET + Core RET */
#define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core RET */
#define OMAP3_STATE_C7 6 /* C7 - MPU OFF + Core OFF */

#define OMAP3_STATE_MAX OMAP3_STATE_C7

#define CPUIDLE_FLAG_CHECK_BM	0x10000	/* use omap3_enter_idle_bm() */

struct omap3_processor_cx {
	u8 valid;
	u8 type;
	u32 sleep_latency;
	u32 wakeup_latency;
	u32 mpu_state;
	u32 core_state;
	u32 threshold;
	u32 flags;
};

struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
struct omap3_processor_cx current_cx_state;
struct powerdomain *mpu_pd, *core_pd, *per_pd;
struct powerdomain *cam_pd;

/*
 * The latencies/thresholds for various C states have
 * to be configured from the respective board files.
 * These are some default values (which might not provide
 * the best power savings) used on boards which do not
 * pass these details from the board file.
 */
static struct cpuidle_params cpuidle_params_table[] = {
	/* C1 */
	{1, 2, 2, 5},
	/* C2 */
	{1, 10, 10, 30},
	/* C3 */
	{1, 50, 50, 300},
	/* C4 */
	{1, 1500, 1800, 4000},
	/* C5 */
	{1, 2500, 7500, 12000},
	/* C6 */
	{1, 3000, 8500, 15000},
	/* C7 */
	{1, 10000, 30000, 300000},
};

static int omap3_idle_bm_check(void)
{
	if (!omap3_can_sleep())
		return 1;
	return 0;
}

static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
				struct clockdomain *clkdm)
{
	clkdm_allow_idle(clkdm);
	return 0;
}

static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
				struct clockdomain *clkdm)
{
	clkdm_deny_idle(clkdm);
	return 0;
}

/**
 * omap3_enter_idle - Programs OMAP3 to enter the specified state
 * @dev: cpuidle device
 * @state: The target state to be programmed
 *
 * Called from the CPUidle framework to program the device to the
 * specified target state selected by the governor.
 */
static int omap3_enter_idle(struct cpuidle_device *dev,
			struct cpuidle_state *state)
{
	struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
	struct timespec ts_preidle, ts_postidle, ts_idle;
	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;

	current_cx_state = *cx;

	/* Used to keep track of the total time in idle */
	getnstimeofday(&ts_preidle);

	local_irq_disable();
	local_fiq_disable();

	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
	pwrdm_set_next_pwrst(core_pd, core_state);

	if (omap_irq_pending() || need_resched())
		goto return_sleep_time;

	if (cx->type == OMAP3_STATE_C1) {
		pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
		pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
	}

	/* Execute ARM wfi */
	omap_sram_idle();

	if (cx->type == OMAP3_STATE_C1) {
		pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
		pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
	}

return_sleep_time:
	getnstimeofday(&ts_postidle);
	ts_idle = timespec_sub(ts_postidle, ts_preidle);

	local_irq_enable();
	local_fiq_enable();

	return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;
}

/**
 * next_valid_state - Find next valid c-state
 * @dev: cpuidle device
 * @state: Currently selected c-state
 *
 * If the current state is valid, it is returned back to the caller.
 * Else, this function searches for a lower c-state which is still
 * valid (as defined in omap3_power_states[]).
 */
static struct cpuidle_state *next_valid_state(struct cpuidle_device *dev,
						struct cpuidle_state *curr)
{
	struct cpuidle_state *next = NULL;
	struct omap3_processor_cx *cx;

	cx = (struct omap3_processor_cx *)cpuidle_get_statedata(curr);

	/* Check if current state is valid */
	if (cx->valid) {
		return curr;
	} else {
		u8 idx = OMAP3_STATE_MAX;

		/*
		 * Reach the current state starting at highest C-state
		 */
		for (; idx >= OMAP3_STATE_C1; idx--) {
			if (&dev->states[idx] == curr) {
				next = &dev->states[idx];
				break;
			}
		}

		/*
		 * Should never hit this condition.
		 */
		WARN_ON(next == NULL);

		/*
		 * Drop to next valid state.
		 * Start search from the next (lower) state.
		 */
		idx--;
		for (; idx >= OMAP3_STATE_C1; idx--) {
			struct omap3_processor_cx *cx;

			cx = cpuidle_get_statedata(&dev->states[idx]);
			if (cx->valid) {
				next = &dev->states[idx];
				break;
			}
		}
		/*
		 * C1 and C2 are always valid.
		 * So, no need to check for 'next==NULL' outside this loop.
		 */
	}

	return next;
}

/**
 * omap3_enter_idle_bm - Checks for any bus activity
 * @dev: cpuidle device
 * @state: The target state to be programmed
 *
 * Used for C states with CPUIDLE_FLAG_CHECK_BM flag set. This
 * function checks for any pending activity and then programs the
 * device to the specified or a safer state.
 */
static int omap3_enter_idle_bm(struct cpuidle_device *dev,
			       struct cpuidle_state *state)
{
	struct cpuidle_state *new_state = next_valid_state(dev, state);
	u32 core_next_state, per_next_state = 0, per_saved_state = 0;
	u32 cam_state;
	struct omap3_processor_cx *cx;
	int ret;

	if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
		BUG_ON(!dev->safe_state);
		new_state = dev->safe_state;
		goto select_state;
	}

	cx = cpuidle_get_statedata(state);
	core_next_state = cx->core_state;

	/*
	 * FIXME: we currently manage device-specific idle states
	 *        for PER and CORE in combination with CPU-specific
	 *        idle states.  This is wrong, and device-specific
	 *        idle management needs to be separated out into 
	 *        its own code.
	 */

	/*
	 * Prevent idle completely if CAM is active.
	 * CAM does not have wakeup capability in OMAP3.
	 */
	cam_state = pwrdm_read_pwrst(cam_pd);
	if (cam_state == PWRDM_POWER_ON) {
		new_state = dev->safe_state;
		goto select_state;
	}

	/*
	 * Prevent PER off if CORE is not in retention or off as this
	 * would disable PER wakeups completely.
	 */
	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
	if ((per_next_state == PWRDM_POWER_OFF) &&
	    (core_next_state > PWRDM_POWER_RET))
		per_next_state = PWRDM_POWER_RET;

	/* Are we changing PER target state? */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_next_state);

select_state:
	dev->last_state = new_state;
	ret = omap3_enter_idle(dev, new_state);

	/* Restore original PER state if it was modified */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_saved_state);

	return ret;
}

DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);

/**
 * omap3_cpuidle_update_states() - Update the cpuidle states
 * @mpu_deepest_state:	Enable states upto and including this for mpu domain
 * @core_deepest_state:	Enable states upto and including this for core domain
 *
 * This goes through the list of states available and enables and disables the
 * validity of C states based on deepest state that can be achieved for the
 * variable domain
 */
void omap3_cpuidle_update_states(u32 mpu_deepest_state, u32 core_deepest_state)
{
	int i;

	for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
		struct omap3_processor_cx *cx = &omap3_power_states[i];

		if ((cx->mpu_state >= mpu_deepest_state) &&
		    (cx->core_state >= core_deepest_state)) {
			cx->valid = 1;
		} else {
			cx->valid = 0;
		}
	}
}

void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
{
	int i;

	if (!cpuidle_board_params)
		return;

	for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
		cpuidle_params_table[i].valid =
			cpuidle_board_params[i].valid;
		cpuidle_params_table[i].sleep_latency =
			cpuidle_board_params[i].sleep_latency;
		cpuidle_params_table[i].wake_latency =
			cpuidle_board_params[i].wake_latency;
		cpuidle_params_table[i].threshold =
			cpuidle_board_params[i].threshold;
	}
	return;
}

/* omap3_init_power_states - Initialises the OMAP3 specific C states.
 *
 * Below is the desciption of each C state.
 * 	C1 . MPU WFI + Core active
 *	C2 . MPU WFI + Core inactive
 *	C3 . MPU CSWR + Core inactive
 *	C4 . MPU OFF + Core inactive
 *	C5 . MPU CSWR + Core CSWR
 *	C6 . MPU OFF + Core CSWR
 *	C7 . MPU OFF + Core OFF
 */
void omap_init_power_states(void)
{
	/* C1 . MPU WFI + Core active */
	omap3_power_states[OMAP3_STATE_C1].valid =
			cpuidle_params_table[OMAP3_STATE_C1].valid;
	omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
	omap3_power_states[OMAP3_STATE_C1].sleep_latency =
			cpuidle_params_table[OMAP3_STATE_C1].sleep_latency;
	omap3_power_states[OMAP3_STATE_C1].wakeup_latency =
			cpuidle_params_table[OMAP3_STATE_C1].wake_latency;
	omap3_power_states[OMAP3_STATE_C1].threshold =
			cpuidle_params_table[OMAP3_STATE_C1].threshold;
	omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
	omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
	omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;

	/* C2 . MPU WFI + Core inactive */
	omap3_power_states[OMAP3_STATE_C2].valid =
			cpuidle_params_table[OMAP3_STATE_C2].valid;
	omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
	omap3_power_states[OMAP3_STATE_C2].sleep_latency =
			cpuidle_params_table[OMAP3_STATE_C2].sleep_latency;
	omap3_power_states[OMAP3_STATE_C2].wakeup_latency =
			cpuidle_params_table[OMAP3_STATE_C2].wake_latency;
	omap3_power_states[OMAP3_STATE_C2].threshold =
			cpuidle_params_table[OMAP3_STATE_C2].threshold;
	omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
	omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
	omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID |
				CPUIDLE_FLAG_CHECK_BM;

	/* C3 . MPU CSWR + Core inactive */
	omap3_power_states[OMAP3_STATE_C3].valid =
			cpuidle_params_table[OMAP3_STATE_C3].valid;
	omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3;
	omap3_power_states[OMAP3_STATE_C3].sleep_latency =
			cpuidle_params_table[OMAP3_STATE_C3].sleep_latency;
	omap3_power_states[OMAP3_STATE_C3].wakeup_latency =
			cpuidle_params_table[OMAP3_STATE_C3].wake_latency;
	omap3_power_states[OMAP3_STATE_C3].threshold =
			cpuidle_params_table[OMAP3_STATE_C3].threshold;
	omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET;
	omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
	omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID |
				CPUIDLE_FLAG_CHECK_BM;

	/* C4 . MPU OFF + Core inactive */
	omap3_power_states[OMAP3_STATE_C4].valid =
			cpuidle_params_table[OMAP3_STATE_C4].valid;
	omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4;
	omap3_power_states[OMAP3_STATE_C4].sleep_latency =
			cpuidle_params_table[OMAP3_STATE_C4].sleep_latency;
	omap3_power_states[OMAP3_STATE_C4].wakeup_latency =
			cpuidle_params_table[OMAP3_STATE_C4].wake_latency;
	omap3_power_states[OMAP3_STATE_C4].threshold =
			cpuidle_params_table[OMAP3_STATE_C4].threshold;
	omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF;
	omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON;
	omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID |
				CPUIDLE_FLAG_CHECK_BM;

	/* C5 . MPU CSWR + Core CSWR*/
	omap3_power_states[OMAP3_STATE_C5].valid =
			cpuidle_params_table[OMAP3_STATE_C5].valid;
	omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5;
	omap3_power_states[OMAP3_STATE_C5].sleep_latency =
			cpuidle_params_table[OMAP3_STATE_C5].sleep_latency;
	omap3_power_states[OMAP3_STATE_C5].wakeup_latency =
			cpuidle_params_table[OMAP3_STATE_C5].wake_latency;
	omap3_power_states[OMAP3_STATE_C5].threshold =
			cpuidle_params_table[OMAP3_STATE_C5].threshold;
	omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET;
	omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
	omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID |
				CPUIDLE_FLAG_CHECK_BM;

	/* C6 . MPU OFF + Core CSWR */
	omap3_power_states[OMAP3_STATE_C6].valid =
			cpuidle_params_table[OMAP3_STATE_C6].valid;
	omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6;
	omap3_power_states[OMAP3_STATE_C6].sleep_latency =
			cpuidle_params_table[OMAP3_STATE_C6].sleep_latency;
	omap3_power_states[OMAP3_STATE_C6].wakeup_latency =
			cpuidle_params_table[OMAP3_STATE_C6].wake_latency;
	omap3_power_states[OMAP3_STATE_C6].threshold =
			cpuidle_params_table[OMAP3_STATE_C6].threshold;
	omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF;
	omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET;
	omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID |
				CPUIDLE_FLAG_CHECK_BM;

	/* C7 . MPU OFF + Core OFF */
	omap3_power_states[OMAP3_STATE_C7].valid =
			cpuidle_params_table[OMAP3_STATE_C7].valid;
	omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7;
	omap3_power_states[OMAP3_STATE_C7].sleep_latency =
			cpuidle_params_table[OMAP3_STATE_C7].sleep_latency;
	omap3_power_states[OMAP3_STATE_C7].wakeup_latency =
			cpuidle_params_table[OMAP3_STATE_C7].wake_latency;
	omap3_power_states[OMAP3_STATE_C7].threshold =
			cpuidle_params_table[OMAP3_STATE_C7].threshold;
	omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF;
	omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
	omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
				CPUIDLE_FLAG_CHECK_BM;

	/*
	 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
	 * enable OFF mode in a stable form for previous revisions.
	 * we disable C7 state as a result.
	 */
	if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
		omap3_power_states[OMAP3_STATE_C7].valid = 0;
		cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
		WARN_ONCE(1, "%s: core off state C7 disabled due to i583\n",
				__func__);
	}
}

struct cpuidle_driver omap3_idle_driver = {
	.name = 	"omap3_idle",
	.owner = 	THIS_MODULE,
};

/**
 * omap3_idle_init - Init routine for OMAP3 idle
 *
 * Registers the OMAP3 specific cpuidle driver with the cpuidle
 * framework with the valid set of states.
 */
int __init omap3_idle_init(void)
{
	int i, count = 0;
	struct omap3_processor_cx *cx;
	struct cpuidle_state *state;
	struct cpuidle_device *dev;

	mpu_pd = pwrdm_lookup("mpu_pwrdm");
	core_pd = pwrdm_lookup("core_pwrdm");
	per_pd = pwrdm_lookup("per_pwrdm");
	cam_pd = pwrdm_lookup("cam_pwrdm");

	omap_init_power_states();
	cpuidle_register_driver(&omap3_idle_driver);

	dev = &per_cpu(omap3_idle_dev, smp_processor_id());

	for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
		cx = &omap3_power_states[i];
		state = &dev->states[count];

		if (!cx->valid)
			continue;
		cpuidle_set_statedata(state, cx);
		state->exit_latency = cx->sleep_latency + cx->wakeup_latency;
		state->target_residency = cx->threshold;
		state->flags = cx->flags;
		state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
			omap3_enter_idle_bm : omap3_enter_idle;
		if (cx->type == OMAP3_STATE_C1)
			dev->safe_state = state;
		sprintf(state->name, "C%d", count+1);
		count++;
	}

	if (!count)
		return -EINVAL;
	dev->state_count = count;

	if (enable_off_mode)
		omap3_cpuidle_update_states(PWRDM_POWER_OFF, PWRDM_POWER_OFF);
	else
		omap3_cpuidle_update_states(PWRDM_POWER_RET, PWRDM_POWER_RET);

	if (cpuidle_register_device(dev)) {
		printk(KERN_ERR "%s: CPUidle register device failed\n",
		       __func__);
		return -EIO;
	}

	return 0;
}
#else
int __init omap3_idle_init(void)
{
	return 0;
}
#endif /* CONFIG_CPU_IDLE */
Commit	Line	Data
99e6a4d2 RN	1	/*
	2	* linux/arch/arm/mach-omap2/cpuidle34xx.c
	3	*
	4	* OMAP3 CPU IDLE Routines
	5	*
	6	* Copyright (C) 2008 Texas Instruments, Inc.
	7	* Rajendra Nayak <rnayak@ti.com>
	8	*
	9	* Copyright (C) 2007 Texas Instruments, Inc.
	10	* Karthik Dasu <karthik-dp@ti.com>
	11	*
	12	* Copyright (C) 2006 Nokia Corporation
	13	* Tony Lindgren <tony@atomide.com>
	14	*
	15	* Copyright (C) 2005 Texas Instruments, Inc.
	16	* Richard Woodruff <r-woodruff2@ti.com>
	17	*
	18	* Based on pm.c for omap2
	19	*
	20	* This program is free software; you can redistribute it and/or modify
	21	* it under the terms of the GNU General Public License version 2 as
	22	* published by the Free Software Foundation.
	23	*/
	24
cf22854c	25	#include <linux/sched.h>
99e6a4d2 RN	26	#include <linux/cpuidle.h>
	27
	28	#include <plat/prcm.h>
20b01669	29	#include <plat/irqs.h>
72e06d08	30	#include "powerdomain.h"
1540f214	31	#include "clockdomain.h"
0f724ed9	32	#include <plat/serial.h>
99e6a4d2	33
c98e2230	34	#include "pm.h"
4814ced5	35	#include "control.h"
c98e2230	36
99e6a4d2 RN	37	#ifdef CONFIG_CPU_IDLE
99e6a4d2 RN	38
8e431edb SP	39	#define OMAP3_MAX_STATES 7
	40	#define OMAP3_STATE_C1 0 /* C1 - MPU WFI + Core active */
	41	#define OMAP3_STATE_C2 1 /* C2 - MPU WFI + Core inactive */
	42	#define OMAP3_STATE_C3 2 /* C3 - MPU CSWR + Core inactive */
	43	#define OMAP3_STATE_C4 3 /* C4 - MPU OFF + Core iactive */
	44	#define OMAP3_STATE_C5 4 /* C5 - MPU RET + Core RET */
	45	#define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core RET */
	46	#define OMAP3_STATE_C7 6 /* C7 - MPU OFF + Core OFF */
99e6a4d2	47
6af83b38 SP	48	#define OMAP3_STATE_MAX OMAP3_STATE_C7
6af83b38 SP	49
53920837 LB	50	#define CPUIDLE_FLAG_CHECK_BM 0x10000 /* use omap3_enter_idle_bm() */
53920837 LB	51
99e6a4d2 RN	52	struct omap3_processor_cx {
	53	u8 valid;
	54	u8 type;
	55	u32 sleep_latency;
	56	u32 wakeup_latency;
	57	u32 mpu_state;
	58	u32 core_state;
	59	u32 threshold;
	60	u32 flags;
	61	};
	62
	63	struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
	64	struct omap3_processor_cx current_cx_state;
e7410cf7 KH	65	struct powerdomain mpu_pd, core_pd, *per_pd;
e7410cf7 KH	66	struct powerdomain *cam_pd;
99e6a4d2	67
bb4de3df KH	68	/*
	69	* The latencies/thresholds for various C states have
	70	* to be configured from the respective board files.
	71	* These are some default values (which might not provide
	72	* the best power savings) used on boards which do not
	73	* pass these details from the board file.
	74	*/
	75	static struct cpuidle_params cpuidle_params_table[] = {
	76	/* C1 */
709731bb	77	{1, 2, 2, 5},
bb4de3df	78	/* C2 */
709731bb	79	{1, 10, 10, 30},
bb4de3df	80	/* C3 */
709731bb	81	{1, 50, 50, 300},
bb4de3df	82	/* C4 */
709731bb	83	{1, 1500, 1800, 4000},
bb4de3df	84	/* C5 */
709731bb	85	{1, 2500, 7500, 12000},
bb4de3df	86	/* C6 */
709731bb	87	{1, 3000, 8500, 15000},
bb4de3df	88	/* C7 */
709731bb	89	{1, 10000, 30000, 300000},
bb4de3df KH	90	};
bb4de3df KH	91
99e6a4d2 RN	92	static int omap3_idle_bm_check(void)
99e6a4d2 RN	93	{
20b01669 RN	94	if (!omap3_can_sleep())
20b01669 RN	95	return 1;
99e6a4d2 RN	96	return 0;
	97	}
	98
06d8f065 PDS	99	static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
	100	struct clockdomain *clkdm)
	101	{
5cd1937b	102	clkdm_allow_idle(clkdm);
06d8f065 PDS	103	return 0;
	104	}
	105
	106	static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
	107	struct clockdomain *clkdm)
	108	{
5cd1937b	109	clkdm_deny_idle(clkdm);
06d8f065 PDS	110	return 0;
	111	}
	112
99e6a4d2 RN	113	/**
	114	* omap3_enter_idle - Programs OMAP3 to enter the specified state
	115	* @dev: cpuidle device
	116	* @state: The target state to be programmed
	117	*
	118	* Called from the CPUidle framework to program the device to the
	119	* specified target state selected by the governor.
	120	*/
	121	static int omap3_enter_idle(struct cpuidle_device *dev,
	122	struct cpuidle_state *state)
	123	{
	124	struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
	125	struct timespec ts_preidle, ts_postidle, ts_idle;
c98e2230	126	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
99e6a4d2 RN	127
	128	current_cx_state = *cx;
	129
	130	/* Used to keep track of the total time in idle */
	131	getnstimeofday(&ts_preidle);
	132
	133	local_irq_disable();
	134	local_fiq_disable();
	135
7139178e JH	136	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
7139178e JH	137	pwrdm_set_next_pwrst(core_pd, core_state);
20b01669	138
cf22854c	139	if (omap_irq_pending() \|\| need_resched())
20b01669	140	goto return_sleep_time;
99e6a4d2	141
06d8f065 PDS	142	if (cx->type == OMAP3_STATE_C1) {
	143	pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
	144	pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
	145	}
	146
99e6a4d2 RN	147	/* Execute ARM wfi */
	148	omap_sram_idle();
	149
06d8f065 PDS	150	if (cx->type == OMAP3_STATE_C1) {
	151	pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
	152	pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
	153	}
	154
20b01669	155	return_sleep_time:
99e6a4d2 RN	156	getnstimeofday(&ts_postidle);
	157	ts_idle = timespec_sub(ts_postidle, ts_preidle);
	158
	159	local_irq_enable();
	160	local_fiq_enable();
	161
afbcf619	162	return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;
99e6a4d2 RN	163	}
99e6a4d2 RN	164
6af83b38 SP	165	/**
	166	* next_valid_state - Find next valid c-state
	167	* @dev: cpuidle device
	168	* @state: Currently selected c-state
	169	*
	170	* If the current state is valid, it is returned back to the caller.
	171	* Else, this function searches for a lower c-state which is still
	172	* valid (as defined in omap3_power_states[]).
	173	*/
	174	static struct cpuidle_state next_valid_state(struct cpuidle_device dev,
	175	struct cpuidle_state *curr)
	176	{
	177	struct cpuidle_state *next = NULL;
	178	struct omap3_processor_cx *cx;
	179
	180	cx = (struct omap3_processor_cx *)cpuidle_get_statedata(curr);
	181
	182	/* Check if current state is valid */
	183	if (cx->valid) {
	184	return curr;
	185	} else {
	186	u8 idx = OMAP3_STATE_MAX;
	187
	188	/*
	189	* Reach the current state starting at highest C-state
	190	*/
	191	for (; idx >= OMAP3_STATE_C1; idx--) {
	192	if (&dev->states[idx] == curr) {
	193	next = &dev->states[idx];
	194	break;
	195	}
	196	}
	197
	198	/*
	199	* Should never hit this condition.
	200	*/
	201	WARN_ON(next == NULL);
	202
	203	/*
	204	* Drop to next valid state.
	205	* Start search from the next (lower) state.
	206	*/
	207	idx--;
	208	for (; idx >= OMAP3_STATE_C1; idx--) {
	209	struct omap3_processor_cx *cx;
	210
	211	cx = cpuidle_get_statedata(&dev->states[idx]);
	212	if (cx->valid) {
	213	next = &dev->states[idx];
	214	break;
	215	}
	216	}
	217	/*
	218	* C1 and C2 are always valid.
	219	* So, no need to check for 'next==NULL' outside this loop.
	220	*/
	221	}
	222
	223	return next;
	224	}
	225
99e6a4d2 RN	226	/**
	227	* omap3_enter_idle_bm - Checks for any bus activity
	228	* @dev: cpuidle device
	229	* @state: The target state to be programmed
	230	*
	231	* Used for C states with CPUIDLE_FLAG_CHECK_BM flag set. This
	232	* function checks for any pending activity and then programs the
	233	* device to the specified or a safer state.
	234	*/
	235	static int omap3_enter_idle_bm(struct cpuidle_device *dev,
	236	struct cpuidle_state *state)
	237	{
6af83b38	238	struct cpuidle_state *new_state = next_valid_state(dev, state);
e7410cf7 KH	239	u32 core_next_state, per_next_state = 0, per_saved_state = 0;
	240	u32 cam_state;
	241	struct omap3_processor_cx *cx;
	242	int ret;
0f724ed9	243
99e6a4d2	244	if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
0f724ed9 KH	245	BUG_ON(!dev->safe_state);
0f724ed9 KH	246	new_state = dev->safe_state;
e7410cf7 KH	247	goto select_state;
	248	}
	249
	250	cx = cpuidle_get_statedata(state);
	251	core_next_state = cx->core_state;
	252
	253	/*
	254	* FIXME: we currently manage device-specific idle states
	255	* for PER and CORE in combination with CPU-specific
	256	* idle states. This is wrong, and device-specific
b595076a	257	* idle management needs to be separated out into
e7410cf7 KH	258	* its own code.
	259	*/
	260
	261	/*
	262	* Prevent idle completely if CAM is active.
	263	* CAM does not have wakeup capability in OMAP3.
	264	*/
	265	cam_state = pwrdm_read_pwrst(cam_pd);
	266	if (cam_state == PWRDM_POWER_ON) {
	267	new_state = dev->safe_state;
	268	goto select_state;
	269	}
	270
	271	/*
	272	* Prevent PER off if CORE is not in retention or off as this
	273	* would disable PER wakeups completely.
	274	*/
	275	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
	276	if ((per_next_state == PWRDM_POWER_OFF) &&
65707fb3	277	(core_next_state > PWRDM_POWER_RET))
e7410cf7	278	per_next_state = PWRDM_POWER_RET;
0f724ed9	279
e7410cf7 KH	280	/* Are we changing PER target state? */
	281	if (per_next_state != per_saved_state)
	282	pwrdm_set_next_pwrst(per_pd, per_next_state);
	283
	284	select_state:
0f724ed9	285	dev->last_state = new_state;
e7410cf7 KH	286	ret = omap3_enter_idle(dev, new_state);
	287
	288	/* Restore original PER state if it was modified */
	289	if (per_next_state != per_saved_state)
	290	pwrdm_set_next_pwrst(per_pd, per_saved_state);
	291
	292	return ret;
99e6a4d2 RN	293	}
	294
	295	DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
	296
6af83b38	297	/**
80723c3f NM	298	* omap3_cpuidle_update_states() - Update the cpuidle states
	299	* @mpu_deepest_state: Enable states upto and including this for mpu domain
	300	* @core_deepest_state: Enable states upto and including this for core domain
6af83b38	301	*
80723c3f NM	302	* This goes through the list of states available and enables and disables the
	303	* validity of C states based on deepest state that can be achieved for the
	304	* variable domain
6af83b38	305	*/
80723c3f	306	void omap3_cpuidle_update_states(u32 mpu_deepest_state, u32 core_deepest_state)
6af83b38 SP	307	{
	308	int i;
	309
	310	for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
	311	struct omap3_processor_cx *cx = &omap3_power_states[i];
	312
80723c3f NM	313	if ((cx->mpu_state >= mpu_deepest_state) &&
80723c3f NM	314	(cx->core_state >= core_deepest_state)) {
6af83b38 SP	315	cx->valid = 1;
6af83b38 SP	316	} else {
80723c3f	317	cx->valid = 0;
6af83b38 SP	318	}
	319	}
	320	}
	321
bb4de3df KH	322	void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
	323	{
	324	int i;
	325
	326	if (!cpuidle_board_params)
	327	return;
	328
	329	for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
709731bb KJ	330	cpuidle_params_table[i].valid =
709731bb KJ	331	cpuidle_board_params[i].valid;
bb4de3df KH	332	cpuidle_params_table[i].sleep_latency =
	333	cpuidle_board_params[i].sleep_latency;
	334	cpuidle_params_table[i].wake_latency =
	335	cpuidle_board_params[i].wake_latency;
	336	cpuidle_params_table[i].threshold =
	337	cpuidle_board_params[i].threshold;
	338	}
	339	return;
	340	}
	341
99e6a4d2 RN	342	/* omap3_init_power_states - Initialises the OMAP3 specific C states.
	343	*
	344	* Below is the desciption of each C state.
06d8f065 PDS	345	* C1 . MPU WFI + Core active
	346	* C2 . MPU WFI + Core inactive
	347	* C3 . MPU CSWR + Core inactive
	348	* C4 . MPU OFF + Core inactive
	349	* C5 . MPU CSWR + Core CSWR
	350	* C6 . MPU OFF + Core CSWR
	351	* C7 . MPU OFF + Core OFF
99e6a4d2 RN	352	*/
	353	void omap_init_power_states(void)
	354	{
	355	/* C1 . MPU WFI + Core active */
709731bb KJ	356	omap3_power_states[OMAP3_STATE_C1].valid =
709731bb KJ	357	cpuidle_params_table[OMAP3_STATE_C1].valid;
99e6a4d2	358	omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
bb4de3df KH	359	omap3_power_states[OMAP3_STATE_C1].sleep_latency =
	360	cpuidle_params_table[OMAP3_STATE_C1].sleep_latency;
	361	omap3_power_states[OMAP3_STATE_C1].wakeup_latency =
	362	cpuidle_params_table[OMAP3_STATE_C1].wake_latency;
	363	omap3_power_states[OMAP3_STATE_C1].threshold =
	364	cpuidle_params_table[OMAP3_STATE_C1].threshold;
99e6a4d2 RN	365	omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
	366	omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
	367	omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
	368
06d8f065	369	/* C2 . MPU WFI + Core inactive */
709731bb KJ	370	omap3_power_states[OMAP3_STATE_C2].valid =
709731bb KJ	371	cpuidle_params_table[OMAP3_STATE_C2].valid;
99e6a4d2	372	omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
bb4de3df KH	373	omap3_power_states[OMAP3_STATE_C2].sleep_latency =
	374	cpuidle_params_table[OMAP3_STATE_C2].sleep_latency;
	375	omap3_power_states[OMAP3_STATE_C2].wakeup_latency =
	376	cpuidle_params_table[OMAP3_STATE_C2].wake_latency;
	377	omap3_power_states[OMAP3_STATE_C2].threshold =
	378	cpuidle_params_table[OMAP3_STATE_C2].threshold;
06d8f065	379	omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
99e6a4d2	380	omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
e7410cf7 KH	381	omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID \|
e7410cf7 KH	382	CPUIDLE_FLAG_CHECK_BM;
99e6a4d2	383
06d8f065	384	/* C3 . MPU CSWR + Core inactive */
709731bb KJ	385	omap3_power_states[OMAP3_STATE_C3].valid =
709731bb KJ	386	cpuidle_params_table[OMAP3_STATE_C3].valid;
99e6a4d2	387	omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3;
bb4de3df KH	388	omap3_power_states[OMAP3_STATE_C3].sleep_latency =
	389	cpuidle_params_table[OMAP3_STATE_C3].sleep_latency;
	390	omap3_power_states[OMAP3_STATE_C3].wakeup_latency =
	391	cpuidle_params_table[OMAP3_STATE_C3].wake_latency;
	392	omap3_power_states[OMAP3_STATE_C3].threshold =
	393	cpuidle_params_table[OMAP3_STATE_C3].threshold;
06d8f065	394	omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET;
99e6a4d2	395	omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
0f724ed9 KH	396	omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID \|
0f724ed9 KH	397	CPUIDLE_FLAG_CHECK_BM;
99e6a4d2	398
06d8f065	399	/* C4 . MPU OFF + Core inactive */
709731bb KJ	400	omap3_power_states[OMAP3_STATE_C4].valid =
709731bb KJ	401	cpuidle_params_table[OMAP3_STATE_C4].valid;
99e6a4d2	402	omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4;
bb4de3df KH	403	omap3_power_states[OMAP3_STATE_C4].sleep_latency =
	404	cpuidle_params_table[OMAP3_STATE_C4].sleep_latency;
	405	omap3_power_states[OMAP3_STATE_C4].wakeup_latency =
	406	cpuidle_params_table[OMAP3_STATE_C4].wake_latency;
	407	omap3_power_states[OMAP3_STATE_C4].threshold =
	408	cpuidle_params_table[OMAP3_STATE_C4].threshold;
06d8f065 PDS	409	omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF;
06d8f065 PDS	410	omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON;
99e6a4d2 RN	411	omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID \|
	412	CPUIDLE_FLAG_CHECK_BM;
	413
06d8f065	414	/* C5 . MPU CSWR + Core CSWR*/
709731bb KJ	415	omap3_power_states[OMAP3_STATE_C5].valid =
709731bb KJ	416	cpuidle_params_table[OMAP3_STATE_C5].valid;
99e6a4d2	417	omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5;
bb4de3df KH	418	omap3_power_states[OMAP3_STATE_C5].sleep_latency =
	419	cpuidle_params_table[OMAP3_STATE_C5].sleep_latency;
	420	omap3_power_states[OMAP3_STATE_C5].wakeup_latency =
	421	cpuidle_params_table[OMAP3_STATE_C5].wake_latency;
	422	omap3_power_states[OMAP3_STATE_C5].threshold =
	423	cpuidle_params_table[OMAP3_STATE_C5].threshold;
06d8f065	424	omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET;
99e6a4d2 RN	425	omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
	426	omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID \|
	427	CPUIDLE_FLAG_CHECK_BM;
	428
06d8f065	429	/* C6 . MPU OFF + Core CSWR */
709731bb KJ	430	omap3_power_states[OMAP3_STATE_C6].valid =
709731bb KJ	431	cpuidle_params_table[OMAP3_STATE_C6].valid;
99e6a4d2	432	omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6;
bb4de3df KH	433	omap3_power_states[OMAP3_STATE_C6].sleep_latency =
	434	cpuidle_params_table[OMAP3_STATE_C6].sleep_latency;
	435	omap3_power_states[OMAP3_STATE_C6].wakeup_latency =
	436	cpuidle_params_table[OMAP3_STATE_C6].wake_latency;
	437	omap3_power_states[OMAP3_STATE_C6].threshold =
	438	cpuidle_params_table[OMAP3_STATE_C6].threshold;
99e6a4d2	439	omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF;
06d8f065	440	omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET;
99e6a4d2 RN	441	omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID \|
99e6a4d2 RN	442	CPUIDLE_FLAG_CHECK_BM;
06d8f065 PDS	443
06d8f065 PDS	444	/* C7 . MPU OFF + Core OFF */
709731bb KJ	445	omap3_power_states[OMAP3_STATE_C7].valid =
709731bb KJ	446	cpuidle_params_table[OMAP3_STATE_C7].valid;
06d8f065	447	omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7;
bb4de3df KH	448	omap3_power_states[OMAP3_STATE_C7].sleep_latency =
	449	cpuidle_params_table[OMAP3_STATE_C7].sleep_latency;
	450	omap3_power_states[OMAP3_STATE_C7].wakeup_latency =
	451	cpuidle_params_table[OMAP3_STATE_C7].wake_latency;
	452	omap3_power_states[OMAP3_STATE_C7].threshold =
	453	cpuidle_params_table[OMAP3_STATE_C7].threshold;
06d8f065 PDS	454	omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF;
	455	omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
	456	omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID \|
	457	CPUIDLE_FLAG_CHECK_BM;
cc1b6028 EV	458
	459	/*
	460	* Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
	461	* enable OFF mode in a stable form for previous revisions.
	462	* we disable C7 state as a result.
	463	*/
	464	if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
	465	omap3_power_states[OMAP3_STATE_C7].valid = 0;
	466	cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
	467	WARN_ONCE(1, "%s: core off state C7 disabled due to i583\n",
	468	__func__);
	469	}
99e6a4d2 RN	470	}
	471
	472	struct cpuidle_driver omap3_idle_driver = {
	473	.name = "omap3_idle",
	474	.owner = THIS_MODULE,
	475	};
	476
	477	/**
	478	* omap3_idle_init - Init routine for OMAP3 idle
	479	*
	480	* Registers the OMAP3 specific cpuidle driver with the cpuidle
	481	* framework with the valid set of states.
	482	*/
0343371e	483	int __init omap3_idle_init(void)
99e6a4d2 RN	484	{
	485	int i, count = 0;
	486	struct omap3_processor_cx *cx;
	487	struct cpuidle_state *state;
	488	struct cpuidle_device *dev;
	489
	490	mpu_pd = pwrdm_lookup("mpu_pwrdm");
20b01669	491	core_pd = pwrdm_lookup("core_pwrdm");
e7410cf7 KH	492	per_pd = pwrdm_lookup("per_pwrdm");
e7410cf7 KH	493	cam_pd = pwrdm_lookup("cam_pwrdm");
99e6a4d2 RN	494
	495	omap_init_power_states();
	496	cpuidle_register_driver(&omap3_idle_driver);
	497
	498	dev = &per_cpu(omap3_idle_dev, smp_processor_id());
	499
8e431edb	500	for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
99e6a4d2 RN	501	cx = &omap3_power_states[i];
	502	state = &dev->states[count];
	503
	504	if (!cx->valid)
	505	continue;
	506	cpuidle_set_statedata(state, cx);
	507	state->exit_latency = cx->sleep_latency + cx->wakeup_latency;
	508	state->target_residency = cx->threshold;
	509	state->flags = cx->flags;
	510	state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
	511	omap3_enter_idle_bm : omap3_enter_idle;
	512	if (cx->type == OMAP3_STATE_C1)
	513	dev->safe_state = state;
	514	sprintf(state->name, "C%d", count+1);
	515	count++;
	516	}
	517
	518	if (!count)
	519	return -EINVAL;
	520	dev->state_count = count;
	521
80723c3f NM	522	if (enable_off_mode)
	523	omap3_cpuidle_update_states(PWRDM_POWER_OFF, PWRDM_POWER_OFF);
	524	else
	525	omap3_cpuidle_update_states(PWRDM_POWER_RET, PWRDM_POWER_RET);
6af83b38	526
99e6a4d2 RN	527	if (cpuidle_register_device(dev)) {
	528	printk(KERN_ERR "%s: CPUidle register device failed\n",
	529	__func__);
	530	return -EIO;
	531	}
	532
	533	return 0;
	534	}
0343371e KJ	535	#else
	536	int __init omap3_idle_init(void)
	537	{
	538	return 0;
	539	}
99e6a4d2	540	#endif /* CONFIG_CPU_IDLE */