[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-omap2 / cpuidle34xx.c

/*
 * linux/arch/arm/mach-omap2/cpuidle34xx.c
 *
 * OMAP3 CPU IDLE Routines
 *
 * Copyright (C) 2008 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Karthik Dasu <karthik-dp@ti.com>
 *
 * Copyright (C) 2006 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * Based on pm.c for omap2
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/cpuidle.h>

#include <plat/prcm.h>
#include <plat/irqs.h>
#include <plat/powerdomain.h>
#include <plat/clockdomain.h>
#include <plat/control.h>
#include <plat/serial.h>

#include "pm.h"

#ifdef CONFIG_CPU_IDLE

#define OMAP3_MAX_STATES 7
#define OMAP3_STATE_C1 0 /* C1 - MPU WFI + Core active */
#define OMAP3_STATE_C2 1 /* C2 - MPU WFI + Core inactive */
#define OMAP3_STATE_C3 2 /* C3 - MPU CSWR + Core inactive */
#define OMAP3_STATE_C4 3 /* C4 - MPU OFF + Core iactive */
#define OMAP3_STATE_C5 4 /* C5 - MPU RET + Core RET */
#define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core RET */
#define OMAP3_STATE_C7 6 /* C7 - MPU OFF + Core OFF */

struct omap3_processor_cx {
	u8 valid;
	u8 type;
	u32 sleep_latency;
	u32 wakeup_latency;
	u32 mpu_state;
	u32 core_state;
	u32 threshold;
	u32 flags;
};

struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
struct omap3_processor_cx current_cx_state;
struct powerdomain *mpu_pd, *core_pd;

static int omap3_idle_bm_check(void)
{
	if (!omap3_can_sleep())
		return 1;
	return 0;
}

static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
				struct clockdomain *clkdm)
{
	omap2_clkdm_allow_idle(clkdm);
	return 0;
}

static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
				struct clockdomain *clkdm)
{
	omap2_clkdm_deny_idle(clkdm);
	return 0;
}

/**
 * omap3_enter_idle - Programs OMAP3 to enter the specified state
 * @dev: cpuidle device
 * @state: The target state to be programmed
 *
 * Called from the CPUidle framework to program the device to the
 * specified target state selected by the governor.
 */
static int omap3_enter_idle(struct cpuidle_device *dev,
			struct cpuidle_state *state)
{
	struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
	struct timespec ts_preidle, ts_postidle, ts_idle;
	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;

	current_cx_state = *cx;

	/* Used to keep track of the total time in idle */
	getnstimeofday(&ts_preidle);

	local_irq_disable();
	local_fiq_disable();

	if (!enable_off_mode) {
		if (mpu_state < PWRDM_POWER_RET)
			mpu_state = PWRDM_POWER_RET;
		if (core_state < PWRDM_POWER_RET)
			core_state = PWRDM_POWER_RET;
	}

	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
	pwrdm_set_next_pwrst(core_pd, core_state);

	if (omap_irq_pending())
		goto return_sleep_time;

	if (cx->type == OMAP3_STATE_C1) {
		pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
		pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
	}

	/* Execute ARM wfi */
	omap_sram_idle();

	if (cx->type == OMAP3_STATE_C1) {
		pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
		pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
	}

return_sleep_time:
	getnstimeofday(&ts_postidle);
	ts_idle = timespec_sub(ts_postidle, ts_preidle);

	local_irq_enable();
	local_fiq_enable();

	return (u32)timespec_to_ns(&ts_idle)/1000;
}

/**
 * omap3_enter_idle_bm - Checks for any bus activity
 * @dev: cpuidle device
 * @state: The target state to be programmed
 *
 * Used for C states with CPUIDLE_FLAG_CHECK_BM flag set. This
 * function checks for any pending activity and then programs the
 * device to the specified or a safer state.
 */
static int omap3_enter_idle_bm(struct cpuidle_device *dev,
			       struct cpuidle_state *state)
{
	struct cpuidle_state *new_state = state;

	if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
		BUG_ON(!dev->safe_state);
		new_state = dev->safe_state;
	}

	dev->last_state = new_state;
	return omap3_enter_idle(dev, new_state);
}

DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);

/* omap3_init_power_states - Initialises the OMAP3 specific C states.
 *
 * Below is the desciption of each C state.
 * 	C1 . MPU WFI + Core active
 *	C2 . MPU WFI + Core inactive
 *	C3 . MPU CSWR + Core inactive
 *	C4 . MPU OFF + Core inactive
 *	C5 . MPU CSWR + Core CSWR
 *	C6 . MPU OFF + Core CSWR
 *	C7 . MPU OFF + Core OFF
 */
void omap_init_power_states(void)
{
	/* C1 . MPU WFI + Core active */
	omap3_power_states[OMAP3_STATE_C1].valid = 1;
	omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
	omap3_power_states[OMAP3_STATE_C1].sleep_latency = 2;
	omap3_power_states[OMAP3_STATE_C1].wakeup_latency = 2;
	omap3_power_states[OMAP3_STATE_C1].threshold = 5;
	omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
	omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
	omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;

	/* C2 . MPU WFI + Core inactive */
	omap3_power_states[OMAP3_STATE_C2].valid = 1;
	omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
	omap3_power_states[OMAP3_STATE_C2].sleep_latency = 10;
	omap3_power_states[OMAP3_STATE_C2].wakeup_latency = 10;
	omap3_power_states[OMAP3_STATE_C2].threshold = 30;
	omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
	omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
	omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID;

	/* C3 . MPU CSWR + Core inactive */
	omap3_power_states[OMAP3_STATE_C3].valid = 1;
	omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3;
	omap3_power_states[OMAP3_STATE_C3].sleep_latency = 50;
	omap3_power_states[OMAP3_STATE_C3].wakeup_latency = 50;
	omap3_power_states[OMAP3_STATE_C3].threshold = 300;
	omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET;
	omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
	omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID |
				CPUIDLE_FLAG_CHECK_BM;

	/* C4 . MPU OFF + Core inactive */
	omap3_power_states[OMAP3_STATE_C4].valid = 1;
	omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4;
	omap3_power_states[OMAP3_STATE_C4].sleep_latency = 1500;
	omap3_power_states[OMAP3_STATE_C4].wakeup_latency = 1800;
	omap3_power_states[OMAP3_STATE_C4].threshold = 4000;
	omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF;
	omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON;
	omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID |
				CPUIDLE_FLAG_CHECK_BM;

	/* C5 . MPU CSWR + Core CSWR*/
	omap3_power_states[OMAP3_STATE_C5].valid = 1;
	omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5;
	omap3_power_states[OMAP3_STATE_C5].sleep_latency = 2500;
	omap3_power_states[OMAP3_STATE_C5].wakeup_latency = 7500;
	omap3_power_states[OMAP3_STATE_C5].threshold = 12000;
	omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET;
	omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
	omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID |
				CPUIDLE_FLAG_CHECK_BM;

	/* C6 . MPU OFF + Core CSWR */
	omap3_power_states[OMAP3_STATE_C6].valid = 1;
	omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6;
	omap3_power_states[OMAP3_STATE_C6].sleep_latency = 3000;
	omap3_power_states[OMAP3_STATE_C6].wakeup_latency = 8500;
	omap3_power_states[OMAP3_STATE_C6].threshold = 15000;
	omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF;
	omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET;
	omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID |
				CPUIDLE_FLAG_CHECK_BM;

	/* C7 . MPU OFF + Core OFF */
	omap3_power_states[OMAP3_STATE_C7].valid = 1;
	omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7;
	omap3_power_states[OMAP3_STATE_C7].sleep_latency = 10000;
	omap3_power_states[OMAP3_STATE_C7].wakeup_latency = 30000;
	omap3_power_states[OMAP3_STATE_C7].threshold = 300000;
	omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF;
	omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
	omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
				CPUIDLE_FLAG_CHECK_BM;
}

struct cpuidle_driver omap3_idle_driver = {
	.name = 	"omap3_idle",
	.owner = 	THIS_MODULE,
};

/**
 * omap3_idle_init - Init routine for OMAP3 idle
 *
 * Registers the OMAP3 specific cpuidle driver with the cpuidle
 * framework with the valid set of states.
 */
int __init omap3_idle_init(void)
{
	int i, count = 0;
	struct omap3_processor_cx *cx;
	struct cpuidle_state *state;
	struct cpuidle_device *dev;

	mpu_pd = pwrdm_lookup("mpu_pwrdm");
	core_pd = pwrdm_lookup("core_pwrdm");

	omap_init_power_states();
	cpuidle_register_driver(&omap3_idle_driver);

	dev = &per_cpu(omap3_idle_dev, smp_processor_id());

	for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
		cx = &omap3_power_states[i];
		state = &dev->states[count];

		if (!cx->valid)
			continue;
		cpuidle_set_statedata(state, cx);
		state->exit_latency = cx->sleep_latency + cx->wakeup_latency;
		state->target_residency = cx->threshold;
		state->flags = cx->flags;
		state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
			omap3_enter_idle_bm : omap3_enter_idle;
		if (cx->type == OMAP3_STATE_C1)
			dev->safe_state = state;
		sprintf(state->name, "C%d", count+1);
		count++;
	}

	if (!count)
		return -EINVAL;
	dev->state_count = count;

	if (cpuidle_register_device(dev)) {
		printk(KERN_ERR "%s: CPUidle register device failed\n",
		       __func__);
		return -EIO;
	}

	return 0;
}
#else
int __init omap3_idle_init(void)
{
	return 0;
}
#endif /* CONFIG_CPU_IDLE */
Commit	Line	Data
99e6a4d2 RN	1	/*
	2	* linux/arch/arm/mach-omap2/cpuidle34xx.c
	3	*
	4	* OMAP3 CPU IDLE Routines
	5	*
	6	* Copyright (C) 2008 Texas Instruments, Inc.
	7	* Rajendra Nayak <rnayak@ti.com>
	8	*
	9	* Copyright (C) 2007 Texas Instruments, Inc.
	10	* Karthik Dasu <karthik-dp@ti.com>
	11	*
	12	* Copyright (C) 2006 Nokia Corporation
	13	* Tony Lindgren <tony@atomide.com>
	14	*
	15	* Copyright (C) 2005 Texas Instruments, Inc.
	16	* Richard Woodruff <r-woodruff2@ti.com>
	17	*
	18	* Based on pm.c for omap2
	19	*
	20	* This program is free software; you can redistribute it and/or modify
	21	* it under the terms of the GNU General Public License version 2 as
	22	* published by the Free Software Foundation.
	23	*/
	24
	25	#include <linux/cpuidle.h>
	26
	27	#include <plat/prcm.h>
20b01669	28	#include <plat/irqs.h>
06d8f065 PDS	29	#include <plat/powerdomain.h>
06d8f065 PDS	30	#include <plat/clockdomain.h>
20b01669	31	#include <plat/control.h>
0f724ed9	32	#include <plat/serial.h>
99e6a4d2	33
c98e2230 KH	34	#include "pm.h"
c98e2230 KH	35
99e6a4d2 RN	36	#ifdef CONFIG_CPU_IDLE
99e6a4d2 RN	37
8e431edb SP	38	#define OMAP3_MAX_STATES 7
	39	#define OMAP3_STATE_C1 0 /* C1 - MPU WFI + Core active */
	40	#define OMAP3_STATE_C2 1 /* C2 - MPU WFI + Core inactive */
	41	#define OMAP3_STATE_C3 2 /* C3 - MPU CSWR + Core inactive */
	42	#define OMAP3_STATE_C4 3 /* C4 - MPU OFF + Core iactive */
	43	#define OMAP3_STATE_C5 4 /* C5 - MPU RET + Core RET */
	44	#define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core RET */
	45	#define OMAP3_STATE_C7 6 /* C7 - MPU OFF + Core OFF */
99e6a4d2 RN	46
	47	struct omap3_processor_cx {
	48	u8 valid;
	49	u8 type;
	50	u32 sleep_latency;
	51	u32 wakeup_latency;
	52	u32 mpu_state;
	53	u32 core_state;
	54	u32 threshold;
	55	u32 flags;
	56	};
	57
	58	struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
	59	struct omap3_processor_cx current_cx_state;
20b01669	60	struct powerdomain mpu_pd, core_pd;
99e6a4d2 RN	61
	62	static int omap3_idle_bm_check(void)
	63	{
20b01669 RN	64	if (!omap3_can_sleep())
20b01669 RN	65	return 1;
99e6a4d2 RN	66	return 0;
	67	}
	68
06d8f065 PDS	69	static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
	70	struct clockdomain *clkdm)
	71	{
	72	omap2_clkdm_allow_idle(clkdm);
	73	return 0;
	74	}
	75
	76	static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
	77	struct clockdomain *clkdm)
	78	{
	79	omap2_clkdm_deny_idle(clkdm);
	80	return 0;
	81	}
	82
99e6a4d2 RN	83	/**
	84	* omap3_enter_idle - Programs OMAP3 to enter the specified state
	85	* @dev: cpuidle device
	86	* @state: The target state to be programmed
	87	*
	88	* Called from the CPUidle framework to program the device to the
	89	* specified target state selected by the governor.
	90	*/
	91	static int omap3_enter_idle(struct cpuidle_device *dev,
	92	struct cpuidle_state *state)
	93	{
	94	struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
	95	struct timespec ts_preidle, ts_postidle, ts_idle;
c98e2230	96	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
99e6a4d2 RN	97
	98	current_cx_state = *cx;
	99
	100	/* Used to keep track of the total time in idle */
	101	getnstimeofday(&ts_preidle);
	102
	103	local_irq_disable();
	104	local_fiq_disable();
	105
c98e2230 KH	106	if (!enable_off_mode) {
	107	if (mpu_state < PWRDM_POWER_RET)
	108	mpu_state = PWRDM_POWER_RET;
	109	if (core_state < PWRDM_POWER_RET)
	110	core_state = PWRDM_POWER_RET;
	111	}
	112
7139178e JH	113	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
7139178e JH	114	pwrdm_set_next_pwrst(core_pd, core_state);
20b01669 RN	115
	116	if (omap_irq_pending())
	117	goto return_sleep_time;
99e6a4d2	118
06d8f065 PDS	119	if (cx->type == OMAP3_STATE_C1) {
	120	pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
	121	pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
	122	}
	123
99e6a4d2 RN	124	/* Execute ARM wfi */
	125	omap_sram_idle();
	126
06d8f065 PDS	127	if (cx->type == OMAP3_STATE_C1) {
	128	pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
	129	pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
	130	}
	131
20b01669	132	return_sleep_time:
99e6a4d2 RN	133	getnstimeofday(&ts_postidle);
	134	ts_idle = timespec_sub(ts_postidle, ts_preidle);
	135
	136	local_irq_enable();
	137	local_fiq_enable();
	138
20b01669	139	return (u32)timespec_to_ns(&ts_idle)/1000;
99e6a4d2 RN	140	}
	141
	142	/**
	143	* omap3_enter_idle_bm - Checks for any bus activity
	144	* @dev: cpuidle device
	145	* @state: The target state to be programmed
	146	*
	147	* Used for C states with CPUIDLE_FLAG_CHECK_BM flag set. This
	148	* function checks for any pending activity and then programs the
	149	* device to the specified or a safer state.
	150	*/
	151	static int omap3_enter_idle_bm(struct cpuidle_device *dev,
	152	struct cpuidle_state *state)
	153	{
0f724ed9 KH	154	struct cpuidle_state *new_state = state;
0f724ed9 KH	155
99e6a4d2	156	if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
0f724ed9 KH	157	BUG_ON(!dev->safe_state);
0f724ed9 KH	158	new_state = dev->safe_state;
99e6a4d2	159	}
0f724ed9 KH	160
	161	dev->last_state = new_state;
	162	return omap3_enter_idle(dev, new_state);
99e6a4d2 RN	163	}
	164
	165	DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
	166
	167	/* omap3_init_power_states - Initialises the OMAP3 specific C states.
	168	*
	169	* Below is the desciption of each C state.
06d8f065 PDS	170	* C1 . MPU WFI + Core active
	171	* C2 . MPU WFI + Core inactive
	172	* C3 . MPU CSWR + Core inactive
	173	* C4 . MPU OFF + Core inactive
	174	* C5 . MPU CSWR + Core CSWR
	175	* C6 . MPU OFF + Core CSWR
	176	* C7 . MPU OFF + Core OFF
99e6a4d2 RN	177	*/
	178	void omap_init_power_states(void)
	179	{
	180	/* C1 . MPU WFI + Core active */
	181	omap3_power_states[OMAP3_STATE_C1].valid = 1;
	182	omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
06d8f065 PDS	183	omap3_power_states[OMAP3_STATE_C1].sleep_latency = 2;
	184	omap3_power_states[OMAP3_STATE_C1].wakeup_latency = 2;
	185	omap3_power_states[OMAP3_STATE_C1].threshold = 5;
99e6a4d2 RN	186	omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
	187	omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
	188	omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
	189
06d8f065	190	/* C2 . MPU WFI + Core inactive */
99e6a4d2 RN	191	omap3_power_states[OMAP3_STATE_C2].valid = 1;
99e6a4d2 RN	192	omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
06d8f065 PDS	193	omap3_power_states[OMAP3_STATE_C2].sleep_latency = 10;
	194	omap3_power_states[OMAP3_STATE_C2].wakeup_latency = 10;
	195	omap3_power_states[OMAP3_STATE_C2].threshold = 30;
	196	omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
99e6a4d2	197	omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
06d8f065	198	omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID;
99e6a4d2	199
06d8f065	200	/* C3 . MPU CSWR + Core inactive */
20b01669	201	omap3_power_states[OMAP3_STATE_C3].valid = 1;
99e6a4d2	202	omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3;
06d8f065 PDS	203	omap3_power_states[OMAP3_STATE_C3].sleep_latency = 50;
	204	omap3_power_states[OMAP3_STATE_C3].wakeup_latency = 50;
	205	omap3_power_states[OMAP3_STATE_C3].threshold = 300;
	206	omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET;
99e6a4d2	207	omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
0f724ed9 KH	208	omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID \|
0f724ed9 KH	209	CPUIDLE_FLAG_CHECK_BM;
99e6a4d2	210
06d8f065	211	/* C4 . MPU OFF + Core inactive */
20b01669	212	omap3_power_states[OMAP3_STATE_C4].valid = 1;
99e6a4d2	213	omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4;
06d8f065 PDS	214	omap3_power_states[OMAP3_STATE_C4].sleep_latency = 1500;
	215	omap3_power_states[OMAP3_STATE_C4].wakeup_latency = 1800;
	216	omap3_power_states[OMAP3_STATE_C4].threshold = 4000;
	217	omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF;
	218	omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON;
99e6a4d2 RN	219	omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID \|
	220	CPUIDLE_FLAG_CHECK_BM;
	221
06d8f065	222	/* C5 . MPU CSWR + Core CSWR*/
20b01669	223	omap3_power_states[OMAP3_STATE_C5].valid = 1;
99e6a4d2	224	omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5;
06d8f065 PDS	225	omap3_power_states[OMAP3_STATE_C5].sleep_latency = 2500;
	226	omap3_power_states[OMAP3_STATE_C5].wakeup_latency = 7500;
	227	omap3_power_states[OMAP3_STATE_C5].threshold = 12000;
	228	omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET;
99e6a4d2 RN	229	omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
	230	omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID \|
	231	CPUIDLE_FLAG_CHECK_BM;
	232
06d8f065	233	/* C6 . MPU OFF + Core CSWR */
0f724ed9	234	omap3_power_states[OMAP3_STATE_C6].valid = 1;
99e6a4d2	235	omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6;
06d8f065 PDS	236	omap3_power_states[OMAP3_STATE_C6].sleep_latency = 3000;
	237	omap3_power_states[OMAP3_STATE_C6].wakeup_latency = 8500;
	238	omap3_power_states[OMAP3_STATE_C6].threshold = 15000;
99e6a4d2	239	omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF;
06d8f065	240	omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET;
99e6a4d2 RN	241	omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID \|
99e6a4d2 RN	242	CPUIDLE_FLAG_CHECK_BM;
06d8f065 PDS	243
	244	/* C7 . MPU OFF + Core OFF */
	245	omap3_power_states[OMAP3_STATE_C7].valid = 1;
	246	omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7;
	247	omap3_power_states[OMAP3_STATE_C7].sleep_latency = 10000;
	248	omap3_power_states[OMAP3_STATE_C7].wakeup_latency = 30000;
	249	omap3_power_states[OMAP3_STATE_C7].threshold = 300000;
	250	omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF;
	251	omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
	252	omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID \|
	253	CPUIDLE_FLAG_CHECK_BM;
99e6a4d2 RN	254	}
	255
	256	struct cpuidle_driver omap3_idle_driver = {
	257	.name = "omap3_idle",
	258	.owner = THIS_MODULE,
	259	};
	260
	261	/**
	262	* omap3_idle_init - Init routine for OMAP3 idle
	263	*
	264	* Registers the OMAP3 specific cpuidle driver with the cpuidle
	265	* framework with the valid set of states.
	266	*/
0343371e	267	int __init omap3_idle_init(void)
99e6a4d2 RN	268	{
	269	int i, count = 0;
	270	struct omap3_processor_cx *cx;
	271	struct cpuidle_state *state;
	272	struct cpuidle_device *dev;
	273
	274	mpu_pd = pwrdm_lookup("mpu_pwrdm");
20b01669	275	core_pd = pwrdm_lookup("core_pwrdm");
99e6a4d2 RN	276
	277	omap_init_power_states();
	278	cpuidle_register_driver(&omap3_idle_driver);
	279
	280	dev = &per_cpu(omap3_idle_dev, smp_processor_id());
	281
8e431edb	282	for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
99e6a4d2 RN	283	cx = &omap3_power_states[i];
	284	state = &dev->states[count];
	285
	286	if (!cx->valid)
	287	continue;
	288	cpuidle_set_statedata(state, cx);
	289	state->exit_latency = cx->sleep_latency + cx->wakeup_latency;
	290	state->target_residency = cx->threshold;
	291	state->flags = cx->flags;
	292	state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
	293	omap3_enter_idle_bm : omap3_enter_idle;
	294	if (cx->type == OMAP3_STATE_C1)
	295	dev->safe_state = state;
	296	sprintf(state->name, "C%d", count+1);
	297	count++;
	298	}
	299
	300	if (!count)
	301	return -EINVAL;
	302	dev->state_count = count;
	303
	304	if (cpuidle_register_device(dev)) {
	305	printk(KERN_ERR "%s: CPUidle register device failed\n",
	306	__func__);
	307	return -EIO;
	308	}
	309
	310	return 0;
	311	}
0343371e KJ	312	#else
	313	int __init omap3_idle_init(void)
	314	{
	315	return 0;
	316	}
99e6a4d2	317	#endif /* CONFIG_CPU_IDLE */