[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / boot / dts / omap5.dtsi

/*
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 * Based on "omap4.dtsi"
 */

/*
 * Carveout for multimedia usecases
 * It should be the last 48MB of the first 512MB memory part
 * In theory, it should not even exist. That zone should be reserved
 * dynamically during the .reserve callback.
 */
/memreserve/ 0x9d000000 0x03000000;

/include/ "skeleton.dtsi"

/ {
	compatible = "ti,omap5";
	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
	};

	cpus {
		cpu@0 {
			compatible = "arm,cortex-a15";
			timer {
				compatible = "arm,armv7-timer";
				/* 14th PPI IRQ, active low level-sensitive */
				interrupts = <1 14 0x308>;
				clock-frequency = <6144000>;
			};
		};
		cpu@1 {
			compatible = "arm,cortex-a15";
			timer {
				compatible = "arm,armv7-timer";
				/* 14th PPI IRQ, active low level-sensitive */
				interrupts = <1 14 0x308>;
				clock-frequency = <6144000>;
			};
		};
	};

	/*
	 * The soc node represents the soc top level view. It is uses for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap5-mpu";
			ti,hwmods = "mpu";
		};
	};

	/*
	 * XXX: Use a flat representation of the OMAP3 interconnect.
	 * The real OMAP interconnect network is quite complex.
	 * Since that will not bring real advantage to represent that in DT for
	 * the moment, just use a fake OCP bus entry to represent the whole bus
	 * hierarchy.
	 */
	ocp {
		compatible = "ti,omap4-l3-noc", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";

		omap5_pmx_core: pinmux@4a002840 {
			compatible = "ti,omap4-padconf", "pinctrl-single";
			reg = <0x4a002840 0x01b6>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0x7fff>;
		};
		omap5_pmx_wkup: pinmux@4ae0c840 {
			compatible = "ti,omap4-padconf", "pinctrl-single";
			reg = <0x4ae0c840 0x0038>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0x7fff>;
		};

		gic: interrupt-controller@48211000 {
			compatible = "arm,cortex-a15-gic";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x48211000 0x1000>,
			      <0x48212000 0x1000>;
		};

		gpio1: gpio@4ae10000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio1";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio2: gpio@48055000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio2";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio3: gpio@48057000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio3";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio4: gpio@48059000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio4";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio5: gpio@4805b000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio5";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio6: gpio@4805d000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio6";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio7: gpio@48051000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio7";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio8: gpio@48053000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio8";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		i2c1: i2c@48070000 {
			compatible = "ti,omap4-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c1";
		};

		i2c2: i2c@48072000 {
			compatible = "ti,omap4-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c2";
		};

		i2c3: i2c@48060000 {
			compatible = "ti,omap4-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c3";
		};

		i2c4: i2c@4807A000 {
			compatible = "ti,omap4-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c4";
		};

		i2c5: i2c@4807C000 {
			compatible = "ti,omap4-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c5";
		};

		uart1: serial@4806a000 {
			compatible = "ti,omap4-uart";
			ti,hwmods = "uart1";
			clock-frequency = <48000000>;
		};

		uart2: serial@4806c000 {
			compatible = "ti,omap4-uart";
			ti,hwmods = "uart2";
			clock-frequency = <48000000>;
		};

		uart3: serial@48020000 {
			compatible = "ti,omap4-uart";
			ti,hwmods = "uart3";
			clock-frequency = <48000000>;
		};

		uart4: serial@4806e000 {
			compatible = "ti,omap4-uart";
			ti,hwmods = "uart4";
			clock-frequency = <48000000>;
		};

		uart5: serial@48066000 {
			compatible = "ti,omap5-uart";
			ti,hwmods = "uart5";
			clock-frequency = <48000000>;
		};

		uart6: serial@48068000 {
			compatible = "ti,omap6-uart";
			ti,hwmods = "uart6";
			clock-frequency = <48000000>;
		};

		mmc1: mmc@4809c000 {
			compatible = "ti,omap4-hsmmc";
			ti,hwmods = "mmc1";
			ti,dual-volt;
			ti,needs-special-reset;
		};

		mmc2: mmc@480b4000 {
			compatible = "ti,omap4-hsmmc";
			ti,hwmods = "mmc2";
			ti,needs-special-reset;
		};

		mmc3: mmc@480ad000 {
			compatible = "ti,omap4-hsmmc";
			ti,hwmods = "mmc3";
			ti,needs-special-reset;
		};

		mmc4: mmc@480d1000 {
			compatible = "ti,omap4-hsmmc";
			ti,hwmods = "mmc4";
			ti,needs-special-reset;
		};

		mmc5: mmc@480d5000 {
			compatible = "ti,omap4-hsmmc";
			ti,hwmods = "mmc5";
			ti,needs-special-reset;
		};

		keypad: keypad@4ae1c000 {
			compatible = "ti,omap4-keypad";
			ti,hwmods = "kbd";
		};

		mcpdm: mcpdm@40132000 {
			compatible = "ti,omap4-mcpdm";
			reg = <0x40132000 0x7f>, /* MPU private access */
			      <0x49032000 0x7f>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 112 0x4>;
			ti,hwmods = "mcpdm";
		};

		dmic: dmic@4012e000 {
			compatible = "ti,omap4-dmic";
			reg = <0x4012e000 0x7f>, /* MPU private access */
			      <0x4902e000 0x7f>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 114 0x4>;
			ti,hwmods = "dmic";
		};

		mcbsp1: mcbsp@40122000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40122000 0xff>, /* MPU private access */
			      <0x49022000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 17 0x4>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp1";
		};

		mcbsp2: mcbsp@40124000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40124000 0xff>, /* MPU private access */
			      <0x49024000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 22 0x4>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp2";
		};

		mcbsp3: mcbsp@40126000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40126000 0xff>, /* MPU private access */
			      <0x49026000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 23 0x4>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp3";
		};
	};
};
Commit	Line	Data
6b5de091 S	1	/*
	2	* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	* Based on "omap4.dtsi"
	8	*/
	9
	10	/*
	11	* Carveout for multimedia usecases
	12	* It should be the last 48MB of the first 512MB memory part
	13	* In theory, it should not even exist. That zone should be reserved
	14	* dynamically during the .reserve callback.
	15	*/
	16	/memreserve/ 0x9d000000 0x03000000;
	17
	18	/include/ "skeleton.dtsi"
	19
	20	/ {
	21	compatible = "ti,omap5";
	22	interrupt-parent = <&gic>;
	23
	24	aliases {
	25	serial0 = &uart1;
	26	serial1 = &uart2;
	27	serial2 = &uart3;
	28	serial3 = &uart4;
	29	serial4 = &uart5;
	30	serial5 = &uart6;
	31	};
	32
	33	cpus {
	34	cpu@0 {
	35	compatible = "arm,cortex-a15";
3c7c5dab SS	36	timer {
	37	compatible = "arm,armv7-timer";
	38	/* 14th PPI IRQ, active low level-sensitive */
	39	interrupts = <1 14 0x308>;
	40	clock-frequency = <6144000>;
	41	};
6b5de091 S	42	};
	43	cpu@1 {
	44	compatible = "arm,cortex-a15";
3c7c5dab SS	45	timer {
	46	compatible = "arm,armv7-timer";
	47	/* 14th PPI IRQ, active low level-sensitive */
	48	interrupts = <1 14 0x308>;
	49	clock-frequency = <6144000>;
	50	};
6b5de091 S	51	};
	52	};
	53
	54	/*
	55	* The soc node represents the soc top level view. It is uses for IPs
	56	* that are not memory mapped in the MPU view or for the MPU itself.
	57	*/
	58	soc {
	59	compatible = "ti,omap-infra";
	60	mpu {
	61	compatible = "ti,omap5-mpu";
	62	ti,hwmods = "mpu";
	63	};
	64	};
	65
	66	/*
	67	* XXX: Use a flat representation of the OMAP3 interconnect.
	68	* The real OMAP interconnect network is quite complex.
	69	* Since that will not bring real advantage to represent that in DT for
	70	* the moment, just use a fake OCP bus entry to represent the whole bus
	71	* hierarchy.
	72	*/
	73	ocp {
	74	compatible = "ti,omap4-l3-noc", "simple-bus";
	75	#address-cells = <1>;
	76	#size-cells = <1>;
	77	ranges;
	78	ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
	79
5da6a2d5 PU	80	omap5_pmx_core: pinmux@4a002840 {
	81	compatible = "ti,omap4-padconf", "pinctrl-single";
	82	reg = <0x4a002840 0x01b6>;
	83	#address-cells = <1>;
	84	#size-cells = <0>;
	85	pinctrl-single,register-width = <16>;
	86	pinctrl-single,function-mask = <0x7fff>;
	87	};
	88	omap5_pmx_wkup: pinmux@4ae0c840 {
	89	compatible = "ti,omap4-padconf", "pinctrl-single";
	90	reg = <0x4ae0c840 0x0038>;
	91	#address-cells = <1>;
	92	#size-cells = <0>;
	93	pinctrl-single,register-width = <16>;
	94	pinctrl-single,function-mask = <0x7fff>;
	95	};
	96
6b5de091 S	97	gic: interrupt-controller@48211000 {
	98	compatible = "arm,cortex-a15-gic";
	99	interrupt-controller;
	100	#interrupt-cells = <3>;
	101	reg = <0x48211000 0x1000>,
	102	<0x48212000 0x1000>;
	103	};
	104
	105	gpio1: gpio@4ae10000 {
	106	compatible = "ti,omap4-gpio";
	107	ti,hwmods = "gpio1";
	108	gpio-controller;
	109	#gpio-cells = <2>;
	110	interrupt-controller;
	111	#interrupt-cells = <1>;
	112	};
	113
	114	gpio2: gpio@48055000 {
	115	compatible = "ti,omap4-gpio";
	116	ti,hwmods = "gpio2";
	117	gpio-controller;
	118	#gpio-cells = <2>;
	119	interrupt-controller;
	120	#interrupt-cells = <1>;
	121	};
	122
	123	gpio3: gpio@48057000 {
	124	compatible = "ti,omap4-gpio";
	125	ti,hwmods = "gpio3";
	126	gpio-controller;
	127	#gpio-cells = <2>;
	128	interrupt-controller;
	129	#interrupt-cells = <1>;
	130	};
	131
	132	gpio4: gpio@48059000 {
	133	compatible = "ti,omap4-gpio";
	134	ti,hwmods = "gpio4";
	135	gpio-controller;
	136	#gpio-cells = <2>;
	137	interrupt-controller;
	138	#interrupt-cells = <1>;
	139	};
	140
	141	gpio5: gpio@4805b000 {
	142	compatible = "ti,omap4-gpio";
	143	ti,hwmods = "gpio5";
	144	gpio-controller;
	145	#gpio-cells = <2>;
	146	interrupt-controller;
	147	#interrupt-cells = <1>;
	148	};
	149
	150	gpio6: gpio@4805d000 {
	151	compatible = "ti,omap4-gpio";
	152	ti,hwmods = "gpio6";
	153	gpio-controller;
	154	#gpio-cells = <2>;
	155	interrupt-controller;
	156	#interrupt-cells = <1>;
	157	};
	158
	159	gpio7: gpio@48051000 {
	160	compatible = "ti,omap4-gpio";
161	ti,hwmods = "gpio7";
162	gpio-controller;
163	#gpio-cells = <2>;
164	interrupt-controller;
165	#interrupt-cells = <1>;
166	};
167
168	gpio8: gpio@48053000 {
169	compatible = "ti,omap4-gpio";
170	ti,hwmods = "gpio8";
171	gpio-controller;
172	#gpio-cells = <2>;
173	interrupt-controller;
174	#interrupt-cells = <1>;
175	};
176
6e6a9a50 SP	177	i2c1: i2c@48070000 {
	178	compatible = "ti,omap4-i2c";
	179	#address-cells = <1>;
	180	#size-cells = <0>;
	181	ti,hwmods = "i2c1";
	182	};
	183
	184	i2c2: i2c@48072000 {
	185	compatible = "ti,omap4-i2c";
	186	#address-cells = <1>;
	187	#size-cells = <0>;
	188	ti,hwmods = "i2c2";
	189	};
	190
	191	i2c3: i2c@48060000 {
	192	compatible = "ti,omap4-i2c";
	193	#address-cells = <1>;
	194	#size-cells = <0>;
	195	ti,hwmods = "i2c3";
	196	};
	197
	198	i2c4: i2c@4807A000 {
	199	compatible = "ti,omap4-i2c";
	200	#address-cells = <1>;
	201	#size-cells = <0>;
	202	ti,hwmods = "i2c4";
	203	};
	204
	205	i2c5: i2c@4807C000 {
	206	compatible = "ti,omap4-i2c";
	207	#address-cells = <1>;
	208	#size-cells = <0>;
	209	ti,hwmods = "i2c5";
	210	};
	211
6b5de091 S	212	uart1: serial@4806a000 {
	213	compatible = "ti,omap4-uart";
	214	ti,hwmods = "uart1";
	215	clock-frequency = <48000000>;
	216	};
	217
	218	uart2: serial@4806c000 {
	219	compatible = "ti,omap4-uart";
	220	ti,hwmods = "uart2";
	221	clock-frequency = <48000000>;
	222	};
	223
	224	uart3: serial@48020000 {
	225	compatible = "ti,omap4-uart";
	226	ti,hwmods = "uart3";
	227	clock-frequency = <48000000>;
	228	};
	229
	230	uart4: serial@4806e000 {
	231	compatible = "ti,omap4-uart";
	232	ti,hwmods = "uart4";
	233	clock-frequency = <48000000>;
	234	};
	235
	236	uart5: serial@48066000 {
	237	compatible = "ti,omap5-uart";
	238	ti,hwmods = "uart5";
	239	clock-frequency = <48000000>;
	240	};
	241
	242	uart6: serial@48068000 {
	243	compatible = "ti,omap6-uart";
	244	ti,hwmods = "uart6";
	245	clock-frequency = <48000000>;
	246	};
5dd18b01 B	247
	248	mmc1: mmc@4809c000 {
	249	compatible = "ti,omap4-hsmmc";
	250	ti,hwmods = "mmc1";
	251	ti,dual-volt;
	252	ti,needs-special-reset;
	253	};
	254
	255	mmc2: mmc@480b4000 {
	256	compatible = "ti,omap4-hsmmc";
	257	ti,hwmods = "mmc2";
	258	ti,needs-special-reset;
	259	};
	260
	261	mmc3: mmc@480ad000 {
	262	compatible = "ti,omap4-hsmmc";
	263	ti,hwmods = "mmc3";
	264	ti,needs-special-reset;
	265	};
	266
	267	mmc4: mmc@480d1000 {
	268	compatible = "ti,omap4-hsmmc";
	269	ti,hwmods = "mmc4";
	270	ti,needs-special-reset;
	271	};
	272
	273	mmc5: mmc@480d5000 {
	274	compatible = "ti,omap4-hsmmc";
	275	ti,hwmods = "mmc5";
	276	ti,needs-special-reset;
	277	};
5449fbc2 SP	278
	279	keypad: keypad@4ae1c000 {
	280	compatible = "ti,omap4-keypad";
	281	ti,hwmods = "kbd";
	282	};
ffd5db24	283
cbb57f07 PU	284	mcpdm: mcpdm@40132000 {
	285	compatible = "ti,omap4-mcpdm";
	286	reg = <0x40132000 0x7f>, /* MPU private access */
	287	<0x49032000 0x7f>; /* L3 Interconnect */
	288	reg-names = "mpu", "dma";
	289	interrupts = <0 112 0x4>;
cbb57f07 PU	290	ti,hwmods = "mcpdm";
	291	};
	292
	293	dmic: dmic@4012e000 {
	294	compatible = "ti,omap4-dmic";
	295	reg = <0x4012e000 0x7f>, /* MPU private access */
	296	<0x4902e000 0x7f>; /* L3 Interconnect */
	297	reg-names = "mpu", "dma";
	298	interrupts = <0 114 0x4>;
cbb57f07 PU	299	ti,hwmods = "dmic";
	300	};
	301
ffd5db24 PU	302	mcbsp1: mcbsp@40122000 {
	303	compatible = "ti,omap4-mcbsp";
	304	reg = <0x40122000 0xff>, /* MPU private access */
	305	<0x49022000 0xff>; /* L3 Interconnect */
	306	reg-names = "mpu", "dma";
	307	interrupts = <0 17 0x4>;
	308	interrupt-names = "common";
ffd5db24 PU	309	ti,buffer-size = <128>;
	310	ti,hwmods = "mcbsp1";
	311	};
	312
	313	mcbsp2: mcbsp@40124000 {
	314	compatible = "ti,omap4-mcbsp";
	315	reg = <0x40124000 0xff>, /* MPU private access */
	316	<0x49024000 0xff>; /* L3 Interconnect */
	317	reg-names = "mpu", "dma";
	318	interrupts = <0 22 0x4>;
	319	interrupt-names = "common";
ffd5db24 PU	320	ti,buffer-size = <128>;
	321	ti,hwmods = "mcbsp2";
	322	};
	323
	324	mcbsp3: mcbsp@40126000 {
	325	compatible = "ti,omap4-mcbsp";
	326	reg = <0x40126000 0xff>, /* MPU private access */
	327	<0x49026000 0xff>; /* L3 Interconnect */
	328	reg-names = "mpu", "dma";
	329	interrupts = <0 23 0x4>;
	330	interrupt-names = "common";
ffd5db24 PU	331	ti,buffer-size = <128>;
	332	ti,hwmods = "mcbsp3";
	333	};
6b5de091 S	334	};
6b5de091 S	335	};