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Merge tag 'v3.10.107' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / tty / serial / 8250 / 8250_pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
1da177e4
LT		 11 */
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/pci.h>
1da177e4
LT		 15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
0ad372b9 20#include <linux/serial_reg.h>
1da177e4
LT		 21#include <linux/serial_core.h>
22#include <linux/8250_pci.h>
23#include <linux/bitops.h>
24
25#include <asm/byteorder.h>
26#include <asm/io.h>
27
28#include "8250.h"
29
30#undef SERIAL_DEBUG_PCI
31
1da177e4
LT		 32/*
33 * init function returns:
34 * > 0 - number of ports
35 * = 0 - use board->num_ports
36 * < 0 - error
37 */
38struct pci_serial_quirk {
39 u32 vendor;
40 u32 device;
41 u32 subvendor;
42 u32 subdevice;
5bf8f501 43 int (*probe)(struct pci_dev *dev);
1da177e4 44 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
2655a2c7 47 struct uart_8250_port *, int);
1da177e4
LT		 48 void (*exit)(struct pci_dev *dev);
49};
50
51#define PCI_NUM_BAR_RESOURCES 6
52
53struct serial_private {
70db3d91 54 struct pci_dev *dev;
1da177e4
LT		 55 unsigned int nr;
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
1d662dc0 58 const struct pciserial_board *board;
1da177e4
LT		 59 int line[0];
60};
61
7808edcd 62static int pci_default_setup(struct serial_private*,
2655a2c7 63 const struct pciserial_board*, struct uart_8250_port *, int);
7808edcd 64
1da177e4
LT		 65static void moan_device(const char *str, struct pci_dev *dev)
66{
ad361c98
JP		 67 printk(KERN_WARNING
68 "%s: %s\n"
69 "Please send the output of lspci -vv, this\n"
70 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
71 "manufacturer and name of serial board or\n"
8706baf7 72 "modem board to <linux-serial@vger.kernel.org>.\n",
1da177e4
LT		 73 pci_name(dev), str, dev->vendor, dev->device,
74 dev->subsystem_vendor, dev->subsystem_device);
75}
76
77static int
2655a2c7 78setup_port(struct serial_private *priv, struct uart_8250_port *port,
1da177e4
LT		 79 int bar, int offset, int regshift)
80{
70db3d91 81 struct pci_dev *dev = priv->dev;
1da177e4
LT		 82 unsigned long base, len;
83
84 if (bar >= PCI_NUM_BAR_RESOURCES)
85 return -EINVAL;
86
72ce9a83
RK		 87 base = pci_resource_start(dev, bar);
88
1da177e4 89 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 90 len = pci_resource_len(dev, bar);
91
92 if (!priv->remapped_bar[bar])
6f441fe9 93 priv->remapped_bar[bar] = ioremap_nocache(base, len);
1da177e4
LT		 94 if (!priv->remapped_bar[bar])
95 return -ENOMEM;
96
2655a2c7
AC		 97 port->port.iotype = UPIO_MEM;
98 port->port.iobase = 0;
99 port->port.mapbase = base + offset;
100 port->port.membase = priv->remapped_bar[bar] + offset;
101 port->port.regshift = regshift;
1da177e4 102 } else {
2655a2c7
AC		 103 port->port.iotype = UPIO_PORT;
104 port->port.iobase = base + offset;
105 port->port.mapbase = 0;
106 port->port.membase = NULL;
107 port->port.regshift = 0;
1da177e4
LT		 108 }
109 return 0;
110}
111
02c9b5cf
KJ		 112/*
113 * ADDI-DATA GmbH communication cards <info@addi-data.com>
114 */
115static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 116 const struct pciserial_board *board,
2655a2c7 117 struct uart_8250_port *port, int idx)
02c9b5cf
KJ		 118{
119 unsigned int bar = 0, offset = board->first_offset;
120 bar = FL_GET_BASE(board->flags);
121
122 if (idx < 2) {
123 offset += idx * board->uart_offset;
124 } else if ((idx >= 2) && (idx < 4)) {
125 bar += 1;
126 offset += ((idx - 2) * board->uart_offset);
127 } else if ((idx >= 4) && (idx < 6)) {
128 bar += 2;
129 offset += ((idx - 4) * board->uart_offset);
130 } else if (idx >= 6) {
131 bar += 3;
132 offset += ((idx - 6) * board->uart_offset);
133 }
134
135 return setup_port(priv, port, bar, offset, board->reg_shift);
136}
137
1da177e4
LT		 138/*
139 * AFAVLAB uses a different mixture of BARs and offsets
140 * Not that ugly ;) -- HW
141 */
142static int
975a1a7d 143afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 144 struct uart_8250_port *port, int idx)
1da177e4
LT		 145{
146 unsigned int bar, offset = board->first_offset;
5756ee99 147
1da177e4
LT		 148 bar = FL_GET_BASE(board->flags);
149 if (idx < 4)
150 bar += idx;
151 else {
152 bar = 4;
153 offset += (idx - 4) * board->uart_offset;
154 }
155
70db3d91 156 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 157}
158
159/*
160 * HP's Remote Management Console. The Diva chip came in several
161 * different versions. N-class, L2000 and A500 have two Diva chips, each
162 * with 3 UARTs (the third UART on the second chip is unused). Superdome
163 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
164 * one Diva chip, but it has been expanded to 5 UARTs.
165 */
61a116ef 166static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 167{
168 int rc = 0;
169
170 switch (dev->subsystem_device) {
171 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
172 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
173 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
174 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
175 rc = 3;
176 break;
177 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
178 rc = 2;
179 break;
180 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
181 rc = 4;
182 break;
183 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 184 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 185 rc = 1;
186 break;
187 }
188
189 return rc;
190}
191
192/*
193 * HP's Diva chip puts the 4th/5th serial port further out, and
194 * some serial ports are supposed to be hidden on certain models.
195 */
196static int
975a1a7d
RK		 197pci_hp_diva_setup(struct serial_private *priv,
198 const struct pciserial_board *board,
2655a2c7 199 struct uart_8250_port *port, int idx)
1da177e4
LT		 200{
201 unsigned int offset = board->first_offset;
202 unsigned int bar = FL_GET_BASE(board->flags);
203
70db3d91 204 switch (priv->dev->subsystem_device) {
1da177e4
LT		 205 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
206 if (idx == 3)
207 idx++;
208 break;
209 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
210 if (idx > 0)
211 idx++;
212 if (idx > 2)
213 idx++;
214 break;
215 }
216 if (idx > 2)
217 offset = 0x18;
218
219 offset += idx * board->uart_offset;
220
70db3d91 221 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 222}
223
224/*
225 * Added for EKF Intel i960 serial boards
226 */
61a116ef 227static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4
LT		 228{
229 unsigned long oldval;
230
231 if (!(dev->subsystem_device & 0x1000))
232 return -ENODEV;
233
234 /* is firmware started? */
5756ee99
AC		 235 pci_read_config_dword(dev, 0x44, (void *)&oldval);
236 if (oldval == 0x00001000L) { /* RESET value */
1da177e4
LT		 237 printk(KERN_DEBUG "Local i960 firmware missing");
238 return -ENODEV;
239 }
240 return 0;
241}
242
243/*
244 * Some PCI serial cards using the PLX 9050 PCI interface chip require
245 * that the card interrupt be explicitly enabled or disabled. This
246 * seems to be mainly needed on card using the PLX which also use I/O
247 * mapped memory.
248 */
61a116ef 249static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 250{
251 u8 irq_config;
252 void __iomem *p;
253
254 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
255 moan_device("no memory in bar 0", dev);
256 return 0;
257 }
258
259 irq_config = 0x41;
add7b58e 260 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 261 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 262 irq_config = 0x43;
5756ee99 263
1da177e4 264 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 265 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 266 /*
267 * As the megawolf cards have the int pins active
268 * high, and have 2 UART chips, both ints must be
269 * enabled on the 9050. Also, the UARTS are set in
270 * 16450 mode by default, so we have to enable the
271 * 16C950 'enhanced' mode so that we can use the
272 * deep FIFOs
273 */
274 irq_config = 0x5b;
1da177e4
LT		 275 /*
276 * enable/disable interrupts
277 */
6f441fe9 278 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 279 if (p == NULL)
280 return -ENOMEM;
281 writel(irq_config, p + 0x4c);
282
283 /*
284 * Read the register back to ensure that it took effect.
285 */
286 readl(p + 0x4c);
287 iounmap(p);
288
289 return 0;
290}
291
ae8d8a14 292static void pci_plx9050_exit(struct pci_dev *dev)
1da177e4
LT		 293{
294 u8 __iomem *p;
295
296 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
297 return;
298
299 /*
300 * disable interrupts
301 */
6f441fe9 302 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 303 if (p != NULL) {
304 writel(0, p + 0x4c);
305
306 /*
307 * Read the register back to ensure that it took effect.
308 */
309 readl(p + 0x4c);
310 iounmap(p);
311 }
312}
313
04bf7e74
WP		 314#define NI8420_INT_ENABLE_REG 0x38
315#define NI8420_INT_ENABLE_BIT 0x2000
316
ae8d8a14 317static void pci_ni8420_exit(struct pci_dev *dev)
04bf7e74
WP		 318{
319 void __iomem *p;
320 unsigned long base, len;
321 unsigned int bar = 0;
322
323 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
324 moan_device("no memory in bar", dev);
325 return;
326 }
327
328 base = pci_resource_start(dev, bar);
329 len = pci_resource_len(dev, bar);
330 p = ioremap_nocache(base, len);
331 if (p == NULL)
332 return;
333
334 /* Disable the CPU Interrupt */
335 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
336 p + NI8420_INT_ENABLE_REG);
337 iounmap(p);
338}
339
340
46a0fac9
SB		 341/* MITE registers */
342#define MITE_IOWBSR1 0xc4
343#define MITE_IOWCR1 0xf4
344#define MITE_LCIMR1 0x08
345#define MITE_LCIMR2 0x10
346
347#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
348
ae8d8a14 349static void pci_ni8430_exit(struct pci_dev *dev)
46a0fac9
SB		 350{
351 void __iomem *p;
352 unsigned long base, len;
353 unsigned int bar = 0;
354
355 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
356 moan_device("no memory in bar", dev);
357 return;
358 }
359
360 base = pci_resource_start(dev, bar);
361 len = pci_resource_len(dev, bar);
362 p = ioremap_nocache(base, len);
363 if (p == NULL)
364 return;
365
366 /* Disable the CPU Interrupt */
367 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
368 iounmap(p);
369}
370
1da177e4
LT		 371/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
372static int
975a1a7d 373sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 374 struct uart_8250_port *port, int idx)
1da177e4
LT		 375{
376 unsigned int bar, offset = board->first_offset;
377
378 bar = 0;
379
380 if (idx < 4) {
381 /* first four channels map to 0, 0x100, 0x200, 0x300 */
382 offset += idx * board->uart_offset;
383 } else if (idx < 8) {
384 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
385 offset += idx * board->uart_offset + 0xC00;
386 } else /* we have only 8 ports on PMC-OCTALPRO */
387 return 1;
388
70db3d91 389 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 390}
391
392/*
393* This does initialization for PMC OCTALPRO cards:
394* maps the device memory, resets the UARTs (needed, bc
395* if the module is removed and inserted again, the card
396* is in the sleep mode) and enables global interrupt.
397*/
398
399/* global control register offset for SBS PMC-OctalPro */
400#define OCT_REG_CR_OFF 0x500
401
61a116ef 402static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 403{
404 u8 __iomem *p;
405
24ed3aba 406 p = pci_ioremap_bar(dev, 0);
1da177e4
LT		 407
408 if (p == NULL)
409 return -ENOMEM;
410 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 411 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 412 udelay(50);
5756ee99 413 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 414
415 /* Set bit-2 (INTENABLE) of Control Register */
416 writeb(0x4, p + OCT_REG_CR_OFF);
417 iounmap(p);
418
419 return 0;
420}
421
422/*
423 * Disables the global interrupt of PMC-OctalPro
424 */
425
ae8d8a14 426static void sbs_exit(struct pci_dev *dev)
1da177e4
LT		 427{
428 u8 __iomem *p;
429
24ed3aba 430 p = pci_ioremap_bar(dev, 0);
5756ee99
AC		 431 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
432 if (p != NULL)
1da177e4 433 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 434 iounmap(p);
435}
436
437/*
438 * SIIG serial cards have an PCI interface chip which also controls
439 * the UART clocking frequency. Each UART can be clocked independently
25985edc 440 * (except cards equipped with 4 UARTs) and initial clocking settings
1da177e4
LT		 441 * are stored in the EEPROM chip. It can cause problems because this
442 * version of serial driver doesn't support differently clocked UART's
443 * on single PCI card. To prevent this, initialization functions set
444 * high frequency clocking for all UART's on given card. It is safe (I
445 * hope) because it doesn't touch EEPROM settings to prevent conflicts
446 * with other OSes (like M$ DOS).
447 *
448 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 449 *
1da177e4
LT		 450 * There is two family of SIIG serial cards with different PCI
451 * interface chip and different configuration methods:
452 * - 10x cards have control registers in IO and/or memory space;
453 * - 20x cards have control registers in standard PCI configuration space.
454 *
67d74b87
RK		 455 * Note: all 10x cards have PCI device ids 0x10..
456 * all 20x cards have PCI device ids 0x20..
457 *
fbc0dc0d
AP		 458 * There are also Quartet Serial cards which use Oxford Semiconductor
459 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
460 *
1da177e4
LT		 461 * Note: some SIIG cards are probed by the parport_serial object.
462 */
463
464#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
465#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
466
467static int pci_siig10x_init(struct pci_dev *dev)
468{
469 u16 data;
470 void __iomem *p;
471
472 switch (dev->device & 0xfff8) {
473 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
474 data = 0xffdf;
475 break;
476 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
477 data = 0xf7ff;
478 break;
479 default: /* 1S1P, 4S */
480 data = 0xfffb;
481 break;
482 }
483
6f441fe9 484 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 485 if (p == NULL)
486 return -ENOMEM;
487
488 writew(readw(p + 0x28) & data, p + 0x28);
489 readw(p + 0x28);
490 iounmap(p);
491 return 0;
492}
493
494#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
495#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
496
497static int pci_siig20x_init(struct pci_dev *dev)
498{
499 u8 data;
500
501 /* Change clock frequency for the first UART. */
502 pci_read_config_byte(dev, 0x6f, &data);
503 pci_write_config_byte(dev, 0x6f, data & 0xef);
504
505 /* If this card has 2 UART, we have to do the same with second UART. */
506 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
507 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
508 pci_read_config_byte(dev, 0x73, &data);
509 pci_write_config_byte(dev, 0x73, data & 0xef);
510 }
511 return 0;
512}
513
67d74b87
RK		 514static int pci_siig_init(struct pci_dev *dev)
515{
516 unsigned int type = dev->device & 0xff00;
517
518 if (type == 0x1000)
519 return pci_siig10x_init(dev);
520 else if (type == 0x2000)
521 return pci_siig20x_init(dev);
522
523 moan_device("Unknown SIIG card", dev);
524 return -ENODEV;
525}
526
3ec9c594 527static int pci_siig_setup(struct serial_private *priv,
975a1a7d 528 const struct pciserial_board *board,
2655a2c7 529 struct uart_8250_port *port, int idx)
3ec9c594
AP		 530{
531 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
532
533 if (idx > 3) {
534 bar = 4;
535 offset = (idx - 4) * 8;
536 }
537
538 return setup_port(priv, port, bar, offset, 0);
539}
540
1da177e4
LT		 541/*
542 * Timedia has an explosion of boards, and to avoid the PCI table from
543 * growing *huge*, we use this function to collapse some 70 entries
544 * in the PCI table into one, for sanity's and compactness's sake.
545 */
e9422e09 546static const unsigned short timedia_single_port[] = {
1da177e4
LT		 547 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
548};
549
e9422e09 550static const unsigned short timedia_dual_port[] = {
1da177e4 551 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 552 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
553 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 554 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
555 0xD079, 0
556};
557
e9422e09 558static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 559 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
560 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 561 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
562 0xB157, 0
563};
564
e9422e09 565static const unsigned short timedia_eight_port[] = {
5756ee99 566 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 567 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
568};
569
cb3592be 570static const struct timedia_struct {
1da177e4 571 int num;
e9422e09 572 const unsigned short *ids;
1da177e4
LT		 573} timedia_data[] = {
574 { 1, timedia_single_port },
575 { 2, timedia_dual_port },
576 { 4, timedia_quad_port },
e9422e09 577 { 8, timedia_eight_port }
1da177e4
LT		 578};
579
b9b24558
FB		 580/*
581 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
582 * listing them individually, this driver merely grabs them all with
583 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
584 * and should be left free to be claimed by parport_serial instead.
585 */
586static int pci_timedia_probe(struct pci_dev *dev)
587{
588 /*
589 * Check the third digit of the subdevice ID
590 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
591 */
592 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
593 dev_info(&dev->dev,
594 "ignoring Timedia subdevice %04x for parport_serial\n",
595 dev->subsystem_device);
596 return -ENODEV;
597 }
598
599 return 0;
600}
601
61a116ef 602static int pci_timedia_init(struct pci_dev *dev)
1da177e4 603{
e9422e09 604 const unsigned short *ids;
1da177e4
LT		 605 int i, j;
606
e9422e09 607 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 608 ids = timedia_data[i].ids;
609 for (j = 0; ids[j]; j++)
610 if (dev->subsystem_device == ids[j])
611 return timedia_data[i].num;
612 }
613 return 0;
614}
615
616/*
617 * Timedia/SUNIX uses a mixture of BARs and offsets
618 * Ugh, this is ugly as all hell --- TYT
619 */
620static int
975a1a7d
RK		 621pci_timedia_setup(struct serial_private *priv,
622 const struct pciserial_board *board,
2655a2c7 623 struct uart_8250_port *port, int idx)
1da177e4
LT		 624{
625 unsigned int bar = 0, offset = board->first_offset;
626
627 switch (idx) {
628 case 0:
629 bar = 0;
630 break;
631 case 1:
632 offset = board->uart_offset;
633 bar = 0;
634 break;
635 case 2:
636 bar = 1;
637 break;
638 case 3:
639 offset = board->uart_offset;
c2cd6d3c 640 /* FALLTHROUGH */
1da177e4
LT		 641 case 4: /* BAR 2 */
642 case 5: /* BAR 3 */
643 case 6: /* BAR 4 */
644 case 7: /* BAR 5 */
645 bar = idx - 2;
646 }
647
70db3d91 648 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 649}
650
651/*
652 * Some Titan cards are also a little weird
653 */
654static int
70db3d91 655titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 656 const struct pciserial_board *board,
2655a2c7 657 struct uart_8250_port *port, int idx)
1da177e4
LT		 658{
659 unsigned int bar, offset = board->first_offset;
660
661 switch (idx) {
662 case 0:
663 bar = 1;
664 break;
665 case 1:
666 bar = 2;
667 break;
668 default:
669 bar = 4;
670 offset = (idx - 2) * board->uart_offset;
671 }
672
70db3d91 673 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 674}
675
61a116ef 676static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 677{
678 msleep(100);
679 return 0;
680}
681
04bf7e74
WP		 682static int pci_ni8420_init(struct pci_dev *dev)
683{
684 void __iomem *p;
685 unsigned long base, len;
686 unsigned int bar = 0;
687
688 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
689 moan_device("no memory in bar", dev);
690 return 0;
691 }
692
693 base = pci_resource_start(dev, bar);
694 len = pci_resource_len(dev, bar);
695 p = ioremap_nocache(base, len);
696 if (p == NULL)
697 return -ENOMEM;
698
699 /* Enable CPU Interrupt */
700 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
701 p + NI8420_INT_ENABLE_REG);
702
703 iounmap(p);
704 return 0;
705}
706
46a0fac9
SB		 707#define MITE_IOWBSR1_WSIZE 0xa
708#define MITE_IOWBSR1_WIN_OFFSET 0x800
709#define MITE_IOWBSR1_WENAB (1 << 7)
710#define MITE_LCIMR1_IO_IE_0 (1 << 24)
711#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
712#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
713
714static int pci_ni8430_init(struct pci_dev *dev)
715{
716 void __iomem *p;
717 unsigned long base, len;
718 u32 device_window;
719 unsigned int bar = 0;
720
721 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
722 moan_device("no memory in bar", dev);
723 return 0;
724 }
725
726 base = pci_resource_start(dev, bar);
727 len = pci_resource_len(dev, bar);
728 p = ioremap_nocache(base, len);
729 if (p == NULL)
730 return -ENOMEM;
731
732 /* Set device window address and size in BAR0 */
733 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
734 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
735 writel(device_window, p + MITE_IOWBSR1);
736
737 /* Set window access to go to RAMSEL IO address space */
738 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
739 p + MITE_IOWCR1);
740
741 /* Enable IO Bus Interrupt 0 */
742 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
743
744 /* Enable CPU Interrupt */
745 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
746
747 iounmap(p);
748 return 0;
749}
750
751/* UART Port Control Register */
752#define NI8430_PORTCON 0x0f
753#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
754
755static int
bf538fe4
AC		 756pci_ni8430_setup(struct serial_private *priv,
757 const struct pciserial_board *board,
2655a2c7 758 struct uart_8250_port *port, int idx)
46a0fac9
SB		 759{
760 void __iomem *p;
761 unsigned long base, len;
762 unsigned int bar, offset = board->first_offset;
763
764 if (idx >= board->num_ports)
765 return 1;
766
767 bar = FL_GET_BASE(board->flags);
768 offset += idx * board->uart_offset;
769
770 base = pci_resource_start(priv->dev, bar);
771 len = pci_resource_len(priv->dev, bar);
772 p = ioremap_nocache(base, len);
773
7c9d440e 774 /* enable the transceiver */
46a0fac9
SB		 775 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
776 p + offset + NI8430_PORTCON);
777
778 iounmap(p);
779
780 return setup_port(priv, port, bar, offset, board->reg_shift);
781}
782
7808edcd
NG		 783static int pci_netmos_9900_setup(struct serial_private *priv,
784 const struct pciserial_board *board,
2655a2c7 785 struct uart_8250_port *port, int idx)
7808edcd
NG		 786{
787 unsigned int bar;
788
789 if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
790 /* netmos apparently orders BARs by datasheet layout, so serial
791 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
792 */
793 bar = 3 * idx;
794
795 return setup_port(priv, port, bar, 0, board->reg_shift);
796 } else {
797 return pci_default_setup(priv, board, port, idx);
798 }
799}
800
801/* the 99xx series comes with a range of device IDs and a variety
802 * of capabilities:
803 *
804 * 9900 has varying capabilities and can cascade to sub-controllers
805 * (cascading should be purely internal)
806 * 9904 is hardwired with 4 serial ports
807 * 9912 and 9922 are hardwired with 2 serial ports
808 */
809static int pci_netmos_9900_numports(struct pci_dev *dev)
810{
811 unsigned int c = dev->class;
812 unsigned int pi;
813 unsigned short sub_serports;
814
815 pi = (c & 0xff);
816
817 if (pi == 2) {
818 return 1;
819 } else if ((pi == 0) &&
820 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
821 /* two possibilities: 0x30ps encodes number of parallel and
822 * serial ports, or 0x1000 indicates *something*. This is not
823 * immediately obvious, since the 2s1p+4s configuration seems
824 * to offer all functionality on functions 0..2, while still
825 * advertising the same function 3 as the 4s+2s1p config.
826 */
827 sub_serports = dev->subsystem_device & 0xf;
828 if (sub_serports > 0) {
829 return sub_serports;
830 } else {
831 printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
832 return 0;
833 }
834 }
835
836 moan_device("unknown NetMos/Mostech program interface", dev);
837 return 0;
838}
46a0fac9 839
61a116ef 840static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 841{
842 /* subdevice 0x00PS means <P> parallel, <S> serial */
843 unsigned int num_serial = dev->subsystem_device & 0xf;
844
ac6ec5b1
IS		 845 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
846 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
c4285b47 847 return 0;
7808edcd 848
25cf9bc1
JS		 849 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
850 dev->subsystem_device == 0x0299)
851 return 0;
852
7808edcd
NG		 853 switch (dev->device) { /* FALLTHROUGH on all */
854 case PCI_DEVICE_ID_NETMOS_9904:
855 case PCI_DEVICE_ID_NETMOS_9912:
856 case PCI_DEVICE_ID_NETMOS_9922:
857 case PCI_DEVICE_ID_NETMOS_9900:
858 num_serial = pci_netmos_9900_numports(dev);
859 break;
860
861 default:
862 if (num_serial == 0 ) {
863 moan_device("unknown NetMos/Mostech device", dev);
864 }
865 }
866
1da177e4
LT		 867 if (num_serial == 0)
868 return -ENODEV;
7808edcd 869
1da177e4
LT		 870 return num_serial;
871}
872
84f8c6fc 873/*
84f8c6fc
NV		 874 * These chips are available with optionally one parallel port and up to
875 * two serial ports. Unfortunately they all have the same product id.
876 *
877 * Basic configuration is done over a region of 32 I/O ports. The base
878 * ioport is called INTA or INTC, depending on docs/other drivers.
879 *
880 * The region of the 32 I/O ports is configured in POSIO0R...
881 */
882
883/* registers */
884#define ITE_887x_MISCR 0x9c
885#define ITE_887x_INTCBAR 0x78
886#define ITE_887x_UARTBAR 0x7c
887#define ITE_887x_PS0BAR 0x10
888#define ITE_887x_POSIO0 0x60
889
890/* I/O space size */
891#define ITE_887x_IOSIZE 32
892/* I/O space size (bits 26-24; 8 bytes = 011b) */
893#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
894/* I/O space size (bits 26-24; 32 bytes = 101b) */
895#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
896/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
897#define ITE_887x_POSIO_SPEED (3 << 29)
898/* enable IO_Space bit */
899#define ITE_887x_POSIO_ENABLE (1 << 31)
900
f79abb82 901static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 902{
903 /* inta_addr are the configuration addresses of the ITE */
904 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
905 0x200, 0x280, 0 };
906 int ret, i, type;
907 struct resource *iobase = NULL;
908 u32 miscr, uartbar, ioport;
909
910 /* search for the base-ioport */
911 i = 0;
912 while (inta_addr[i] && iobase == NULL) {
913 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
914 "ite887x");
915 if (iobase != NULL) {
916 /* write POSIO0R - speed | size | ioport */
917 pci_write_config_dword(dev, ITE_887x_POSIO0,
918 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
919 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
920 /* write INTCBAR - ioport */
5756ee99
AC		 921 pci_write_config_dword(dev, ITE_887x_INTCBAR,
922 inta_addr[i]);
84f8c6fc
NV		 923 ret = inb(inta_addr[i]);
924 if (ret != 0xff) {
925 /* ioport connected */
926 break;
927 }
928 release_region(iobase->start, ITE_887x_IOSIZE);
929 iobase = NULL;
930 }
931 i++;
932 }
933
934 if (!inta_addr[i]) {
935 printk(KERN_ERR "ite887x: could not find iobase\n");
936 return -ENODEV;
937 }
938
939 /* start of undocumented type checking (see parport_pc.c) */
940 type = inb(iobase->start + 0x18) & 0x0f;
941
942 switch (type) {
943 case 0x2: /* ITE8871 (1P) */
944 case 0xa: /* ITE8875 (1P) */
945 ret = 0;
946 break;
947 case 0xe: /* ITE8872 (2S1P) */
948 ret = 2;
949 break;
950 case 0x6: /* ITE8873 (1S) */
951 ret = 1;
952 break;
953 case 0x8: /* ITE8874 (2S) */
954 ret = 2;
955 break;
956 default:
957 moan_device("Unknown ITE887x", dev);
958 ret = -ENODEV;
959 }
960
961 /* configure all serial ports */
962 for (i = 0; i < ret; i++) {
963 /* read the I/O port from the device */
964 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
965 &ioport);
966 ioport &= 0x0000FF00; /* the actual base address */
967 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
968 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
969 ITE_887x_POSIO_IOSIZE_8 | ioport);
970
971 /* write the ioport to the UARTBAR */
972 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
973 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
974 uartbar |= (ioport << (16 * i)); /* set the ioport */
975 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
976
977 /* get current config */
978 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
979 /* disable interrupts (UARTx_Routing[3:0]) */
980 miscr &= ~(0xf << (12 - 4 * i));
981 /* activate the UART (UARTx_En) */
982 miscr |= 1 << (23 - i);
983 /* write new config with activated UART */
984 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
985 }
986
987 if (ret <= 0) {
988 /* the device has no UARTs if we get here */
989 release_region(iobase->start, ITE_887x_IOSIZE);
990 }
991
992 return ret;
993}
994
ae8d8a14 995static void pci_ite887x_exit(struct pci_dev *dev)
84f8c6fc
NV		 996{
997 u32 ioport;
998 /* the ioport is bit 0-15 in POSIO0R */
999 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
1000 ioport &= 0xffff;
1001 release_region(ioport, ITE_887x_IOSIZE);
1002}
1003
9f2a036a
RK		 1004/*
1005 * Oxford Semiconductor Inc.
1006 * Check that device is part of the Tornado range of devices, then determine
1007 * the number of ports available on the device.
1008 */
1009static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1010{
1011 u8 __iomem *p;
1012 unsigned long deviceID;
1013 unsigned int number_uarts = 0;
1014
1015 /* OxSemi Tornado devices are all 0xCxxx */
1016 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1017 (dev->device & 0xF000) != 0xC000)
1018 return 0;
1019
1020 p = pci_iomap(dev, 0, 5);
1021 if (p == NULL)
1022 return -ENOMEM;
1023
1024 deviceID = ioread32(p);
1025 /* Tornado device */
1026 if (deviceID == 0x07000200) {
1027 number_uarts = ioread8(p + 4);
1028 printk(KERN_DEBUG
1029 "%d ports detected on Oxford PCI Express device\n",
1030 number_uarts);
1031 }
1032 pci_iounmap(dev, p);
1033 return number_uarts;
1034}
1035
eb26dfe8
AC		 1036static int pci_asix_setup(struct serial_private *priv,
1037 const struct pciserial_board *board,
1038 struct uart_8250_port *port, int idx)
1039{
1040 port->bugs |= UART_BUG_PARITY;
1041 return pci_default_setup(priv, board, port, idx);
1042}
1043
55c7c0fd
AC		 1044/* Quatech devices have their own extra interface features */
1045
1046struct quatech_feature {
1047 u16 devid;
1048 bool amcc;
1049};
1050
1051#define QPCR_TEST_FOR1 0x3F
1052#define QPCR_TEST_GET1 0x00
1053#define QPCR_TEST_FOR2 0x40
1054#define QPCR_TEST_GET2 0x40
1055#define QPCR_TEST_FOR3 0x80
1056#define QPCR_TEST_GET3 0x40
1057#define QPCR_TEST_FOR4 0xC0
1058#define QPCR_TEST_GET4 0x80
1059
1060#define QOPR_CLOCK_X1 0x0000
1061#define QOPR_CLOCK_X2 0x0001
1062#define QOPR_CLOCK_X4 0x0002
1063#define QOPR_CLOCK_X8 0x0003
1064#define QOPR_CLOCK_RATE_MASK 0x0003
1065
1066
1067static struct quatech_feature quatech_cards[] = {
1068 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1069 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1070 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1071 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1072 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1073 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1074 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1075 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1076 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1077 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1078 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1079 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1080 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1081 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1082 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1083 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1084 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1085 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1086 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1087 { 0, }
1088};
1089
1090static int pci_quatech_amcc(u16 devid)
1091{
1092 struct quatech_feature *qf = &quatech_cards[0];
1093 while (qf->devid) {
1094 if (qf->devid == devid)
1095 return qf->amcc;
1096 qf++;
1097 }
1098 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1099 return 0;
1100};
1101
1102static int pci_quatech_rqopr(struct uart_8250_port *port)
1103{
1104 unsigned long base = port->port.iobase;
1105 u8 LCR, val;
1106
1107 LCR = inb(base + UART_LCR);
1108 outb(0xBF, base + UART_LCR);
1109 val = inb(base + UART_SCR);
1110 outb(LCR, base + UART_LCR);
1111 return val;
1112}
1113
1114static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1115{
1116 unsigned long base = port->port.iobase;
1117 u8 LCR, val;
1118
1119 LCR = inb(base + UART_LCR);
1120 outb(0xBF, base + UART_LCR);
1121 val = inb(base + UART_SCR);
1122 outb(qopr, base + UART_SCR);
1123 outb(LCR, base + UART_LCR);
1124}
1125
1126static int pci_quatech_rqmcr(struct uart_8250_port *port)
1127{
1128 unsigned long base = port->port.iobase;
1129 u8 LCR, val, qmcr;
1130
1131 LCR = inb(base + UART_LCR);
1132 outb(0xBF, base + UART_LCR);
1133 val = inb(base + UART_SCR);
1134 outb(val | 0x10, base + UART_SCR);
1135 qmcr = inb(base + UART_MCR);
1136 outb(val, base + UART_SCR);
1137 outb(LCR, base + UART_LCR);
1138
1139 return qmcr;
1140}
1141
1142static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1143{
1144 unsigned long base = port->port.iobase;
1145 u8 LCR, val;
1146
1147 LCR = inb(base + UART_LCR);
1148 outb(0xBF, base + UART_LCR);
1149 val = inb(base + UART_SCR);
1150 outb(val | 0x10, base + UART_SCR);
1151 outb(qmcr, base + UART_MCR);
1152 outb(val, base + UART_SCR);
1153 outb(LCR, base + UART_LCR);
1154}
1155
1156static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1157{
1158 unsigned long base = port->port.iobase;
1159 u8 LCR, val;
1160
1161 LCR = inb(base + UART_LCR);
1162 outb(0xBF, base + UART_LCR);
1163 val = inb(base + UART_SCR);
1164 if (val & 0x20) {
1165 outb(0x80, UART_LCR);
1166 if (!(inb(UART_SCR) & 0x20)) {
1167 outb(LCR, base + UART_LCR);
1168 return 1;
1169 }
1170 }
1171 return 0;
1172}
1173
1174static int pci_quatech_test(struct uart_8250_port *port)
1175{
1176 u8 reg;
1177 u8 qopr = pci_quatech_rqopr(port);
1178 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1179 reg = pci_quatech_rqopr(port) & 0xC0;
1180 if (reg != QPCR_TEST_GET1)
1181 return -EINVAL;
1182 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1183 reg = pci_quatech_rqopr(port) & 0xC0;
1184 if (reg != QPCR_TEST_GET2)
1185 return -EINVAL;
1186 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1187 reg = pci_quatech_rqopr(port) & 0xC0;
1188 if (reg != QPCR_TEST_GET3)
1189 return -EINVAL;
1190 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1191 reg = pci_quatech_rqopr(port) & 0xC0;
1192 if (reg != QPCR_TEST_GET4)
1193 return -EINVAL;
1194
1195 pci_quatech_wqopr(port, qopr);
1196 return 0;
1197}
1198
1199static int pci_quatech_clock(struct uart_8250_port *port)
1200{
1201 u8 qopr, reg, set;
1202 unsigned long clock;
1203
1204 if (pci_quatech_test(port) < 0)
1205 return 1843200;
1206
1207 qopr = pci_quatech_rqopr(port);
1208
1209 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1210 reg = pci_quatech_rqopr(port);
1211 if (reg & QOPR_CLOCK_X8) {
1212 clock = 1843200;
1213 goto out;
1214 }
1215 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1216 reg = pci_quatech_rqopr(port);
1217 if (!(reg & QOPR_CLOCK_X8)) {
1218 clock = 1843200;
1219 goto out;
1220 }
1221 reg &= QOPR_CLOCK_X8;
1222 if (reg == QOPR_CLOCK_X2) {
1223 clock = 3685400;
1224 set = QOPR_CLOCK_X2;
1225 } else if (reg == QOPR_CLOCK_X4) {
1226 clock = 7372800;
1227 set = QOPR_CLOCK_X4;
1228 } else if (reg == QOPR_CLOCK_X8) {
1229 clock = 14745600;
1230 set = QOPR_CLOCK_X8;
1231 } else {
1232 clock = 1843200;
1233 set = QOPR_CLOCK_X1;
1234 }
1235 qopr &= ~QOPR_CLOCK_RATE_MASK;
1236 qopr |= set;
1237
1238out:
1239 pci_quatech_wqopr(port, qopr);
1240 return clock;
1241}
1242
1243static int pci_quatech_rs422(struct uart_8250_port *port)
1244{
1245 u8 qmcr;
1246 int rs422 = 0;
1247
1248 if (!pci_quatech_has_qmcr(port))
1249 return 0;
1250 qmcr = pci_quatech_rqmcr(port);
1251 pci_quatech_wqmcr(port, 0xFF);
1252 if (pci_quatech_rqmcr(port))
1253 rs422 = 1;
1254 pci_quatech_wqmcr(port, qmcr);
1255 return rs422;
1256}
1257
1258static int pci_quatech_init(struct pci_dev *dev)
1259{
1260 if (pci_quatech_amcc(dev->device)) {
1261 unsigned long base = pci_resource_start(dev, 0);
1262 if (base) {
1263 u32 tmp;
2f8cef8c 1264 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
55c7c0fd
AC		 1265 tmp = inl(base + 0x3c);
1266 outl(tmp | 0x01000000, base + 0x3c);
2f8cef8c 1267 outl(tmp &= ~0x01000000, base + 0x3c);
55c7c0fd
AC		 1268 }
1269 }
1270 return 0;
1271}
1272
1273static int pci_quatech_setup(struct serial_private *priv,
1274 const struct pciserial_board *board,
1275 struct uart_8250_port *port, int idx)
1276{
1277 /* Needed by pci_quatech calls below */
1278 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1279 /* Set up the clocking */
1280 port->port.uartclk = pci_quatech_clock(port);
1281 /* For now just warn about RS422 */
1282 if (pci_quatech_rs422(port))
1283 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1284 return pci_default_setup(priv, board, port, idx);
1285}
1286
d73dfc6a 1287static void pci_quatech_exit(struct pci_dev *dev)
55c7c0fd
AC		 1288{
1289}
1290
eb26dfe8 1291static int pci_default_setup(struct serial_private *priv,
975a1a7d 1292 const struct pciserial_board *board,
2655a2c7 1293 struct uart_8250_port *port, int idx)
1da177e4
LT		 1294{
1295 unsigned int bar, offset = board->first_offset, maxnr;
1296
1297 bar = FL_GET_BASE(board->flags);
1298 if (board->flags & FL_BASE_BARS)
1299 bar += idx;
1300 else
1301 offset += idx * board->uart_offset;
1302
2427ddd8
GKH		 1303 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1304 (board->reg_shift + 3);
1da177e4
LT		 1305
1306 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1307 return 1;
5756ee99 1308
70db3d91 1309 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 1310}
1311
095e24b0
DB		 1312static int
1313ce4100_serial_setup(struct serial_private *priv,
1314 const struct pciserial_board *board,
2655a2c7 1315 struct uart_8250_port *port, int idx)
095e24b0
DB		 1316{
1317 int ret;
1318
08ec212c 1319 ret = setup_port(priv, port, idx, 0, board->reg_shift);
2655a2c7
AC		 1320 port->port.iotype = UPIO_MEM32;
1321 port->port.type = PORT_XSCALE;
1322 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1323 port->port.regshift = 2;
095e24b0
DB		 1324
1325 return ret;
1326}
1327
d9a0fbfd
AP		 1328static int
1329pci_omegapci_setup(struct serial_private *priv,
1798ca13 1330 const struct pciserial_board *board,
2655a2c7 1331 struct uart_8250_port *port, int idx)
d9a0fbfd
AP		 1332{
1333 return setup_port(priv, port, 2, idx * 8, 0);
1334}
1335
ebebd49a
SH		 1336static int
1337pci_brcm_trumanage_setup(struct serial_private *priv,
1338 const struct pciserial_board *board,
1339 struct uart_8250_port *port, int idx)
1340{
1341 int ret = pci_default_setup(priv, board, port, idx);
1342
1343 port->port.type = PORT_BRCM_TRUMANAGE;
1344 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1345 return ret;
1346}
1347
b6adea33
MCC		 1348static int skip_tx_en_setup(struct serial_private *priv,
1349 const struct pciserial_board *board,
2655a2c7 1350 struct uart_8250_port *port, int idx)
b6adea33 1351{
2655a2c7 1352 port->port.flags |= UPF_NO_TXEN_TEST;
b6adea33
MCC		 1353 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1354 "[%04x:%04x] subsystem [%04x:%04x]\n",
1355 priv->dev->vendor,
1356 priv->dev->device,
1357 priv->dev->subsystem_vendor,
1358 priv->dev->subsystem_device);
1359
1360 return pci_default_setup(priv, board, port, idx);
1361}
1362
0ad372b9
SM		 1363static void kt_handle_break(struct uart_port *p)
1364{
1365 struct uart_8250_port *up =
1366 container_of(p, struct uart_8250_port, port);
1367 /*
1368 * On receipt of a BI, serial device in Intel ME (Intel
1369 * management engine) needs to have its fifos cleared for sane
1370 * SOL (Serial Over Lan) output.
1371 */
1372 serial8250_clear_and_reinit_fifos(up);
1373}
1374
1375static unsigned int kt_serial_in(struct uart_port *p, int offset)
1376{
1377 struct uart_8250_port *up =
1378 container_of(p, struct uart_8250_port, port);
1379 unsigned int val;
1380
1381 /*
1382 * When the Intel ME (management engine) gets reset its serial
1383 * port registers could return 0 momentarily. Functions like
1384 * serial8250_console_write, read and save the IER, perform
1385 * some operation and then restore it. In order to avoid
1386 * setting IER register inadvertently to 0, if the value read
1387 * is 0, double check with ier value in uart_8250_port and use
1388 * that instead. up->ier should be the same value as what is
1389 * currently configured.
1390 */
1391 val = inb(p->iobase + offset);
1392 if (offset == UART_IER) {
1393 if (val == 0)
1394 val = up->ier;
1395 }
1396 return val;
1397}
1398
bc02d15a
DW		 1399static int kt_serial_setup(struct serial_private *priv,
1400 const struct pciserial_board *board,
2655a2c7 1401 struct uart_8250_port *port, int idx)
bc02d15a 1402{
2655a2c7
AC		 1403 port->port.flags |= UPF_BUG_THRE;
1404 port->port.serial_in = kt_serial_in;
1405 port->port.handle_break = kt_handle_break;
bc02d15a
DW		 1406 return skip_tx_en_setup(priv, board, port, idx);
1407}
1408
eb7073db
TM		 1409static int pci_eg20t_init(struct pci_dev *dev)
1410{
1411#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1412 return -ENODEV;
1413#else
1414 return 0;
1415#endif
1416}
1417
06315348
SH		 1418static int
1419pci_xr17c154_setup(struct serial_private *priv,
1420 const struct pciserial_board *board,
2655a2c7 1421 struct uart_8250_port *port, int idx)
06315348 1422{
2655a2c7 1423 port->port.flags |= UPF_EXAR_EFR;
06315348
SH		 1424 return pci_default_setup(priv, board, port, idx);
1425}
1426
dc96efb7
MS		 1427static int
1428pci_xr17v35x_setup(struct serial_private *priv,
1429 const struct pciserial_board *board,
1430 struct uart_8250_port *port, int idx)
1431{
1432 u8 __iomem *p;
1433
1434 p = pci_ioremap_bar(priv->dev, 0);
13c3237d
MS		 1435 if (p == NULL)
1436 return -ENOMEM;
dc96efb7
MS		 1437
1438 port->port.flags |= UPF_EXAR_EFR;
1439
1440 /*
1441 * Setup Multipurpose Input/Output pins.
1442 */
1443 if (idx == 0) {
1444 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1445 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1446 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1447 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1448 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1449 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1450 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1451 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1452 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1453 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1454 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1455 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1456 }
f965b9c4
MS		 1457 writeb(0x00, p + UART_EXAR_8XMODE);
1458 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1459 writeb(128, p + UART_EXAR_TXTRG);
1460 writeb(128, p + UART_EXAR_RXTRG);
dc96efb7
MS		 1461 iounmap(p);
1462
1463 return pci_default_setup(priv, board, port, idx);
1464}
1465
14faa8cc
MS		 1466#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1467#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1468#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1469#define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1470
1471static int
1472pci_fastcom335_setup(struct serial_private *priv,
1473 const struct pciserial_board *board,
1474 struct uart_8250_port *port, int idx)
1475{
1476 u8 __iomem *p;
1477
1478 p = pci_ioremap_bar(priv->dev, 0);
1479 if (p == NULL)
1480 return -ENOMEM;
1481
1482 port->port.flags |= UPF_EXAR_EFR;
1483
1484 /*
1485 * Setup Multipurpose Input/Output pins.
1486 */
1487 if (idx == 0) {
1488 switch (priv->dev->device) {
1489 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1490 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1491 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1492 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1493 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1494 break;
1495 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1496 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1497 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1498 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1499 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1500 break;
1501 }
1502 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1503 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1504 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1505 }
1506 writeb(0x00, p + UART_EXAR_8XMODE);
1507 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1508 writeb(32, p + UART_EXAR_TXTRG);
1509 writeb(32, p + UART_EXAR_RXTRG);
1510 iounmap(p);
1511
1512 return pci_default_setup(priv, board, port, idx);
1513}
1514
6971c635
GA		 1515static int
1516pci_wch_ch353_setup(struct serial_private *priv,
1517 const struct pciserial_board *board,
1518 struct uart_8250_port *port, int idx)
1519{
1520 port->port.flags |= UPF_FIXED_TYPE;
1521 port->port.type = PORT_16550A;
06315348
SH		 1522 return pci_default_setup(priv, board, port, idx);
1523}
1524
1da177e4
LT		 1525#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1526#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1527#define PCI_DEVICE_ID_OCTPRO 0x0001
1528#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1529#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1530#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1531#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
26e8220a
FL		 1532#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1533#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
78d70d48 1534#define PCI_VENDOR_ID_ADVANTECH 0x13fe
095e24b0 1535#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
78d70d48 1536#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
66169ad1
YY		 1537#define PCI_DEVICE_ID_TITAN_200I 0x8028
1538#define PCI_DEVICE_ID_TITAN_400I 0x8048
1539#define PCI_DEVICE_ID_TITAN_800I 0x8088
1540#define PCI_DEVICE_ID_TITAN_800EH 0xA007
1541#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1542#define PCI_DEVICE_ID_TITAN_400EH 0xA009
1543#define PCI_DEVICE_ID_TITAN_100E 0xA010
1544#define PCI_DEVICE_ID_TITAN_200E 0xA012
1545#define PCI_DEVICE_ID_TITAN_400E 0xA013
1546#define PCI_DEVICE_ID_TITAN_800E 0xA014
1547#define PCI_DEVICE_ID_TITAN_200EI 0xA016
1548#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1459439f 1549#define PCI_DEVICE_ID_TITAN_200V3 0xA306
1e9deb11
YY		 1550#define PCI_DEVICE_ID_TITAN_400V3 0xA310
1551#define PCI_DEVICE_ID_TITAN_410V3 0xA312
1552#define PCI_DEVICE_ID_TITAN_800V3 0xA314
1553#define PCI_DEVICE_ID_TITAN_800V3B 0xA315
e847003f 1554#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
aa273ae5 1555#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
d9a0fbfd 1556#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
bc02d15a 1557#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
27788c5f 1558#define PCI_VENDOR_ID_WCH 0x4348
8b5c913f 1559#define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
27788c5f
AC		 1560#define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1561#define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1562#define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
6683549e
AC		 1563#define PCI_VENDOR_ID_AGESTAR 0x5372
1564#define PCI_DEVICE_ID_AGESTAR_9375 0x6872
eb26dfe8 1565#define PCI_VENDOR_ID_ASIX 0x9710
14faa8cc
MS		 1566#define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1567#define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
b7b9041b 1568#define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
ebebd49a 1569#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
14faa8cc 1570
abd7baca
SC		 1571#define PCI_VENDOR_ID_SUNIX 0x1fd4
1572#define PCI_DEVICE_ID_SUNIX_1999 0x1999
1573
1da177e4 1574
b76c5a07
CB		 1575/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1576#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
d13402a4 1577#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
b76c5a07 1578
1da177e4
LT		 1579/*
1580 * Master list of serial port init/setup/exit quirks.
1581 * This does not describe the general nature of the port.
1582 * (ie, baud base, number and location of ports, etc)
1583 *
1584 * This list is ordered alphabetically by vendor then device.
1585 * Specific entries must come before more generic entries.
1586 */
7a63ce5a 1587static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 1588 /*
1589 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1590 */
1591 {
1592 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1593 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1594 .subvendor = PCI_ANY_ID,
1595 .subdevice = PCI_ANY_ID,
1596 .setup = addidata_apci7800_setup,
1597 },
1da177e4 1598 /*
61a116ef 1599 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 1600 * It is not clear whether this applies to all products.
1601 */
1602 {
1603 .vendor = PCI_VENDOR_ID_AFAVLAB,
1604 .device = PCI_ANY_ID,
1605 .subvendor = PCI_ANY_ID,
1606 .subdevice = PCI_ANY_ID,
1607 .setup = afavlab_setup,
1608 },
1609 /*
1610 * HP Diva
1611 */
1612 {
1613 .vendor = PCI_VENDOR_ID_HP,
1614 .device = PCI_DEVICE_ID_HP_DIVA,
1615 .subvendor = PCI_ANY_ID,
1616 .subdevice = PCI_ANY_ID,
1617 .init = pci_hp_diva_init,
1618 .setup = pci_hp_diva_setup,
1619 },
1620 /*
1621 * Intel
1622 */
1623 {
1624 .vendor = PCI_VENDOR_ID_INTEL,
1625 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1626 .subvendor = 0xe4bf,
1627 .subdevice = PCI_ANY_ID,
1628 .init = pci_inteli960ni_init,
1629 .setup = pci_default_setup,
1630 },
b6adea33
MCC		 1631 {
1632 .vendor = PCI_VENDOR_ID_INTEL,
1633 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1634 .subvendor = PCI_ANY_ID,
1635 .subdevice = PCI_ANY_ID,
1636 .setup = skip_tx_en_setup,
1637 },
1638 {
1639 .vendor = PCI_VENDOR_ID_INTEL,
1640 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1641 .subvendor = PCI_ANY_ID,
1642 .subdevice = PCI_ANY_ID,
1643 .setup = skip_tx_en_setup,
1644 },
1645 {
1646 .vendor = PCI_VENDOR_ID_INTEL,
1647 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1648 .subvendor = PCI_ANY_ID,
1649 .subdevice = PCI_ANY_ID,
1650 .setup = skip_tx_en_setup,
1651 },
095e24b0
DB		 1652 {
1653 .vendor = PCI_VENDOR_ID_INTEL,
1654 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1655 .subvendor = PCI_ANY_ID,
1656 .subdevice = PCI_ANY_ID,
1657 .setup = ce4100_serial_setup,
1658 },
bc02d15a
DW		 1659 {
1660 .vendor = PCI_VENDOR_ID_INTEL,
1661 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1662 .subvendor = PCI_ANY_ID,
1663 .subdevice = PCI_ANY_ID,
1664 .setup = kt_serial_setup,
1665 },
84f8c6fc
NV		 1666 /*
1667 * ITE
1668 */
1669 {
1670 .vendor = PCI_VENDOR_ID_ITE,
1671 .device = PCI_DEVICE_ID_ITE_8872,
1672 .subvendor = PCI_ANY_ID,
1673 .subdevice = PCI_ANY_ID,
1674 .init = pci_ite887x_init,
1675 .setup = pci_default_setup,
2d47b716 1676 .exit = pci_ite887x_exit,
84f8c6fc 1677 },
46a0fac9
SB		 1678 /*
1679 * National Instruments
1680 */
04bf7e74
WP		 1681 {
1682 .vendor = PCI_VENDOR_ID_NI,
1683 .device = PCI_DEVICE_ID_NI_PCI23216,
1684 .subvendor = PCI_ANY_ID,
1685 .subdevice = PCI_ANY_ID,
1686 .init = pci_ni8420_init,
1687 .setup = pci_default_setup,
2d47b716 1688 .exit = pci_ni8420_exit,
04bf7e74
WP		 1689 },
1690 {
1691 .vendor = PCI_VENDOR_ID_NI,
1692 .device = PCI_DEVICE_ID_NI_PCI2328,
1693 .subvendor = PCI_ANY_ID,
1694 .subdevice = PCI_ANY_ID,
1695 .init = pci_ni8420_init,
1696 .setup = pci_default_setup,
2d47b716 1697 .exit = pci_ni8420_exit,
04bf7e74
WP		 1698 },
1699 {
1700 .vendor = PCI_VENDOR_ID_NI,
1701 .device = PCI_DEVICE_ID_NI_PCI2324,
1702 .subvendor = PCI_ANY_ID,
1703 .subdevice = PCI_ANY_ID,
1704 .init = pci_ni8420_init,
1705 .setup = pci_default_setup,
2d47b716 1706 .exit = pci_ni8420_exit,
04bf7e74
WP		 1707 },
1708 {
1709 .vendor = PCI_VENDOR_ID_NI,
1710 .device = PCI_DEVICE_ID_NI_PCI2322,
1711 .subvendor = PCI_ANY_ID,
1712 .subdevice = PCI_ANY_ID,
1713 .init = pci_ni8420_init,
1714 .setup = pci_default_setup,
2d47b716 1715 .exit = pci_ni8420_exit,
04bf7e74
WP		 1716 },
1717 {
1718 .vendor = PCI_VENDOR_ID_NI,
1719 .device = PCI_DEVICE_ID_NI_PCI2324I,
1720 .subvendor = PCI_ANY_ID,
1721 .subdevice = PCI_ANY_ID,
1722 .init = pci_ni8420_init,
1723 .setup = pci_default_setup,
2d47b716 1724 .exit = pci_ni8420_exit,
04bf7e74
WP		 1725 },
1726 {
1727 .vendor = PCI_VENDOR_ID_NI,
1728 .device = PCI_DEVICE_ID_NI_PCI2322I,
1729 .subvendor = PCI_ANY_ID,
1730 .subdevice = PCI_ANY_ID,
1731 .init = pci_ni8420_init,
1732 .setup = pci_default_setup,
2d47b716 1733 .exit = pci_ni8420_exit,
04bf7e74
WP		 1734 },
1735 {
1736 .vendor = PCI_VENDOR_ID_NI,
1737 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1738 .subvendor = PCI_ANY_ID,
1739 .subdevice = PCI_ANY_ID,
1740 .init = pci_ni8420_init,
1741 .setup = pci_default_setup,
2d47b716 1742 .exit = pci_ni8420_exit,
04bf7e74
WP		 1743 },
1744 {
1745 .vendor = PCI_VENDOR_ID_NI,
1746 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1747 .subvendor = PCI_ANY_ID,
1748 .subdevice = PCI_ANY_ID,
1749 .init = pci_ni8420_init,
1750 .setup = pci_default_setup,
2d47b716 1751 .exit = pci_ni8420_exit,
04bf7e74
WP		 1752 },
1753 {
1754 .vendor = PCI_VENDOR_ID_NI,
1755 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1756 .subvendor = PCI_ANY_ID,
1757 .subdevice = PCI_ANY_ID,
1758 .init = pci_ni8420_init,
1759 .setup = pci_default_setup,
2d47b716 1760 .exit = pci_ni8420_exit,
04bf7e74
WP		 1761 },
1762 {
1763 .vendor = PCI_VENDOR_ID_NI,
1764 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1765 .subvendor = PCI_ANY_ID,
1766 .subdevice = PCI_ANY_ID,
1767 .init = pci_ni8420_init,
1768 .setup = pci_default_setup,
2d47b716 1769 .exit = pci_ni8420_exit,
04bf7e74
WP		 1770 },
1771 {
1772 .vendor = PCI_VENDOR_ID_NI,
1773 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1774 .subvendor = PCI_ANY_ID,
1775 .subdevice = PCI_ANY_ID,
1776 .init = pci_ni8420_init,
1777 .setup = pci_default_setup,
2d47b716 1778 .exit = pci_ni8420_exit,
04bf7e74
WP		 1779 },
1780 {
1781 .vendor = PCI_VENDOR_ID_NI,
1782 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1783 .subvendor = PCI_ANY_ID,
1784 .subdevice = PCI_ANY_ID,
1785 .init = pci_ni8420_init,
1786 .setup = pci_default_setup,
2d47b716 1787 .exit = pci_ni8420_exit,
04bf7e74 1788 },
46a0fac9
SB		 1789 {
1790 .vendor = PCI_VENDOR_ID_NI,
1791 .device = PCI_ANY_ID,
1792 .subvendor = PCI_ANY_ID,
1793 .subdevice = PCI_ANY_ID,
1794 .init = pci_ni8430_init,
1795 .setup = pci_ni8430_setup,
2d47b716 1796 .exit = pci_ni8430_exit,
46a0fac9 1797 },
55c7c0fd
AC		 1798 /* Quatech */
1799 {
1800 .vendor = PCI_VENDOR_ID_QUATECH,
1801 .device = PCI_ANY_ID,
1802 .subvendor = PCI_ANY_ID,
1803 .subdevice = PCI_ANY_ID,
1804 .init = pci_quatech_init,
1805 .setup = pci_quatech_setup,
d73dfc6a 1806 .exit = pci_quatech_exit,
55c7c0fd 1807 },
1da177e4
LT		 1808 /*
1809 * Panacom
1810 */
1811 {
1812 .vendor = PCI_VENDOR_ID_PANACOM,
1813 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1814 .subvendor = PCI_ANY_ID,
1815 .subdevice = PCI_ANY_ID,
1816 .init = pci_plx9050_init,
1817 .setup = pci_default_setup,
2d47b716 1818 .exit = pci_plx9050_exit,
5756ee99 1819 },
1da177e4
LT		 1820 {
1821 .vendor = PCI_VENDOR_ID_PANACOM,
1822 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1823 .subvendor = PCI_ANY_ID,
1824 .subdevice = PCI_ANY_ID,
1825 .init = pci_plx9050_init,
1826 .setup = pci_default_setup,
2d47b716 1827 .exit = pci_plx9050_exit,
1da177e4
LT		 1828 },
1829 /*
1830 * PLX
1831 */
48212008
TH		 1832 {
1833 .vendor = PCI_VENDOR_ID_PLX,
1834 .device = PCI_DEVICE_ID_PLX_9030,
1835 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1836 .subdevice = PCI_ANY_ID,
1837 .setup = pci_default_setup,
1838 },
add7b58e
BH		 1839 {
1840 .vendor = PCI_VENDOR_ID_PLX,
1841 .device = PCI_DEVICE_ID_PLX_9050,
1842 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1843 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1844 .init = pci_plx9050_init,
1845 .setup = pci_default_setup,
2d47b716 1846 .exit = pci_plx9050_exit,
add7b58e 1847 },
1da177e4
LT		 1848 {
1849 .vendor = PCI_VENDOR_ID_PLX,
1850 .device = PCI_DEVICE_ID_PLX_9050,
1851 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1852 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1853 .init = pci_plx9050_init,
1854 .setup = pci_default_setup,
2d47b716 1855 .exit = pci_plx9050_exit,
1da177e4
LT		 1856 },
1857 {
1858 .vendor = PCI_VENDOR_ID_PLX,
1859 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1860 .subvendor = PCI_VENDOR_ID_PLX,
1861 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1862 .init = pci_plx9050_init,
1863 .setup = pci_default_setup,
2d47b716 1864 .exit = pci_plx9050_exit,
1da177e4
LT		 1865 },
1866 /*
1867 * SBS Technologies, Inc., PMC-OCTALPRO 232
1868 */
1869 {
1870 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1871 .device = PCI_DEVICE_ID_OCTPRO,
1872 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1873 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1874 .init = sbs_init,
1875 .setup = sbs_setup,
2d47b716 1876 .exit = sbs_exit,
1da177e4
LT		 1877 },
1878 /*
1879 * SBS Technologies, Inc., PMC-OCTALPRO 422
1880 */
1881 {
1882 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1883 .device = PCI_DEVICE_ID_OCTPRO,
1884 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1885 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1886 .init = sbs_init,
1887 .setup = sbs_setup,
2d47b716 1888 .exit = sbs_exit,
1da177e4
LT		 1889 },
1890 /*
1891 * SBS Technologies, Inc., P-Octal 232
1892 */
1893 {
1894 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1895 .device = PCI_DEVICE_ID_OCTPRO,
1896 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1897 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1898 .init = sbs_init,
1899 .setup = sbs_setup,
2d47b716 1900 .exit = sbs_exit,
1da177e4
LT		 1901 },
1902 /*
1903 * SBS Technologies, Inc., P-Octal 422
1904 */
1905 {
1906 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1907 .device = PCI_DEVICE_ID_OCTPRO,
1908 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1909 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1910 .init = sbs_init,
1911 .setup = sbs_setup,
2d47b716 1912 .exit = sbs_exit,
1da177e4 1913 },
1da177e4 1914 /*
61a116ef 1915 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 1916 */
1917 {
1918 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 1919 .device = PCI_ANY_ID,
1da177e4
LT		 1920 .subvendor = PCI_ANY_ID,
1921 .subdevice = PCI_ANY_ID,
67d74b87 1922 .init = pci_siig_init,
3ec9c594 1923 .setup = pci_siig_setup,
1da177e4
LT		 1924 },
1925 /*
1926 * Titan cards
1927 */
1928 {
1929 .vendor = PCI_VENDOR_ID_TITAN,
1930 .device = PCI_DEVICE_ID_TITAN_400L,
1931 .subvendor = PCI_ANY_ID,
1932 .subdevice = PCI_ANY_ID,
1933 .setup = titan_400l_800l_setup,
1934 },
1935 {
1936 .vendor = PCI_VENDOR_ID_TITAN,
1937 .device = PCI_DEVICE_ID_TITAN_800L,
1938 .subvendor = PCI_ANY_ID,
1939 .subdevice = PCI_ANY_ID,
1940 .setup = titan_400l_800l_setup,
1941 },
1942 /*
1943 * Timedia cards
1944 */
1945 {
1946 .vendor = PCI_VENDOR_ID_TIMEDIA,
1947 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1948 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1949 .subdevice = PCI_ANY_ID,
b9b24558 1950 .probe = pci_timedia_probe,
1da177e4
LT		 1951 .init = pci_timedia_init,
1952 .setup = pci_timedia_setup,
1953 },
1954 {
1955 .vendor = PCI_VENDOR_ID_TIMEDIA,
1956 .device = PCI_ANY_ID,
1957 .subvendor = PCI_ANY_ID,
1958 .subdevice = PCI_ANY_ID,
1959 .setup = pci_timedia_setup,
1960 },
abd7baca
SC		 1961 /*
1962 * SUNIX (Timedia) cards
1963 * Do not "probe" for these cards as there is at least one combination
1964 * card that should be handled by parport_pc that doesn't match the
1965 * rule in pci_timedia_probe.
1966 * It is part number is MIO5079A but its subdevice ID is 0x0102.
1967 * There are some boards with part number SER5037AL that report
1968 * subdevice ID 0x0002.
1969 */
1970 {
1971 .vendor = PCI_VENDOR_ID_SUNIX,
1972 .device = PCI_DEVICE_ID_SUNIX_1999,
1973 .subvendor = PCI_VENDOR_ID_SUNIX,
1974 .subdevice = PCI_ANY_ID,
1975 .init = pci_timedia_init,
1976 .setup = pci_timedia_setup,
1977 },
06315348
SH		 1978 /*
1979 * Exar cards
1980 */
1981 {
1982 .vendor = PCI_VENDOR_ID_EXAR,
1983 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1984 .subvendor = PCI_ANY_ID,
1985 .subdevice = PCI_ANY_ID,
1986 .setup = pci_xr17c154_setup,
1987 },
1988 {
1989 .vendor = PCI_VENDOR_ID_EXAR,
1990 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1991 .subvendor = PCI_ANY_ID,
1992 .subdevice = PCI_ANY_ID,
1993 .setup = pci_xr17c154_setup,
1994 },
1995 {
1996 .vendor = PCI_VENDOR_ID_EXAR,
1997 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1998 .subvendor = PCI_ANY_ID,
1999 .subdevice = PCI_ANY_ID,
2000 .setup = pci_xr17c154_setup,
2001 },
dc96efb7
MS		 2002 {
2003 .vendor = PCI_VENDOR_ID_EXAR,
2004 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2005 .subvendor = PCI_ANY_ID,
2006 .subdevice = PCI_ANY_ID,
2007 .setup = pci_xr17v35x_setup,
2008 },
2009 {
2010 .vendor = PCI_VENDOR_ID_EXAR,
2011 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2012 .subvendor = PCI_ANY_ID,
2013 .subdevice = PCI_ANY_ID,
2014 .setup = pci_xr17v35x_setup,
2015 },
2016 {
2017 .vendor = PCI_VENDOR_ID_EXAR,
2018 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2019 .subvendor = PCI_ANY_ID,
2020 .subdevice = PCI_ANY_ID,
2021 .setup = pci_xr17v35x_setup,
2022 },
1da177e4
LT		 2023 /*
2024 * Xircom cards
2025 */
2026 {
2027 .vendor = PCI_VENDOR_ID_XIRCOM,
2028 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2029 .subvendor = PCI_ANY_ID,
2030 .subdevice = PCI_ANY_ID,
2031 .init = pci_xircom_init,
2032 .setup = pci_default_setup,
2033 },
2034 /*
61a116ef 2035 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 2036 */
2037 {
2038 .vendor = PCI_VENDOR_ID_NETMOS,
2039 .device = PCI_ANY_ID,
2040 .subvendor = PCI_ANY_ID,
2041 .subdevice = PCI_ANY_ID,
2042 .init = pci_netmos_init,
7808edcd 2043 .setup = pci_netmos_9900_setup,
1da177e4 2044 },
9f2a036a 2045 /*
aa273ae5 2046 * For Oxford Semiconductor Tornado based devices
9f2a036a
RK		 2047 */
2048 {
2049 .vendor = PCI_VENDOR_ID_OXSEMI,
2050 .device = PCI_ANY_ID,
2051 .subvendor = PCI_ANY_ID,
2052 .subdevice = PCI_ANY_ID,
2053 .init = pci_oxsemi_tornado_init,
2054 .setup = pci_default_setup,
2055 },
2056 {
2057 .vendor = PCI_VENDOR_ID_MAINPINE,
2058 .device = PCI_ANY_ID,
2059 .subvendor = PCI_ANY_ID,
2060 .subdevice = PCI_ANY_ID,
2061 .init = pci_oxsemi_tornado_init,
2062 .setup = pci_default_setup,
2063 },
aa273ae5
SK		 2064 {
2065 .vendor = PCI_VENDOR_ID_DIGI,
2066 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2067 .subvendor = PCI_SUBVENDOR_ID_IBM,
2068 .subdevice = PCI_ANY_ID,
2069 .init = pci_oxsemi_tornado_init,
2070 .setup = pci_default_setup,
2071 },
eb7073db
TM		 2072 {
2073 .vendor = PCI_VENDOR_ID_INTEL,
2074 .device = 0x8811,
aaa10eb1
AP		 2075 .subvendor = PCI_ANY_ID,
2076 .subdevice = PCI_ANY_ID,
eb7073db 2077 .init = pci_eg20t_init,
64d91cfa 2078 .setup = pci_default_setup,
eb7073db
TM		 2079 },
2080 {
2081 .vendor = PCI_VENDOR_ID_INTEL,
2082 .device = 0x8812,
aaa10eb1
AP		 2083 .subvendor = PCI_ANY_ID,
2084 .subdevice = PCI_ANY_ID,
eb7073db 2085 .init = pci_eg20t_init,
64d91cfa 2086 .setup = pci_default_setup,
eb7073db
TM		 2087 },
2088 {
2089 .vendor = PCI_VENDOR_ID_INTEL,
2090 .device = 0x8813,
aaa10eb1
AP		 2091 .subvendor = PCI_ANY_ID,
2092 .subdevice = PCI_ANY_ID,
eb7073db 2093 .init = pci_eg20t_init,
64d91cfa 2094 .setup = pci_default_setup,
eb7073db
TM		 2095 },
2096 {
2097 .vendor = PCI_VENDOR_ID_INTEL,
2098 .device = 0x8814,
aaa10eb1
AP		 2099 .subvendor = PCI_ANY_ID,
2100 .subdevice = PCI_ANY_ID,
eb7073db 2101 .init = pci_eg20t_init,
64d91cfa 2102 .setup = pci_default_setup,
eb7073db
TM		 2103 },
2104 {
2105 .vendor = 0x10DB,
2106 .device = 0x8027,
aaa10eb1
AP		 2107 .subvendor = PCI_ANY_ID,
2108 .subdevice = PCI_ANY_ID,
eb7073db 2109 .init = pci_eg20t_init,
64d91cfa 2110 .setup = pci_default_setup,
eb7073db
TM		 2111 },
2112 {
2113 .vendor = 0x10DB,
2114 .device = 0x8028,
aaa10eb1
AP		 2115 .subvendor = PCI_ANY_ID,
2116 .subdevice = PCI_ANY_ID,
eb7073db 2117 .init = pci_eg20t_init,
64d91cfa 2118 .setup = pci_default_setup,
eb7073db
TM		 2119 },
2120 {
2121 .vendor = 0x10DB,
2122 .device = 0x8029,
aaa10eb1
AP		 2123 .subvendor = PCI_ANY_ID,
2124 .subdevice = PCI_ANY_ID,
eb7073db 2125 .init = pci_eg20t_init,
64d91cfa 2126 .setup = pci_default_setup,
eb7073db
TM		 2127 },
2128 {
2129 .vendor = 0x10DB,
2130 .device = 0x800C,
aaa10eb1
AP		 2131 .subvendor = PCI_ANY_ID,
2132 .subdevice = PCI_ANY_ID,
eb7073db 2133 .init = pci_eg20t_init,
64d91cfa 2134 .setup = pci_default_setup,
eb7073db
TM		 2135 },
2136 {
2137 .vendor = 0x10DB,
2138 .device = 0x800D,
aaa10eb1
AP		 2139 .subvendor = PCI_ANY_ID,
2140 .subdevice = PCI_ANY_ID,
eb7073db 2141 .init = pci_eg20t_init,
64d91cfa 2142 .setup = pci_default_setup,
eb7073db 2143 },
d9a0fbfd
AP		 2144 /*
2145 * Cronyx Omega PCI (PLX-chip based)
2146 */
2147 {
2148 .vendor = PCI_VENDOR_ID_PLX,
2149 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2150 .subvendor = PCI_ANY_ID,
2151 .subdevice = PCI_ANY_ID,
2152 .setup = pci_omegapci_setup,
eb26dfe8 2153 },
6971c635
GA		 2154 /* WCH CH353 2S1P card (16550 clone) */
2155 {
27788c5f
AC		 2156 .vendor = PCI_VENDOR_ID_WCH,
2157 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2158 .subvendor = PCI_ANY_ID,
2159 .subdevice = PCI_ANY_ID,
2160 .setup = pci_wch_ch353_setup,
2161 },
2162 /* WCH CH353 4S card (16550 clone) */
2163 {
2164 .vendor = PCI_VENDOR_ID_WCH,
2165 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2166 .subvendor = PCI_ANY_ID,
2167 .subdevice = PCI_ANY_ID,
2168 .setup = pci_wch_ch353_setup,
2169 },
2170 /* WCH CH353 2S1PF card (16550 clone) */
2171 {
2172 .vendor = PCI_VENDOR_ID_WCH,
2173 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2174 .subvendor = PCI_ANY_ID,
2175 .subdevice = PCI_ANY_ID,
6971c635
GA		 2176 .setup = pci_wch_ch353_setup,
2177 },
8b5c913f
WY		 2178 /* WCH CH352 2S card (16550 clone) */
2179 {
2180 .vendor = PCI_VENDOR_ID_WCH,
2181 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2182 .subvendor = PCI_ANY_ID,
2183 .subdevice = PCI_ANY_ID,
2184 .setup = pci_wch_ch353_setup,
2185 },
eb26dfe8
AC		 2186 /*
2187 * ASIX devices with FIFO bug
2188 */
2189 {
2190 .vendor = PCI_VENDOR_ID_ASIX,
2191 .device = PCI_ANY_ID,
2192 .subvendor = PCI_ANY_ID,
2193 .subdevice = PCI_ANY_ID,
2194 .setup = pci_asix_setup,
2195 },
14faa8cc
MS		 2196 /*
2197 * Commtech, Inc. Fastcom adapters
2198 *
2199 */
2200 {
2201 .vendor = PCI_VENDOR_ID_COMMTECH,
2202 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2203 .subvendor = PCI_ANY_ID,
2204 .subdevice = PCI_ANY_ID,
2205 .setup = pci_fastcom335_setup,
2206 },
2207 {
2208 .vendor = PCI_VENDOR_ID_COMMTECH,
2209 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2210 .subvendor = PCI_ANY_ID,
2211 .subdevice = PCI_ANY_ID,
2212 .setup = pci_fastcom335_setup,
2213 },
2214 {
2215 .vendor = PCI_VENDOR_ID_COMMTECH,
2216 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2217 .subvendor = PCI_ANY_ID,
2218 .subdevice = PCI_ANY_ID,
2219 .setup = pci_fastcom335_setup,
2220 },
2221 {
2222 .vendor = PCI_VENDOR_ID_COMMTECH,
2223 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2224 .subvendor = PCI_ANY_ID,
2225 .subdevice = PCI_ANY_ID,
2226 .setup = pci_fastcom335_setup,
2227 },
2228 {
2229 .vendor = PCI_VENDOR_ID_COMMTECH,
2230 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2231 .subvendor = PCI_ANY_ID,
2232 .subdevice = PCI_ANY_ID,
2233 .setup = pci_xr17v35x_setup,
2234 },
2235 {
2236 .vendor = PCI_VENDOR_ID_COMMTECH,
2237 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2238 .subvendor = PCI_ANY_ID,
2239 .subdevice = PCI_ANY_ID,
2240 .setup = pci_xr17v35x_setup,
2241 },
2242 {
2243 .vendor = PCI_VENDOR_ID_COMMTECH,
2244 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2245 .subvendor = PCI_ANY_ID,
2246 .subdevice = PCI_ANY_ID,
2247 .setup = pci_xr17v35x_setup,
2248 },
ebebd49a
SH		 2249 /*
2250 * Broadcom TruManage (NetXtreme)
2251 */
2252 {
2253 .vendor = PCI_VENDOR_ID_BROADCOM,
2254 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2255 .subvendor = PCI_ANY_ID,
2256 .subdevice = PCI_ANY_ID,
2257 .setup = pci_brcm_trumanage_setup,
2258 },
2259
1da177e4
LT		 2260 /*
2261 * Default "match everything" terminator entry
2262 */
2263 {
2264 .vendor = PCI_ANY_ID,
2265 .device = PCI_ANY_ID,
2266 .subvendor = PCI_ANY_ID,
2267 .subdevice = PCI_ANY_ID,
2268 .setup = pci_default_setup,
2269 }
2270};
2271
2272static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2273{
2274 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2275}
2276
2277static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2278{
2279 struct pci_serial_quirk *quirk;
2280
2281 for (quirk = pci_serial_quirks; ; quirk++)
2282 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2283 quirk_id_matches(quirk->device, dev->device) &&
2284 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2285 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 2286 break;
1da177e4
LT		 2287 return quirk;
2288}
2289
dd68e88c 2290static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 2291 const struct pciserial_board *board)
1da177e4
LT		 2292{
2293 if (board->flags & FL_NOIRQ)
2294 return 0;
2295 else
2296 return dev->irq;
2297}
2298
2299/*
2300 * This is the configuration table for all of the PCI serial boards
2301 * which we support. It is directly indexed by the pci_board_num_t enum
2302 * value, which is encoded in the pci_device_id PCI probe table's
2303 * driver_data member.
2304 *
2305 * The makeup of these names are:
26e92861 2306 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 2307 *
26e92861
GH		 2308 * bn = PCI BAR number
2309 * bt = Index using PCI BARs
2310 * n = number of serial ports
2311 * baud = baud rate
2312 * offsetinhex = offset for each sequential port (in hex)
1da177e4 2313 *
26e92861 2314 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 2315 *
1da177e4
LT		 2316 * Please note: in theory if n = 1, _bt infix should make no difference.
2317 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2318 */
2319enum pci_board_num_t {
2320 pbn_default = 0,
2321
2322 pbn_b0_1_115200,
2323 pbn_b0_2_115200,
2324 pbn_b0_4_115200,
2325 pbn_b0_5_115200,
bf0df636 2326 pbn_b0_8_115200,
1da177e4
LT		 2327
2328 pbn_b0_1_921600,
2329 pbn_b0_2_921600,
2330 pbn_b0_4_921600,
2331
db1de159
DR		 2332 pbn_b0_2_1130000,
2333
fbc0dc0d
AP		 2334 pbn_b0_4_1152000,
2335
14faa8cc
MS		 2336 pbn_b0_2_1152000_200,
2337 pbn_b0_4_1152000_200,
2338 pbn_b0_8_1152000_200,
2339
26e92861
GH		 2340 pbn_b0_2_1843200,
2341 pbn_b0_4_1843200,
2342
2343 pbn_b0_2_1843200_200,
2344 pbn_b0_4_1843200_200,
2345 pbn_b0_8_1843200_200,
2346
7106b4e3
LH		 2347 pbn_b0_1_4000000,
2348
1da177e4
LT		 2349 pbn_b0_bt_1_115200,
2350 pbn_b0_bt_2_115200,
ac6ec5b1 2351 pbn_b0_bt_4_115200,
1da177e4
LT		 2352 pbn_b0_bt_8_115200,
2353
2354 pbn_b0_bt_1_460800,
2355 pbn_b0_bt_2_460800,
2356 pbn_b0_bt_4_460800,
2357
2358 pbn_b0_bt_1_921600,
2359 pbn_b0_bt_2_921600,
2360 pbn_b0_bt_4_921600,
2361 pbn_b0_bt_8_921600,
2362
2363 pbn_b1_1_115200,
2364 pbn_b1_2_115200,
2365 pbn_b1_4_115200,
2366 pbn_b1_8_115200,
04bf7e74 2367 pbn_b1_16_115200,
1da177e4
LT		 2368
2369 pbn_b1_1_921600,
2370 pbn_b1_2_921600,
2371 pbn_b1_4_921600,
2372 pbn_b1_8_921600,
2373
26e92861
GH		 2374 pbn_b1_2_1250000,
2375
84f8c6fc 2376 pbn_b1_bt_1_115200,
04bf7e74
WP		 2377 pbn_b1_bt_2_115200,
2378 pbn_b1_bt_4_115200,
2379
1da177e4
LT		 2380 pbn_b1_bt_2_921600,
2381
2382 pbn_b1_1_1382400,
2383 pbn_b1_2_1382400,
2384 pbn_b1_4_1382400,
2385 pbn_b1_8_1382400,
2386
2387 pbn_b2_1_115200,
737c1756 2388 pbn_b2_2_115200,
a9cccd34 2389 pbn_b2_4_115200,
1da177e4
LT		 2390 pbn_b2_8_115200,
2391
2392 pbn_b2_1_460800,
2393 pbn_b2_4_460800,
2394 pbn_b2_8_460800,
2395 pbn_b2_16_460800,
2396
2397 pbn_b2_1_921600,
2398 pbn_b2_4_921600,
2399 pbn_b2_8_921600,
2400
e847003f
LB		 2401 pbn_b2_8_1152000,
2402
1da177e4
LT		 2403 pbn_b2_bt_1_115200,
2404 pbn_b2_bt_2_115200,
2405 pbn_b2_bt_4_115200,
2406
2407 pbn_b2_bt_2_921600,
2408 pbn_b2_bt_4_921600,
2409
d9004eb4 2410 pbn_b3_2_115200,
1da177e4
LT		 2411 pbn_b3_4_115200,
2412 pbn_b3_8_115200,
2413
66169ad1
YY		 2414 pbn_b4_bt_2_921600,
2415 pbn_b4_bt_4_921600,
2416 pbn_b4_bt_8_921600,
2417
1da177e4
LT		 2418 /*
2419 * Board-specific versions.
2420 */
2421 pbn_panacom,
2422 pbn_panacom2,
2423 pbn_panacom4,
2424 pbn_plx_romulus,
2425 pbn_oxsemi,
7106b4e3
LH		 2426 pbn_oxsemi_1_4000000,
2427 pbn_oxsemi_2_4000000,
2428 pbn_oxsemi_4_4000000,
2429 pbn_oxsemi_8_4000000,
1da177e4
LT		 2430 pbn_intel_i960,
2431 pbn_sgi_ioc3,
1da177e4
LT		 2432 pbn_computone_4,
2433 pbn_computone_6,
2434 pbn_computone_8,
2435 pbn_sbsxrsio,
2436 pbn_exar_XR17C152,
2437 pbn_exar_XR17C154,
2438 pbn_exar_XR17C158,
dc96efb7
MS		 2439 pbn_exar_XR17V352,
2440 pbn_exar_XR17V354,
2441 pbn_exar_XR17V358,
c68d2b15 2442 pbn_exar_ibm_saturn,
aa798505 2443 pbn_pasemi_1682M,
46a0fac9
SB		 2444 pbn_ni8430_2,
2445 pbn_ni8430_4,
2446 pbn_ni8430_8,
2447 pbn_ni8430_16,
1b62cbf2
KJ		 2448 pbn_ADDIDATA_PCIe_1_3906250,
2449 pbn_ADDIDATA_PCIe_2_3906250,
2450 pbn_ADDIDATA_PCIe_4_3906250,
2451 pbn_ADDIDATA_PCIe_8_3906250,
095e24b0 2452 pbn_ce4100_1_115200,
d9a0fbfd 2453 pbn_omegapci,
7808edcd 2454 pbn_NETMOS9900_2s_115200,
ebebd49a 2455 pbn_brcm_trumanage,
1da177e4
LT		 2456};
2457
2458/*
2459 * uart_offset - the space between channels
2460 * reg_shift - describes how the UART registers are mapped
2461 * to PCI memory by the card.
2462 * For example IER register on SBS, Inc. PMC-OctPro is located at
2463 * offset 0x10 from the UART base, while UART_IER is defined as 1
2464 * in include/linux/serial_reg.h,
2465 * see first lines of serial_in() and serial_out() in 8250.c
2466*/
2467
de88b340 2468static struct pciserial_board pci_boards[] = {
1da177e4
LT		 2469 [pbn_default] = {
2470 .flags = FL_BASE0,
2471 .num_ports = 1,
2472 .base_baud = 115200,
2473 .uart_offset = 8,
2474 },
2475 [pbn_b0_1_115200] = {
2476 .flags = FL_BASE0,
2477 .num_ports = 1,
2478 .base_baud = 115200,
2479 .uart_offset = 8,
2480 },
2481 [pbn_b0_2_115200] = {
2482 .flags = FL_BASE0,
2483 .num_ports = 2,
2484 .base_baud = 115200,
2485 .uart_offset = 8,
2486 },
2487 [pbn_b0_4_115200] = {
2488 .flags = FL_BASE0,
2489 .num_ports = 4,
2490 .base_baud = 115200,
2491 .uart_offset = 8,
2492 },
2493 [pbn_b0_5_115200] = {
2494 .flags = FL_BASE0,
2495 .num_ports = 5,
2496 .base_baud = 115200,
2497 .uart_offset = 8,
2498 },
bf0df636
AC		 2499 [pbn_b0_8_115200] = {
2500 .flags = FL_BASE0,
2501 .num_ports = 8,
2502 .base_baud = 115200,
2503 .uart_offset = 8,
2504 },
1da177e4
LT		 2505 [pbn_b0_1_921600] = {
2506 .flags = FL_BASE0,
2507 .num_ports = 1,
2508 .base_baud = 921600,
2509 .uart_offset = 8,
2510 },
2511 [pbn_b0_2_921600] = {
2512 .flags = FL_BASE0,
2513 .num_ports = 2,
2514 .base_baud = 921600,
2515 .uart_offset = 8,
2516 },
2517 [pbn_b0_4_921600] = {
2518 .flags = FL_BASE0,
2519 .num_ports = 4,
2520 .base_baud = 921600,
2521 .uart_offset = 8,
2522 },
db1de159
DR		 2523
2524 [pbn_b0_2_1130000] = {
2525 .flags = FL_BASE0,
2526 .num_ports = 2,
2527 .base_baud = 1130000,
2528 .uart_offset = 8,
2529 },
2530
fbc0dc0d
AP		 2531 [pbn_b0_4_1152000] = {
2532 .flags = FL_BASE0,
2533 .num_ports = 4,
2534 .base_baud = 1152000,
2535 .uart_offset = 8,
2536 },
1da177e4 2537
14faa8cc
MS		 2538 [pbn_b0_2_1152000_200] = {
2539 .flags = FL_BASE0,
2540 .num_ports = 2,
2541 .base_baud = 1152000,
2542 .uart_offset = 0x200,
2543 },
2544
2545 [pbn_b0_4_1152000_200] = {
2546 .flags = FL_BASE0,
2547 .num_ports = 4,
2548 .base_baud = 1152000,
2549 .uart_offset = 0x200,
2550 },
2551
2552 [pbn_b0_8_1152000_200] = {
2553 .flags = FL_BASE0,
4f7d67d0 2554 .num_ports = 8,
14faa8cc
MS		 2555 .base_baud = 1152000,
2556 .uart_offset = 0x200,
2557 },
2558
26e92861
GH		 2559 [pbn_b0_2_1843200] = {
2560 .flags = FL_BASE0,
2561 .num_ports = 2,
2562 .base_baud = 1843200,
2563 .uart_offset = 8,
2564 },
2565 [pbn_b0_4_1843200] = {
2566 .flags = FL_BASE0,
2567 .num_ports = 4,
2568 .base_baud = 1843200,
2569 .uart_offset = 8,
2570 },
2571
2572 [pbn_b0_2_1843200_200] = {
2573 .flags = FL_BASE0,
2574 .num_ports = 2,
2575 .base_baud = 1843200,
2576 .uart_offset = 0x200,
2577 },
2578 [pbn_b0_4_1843200_200] = {
2579 .flags = FL_BASE0,
2580 .num_ports = 4,
2581 .base_baud = 1843200,
2582 .uart_offset = 0x200,
2583 },
2584 [pbn_b0_8_1843200_200] = {
2585 .flags = FL_BASE0,
2586 .num_ports = 8,
2587 .base_baud = 1843200,
2588 .uart_offset = 0x200,
2589 },
7106b4e3
LH		 2590 [pbn_b0_1_4000000] = {
2591 .flags = FL_BASE0,
2592 .num_ports = 1,
2593 .base_baud = 4000000,
2594 .uart_offset = 8,
2595 },
26e92861 2596
1da177e4
LT		 2597 [pbn_b0_bt_1_115200] = {
2598 .flags = FL_BASE0|FL_BASE_BARS,
2599 .num_ports = 1,
2600 .base_baud = 115200,
2601 .uart_offset = 8,
2602 },
2603 [pbn_b0_bt_2_115200] = {
2604 .flags = FL_BASE0|FL_BASE_BARS,
2605 .num_ports = 2,
2606 .base_baud = 115200,
2607 .uart_offset = 8,
2608 },
ac6ec5b1
IS		 2609 [pbn_b0_bt_4_115200] = {
2610 .flags = FL_BASE0|FL_BASE_BARS,
2611 .num_ports = 4,
2612 .base_baud = 115200,
2613 .uart_offset = 8,
2614 },
1da177e4
LT		 2615 [pbn_b0_bt_8_115200] = {
2616 .flags = FL_BASE0|FL_BASE_BARS,
2617 .num_ports = 8,
2618 .base_baud = 115200,
2619 .uart_offset = 8,
2620 },
2621
2622 [pbn_b0_bt_1_460800] = {
2623 .flags = FL_BASE0|FL_BASE_BARS,
2624 .num_ports = 1,
2625 .base_baud = 460800,
2626 .uart_offset = 8,
2627 },
2628 [pbn_b0_bt_2_460800] = {
2629 .flags = FL_BASE0|FL_BASE_BARS,
2630 .num_ports = 2,
2631 .base_baud = 460800,
2632 .uart_offset = 8,
2633 },
2634 [pbn_b0_bt_4_460800] = {
2635 .flags = FL_BASE0|FL_BASE_BARS,
2636 .num_ports = 4,
2637 .base_baud = 460800,
2638 .uart_offset = 8,
2639 },
2640
2641 [pbn_b0_bt_1_921600] = {
2642 .flags = FL_BASE0|FL_BASE_BARS,
2643 .num_ports = 1,
2644 .base_baud = 921600,
2645 .uart_offset = 8,
2646 },
2647 [pbn_b0_bt_2_921600] = {
2648 .flags = FL_BASE0|FL_BASE_BARS,
2649 .num_ports = 2,
2650 .base_baud = 921600,
2651 .uart_offset = 8,
2652 },
2653 [pbn_b0_bt_4_921600] = {
2654 .flags = FL_BASE0|FL_BASE_BARS,
2655 .num_ports = 4,
2656 .base_baud = 921600,
2657 .uart_offset = 8,
2658 },
2659 [pbn_b0_bt_8_921600] = {
2660 .flags = FL_BASE0|FL_BASE_BARS,
2661 .num_ports = 8,
2662 .base_baud = 921600,
2663 .uart_offset = 8,
2664 },
2665
2666 [pbn_b1_1_115200] = {
2667 .flags = FL_BASE1,
2668 .num_ports = 1,
2669 .base_baud = 115200,
2670 .uart_offset = 8,
2671 },
2672 [pbn_b1_2_115200] = {
2673 .flags = FL_BASE1,
2674 .num_ports = 2,
2675 .base_baud = 115200,
2676 .uart_offset = 8,
2677 },
2678 [pbn_b1_4_115200] = {
2679 .flags = FL_BASE1,
2680 .num_ports = 4,
2681 .base_baud = 115200,
2682 .uart_offset = 8,
2683 },
2684 [pbn_b1_8_115200] = {
2685 .flags = FL_BASE1,
2686 .num_ports = 8,
2687 .base_baud = 115200,
2688 .uart_offset = 8,
2689 },
04bf7e74
WP		 2690 [pbn_b1_16_115200] = {
2691 .flags = FL_BASE1,
2692 .num_ports = 16,
2693 .base_baud = 115200,
2694 .uart_offset = 8,
2695 },
1da177e4
LT		 2696
2697 [pbn_b1_1_921600] = {
2698 .flags = FL_BASE1,
2699 .num_ports = 1,
2700 .base_baud = 921600,
2701 .uart_offset = 8,
2702 },
2703 [pbn_b1_2_921600] = {
2704 .flags = FL_BASE1,
2705 .num_ports = 2,
2706 .base_baud = 921600,
2707 .uart_offset = 8,
2708 },
2709 [pbn_b1_4_921600] = {
2710 .flags = FL_BASE1,
2711 .num_ports = 4,
2712 .base_baud = 921600,
2713 .uart_offset = 8,
2714 },
2715 [pbn_b1_8_921600] = {
2716 .flags = FL_BASE1,
2717 .num_ports = 8,
2718 .base_baud = 921600,
2719 .uart_offset = 8,
2720 },
26e92861
GH		 2721 [pbn_b1_2_1250000] = {
2722 .flags = FL_BASE1,
2723 .num_ports = 2,
2724 .base_baud = 1250000,
2725 .uart_offset = 8,
2726 },
1da177e4 2727
84f8c6fc
NV		 2728 [pbn_b1_bt_1_115200] = {
2729 .flags = FL_BASE1|FL_BASE_BARS,
2730 .num_ports = 1,
2731 .base_baud = 115200,
2732 .uart_offset = 8,
2733 },
04bf7e74
WP		 2734 [pbn_b1_bt_2_115200] = {
2735 .flags = FL_BASE1|FL_BASE_BARS,
2736 .num_ports = 2,
2737 .base_baud = 115200,
2738 .uart_offset = 8,
2739 },
2740 [pbn_b1_bt_4_115200] = {
2741 .flags = FL_BASE1|FL_BASE_BARS,
2742 .num_ports = 4,
2743 .base_baud = 115200,
2744 .uart_offset = 8,
2745 },
84f8c6fc 2746
1da177e4
LT		 2747 [pbn_b1_bt_2_921600] = {
2748 .flags = FL_BASE1|FL_BASE_BARS,
2749 .num_ports = 2,
2750 .base_baud = 921600,
2751 .uart_offset = 8,
2752 },
2753
2754 [pbn_b1_1_1382400] = {
2755 .flags = FL_BASE1,
2756 .num_ports = 1,
2757 .base_baud = 1382400,
2758 .uart_offset = 8,
2759 },
2760 [pbn_b1_2_1382400] = {
2761 .flags = FL_BASE1,
2762 .num_ports = 2,
2763 .base_baud = 1382400,
2764 .uart_offset = 8,
2765 },
2766 [pbn_b1_4_1382400] = {
2767 .flags = FL_BASE1,
2768 .num_ports = 4,
2769 .base_baud = 1382400,
2770 .uart_offset = 8,
2771 },
2772 [pbn_b1_8_1382400] = {
2773 .flags = FL_BASE1,
2774 .num_ports = 8,
2775 .base_baud = 1382400,
2776 .uart_offset = 8,
2777 },
2778
2779 [pbn_b2_1_115200] = {
2780 .flags = FL_BASE2,
2781 .num_ports = 1,
2782 .base_baud = 115200,
2783 .uart_offset = 8,
2784 },
737c1756
PH		 2785 [pbn_b2_2_115200] = {
2786 .flags = FL_BASE2,
2787 .num_ports = 2,
2788 .base_baud = 115200,
2789 .uart_offset = 8,
2790 },
a9cccd34
MF		 2791 [pbn_b2_4_115200] = {
2792 .flags = FL_BASE2,
2793 .num_ports = 4,
2794 .base_baud = 115200,
2795 .uart_offset = 8,
2796 },
1da177e4
LT		 2797 [pbn_b2_8_115200] = {
2798 .flags = FL_BASE2,
2799 .num_ports = 8,
2800 .base_baud = 115200,
2801 .uart_offset = 8,
2802 },
2803
2804 [pbn_b2_1_460800] = {
2805 .flags = FL_BASE2,
2806 .num_ports = 1,
2807 .base_baud = 460800,
2808 .uart_offset = 8,
2809 },
2810 [pbn_b2_4_460800] = {
2811 .flags = FL_BASE2,
2812 .num_ports = 4,
2813 .base_baud = 460800,
2814 .uart_offset = 8,
2815 },
2816 [pbn_b2_8_460800] = {
2817 .flags = FL_BASE2,
2818 .num_ports = 8,
2819 .base_baud = 460800,
2820 .uart_offset = 8,
2821 },
2822 [pbn_b2_16_460800] = {
2823 .flags = FL_BASE2,
2824 .num_ports = 16,
2825 .base_baud = 460800,
2826 .uart_offset = 8,
2827 },
2828
2829 [pbn_b2_1_921600] = {
2830 .flags = FL_BASE2,
2831 .num_ports = 1,
2832 .base_baud = 921600,
2833 .uart_offset = 8,
2834 },
2835 [pbn_b2_4_921600] = {
2836 .flags = FL_BASE2,
2837 .num_ports = 4,
2838 .base_baud = 921600,
2839 .uart_offset = 8,
2840 },
2841 [pbn_b2_8_921600] = {
2842 .flags = FL_BASE2,
2843 .num_ports = 8,
2844 .base_baud = 921600,
2845 .uart_offset = 8,
2846 },
2847
e847003f
LB		 2848 [pbn_b2_8_1152000] = {
2849 .flags = FL_BASE2,
2850 .num_ports = 8,
2851 .base_baud = 1152000,
2852 .uart_offset = 8,
2853 },
2854
1da177e4
LT		 2855 [pbn_b2_bt_1_115200] = {
2856 .flags = FL_BASE2|FL_BASE_BARS,
2857 .num_ports = 1,
2858 .base_baud = 115200,
2859 .uart_offset = 8,
2860 },
2861 [pbn_b2_bt_2_115200] = {
2862 .flags = FL_BASE2|FL_BASE_BARS,
2863 .num_ports = 2,
2864 .base_baud = 115200,
2865 .uart_offset = 8,
2866 },
2867 [pbn_b2_bt_4_115200] = {
2868 .flags = FL_BASE2|FL_BASE_BARS,
2869 .num_ports = 4,
2870 .base_baud = 115200,
2871 .uart_offset = 8,
2872 },
2873
2874 [pbn_b2_bt_2_921600] = {
2875 .flags = FL_BASE2|FL_BASE_BARS,
2876 .num_ports = 2,
2877 .base_baud = 921600,
2878 .uart_offset = 8,
2879 },
2880 [pbn_b2_bt_4_921600] = {
2881 .flags = FL_BASE2|FL_BASE_BARS,
2882 .num_ports = 4,
2883 .base_baud = 921600,
2884 .uart_offset = 8,
2885 },
2886
d9004eb4
ABL		 2887 [pbn_b3_2_115200] = {
2888 .flags = FL_BASE3,
2889 .num_ports = 2,
2890 .base_baud = 115200,
2891 .uart_offset = 8,
2892 },
1da177e4
LT		 2893 [pbn_b3_4_115200] = {
2894 .flags = FL_BASE3,
2895 .num_ports = 4,
2896 .base_baud = 115200,
2897 .uart_offset = 8,
2898 },
2899 [pbn_b3_8_115200] = {
2900 .flags = FL_BASE3,
2901 .num_ports = 8,
2902 .base_baud = 115200,
2903 .uart_offset = 8,
2904 },
2905
66169ad1
YY		 2906 [pbn_b4_bt_2_921600] = {
2907 .flags = FL_BASE4,
2908 .num_ports = 2,
2909 .base_baud = 921600,
2910 .uart_offset = 8,
2911 },
2912 [pbn_b4_bt_4_921600] = {
2913 .flags = FL_BASE4,
2914 .num_ports = 4,
2915 .base_baud = 921600,
2916 .uart_offset = 8,
2917 },
2918 [pbn_b4_bt_8_921600] = {
2919 .flags = FL_BASE4,
2920 .num_ports = 8,
2921 .base_baud = 921600,
2922 .uart_offset = 8,
2923 },
2924
1da177e4
LT		 2925 /*
2926 * Entries following this are board-specific.
2927 */
2928
2929 /*
2930 * Panacom - IOMEM
2931 */
2932 [pbn_panacom] = {
2933 .flags = FL_BASE2,
2934 .num_ports = 2,
2935 .base_baud = 921600,
2936 .uart_offset = 0x400,
2937 .reg_shift = 7,
2938 },
2939 [pbn_panacom2] = {
2940 .flags = FL_BASE2|FL_BASE_BARS,
2941 .num_ports = 2,
2942 .base_baud = 921600,
2943 .uart_offset = 0x400,
2944 .reg_shift = 7,
2945 },
2946 [pbn_panacom4] = {
2947 .flags = FL_BASE2|FL_BASE_BARS,
2948 .num_ports = 4,
2949 .base_baud = 921600,
2950 .uart_offset = 0x400,
2951 .reg_shift = 7,
2952 },
2953
2954 /* I think this entry is broken - the first_offset looks wrong --rmk */
2955 [pbn_plx_romulus] = {
2956 .flags = FL_BASE2,
2957 .num_ports = 4,
2958 .base_baud = 921600,
2959 .uart_offset = 8 << 2,
2960 .reg_shift = 2,
2961 .first_offset = 0x03,
2962 },
2963
2964 /*
2965 * This board uses the size of PCI Base region 0 to
2966 * signal now many ports are available
2967 */
2968 [pbn_oxsemi] = {
2969 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2970 .num_ports = 32,
2971 .base_baud = 115200,
2972 .uart_offset = 8,
2973 },
7106b4e3
LH		 2974 [pbn_oxsemi_1_4000000] = {
2975 .flags = FL_BASE0,
2976 .num_ports = 1,
2977 .base_baud = 4000000,
2978 .uart_offset = 0x200,
2979 .first_offset = 0x1000,
2980 },
2981 [pbn_oxsemi_2_4000000] = {
2982 .flags = FL_BASE0,
2983 .num_ports = 2,
2984 .base_baud = 4000000,
2985 .uart_offset = 0x200,
2986 .first_offset = 0x1000,
2987 },
2988 [pbn_oxsemi_4_4000000] = {
2989 .flags = FL_BASE0,
2990 .num_ports = 4,
2991 .base_baud = 4000000,
2992 .uart_offset = 0x200,
2993 .first_offset = 0x1000,
2994 },
2995 [pbn_oxsemi_8_4000000] = {
2996 .flags = FL_BASE0,
2997 .num_ports = 8,
2998 .base_baud = 4000000,
2999 .uart_offset = 0x200,
3000 .first_offset = 0x1000,
3001 },
3002
1da177e4
LT		 3003
3004 /*
3005 * EKF addition for i960 Boards form EKF with serial port.
3006 * Max 256 ports.
3007 */
3008 [pbn_intel_i960] = {
3009 .flags = FL_BASE0,
3010 .num_ports = 32,
3011 .base_baud = 921600,
3012 .uart_offset = 8 << 2,
3013 .reg_shift = 2,
3014 .first_offset = 0x10000,
3015 },
3016 [pbn_sgi_ioc3] = {
3017 .flags = FL_BASE0|FL_NOIRQ,
3018 .num_ports = 1,
3019 .base_baud = 458333,
3020 .uart_offset = 8,
3021 .reg_shift = 0,
3022 .first_offset = 0x20178,
3023 },
3024
1da177e4
LT		 3025 /*
3026 * Computone - uses IOMEM.
3027 */
3028 [pbn_computone_4] = {
3029 .flags = FL_BASE0,
3030 .num_ports = 4,
3031 .base_baud = 921600,
3032 .uart_offset = 0x40,
3033 .reg_shift = 2,
3034 .first_offset = 0x200,
3035 },
3036 [pbn_computone_6] = {
3037 .flags = FL_BASE0,
3038 .num_ports = 6,
3039 .base_baud = 921600,
3040 .uart_offset = 0x40,
3041 .reg_shift = 2,
3042 .first_offset = 0x200,
3043 },
3044 [pbn_computone_8] = {
3045 .flags = FL_BASE0,
3046 .num_ports = 8,
3047 .base_baud = 921600,
3048 .uart_offset = 0x40,
3049 .reg_shift = 2,
3050 .first_offset = 0x200,
3051 },
3052 [pbn_sbsxrsio] = {
3053 .flags = FL_BASE0,
3054 .num_ports = 8,
3055 .base_baud = 460800,
3056 .uart_offset = 256,
3057 .reg_shift = 4,
3058 },
3059 /*
3060 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3061 * Only basic 16550A support.
3062 * XR17C15[24] are not tested, but they should work.
3063 */
3064 [pbn_exar_XR17C152] = {
3065 .flags = FL_BASE0,
3066 .num_ports = 2,
3067 .base_baud = 921600,
3068 .uart_offset = 0x200,
3069 },
3070 [pbn_exar_XR17C154] = {
3071 .flags = FL_BASE0,
3072 .num_ports = 4,
3073 .base_baud = 921600,
3074 .uart_offset = 0x200,
3075 },
3076 [pbn_exar_XR17C158] = {
3077 .flags = FL_BASE0,
3078 .num_ports = 8,
3079 .base_baud = 921600,
3080 .uart_offset = 0x200,
3081 },
dc96efb7
MS		 3082 [pbn_exar_XR17V352] = {
3083 .flags = FL_BASE0,
3084 .num_ports = 2,
3085 .base_baud = 7812500,
3086 .uart_offset = 0x400,
3087 .reg_shift = 0,
3088 .first_offset = 0,
3089 },
3090 [pbn_exar_XR17V354] = {
3091 .flags = FL_BASE0,
3092 .num_ports = 4,
3093 .base_baud = 7812500,
3094 .uart_offset = 0x400,
3095 .reg_shift = 0,
3096 .first_offset = 0,
3097 },
3098 [pbn_exar_XR17V358] = {
3099 .flags = FL_BASE0,
3100 .num_ports = 8,
3101 .base_baud = 7812500,
3102 .uart_offset = 0x400,
3103 .reg_shift = 0,
3104 .first_offset = 0,
3105 },
c68d2b15
BH		 3106 [pbn_exar_ibm_saturn] = {
3107 .flags = FL_BASE0,
3108 .num_ports = 1,
3109 .base_baud = 921600,
3110 .uart_offset = 0x200,
3111 },
3112
aa798505
OJ		 3113 /*
3114 * PA Semi PWRficient PA6T-1682M on-chip UART
3115 */
3116 [pbn_pasemi_1682M] = {
3117 .flags = FL_BASE0,
3118 .num_ports = 1,
3119 .base_baud = 8333333,
3120 },
46a0fac9
SB		 3121 /*
3122 * National Instruments 843x
3123 */
3124 [pbn_ni8430_16] = {
3125 .flags = FL_BASE0,
3126 .num_ports = 16,
3127 .base_baud = 3686400,
3128 .uart_offset = 0x10,
3129 .first_offset = 0x800,
3130 },
3131 [pbn_ni8430_8] = {
3132 .flags = FL_BASE0,
3133 .num_ports = 8,
3134 .base_baud = 3686400,
3135 .uart_offset = 0x10,
3136 .first_offset = 0x800,
3137 },
3138 [pbn_ni8430_4] = {
3139 .flags = FL_BASE0,
3140 .num_ports = 4,
3141 .base_baud = 3686400,
3142 .uart_offset = 0x10,
3143 .first_offset = 0x800,
3144 },
3145 [pbn_ni8430_2] = {
3146 .flags = FL_BASE0,
3147 .num_ports = 2,
3148 .base_baud = 3686400,
3149 .uart_offset = 0x10,
3150 .first_offset = 0x800,
3151 },
1b62cbf2
KJ		 3152 /*
3153 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3154 */
3155 [pbn_ADDIDATA_PCIe_1_3906250] = {
3156 .flags = FL_BASE0,
3157 .num_ports = 1,
3158 .base_baud = 3906250,
3159 .uart_offset = 0x200,
3160 .first_offset = 0x1000,
3161 },
3162 [pbn_ADDIDATA_PCIe_2_3906250] = {
3163 .flags = FL_BASE0,
3164 .num_ports = 2,
3165 .base_baud = 3906250,
3166 .uart_offset = 0x200,
3167 .first_offset = 0x1000,
3168 },
3169 [pbn_ADDIDATA_PCIe_4_3906250] = {
3170 .flags = FL_BASE0,
3171 .num_ports = 4,
3172 .base_baud = 3906250,
3173 .uart_offset = 0x200,
3174 .first_offset = 0x1000,
3175 },
3176 [pbn_ADDIDATA_PCIe_8_3906250] = {
3177 .flags = FL_BASE0,
3178 .num_ports = 8,
3179 .base_baud = 3906250,
3180 .uart_offset = 0x200,
3181 .first_offset = 0x1000,
3182 },
095e24b0 3183 [pbn_ce4100_1_115200] = {
08ec212c
MB		 3184 .flags = FL_BASE_BARS,
3185 .num_ports = 2,
095e24b0
DB		 3186 .base_baud = 921600,
3187 .reg_shift = 2,
3188 },
d9a0fbfd
AP		 3189 [pbn_omegapci] = {
3190 .flags = FL_BASE0,
3191 .num_ports = 8,
3192 .base_baud = 115200,
3193 .uart_offset = 0x200,
3194 },
7808edcd
NG		 3195 [pbn_NETMOS9900_2s_115200] = {
3196 .flags = FL_BASE0,
3197 .num_ports = 2,
3198 .base_baud = 115200,
3199 },
ebebd49a
SH		 3200 [pbn_brcm_trumanage] = {
3201 .flags = FL_BASE0,
3202 .num_ports = 1,
3203 .reg_shift = 2,
3204 .base_baud = 115200,
3205 },
1da177e4
LT		 3206};
3207
6971c635
GA		 3208static const struct pci_device_id blacklist[] = {
3209 /* softmodems */
5756ee99 3210 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
ebf7c066
MS		 3211 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3212 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
6971c635
GA		 3213
3214 /* multi-io cards handled by parport_serial */
3215 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
436bbd43
CS		 3216};
3217
1da177e4
LT		 3218/*
3219 * Given a complete unknown PCI device, try to use some heuristics to
3220 * guess what the configuration might be, based on the pitiful PCI
3221 * serial specs. Returns 0 on success, 1 on failure.
3222 */
9671f099 3223static int
1c7c1fe5 3224serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 3225{
6971c635 3226 const struct pci_device_id *bldev;
1da177e4 3227 int num_iomem, num_port, first_port = -1, i;
5756ee99 3228
1da177e4
LT		 3229 /*
3230 * If it is not a communications device or the programming
3231 * interface is greater than 6, give up.
3232 *
3233 * (Should we try to make guesses for multiport serial devices
5756ee99 3234 * later?)
1da177e4
LT		 3235 */
3236 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3237 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3238 (dev->class & 0xff) > 6)
3239 return -ENODEV;
3240
436bbd43
CS		 3241 /*
3242 * Do not access blacklisted devices that are known not to
6971c635 3243 * feature serial ports or are handled by other modules.
436bbd43 3244 */
6971c635
GA		 3245 for (bldev = blacklist;
3246 bldev < blacklist + ARRAY_SIZE(blacklist);
3247 bldev++) {
3248 if (dev->vendor == bldev->vendor &&
3249 dev->device == bldev->device)
436bbd43
CS		 3250 return -ENODEV;
3251 }
3252
1da177e4
LT		 3253 num_iomem = num_port = 0;
3254 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3255 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3256 num_port++;
3257 if (first_port == -1)
3258 first_port = i;
3259 }
3260 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3261 num_iomem++;
3262 }
3263
3264 /*
3265 * If there is 1 or 0 iomem regions, and exactly one port,
3266 * use it. We guess the number of ports based on the IO
3267 * region size.
3268 */
3269 if (num_iomem <= 1 && num_port == 1) {
3270 board->flags = first_port;
3271 board->num_ports = pci_resource_len(dev, first_port) / 8;
3272 return 0;
3273 }
3274
3275 /*
3276 * Now guess if we've got a board which indexes by BARs.
3277 * Each IO BAR should be 8 bytes, and they should follow
3278 * consecutively.
3279 */
3280 first_port = -1;
3281 num_port = 0;
3282 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3283 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3284 pci_resource_len(dev, i) == 8 &&
3285 (first_port == -1 || (first_port + num_port) == i)) {
3286 num_port++;
3287 if (first_port == -1)
3288 first_port = i;
3289 }
3290 }
3291
3292 if (num_port > 1) {
3293 board->flags = first_port | FL_BASE_BARS;
3294 board->num_ports = num_port;
3295 return 0;
3296 }
3297
3298 return -ENODEV;
3299}
3300
3301static inline int
975a1a7d
RK		 3302serial_pci_matches(const struct pciserial_board *board,
3303 const struct pciserial_board *guessed)
1da177e4
LT		 3304{
3305 return
3306 board->num_ports == guessed->num_ports &&
3307 board->base_baud == guessed->base_baud &&
3308 board->uart_offset == guessed->uart_offset &&
3309 board->reg_shift == guessed->reg_shift &&
3310 board->first_offset == guessed->first_offset;
3311}
3312
241fc436 3313struct serial_private *
975a1a7d 3314pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 3315{
2655a2c7 3316 struct uart_8250_port uart;
1da177e4 3317 struct serial_private *priv;
1da177e4
LT		 3318 struct pci_serial_quirk *quirk;
3319 int rc, nr_ports, i;
3320
1da177e4
LT		 3321 nr_ports = board->num_ports;
3322
3323 /*
3324 * Find an init and setup quirks.
3325 */
3326 quirk = find_quirk(dev);
3327
3328 /*
3329 * Run the new-style initialization function.
3330 * The initialization function returns:
3331 * <0 - error
3332 * 0 - use board->num_ports
3333 * >0 - number of ports
3334 */
3335 if (quirk->init) {
3336 rc = quirk->init(dev);
241fc436
RK		 3337 if (rc < 0) {
3338 priv = ERR_PTR(rc);
3339 goto err_out;
3340 }
1da177e4
LT		 3341 if (rc)
3342 nr_ports = rc;
3343 }
3344
8f31bb39 3345 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 3346 sizeof(unsigned int) * nr_ports,
3347 GFP_KERNEL);
3348 if (!priv) {
241fc436
RK		 3349 priv = ERR_PTR(-ENOMEM);
3350 goto err_deinit;
1da177e4
LT		 3351 }
3352
70db3d91 3353 priv->dev = dev;
1da177e4 3354 priv->quirk = quirk;
1da177e4 3355
2655a2c7
AC		 3356 memset(&uart, 0, sizeof(uart));
3357 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3358 uart.port.uartclk = board->base_baud * 16;
3359 uart.port.irq = get_pci_irq(dev, board);
3360 uart.port.dev = &dev->dev;
72ce9a83 3361
1da177e4 3362 for (i = 0; i < nr_ports; i++) {
2655a2c7 3363 if (quirk->setup(priv, board, &uart, i))
1da177e4 3364 break;
72ce9a83 3365
1da177e4 3366#ifdef SERIAL_DEBUG_PCI
80647b95 3367 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2655a2c7 3368 uart.port.iobase, uart.port.irq, uart.port.iotype);
1da177e4 3369#endif
5756ee99 3370
2655a2c7 3371 priv->line[i] = serial8250_register_8250_port(&uart);
1da177e4
LT		 3372 if (priv->line[i] < 0) {
3373 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
3374 break;
3375 }
3376 }
1da177e4 3377 priv->nr = i;
1d662dc0 3378 priv->board = board;
241fc436 3379 return priv;
1da177e4 3380
5756ee99 3381err_deinit:
1da177e4
LT		 3382 if (quirk->exit)
3383 quirk->exit(dev);
5756ee99 3384err_out:
241fc436 3385 return priv;
1da177e4 3386}
241fc436 3387EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 3388
1d662dc0 3389void pciserial_detach_ports(struct serial_private *priv)
1da177e4 3390{
056a8763
RK		 3391 struct pci_serial_quirk *quirk;
3392 int i;
1da177e4 3393
056a8763
RK		 3394 for (i = 0; i < priv->nr; i++)
3395 serial8250_unregister_port(priv->line[i]);
1da177e4 3396
056a8763
RK		 3397 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3398 if (priv->remapped_bar[i])
3399 iounmap(priv->remapped_bar[i]);
3400 priv->remapped_bar[i] = NULL;
3401 }
1da177e4 3402
056a8763
RK		 3403 /*
3404 * Find the exit quirks.
3405 */
241fc436 3406 quirk = find_quirk(priv->dev);
056a8763 3407 if (quirk->exit)
241fc436 3408 quirk->exit(priv->dev);
1d662dc0 3409}
241fc436 3410
1d662dc0
GKB		 3411void pciserial_remove_ports(struct serial_private *priv)
3412{
3413 pciserial_detach_ports(priv);
241fc436
RK		 3414 kfree(priv);
3415}
3416EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3417
3418void pciserial_suspend_ports(struct serial_private *priv)
3419{
3420 int i;
3421
3422 for (i = 0; i < priv->nr; i++)
3423 if (priv->line[i] >= 0)
3424 serial8250_suspend_port(priv->line[i]);
5f1a3895
DW		 3425
3426 /*
3427 * Ensure that every init quirk is properly torn down
3428 */
3429 if (priv->quirk->exit)
3430 priv->quirk->exit(priv->dev);
241fc436
RK		 3431}
3432EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3433
3434void pciserial_resume_ports(struct serial_private *priv)
3435{
3436 int i;
3437
3438 /*
3439 * Ensure that the board is correctly configured.
3440 */
3441 if (priv->quirk->init)
3442 priv->quirk->init(priv->dev);
3443
3444 for (i = 0; i < priv->nr; i++)
3445 if (priv->line[i] >= 0)
3446 serial8250_resume_port(priv->line[i]);
3447}
3448EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3449
3450/*
3451 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3452 * to the arrangement of serial ports on a PCI card.
3453 */
9671f099 3454static int
241fc436
RK		 3455pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3456{
5bf8f501 3457 struct pci_serial_quirk *quirk;
241fc436 3458 struct serial_private *priv;
975a1a7d
RK		 3459 const struct pciserial_board *board;
3460 struct pciserial_board tmp;
241fc436
RK		 3461 int rc;
3462
5bf8f501
FB		 3463 quirk = find_quirk(dev);
3464 if (quirk->probe) {
3465 rc = quirk->probe(dev);
3466 if (rc)
3467 return rc;
3468 }
3469
241fc436
RK		 3470 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3471 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
3472 ent->driver_data);
3473 return -EINVAL;
3474 }
3475
3476 board = &pci_boards[ent->driver_data];
3477
3478 rc = pci_enable_device(dev);
2807190b 3479 pci_save_state(dev);
241fc436
RK		 3480 if (rc)
3481 return rc;
3482
3483 if (ent->driver_data == pbn_default) {
3484 /*
3485 * Use a copy of the pci_board entry for this;
3486 * avoid changing entries in the table.
3487 */
3488 memcpy(&tmp, board, sizeof(struct pciserial_board));
3489 board = &tmp;
3490
3491 /*
3492 * We matched one of our class entries. Try to
3493 * determine the parameters of this board.
3494 */
975a1a7d 3495 rc = serial_pci_guess_board(dev, &tmp);
241fc436
RK		 3496 if (rc)
3497 goto disable;
3498 } else {
3499 /*
3500 * We matched an explicit entry. If we are able to
3501 * detect this boards settings with our heuristic,
3502 * then we no longer need this entry.
3503 */
3504 memcpy(&tmp, &pci_boards[pbn_default],
3505 sizeof(struct pciserial_board));
3506 rc = serial_pci_guess_board(dev, &tmp);
3507 if (rc == 0 && serial_pci_matches(board, &tmp))
3508 moan_device("Redundant entry in serial pci_table.",
3509 dev);
3510 }
3511
3512 priv = pciserial_init_ports(dev, board);
3513 if (!IS_ERR(priv)) {
3514 pci_set_drvdata(dev, priv);
3515 return 0;
3516 }
3517
3518 rc = PTR_ERR(priv);
1da177e4 3519
241fc436 3520 disable:
056a8763 3521 pci_disable_device(dev);
241fc436
RK		 3522 return rc;
3523}
1da177e4 3524
ae8d8a14 3525static void pciserial_remove_one(struct pci_dev *dev)
241fc436
RK		 3526{
3527 struct serial_private *priv = pci_get_drvdata(dev);
3528
3529 pci_set_drvdata(dev, NULL);
3530
3531 pciserial_remove_ports(priv);
3532
3533 pci_disable_device(dev);
1da177e4
LT		 3534}
3535
1d5e7996 3536#ifdef CONFIG_PM
1da177e4
LT		 3537static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3538{
3539 struct serial_private *priv = pci_get_drvdata(dev);
3540
241fc436
RK		 3541 if (priv)
3542 pciserial_suspend_ports(priv);
1da177e4 3543
1da177e4
LT		 3544 pci_save_state(dev);
3545 pci_set_power_state(dev, pci_choose_state(dev, state));
3546 return 0;
3547}
3548
3549static int pciserial_resume_one(struct pci_dev *dev)
3550{
ccb9d59e 3551 int err;
1da177e4
LT		 3552 struct serial_private *priv = pci_get_drvdata(dev);
3553
3554 pci_set_power_state(dev, PCI_D0);
3555 pci_restore_state(dev);
3556
3557 if (priv) {
1da177e4
LT		 3558 /*
3559 * The device may have been disabled. Re-enable it.
3560 */
ccb9d59e 3561 err = pci_enable_device(dev);
40836c48 3562 /* FIXME: We cannot simply error out here */
ccb9d59e 3563 if (err)
40836c48 3564 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
241fc436 3565 pciserial_resume_ports(priv);
1da177e4
LT		 3566 }
3567 return 0;
3568}
1d5e7996 3569#endif
1da177e4
LT		 3570
3571static struct pci_device_id serial_pci_tbl[] = {
78d70d48
MB		 3572 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3573 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3574 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3575 pbn_b2_8_921600 },
1da177e4
LT		 3576 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3577 PCI_SUBVENDOR_ID_CONNECT_TECH,
3578 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3579 pbn_b1_8_1382400 },
3580 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3581 PCI_SUBVENDOR_ID_CONNECT_TECH,
3582 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3583 pbn_b1_4_1382400 },
3584 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3585 PCI_SUBVENDOR_ID_CONNECT_TECH,
3586 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3587 pbn_b1_2_1382400 },
3588 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3589 PCI_SUBVENDOR_ID_CONNECT_TECH,
3590 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3591 pbn_b1_8_1382400 },
3592 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3593 PCI_SUBVENDOR_ID_CONNECT_TECH,
3594 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3595 pbn_b1_4_1382400 },
3596 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3597 PCI_SUBVENDOR_ID_CONNECT_TECH,
3598 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3599 pbn_b1_2_1382400 },
3600 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3601 PCI_SUBVENDOR_ID_CONNECT_TECH,
3602 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3603 pbn_b1_8_921600 },
3604 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3605 PCI_SUBVENDOR_ID_CONNECT_TECH,
3606 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3607 pbn_b1_8_921600 },
3608 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3609 PCI_SUBVENDOR_ID_CONNECT_TECH,
3610 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3611 pbn_b1_4_921600 },
3612 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3613 PCI_SUBVENDOR_ID_CONNECT_TECH,
3614 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3615 pbn_b1_4_921600 },
3616 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3617 PCI_SUBVENDOR_ID_CONNECT_TECH,
3618 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3619 pbn_b1_2_921600 },
3620 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3621 PCI_SUBVENDOR_ID_CONNECT_TECH,
3622 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3623 pbn_b1_8_921600 },
3624 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3625 PCI_SUBVENDOR_ID_CONNECT_TECH,
3626 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3627 pbn_b1_8_921600 },
3628 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3629 PCI_SUBVENDOR_ID_CONNECT_TECH,
3630 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3631 pbn_b1_4_921600 },
26e92861
GH		 3632 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3633 PCI_SUBVENDOR_ID_CONNECT_TECH,
3634 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3635 pbn_b1_2_1250000 },
3636 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3637 PCI_SUBVENDOR_ID_CONNECT_TECH,
3638 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3639 pbn_b0_2_1843200 },
3640 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3641 PCI_SUBVENDOR_ID_CONNECT_TECH,
3642 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3643 pbn_b0_4_1843200 },
85d1494e
YY		 3644 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3645 PCI_VENDOR_ID_AFAVLAB,
3646 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3647 pbn_b0_4_1152000 },
26e92861
GH		 3648 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3649 PCI_SUBVENDOR_ID_CONNECT_TECH,
3650 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3651 pbn_b0_2_1843200_200 },
3652 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3653 PCI_SUBVENDOR_ID_CONNECT_TECH,
3654 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3655 pbn_b0_4_1843200_200 },
3656 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3657 PCI_SUBVENDOR_ID_CONNECT_TECH,
3658 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3659 pbn_b0_8_1843200_200 },
3660 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3661 PCI_SUBVENDOR_ID_CONNECT_TECH,
3662 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3663 pbn_b0_2_1843200_200 },
3664 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3665 PCI_SUBVENDOR_ID_CONNECT_TECH,
3666 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3667 pbn_b0_4_1843200_200 },
3668 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3669 PCI_SUBVENDOR_ID_CONNECT_TECH,
3670 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3671 pbn_b0_8_1843200_200 },
3672 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3673 PCI_SUBVENDOR_ID_CONNECT_TECH,
3674 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3675 pbn_b0_2_1843200_200 },
3676 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3677 PCI_SUBVENDOR_ID_CONNECT_TECH,
3678 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3679 pbn_b0_4_1843200_200 },
3680 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3681 PCI_SUBVENDOR_ID_CONNECT_TECH,
3682 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3683 pbn_b0_8_1843200_200 },
3684 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3685 PCI_SUBVENDOR_ID_CONNECT_TECH,
3686 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3687 pbn_b0_2_1843200_200 },
3688 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3689 PCI_SUBVENDOR_ID_CONNECT_TECH,
3690 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3691 pbn_b0_4_1843200_200 },
3692 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3693 PCI_SUBVENDOR_ID_CONNECT_TECH,
3694 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3695 pbn_b0_8_1843200_200 },
c68d2b15
BH		 3696 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3697 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3698 0, 0, pbn_exar_ibm_saturn },
1da177e4
LT		 3699
3700 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 3701 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3702 pbn_b2_bt_1_115200 },
3703 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 3704 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3705 pbn_b2_bt_2_115200 },
3706 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 3707 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3708 pbn_b2_bt_4_115200 },
3709 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 3710 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3711 pbn_b2_bt_2_115200 },
3712 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 3713 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3714 pbn_b2_bt_4_115200 },
3715 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 3716 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 3717 pbn_b2_8_115200 },
e65f0f82
FL		 3718 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3719 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3720 pbn_b2_8_460800 },
1da177e4
LT		 3721 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3722 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3723 pbn_b2_8_115200 },
3724
3725 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3726 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3727 pbn_b2_bt_2_115200 },
3728 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3729 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3730 pbn_b2_bt_2_921600 },
3731 /*
3732 * VScom SPCOM800, from sl@s.pl
3733 */
5756ee99
AC		 3734 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3735 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3736 pbn_b2_8_921600 },
3737 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 3738 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 3739 pbn_b2_4_921600 },
b76c5a07
CB		 3740 /* Unknown card - subdevice 0x1584 */
3741 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3742 PCI_VENDOR_ID_PLX,
3743 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
d13402a4
SA		 3744 pbn_b2_4_115200 },
3745 /* Unknown card - subdevice 0x1588 */
3746 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3747 PCI_VENDOR_ID_PLX,
3748 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
3749 pbn_b2_8_115200 },
1da177e4
LT		 3750 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3751 PCI_SUBVENDOR_ID_KEYSPAN,
3752 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3753 pbn_panacom },
3754 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3755 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3756 pbn_panacom4 },
3757 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3758 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3759 pbn_panacom2 },
a9cccd34
MF		 3760 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3761 PCI_VENDOR_ID_ESDGMBH,
3762 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3763 pbn_b2_4_115200 },
1da177e4
LT		 3764 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3765 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3766 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 3767 pbn_b2_4_460800 },
3768 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3769 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3770 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 3771 pbn_b2_8_460800 },
3772 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3773 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3774 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 3775 pbn_b2_16_460800 },
3776 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3777 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3778 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 3779 pbn_b2_16_460800 },
3780 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3781 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 3782 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 3783 pbn_b2_4_460800 },
3784 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3785 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 3786 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 3787 pbn_b2_8_460800 },
add7b58e
BH		 3788 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3789 PCI_SUBVENDOR_ID_EXSYS,
3790 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
ee4cd1b2 3791 pbn_b2_4_115200 },
1da177e4
LT		 3792 /*
3793 * Megawolf Romulus PCI Serial Card, from Mike Hudson
3794 * (Exoray@isys.ca)
3795 */
3796 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3797 0x10b5, 0x106a, 0, 0,
3798 pbn_plx_romulus },
55c7c0fd
AC		 3799 /*
3800 * Quatech cards. These actually have configurable clocks but for
3801 * now we just use the default.
3802 *
3803 * 100 series are RS232, 200 series RS422,
3804 */
1da177e4
LT		 3805 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3806 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3807 pbn_b1_4_115200 },
3808 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3809 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3810 pbn_b1_2_115200 },
55c7c0fd
AC		 3811 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
3812 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3813 pbn_b2_2_115200 },
3814 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
3815 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3816 pbn_b1_2_115200 },
3817 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
3818 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3819 pbn_b2_2_115200 },
3820 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
3821 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3822 pbn_b1_4_115200 },
1da177e4
LT		 3823 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3824 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3825 pbn_b1_8_115200 },
3826 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3827 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3828 pbn_b1_8_115200 },
55c7c0fd
AC		 3829 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
3830 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3831 pbn_b1_4_115200 },
3832 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
3833 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3834 pbn_b1_2_115200 },
3835 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
3836 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3837 pbn_b1_4_115200 },
3838 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
3839 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3840 pbn_b1_2_115200 },
3841 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
3842 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3843 pbn_b2_4_115200 },
3844 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
3845 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3846 pbn_b2_2_115200 },
3847 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
3848 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3849 pbn_b2_1_115200 },
3850 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
3851 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3852 pbn_b2_4_115200 },
3853 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
3854 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3855 pbn_b2_2_115200 },
3856 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
3857 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3858 pbn_b2_1_115200 },
3859 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
3860 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3861 pbn_b0_8_115200 },
3862
1da177e4 3863 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 3864 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3865 0, 0,
1da177e4 3866 pbn_b0_4_921600 },
fbc0dc0d 3867 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 3868 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3869 0, 0,
fbc0dc0d 3870 pbn_b0_4_1152000 },
c9bd9d01
MP		 3871 { PCI_VENDOR_ID_OXSEMI, 0x9505,
3872 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3873 pbn_b0_bt_2_921600 },
db1de159
DR		 3874
3875 /*
3876 * The below card is a little controversial since it is the
3877 * subject of a PCI vendor/device ID clash. (See
3878 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3879 * For now just used the hex ID 0x950a.
3880 */
39aced68 3881 { PCI_VENDOR_ID_OXSEMI, 0x950a,
26e8220a
FL		 3882 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
3883 0, 0, pbn_b0_2_115200 },
3884 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3885 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
3886 0, 0, pbn_b0_2_115200 },
db1de159
DR		 3887 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3888 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3889 pbn_b0_2_1130000 },
70fd8fde
AP		 3890 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3891 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3892 pbn_b0_1_921600 },
1da177e4
LT		 3893 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3894 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3895 pbn_b0_4_115200 },
3896 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3897 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3898 pbn_b0_bt_2_921600 },
e847003f
LB		 3899 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3900 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3901 pbn_b2_8_1152000 },
1da177e4 3902
7106b4e3
LH		 3903 /*
3904 * Oxford Semiconductor Inc. Tornado PCI express device range.
3905 */
3906 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
3907 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3908 pbn_b0_1_4000000 },
3909 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
3910 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3911 pbn_b0_1_4000000 },
3912 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
3913 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3914 pbn_oxsemi_1_4000000 },
3915 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
3916 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3917 pbn_oxsemi_1_4000000 },
3918 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
3919 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3920 pbn_b0_1_4000000 },
3921 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
3922 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3923 pbn_b0_1_4000000 },
3924 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
3925 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3926 pbn_oxsemi_1_4000000 },
3927 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
3928 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3929 pbn_oxsemi_1_4000000 },
3930 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
3931 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3932 pbn_b0_1_4000000 },
3933 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
3934 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3935 pbn_b0_1_4000000 },
3936 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
3937 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3938 pbn_b0_1_4000000 },
3939 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
3940 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3941 pbn_b0_1_4000000 },
3942 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
3943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3944 pbn_oxsemi_2_4000000 },
3945 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
3946 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3947 pbn_oxsemi_2_4000000 },
3948 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
3949 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3950 pbn_oxsemi_4_4000000 },
3951 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
3952 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3953 pbn_oxsemi_4_4000000 },
3954 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
3955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3956 pbn_oxsemi_8_4000000 },
3957 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
3958 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3959 pbn_oxsemi_8_4000000 },
3960 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
3961 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3962 pbn_oxsemi_1_4000000 },
3963 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
3964 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3965 pbn_oxsemi_1_4000000 },
3966 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
3967 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3968 pbn_oxsemi_1_4000000 },
3969 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
3970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3971 pbn_oxsemi_1_4000000 },
3972 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
3973 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3974 pbn_oxsemi_1_4000000 },
3975 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
3976 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3977 pbn_oxsemi_1_4000000 },
3978 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3979 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3980 pbn_oxsemi_1_4000000 },
3981 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3982 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3983 pbn_oxsemi_1_4000000 },
3984 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3985 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3986 pbn_oxsemi_1_4000000 },
3987 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3989 pbn_oxsemi_1_4000000 },
3990 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3991 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3992 pbn_oxsemi_1_4000000 },
3993 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3994 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3995 pbn_oxsemi_1_4000000 },
3996 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3997 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3998 pbn_oxsemi_1_4000000 },
3999 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4000 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4001 pbn_oxsemi_1_4000000 },
4002 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4003 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4004 pbn_oxsemi_1_4000000 },
4005 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4006 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4007 pbn_oxsemi_1_4000000 },
4008 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4009 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4010 pbn_oxsemi_1_4000000 },
4011 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4012 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4013 pbn_oxsemi_1_4000000 },
4014 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4015 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4016 pbn_oxsemi_1_4000000 },
4017 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4018 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4019 pbn_oxsemi_1_4000000 },
4020 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4021 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4022 pbn_oxsemi_1_4000000 },
4023 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4024 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4025 pbn_oxsemi_1_4000000 },
4026 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4027 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4028 pbn_oxsemi_1_4000000 },
4029 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4030 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4031 pbn_oxsemi_1_4000000 },
4032 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4033 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4034 pbn_oxsemi_1_4000000 },
4035 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4036 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4037 pbn_oxsemi_1_4000000 },
b80de369
LH		 4038 /*
4039 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4040 */
4041 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4042 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4043 pbn_oxsemi_1_4000000 },
4044 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4045 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4046 pbn_oxsemi_2_4000000 },
4047 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4048 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4049 pbn_oxsemi_4_4000000 },
4050 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4051 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4052 pbn_oxsemi_8_4000000 },
aa273ae5
SK		 4053
4054 /*
4055 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4056 */
4057 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4058 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4059 pbn_oxsemi_2_4000000 },
4060
1da177e4
LT		 4061 /*
4062 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4063 * from skokodyn@yahoo.com
4064 */
4065 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4066 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4067 pbn_sbsxrsio },
4068 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4069 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4070 pbn_sbsxrsio },
4071 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4072 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4073 pbn_sbsxrsio },
4074 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4075 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4076 pbn_sbsxrsio },
4077
4078 /*
4079 * Digitan DS560-558, from jimd@esoft.com
4080 */
4081 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 4082 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4083 pbn_b1_1_115200 },
4084
4085 /*
4086 * Titan Electronic cards
4087 * The 400L and 800L have a custom setup quirk.
4088 */
4089 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 4090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4091 pbn_b0_1_921600 },
4092 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 4093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4094 pbn_b0_2_921600 },
4095 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 4096 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4097 pbn_b0_4_921600 },
4098 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 4099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4100 pbn_b0_4_921600 },
4101 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4102 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4103 pbn_b1_1_921600 },
4104 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4106 pbn_b1_bt_2_921600 },
4107 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4108 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4109 pbn_b0_bt_4_921600 },
4110 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4112 pbn_b0_bt_8_921600 },
66169ad1
YY		 4113 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4114 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4115 pbn_b4_bt_2_921600 },
4116 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4117 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4118 pbn_b4_bt_4_921600 },
4119 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4120 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4121 pbn_b4_bt_8_921600 },
4122 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4123 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4124 pbn_b0_4_921600 },
4125 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4126 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4127 pbn_b0_4_921600 },
4128 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4129 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4130 pbn_b0_4_921600 },
4131 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4133 pbn_oxsemi_1_4000000 },
4134 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4136 pbn_oxsemi_2_4000000 },
4137 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4139 pbn_oxsemi_4_4000000 },
4140 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4142 pbn_oxsemi_8_4000000 },
4143 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4145 pbn_oxsemi_2_4000000 },
4146 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4148 pbn_oxsemi_2_4000000 },
1459439f
YY		 4149 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4150 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4151 pbn_b0_bt_2_921600 },
1e9deb11
YY		 4152 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4154 pbn_b0_4_921600 },
4155 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4156 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4157 pbn_b0_4_921600 },
4158 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4159 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4160 pbn_b0_4_921600 },
4161 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4162 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4163 pbn_b0_4_921600 },
1da177e4
LT		 4164
4165 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4166 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4167 pbn_b2_1_460800 },
4168 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4170 pbn_b2_1_460800 },
4171 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4172 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4173 pbn_b2_1_460800 },
4174 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4175 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4176 pbn_b2_bt_2_921600 },
4177 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4178 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4179 pbn_b2_bt_2_921600 },
4180 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4181 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4182 pbn_b2_bt_2_921600 },
4183 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4184 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4185 pbn_b2_bt_4_921600 },
4186 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4187 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4188 pbn_b2_bt_4_921600 },
4189 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4190 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4191 pbn_b2_bt_4_921600 },
4192 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4193 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4194 pbn_b0_1_921600 },
4195 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4196 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4197 pbn_b0_1_921600 },
4198 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4199 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4200 pbn_b0_1_921600 },
4201 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4202 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4203 pbn_b0_bt_2_921600 },
4204 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4205 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4206 pbn_b0_bt_2_921600 },
4207 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4208 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4209 pbn_b0_bt_2_921600 },
4210 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4211 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4212 pbn_b0_bt_4_921600 },
4213 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4214 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4215 pbn_b0_bt_4_921600 },
4216 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4218 pbn_b0_bt_4_921600 },
3ec9c594
AP		 4219 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4220 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4221 pbn_b0_bt_8_921600 },
4222 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4223 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4224 pbn_b0_bt_8_921600 },
4225 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4226 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4227 pbn_b0_bt_8_921600 },
1da177e4
LT		 4228
4229 /*
4230 * Computone devices submitted by Doug McNash dmcnash@computone.com
4231 */
4232 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4233 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4234 0, 0, pbn_computone_4 },
4235 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4236 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4237 0, 0, pbn_computone_8 },
4238 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4239 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4240 0, 0, pbn_computone_6 },
4241
4242 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4243 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4244 pbn_oxsemi },
4245 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4246 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4247 pbn_b0_bt_1_921600 },
4248
abd7baca
SC		 4249 /*
4250 * SUNIX (TIMEDIA)
4251 */
4252 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4253 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4254 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4255 pbn_b0_bt_1_921600 },
4256
4257 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4258 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4259 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4260 pbn_b0_bt_1_921600 },
4261
1da177e4
LT		 4262 /*
4263 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4264 */
4265 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4266 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4267 pbn_b0_bt_8_115200 },
4268 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4270 pbn_b0_bt_8_115200 },
4271
4272 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4273 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4274 pbn_b0_bt_2_115200 },
4275 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4276 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4277 pbn_b0_bt_2_115200 },
4278 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4279 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4280 pbn_b0_bt_2_115200 },
b87e5e2b
LB		 4281 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4282 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4283 pbn_b0_bt_2_115200 },
4284 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4285 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4286 pbn_b0_bt_2_115200 },
1da177e4
LT		 4287 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4288 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4289 pbn_b0_bt_4_460800 },
4290 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4291 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4292 pbn_b0_bt_4_460800 },
4293 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4294 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4295 pbn_b0_bt_2_460800 },
4296 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4297 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4298 pbn_b0_bt_2_460800 },
4299 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4300 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4301 pbn_b0_bt_2_460800 },
4302 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4303 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4304 pbn_b0_bt_1_115200 },
4305 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4306 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4307 pbn_b0_bt_1_460800 },
4308
1fb8cacc
RK		 4309 /*
4310 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4311 * Cards are identified by their subsystem vendor IDs, which
4312 * (in hex) match the model number.
4313 *
4314 * Note that JC140x are RS422/485 cards which require ox950
4315 * ACR = 0x10, and as such are not currently fully supported.
4316 */
4317 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4318 0x1204, 0x0004, 0, 0,
4319 pbn_b0_4_921600 },
4320 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4321 0x1208, 0x0004, 0, 0,
4322 pbn_b0_4_921600 },
4323/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4324 0x1402, 0x0002, 0, 0,
4325 pbn_b0_2_921600 }, */
4326/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4327 0x1404, 0x0004, 0, 0,
4328 pbn_b0_4_921600 }, */
4329 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4330 0x1208, 0x0004, 0, 0,
4331 pbn_b0_4_921600 },
4332
2a52fcb5
KY		 4333 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4334 0x1204, 0x0004, 0, 0,
4335 pbn_b0_4_921600 },
4336 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4337 0x1208, 0x0004, 0, 0,
4338 pbn_b0_4_921600 },
4339 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4340 0x1208, 0x0004, 0, 0,
4341 pbn_b0_4_921600 },
1da177e4
LT		 4342 /*
4343 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4344 */
4345 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4346 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4347 pbn_b1_1_1382400 },
4348
4349 /*
4350 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4351 */
4352 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4353 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4354 pbn_b1_1_1382400 },
4355
4356 /*
4357 * RAStel 2 port modem, gerg@moreton.com.au
4358 */
4359 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4360 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4361 pbn_b2_bt_2_115200 },
4362
4363 /*
4364 * EKF addition for i960 Boards form EKF with serial port
4365 */
4366 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4367 0xE4BF, PCI_ANY_ID, 0, 0,
4368 pbn_intel_i960 },
4369
4370 /*
4371 * Xircom Cardbus/Ethernet combos
4372 */
4373 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4374 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4375 pbn_b0_1_115200 },
4376 /*
4377 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4378 */
4379 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4380 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4381 pbn_b0_1_115200 },
4382
4383 /*
4384 * Untested PCI modems, sent in from various folks...
4385 */
4386
4387 /*
4388 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4389 */
4390 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4391 0x1048, 0x1500, 0, 0,
4392 pbn_b1_1_115200 },
4393
4394 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4395 0xFF00, 0, 0, 0,
4396 pbn_sgi_ioc3 },
4397
4398 /*
4399 * HP Diva card
4400 */
4401 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4402 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4403 pbn_b1_1_115200 },
4404 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4405 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4406 pbn_b0_5_115200 },
4407 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4408 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4409 pbn_b2_1_115200 },
4410
d9004eb4
ABL		 4411 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4412 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4413 pbn_b3_2_115200 },
1da177e4
LT		 4414 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4415 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4416 pbn_b3_4_115200 },
4417 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4418 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4419 pbn_b3_8_115200 },
4420
4421 /*
4422 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4423 */
4424 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4425 PCI_ANY_ID, PCI_ANY_ID,
4426 0,
4427 0, pbn_exar_XR17C152 },
4428 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4429 PCI_ANY_ID, PCI_ANY_ID,
4430 0,
4431 0, pbn_exar_XR17C154 },
4432 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4433 PCI_ANY_ID, PCI_ANY_ID,
4434 0,
4435 0, pbn_exar_XR17C158 },
dc96efb7
MS		 4436 /*
4437 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
4438 */
4439 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4440 PCI_ANY_ID, PCI_ANY_ID,
4441 0,
4442 0, pbn_exar_XR17V352 },
4443 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4444 PCI_ANY_ID, PCI_ANY_ID,
4445 0,
4446 0, pbn_exar_XR17V354 },
4447 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4448 PCI_ANY_ID, PCI_ANY_ID,
4449 0,
4450 0, pbn_exar_XR17V358 },
1da177e4
LT		 4451
4452 /*
4453 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4454 */
4455 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4457 pbn_b0_1_115200 },
84f8c6fc
NV		 4458 /*
4459 * ITE
4460 */
4461 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4462 PCI_ANY_ID, PCI_ANY_ID,
4463 0, 0,
4464 pbn_b1_bt_1_115200 },
1da177e4 4465
737c1756
PH		 4466 /*
4467 * IntaShield IS-200
4468 */
4469 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4470 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4471 pbn_b2_2_115200 },
4b6f6ce9
IGP		 4472 /*
4473 * IntaShield IS-400
4474 */
4475 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4476 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4477 pbn_b2_4_115200 },
48212008
TH		 4478 /*
4479 * Perle PCI-RAS cards
4480 */
4481 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4482 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4483 0, 0, pbn_b2_4_921600 },
4484 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4485 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4486 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 4487
4488 /*
4489 * Mainpine series cards: Fairly standard layout but fools
4490 * parts of the autodetect in some cases and uses otherwise
4491 * unmatched communications subclasses in the PCI Express case
4492 */
4493
4494 { /* RockForceDUO */
4495 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4496 PCI_VENDOR_ID_MAINPINE, 0x0200,
4497 0, 0, pbn_b0_2_115200 },
4498 { /* RockForceQUATRO */
4499 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4500 PCI_VENDOR_ID_MAINPINE, 0x0300,
4501 0, 0, pbn_b0_4_115200 },
4502 { /* RockForceDUO+ */
4503 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4504 PCI_VENDOR_ID_MAINPINE, 0x0400,
4505 0, 0, pbn_b0_2_115200 },
4506 { /* RockForceQUATRO+ */
4507 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4508 PCI_VENDOR_ID_MAINPINE, 0x0500,
4509 0, 0, pbn_b0_4_115200 },
4510 { /* RockForce+ */
4511 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4512 PCI_VENDOR_ID_MAINPINE, 0x0600,
4513 0, 0, pbn_b0_2_115200 },
4514 { /* RockForce+ */
4515 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4516 PCI_VENDOR_ID_MAINPINE, 0x0700,
4517 0, 0, pbn_b0_4_115200 },
4518 { /* RockForceOCTO+ */
4519 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4520 PCI_VENDOR_ID_MAINPINE, 0x0800,
4521 0, 0, pbn_b0_8_115200 },
4522 { /* RockForceDUO+ */
4523 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4524 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4525 0, 0, pbn_b0_2_115200 },
4526 { /* RockForceQUARTRO+ */
4527 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4528 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4529 0, 0, pbn_b0_4_115200 },
4530 { /* RockForceOCTO+ */
4531 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4532 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4533 0, 0, pbn_b0_8_115200 },
4534 { /* RockForceD1 */
4535 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4536 PCI_VENDOR_ID_MAINPINE, 0x2000,
4537 0, 0, pbn_b0_1_115200 },
4538 { /* RockForceF1 */
4539 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4540 PCI_VENDOR_ID_MAINPINE, 0x2100,
4541 0, 0, pbn_b0_1_115200 },
4542 { /* RockForceD2 */
4543 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4544 PCI_VENDOR_ID_MAINPINE, 0x2200,
4545 0, 0, pbn_b0_2_115200 },
4546 { /* RockForceF2 */
4547 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4548 PCI_VENDOR_ID_MAINPINE, 0x2300,
4549 0, 0, pbn_b0_2_115200 },
4550 { /* RockForceD4 */
4551 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4552 PCI_VENDOR_ID_MAINPINE, 0x2400,
4553 0, 0, pbn_b0_4_115200 },
4554 { /* RockForceF4 */
4555 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4556 PCI_VENDOR_ID_MAINPINE, 0x2500,
4557 0, 0, pbn_b0_4_115200 },
4558 { /* RockForceD8 */
4559 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4560 PCI_VENDOR_ID_MAINPINE, 0x2600,
4561 0, 0, pbn_b0_8_115200 },
4562 { /* RockForceF8 */
4563 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4564 PCI_VENDOR_ID_MAINPINE, 0x2700,
4565 0, 0, pbn_b0_8_115200 },
4566 { /* IQ Express D1 */
4567 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4568 PCI_VENDOR_ID_MAINPINE, 0x3000,
4569 0, 0, pbn_b0_1_115200 },
4570 { /* IQ Express F1 */
4571 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4572 PCI_VENDOR_ID_MAINPINE, 0x3100,
4573 0, 0, pbn_b0_1_115200 },
4574 { /* IQ Express D2 */
4575 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4576 PCI_VENDOR_ID_MAINPINE, 0x3200,
4577 0, 0, pbn_b0_2_115200 },
4578 { /* IQ Express F2 */
4579 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4580 PCI_VENDOR_ID_MAINPINE, 0x3300,
4581 0, 0, pbn_b0_2_115200 },
4582 { /* IQ Express D4 */
4583 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4584 PCI_VENDOR_ID_MAINPINE, 0x3400,
4585 0, 0, pbn_b0_4_115200 },
4586 { /* IQ Express F4 */
4587 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4588 PCI_VENDOR_ID_MAINPINE, 0x3500,
4589 0, 0, pbn_b0_4_115200 },
4590 { /* IQ Express D8 */
4591 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4592 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4593 0, 0, pbn_b0_8_115200 },
4594 { /* IQ Express F8 */
4595 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4596 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4597 0, 0, pbn_b0_8_115200 },
4598
4599
aa798505
OJ		 4600 /*
4601 * PA Semi PA6T-1682M on-chip UART
4602 */
4603 { PCI_VENDOR_ID_PASEMI, 0xa004,
4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 pbn_pasemi_1682M },
4606
46a0fac9
SB		 4607 /*
4608 * National Instruments
4609 */
04bf7e74
WP		 4610 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4611 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4612 pbn_b1_16_115200 },
4613 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4614 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4615 pbn_b1_8_115200 },
4616 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4617 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4618 pbn_b1_bt_4_115200 },
4619 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4620 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4621 pbn_b1_bt_2_115200 },
4622 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4623 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4624 pbn_b1_bt_4_115200 },
4625 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4626 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4627 pbn_b1_bt_2_115200 },
4628 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4629 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4630 pbn_b1_16_115200 },
4631 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4632 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4633 pbn_b1_8_115200 },
4634 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4635 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4636 pbn_b1_bt_4_115200 },
4637 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4639 pbn_b1_bt_2_115200 },
4640 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4641 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4642 pbn_b1_bt_4_115200 },
4643 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4644 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4645 pbn_b1_bt_2_115200 },
46a0fac9
SB		 4646 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4647 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4648 pbn_ni8430_2 },
4649 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4650 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4651 pbn_ni8430_2 },
4652 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4653 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4654 pbn_ni8430_4 },
4655 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4656 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4657 pbn_ni8430_4 },
4658 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4659 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4660 pbn_ni8430_8 },
4661 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4662 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4663 pbn_ni8430_8 },
4664 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4665 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4666 pbn_ni8430_16 },
4667 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4668 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4669 pbn_ni8430_16 },
4670 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4672 pbn_ni8430_2 },
4673 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
4674 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4675 pbn_ni8430_2 },
4676 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4677 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4678 pbn_ni8430_4 },
4679 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4680 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4681 pbn_ni8430_4 },
4682
02c9b5cf
KJ		 4683 /*
4684 * ADDI-DATA GmbH communication cards <info@addi-data.com>
4685 */
4686 { PCI_VENDOR_ID_ADDIDATA,
4687 PCI_DEVICE_ID_ADDIDATA_APCI7500,
4688 PCI_ANY_ID,
4689 PCI_ANY_ID,
4690 0,
4691 0,
4692 pbn_b0_4_115200 },
4693
4694 { PCI_VENDOR_ID_ADDIDATA,
4695 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4696 PCI_ANY_ID,
4697 PCI_ANY_ID,
4698 0,
4699 0,
4700 pbn_b0_2_115200 },
4701
4702 { PCI_VENDOR_ID_ADDIDATA,
4703 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4704 PCI_ANY_ID,
4705 PCI_ANY_ID,
4706 0,
4707 0,
4708 pbn_b0_1_115200 },
4709
4710 { PCI_VENDOR_ID_ADDIDATA_OLD,
4711 PCI_DEVICE_ID_ADDIDATA_APCI7800,
4712 PCI_ANY_ID,
4713 PCI_ANY_ID,
4714 0,
4715 0,
4716 pbn_b1_8_115200 },
4717
4718 { PCI_VENDOR_ID_ADDIDATA,
4719 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4720 PCI_ANY_ID,
4721 PCI_ANY_ID,
4722 0,
4723 0,
4724 pbn_b0_4_115200 },
4725
4726 { PCI_VENDOR_ID_ADDIDATA,
4727 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4728 PCI_ANY_ID,
4729 PCI_ANY_ID,
4730 0,
4731 0,
4732 pbn_b0_2_115200 },
4733
4734 { PCI_VENDOR_ID_ADDIDATA,
4735 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4736 PCI_ANY_ID,
4737 PCI_ANY_ID,
4738 0,
4739 0,
4740 pbn_b0_1_115200 },
4741
4742 { PCI_VENDOR_ID_ADDIDATA,
4743 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4744 PCI_ANY_ID,
4745 PCI_ANY_ID,
4746 0,
4747 0,
4748 pbn_b0_4_115200 },
4749
4750 { PCI_VENDOR_ID_ADDIDATA,
4751 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4752 PCI_ANY_ID,
4753 PCI_ANY_ID,
4754 0,
4755 0,
4756 pbn_b0_2_115200 },
4757
4758 { PCI_VENDOR_ID_ADDIDATA,
4759 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4760 PCI_ANY_ID,
4761 PCI_ANY_ID,
4762 0,
4763 0,
4764 pbn_b0_1_115200 },
4765
4766 { PCI_VENDOR_ID_ADDIDATA,
4767 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4768 PCI_ANY_ID,
4769 PCI_ANY_ID,
4770 0,
4771 0,
4772 pbn_b0_8_115200 },
4773
1b62cbf2
KJ		 4774 { PCI_VENDOR_ID_ADDIDATA,
4775 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4776 PCI_ANY_ID,
4777 PCI_ANY_ID,
4778 0,
4779 0,
4780 pbn_ADDIDATA_PCIe_4_3906250 },
4781
4782 { PCI_VENDOR_ID_ADDIDATA,
4783 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4784 PCI_ANY_ID,
4785 PCI_ANY_ID,
4786 0,
4787 0,
4788 pbn_ADDIDATA_PCIe_2_3906250 },
4789
4790 { PCI_VENDOR_ID_ADDIDATA,
4791 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4792 PCI_ANY_ID,
4793 PCI_ANY_ID,
4794 0,
4795 0,
4796 pbn_ADDIDATA_PCIe_1_3906250 },
4797
4798 { PCI_VENDOR_ID_ADDIDATA,
4799 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4800 PCI_ANY_ID,
4801 PCI_ANY_ID,
4802 0,
4803 0,
4804 pbn_ADDIDATA_PCIe_8_3906250 },
4805
25cf9bc1
JS		 4806 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4807 PCI_VENDOR_ID_IBM, 0x0299,
4808 0, 0, pbn_b0_bt_2_115200 },
4809
c4285b47
MB		 4810 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4811 0xA000, 0x1000,
4812 0, 0, pbn_b0_1_115200 },
4813
7808edcd
NG		 4814 /* the 9901 is a rebranded 9912 */
4815 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4816 0xA000, 0x1000,
4817 0, 0, pbn_b0_1_115200 },
4818
4819 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4820 0xA000, 0x1000,
4821 0, 0, pbn_b0_1_115200 },
4822
4823 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4824 0xA000, 0x1000,
4825 0, 0, pbn_b0_1_115200 },
4826
4827 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4828 0xA000, 0x1000,
4829 0, 0, pbn_b0_1_115200 },
4830
4831 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4832 0xA000, 0x3002,
4833 0, 0, pbn_NETMOS9900_2s_115200 },
4834
ac6ec5b1 4835 /*
44178176 4836 * Best Connectivity and Rosewill PCI Multi I/O cards
ac6ec5b1
IS		 4837 */
4838
4839 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4840 0xA000, 0x1000,
4841 0, 0, pbn_b0_1_115200 },
4842
44178176
ES		 4843 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4844 0xA000, 0x3002,
4845 0, 0, pbn_b0_bt_2_115200 },
4846
ac6ec5b1
IS		 4847 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4848 0xA000, 0x3004,
4849 0, 0, pbn_b0_bt_4_115200 },
095e24b0
DB		 4850 /* Intel CE4100 */
4851 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4852 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4853 pbn_ce4100_1_115200 },
4854
d9a0fbfd
AP		 4855 /*
4856 * Cronyx Omega PCI
4857 */
4858 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4859 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4860 pbn_omegapci },
ac6ec5b1 4861
ebebd49a
SH		 4862 /*
4863 * Broadcom TruManage
4864 */
4865 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
4866 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4867 pbn_brcm_trumanage },
4868
6683549e
AC		 4869 /*
4870 * AgeStar as-prs2-009
4871 */
4872 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
4873 PCI_ANY_ID, PCI_ANY_ID,
4874 0, 0, pbn_b0_bt_2_115200 },
27788c5f
AC		 4875
4876 /*
4877 * WCH CH353 series devices: The 2S1P is handled by parport_serial
4878 * so not listed here.
4879 */
4880 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
4881 PCI_ANY_ID, PCI_ANY_ID,
4882 0, 0, pbn_b0_bt_4_115200 },
4883
4884 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
4885 PCI_ANY_ID, PCI_ANY_ID,
4886 0, 0, pbn_b0_bt_2_115200 },
4887
8b5c913f
WY		 4888 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S,
4889 PCI_ANY_ID, PCI_ANY_ID,
4890 0, 0, pbn_b0_bt_2_115200 },
4891
14faa8cc
MS		 4892 /*
4893 * Commtech, Inc. Fastcom adapters
4894 */
4895 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
4896 PCI_ANY_ID, PCI_ANY_ID,
4897 0,
4898 0, pbn_b0_2_1152000_200 },
4899 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
4900 PCI_ANY_ID, PCI_ANY_ID,
4901 0,
4902 0, pbn_b0_4_1152000_200 },
4903 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
4904 PCI_ANY_ID, PCI_ANY_ID,
4905 0,
4906 0, pbn_b0_4_1152000_200 },
4907 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
4908 PCI_ANY_ID, PCI_ANY_ID,
4909 0,
4910 0, pbn_b0_8_1152000_200 },
4911 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
4912 PCI_ANY_ID, PCI_ANY_ID,
4913 0,
4914 0, pbn_exar_XR17V352 },
4915 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
4916 PCI_ANY_ID, PCI_ANY_ID,
4917 0,
4918 0, pbn_exar_XR17V354 },
4919 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
4920 PCI_ANY_ID, PCI_ANY_ID,
4921 0,
4922 0, pbn_exar_XR17V358 },
4923
1da177e4
LT		 4924 /*
4925 * These entries match devices with class COMMUNICATION_SERIAL,
4926 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4927 */
4928 { PCI_ANY_ID, PCI_ANY_ID,
4929 PCI_ANY_ID, PCI_ANY_ID,
4930 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4931 0xffff00, pbn_default },
4932 { PCI_ANY_ID, PCI_ANY_ID,
4933 PCI_ANY_ID, PCI_ANY_ID,
4934 PCI_CLASS_COMMUNICATION_MODEM << 8,
4935 0xffff00, pbn_default },
4936 { PCI_ANY_ID, PCI_ANY_ID,
4937 PCI_ANY_ID, PCI_ANY_ID,
4938 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4939 0xffff00, pbn_default },
4940 { 0, }
4941};
4942
2807190b
MR		 4943static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4944 pci_channel_state_t state)
4945{
4946 struct serial_private *priv = pci_get_drvdata(dev);
4947
4948 if (state == pci_channel_io_perm_failure)
4949 return PCI_ERS_RESULT_DISCONNECT;
4950
4951 if (priv)
1d662dc0 4952 pciserial_detach_ports(priv);
2807190b
MR		 4953
4954 pci_disable_device(dev);
4955
4956 return PCI_ERS_RESULT_NEED_RESET;
4957}
4958
4959static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4960{
4961 int rc;
4962
4963 rc = pci_enable_device(dev);
4964
4965 if (rc)
4966 return PCI_ERS_RESULT_DISCONNECT;
4967
4968 pci_restore_state(dev);
4969 pci_save_state(dev);
4970
4971 return PCI_ERS_RESULT_RECOVERED;
4972}
4973
4974static void serial8250_io_resume(struct pci_dev *dev)
4975{
4976 struct serial_private *priv = pci_get_drvdata(dev);
1d662dc0 4977 const struct pciserial_board *board;
2807190b 4978
1d662dc0
GKB		 4979 if (!priv)
4980 return;
4981
4982 board = priv->board;
4983 kfree(priv);
4984 priv = pciserial_init_ports(dev, board);
4985
4986 if (!IS_ERR(priv)) {
4987 pci_set_drvdata(dev, priv);
4988 }
2807190b
MR		 4989}
4990
1d352035 4991static const struct pci_error_handlers serial8250_err_handler = {
2807190b
MR		 4992 .error_detected = serial8250_io_error_detected,
4993 .slot_reset = serial8250_io_slot_reset,
4994 .resume = serial8250_io_resume,
4995};
4996
1da177e4
LT		 4997static struct pci_driver serial_pci_driver = {
4998 .name = "serial",
4999 .probe = pciserial_init_one,
2d47b716 5000 .remove = pciserial_remove_one,
1d5e7996 5001#ifdef CONFIG_PM
1da177e4
LT		 5002 .suspend = pciserial_suspend_one,
5003 .resume = pciserial_resume_one,
1d5e7996 5004#endif
1da177e4 5005 .id_table = serial_pci_tbl,
2807190b 5006 .err_handler = &serial8250_err_handler,
1da177e4
LT		 5007};
5008
15a12e83 5009module_pci_driver(serial_pci_driver);
1da177e4
LT		 5010
5011MODULE_LICENSE("GPL");
5012MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5013MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
kernel source for telekom puls (alcatel/mediatek)