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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / serial / 8250_pci.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
15 */
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/pci.h>
1da177e4
LT		 19#include <linux/string.h>
20#include <linux/kernel.h>
21#include <linux/slab.h>
22#include <linux/delay.h>
23#include <linux/tty.h>
24#include <linux/serial_core.h>
25#include <linux/8250_pci.h>
26#include <linux/bitops.h>
27
28#include <asm/byteorder.h>
29#include <asm/io.h>
30
31#include "8250.h"
32
33#undef SERIAL_DEBUG_PCI
34
1da177e4
LT		 35/*
36 * init function returns:
37 * > 0 - number of ports
38 * = 0 - use board->num_ports
39 * < 0 - error
40 */
41struct pci_serial_quirk {
42 u32 vendor;
43 u32 device;
44 u32 subvendor;
45 u32 subdevice;
46 int (*init)(struct pci_dev *dev);
70db3d91 47 int (*setup)(struct serial_private *, struct pciserial_board *,
05caac58 48 struct uart_port *, int);
1da177e4
LT		 49 void (*exit)(struct pci_dev *dev);
50};
51
52#define PCI_NUM_BAR_RESOURCES 6
53
54struct serial_private {
70db3d91 55 struct pci_dev *dev;
1da177e4
LT		 56 unsigned int nr;
57 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
58 struct pci_serial_quirk *quirk;
59 int line[0];
60};
61
62static void moan_device(const char *str, struct pci_dev *dev)
63{
64 printk(KERN_WARNING "%s: %s\n"
65 KERN_WARNING "Please send the output of lspci -vv, this\n"
66 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
67 KERN_WARNING "manufacturer and name of serial board or\n"
68 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
69 pci_name(dev), str, dev->vendor, dev->device,
70 dev->subsystem_vendor, dev->subsystem_device);
71}
72
73static int
70db3d91 74setup_port(struct serial_private *priv, struct uart_port *port,
1da177e4
LT		 75 int bar, int offset, int regshift)
76{
70db3d91 77 struct pci_dev *dev = priv->dev;
1da177e4
LT		 78 unsigned long base, len;
79
80 if (bar >= PCI_NUM_BAR_RESOURCES)
81 return -EINVAL;
82
72ce9a83
RK		 83 base = pci_resource_start(dev, bar);
84
1da177e4 85 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 86 len = pci_resource_len(dev, bar);
87
88 if (!priv->remapped_bar[bar])
89 priv->remapped_bar[bar] = ioremap(base, len);
90 if (!priv->remapped_bar[bar])
91 return -ENOMEM;
92
93 port->iotype = UPIO_MEM;
72ce9a83 94 port->iobase = 0;
1da177e4
LT		 95 port->mapbase = base + offset;
96 port->membase = priv->remapped_bar[bar] + offset;
97 port->regshift = regshift;
98 } else {
1da177e4 99 port->iotype = UPIO_PORT;
72ce9a83
RK		 100 port->iobase = base + offset;
101 port->mapbase = 0;
102 port->membase = NULL;
103 port->regshift = 0;
1da177e4
LT		 104 }
105 return 0;
106}
107
108/*
109 * AFAVLAB uses a different mixture of BARs and offsets
110 * Not that ugly ;) -- HW
111 */
112static int
70db3d91 113afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 114 struct uart_port *port, int idx)
115{
116 unsigned int bar, offset = board->first_offset;
117
118 bar = FL_GET_BASE(board->flags);
119 if (idx < 4)
120 bar += idx;
121 else {
122 bar = 4;
123 offset += (idx - 4) * board->uart_offset;
124 }
125
70db3d91 126 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 127}
128
129/*
130 * HP's Remote Management Console. The Diva chip came in several
131 * different versions. N-class, L2000 and A500 have two Diva chips, each
132 * with 3 UARTs (the third UART on the second chip is unused). Superdome
133 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
134 * one Diva chip, but it has been expanded to 5 UARTs.
135 */
61a116ef 136static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 137{
138 int rc = 0;
139
140 switch (dev->subsystem_device) {
141 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
142 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
143 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
144 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
145 rc = 3;
146 break;
147 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
148 rc = 2;
149 break;
150 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
151 rc = 4;
152 break;
153 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 154 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 155 rc = 1;
156 break;
157 }
158
159 return rc;
160}
161
162/*
163 * HP's Diva chip puts the 4th/5th serial port further out, and
164 * some serial ports are supposed to be hidden on certain models.
165 */
166static int
70db3d91 167pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 168 struct uart_port *port, int idx)
169{
170 unsigned int offset = board->first_offset;
171 unsigned int bar = FL_GET_BASE(board->flags);
172
70db3d91 173 switch (priv->dev->subsystem_device) {
1da177e4
LT		 174 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
175 if (idx == 3)
176 idx++;
177 break;
178 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
179 if (idx > 0)
180 idx++;
181 if (idx > 2)
182 idx++;
183 break;
184 }
185 if (idx > 2)
186 offset = 0x18;
187
188 offset += idx * board->uart_offset;
189
70db3d91 190 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 191}
192
193/*
194 * Added for EKF Intel i960 serial boards
195 */
61a116ef 196static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4
LT		 197{
198 unsigned long oldval;
199
200 if (!(dev->subsystem_device & 0x1000))
201 return -ENODEV;
202
203 /* is firmware started? */
204 pci_read_config_dword(dev, 0x44, (void*) &oldval);
205 if (oldval == 0x00001000L) { /* RESET value */
206 printk(KERN_DEBUG "Local i960 firmware missing");
207 return -ENODEV;
208 }
209 return 0;
210}
211
212/*
213 * Some PCI serial cards using the PLX 9050 PCI interface chip require
214 * that the card interrupt be explicitly enabled or disabled. This
215 * seems to be mainly needed on card using the PLX which also use I/O
216 * mapped memory.
217 */
61a116ef 218static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 219{
220 u8 irq_config;
221 void __iomem *p;
222
223 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
224 moan_device("no memory in bar 0", dev);
225 return 0;
226 }
227
228 irq_config = 0x41;
add7b58e
BH		 229 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
230 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) {
1da177e4 231 irq_config = 0x43;
add7b58e 232 }
1da177e4
LT		 233 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
234 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
235 /*
236 * As the megawolf cards have the int pins active
237 * high, and have 2 UART chips, both ints must be
238 * enabled on the 9050. Also, the UARTS are set in
239 * 16450 mode by default, so we have to enable the
240 * 16C950 'enhanced' mode so that we can use the
241 * deep FIFOs
242 */
243 irq_config = 0x5b;
244 }
245
246 /*
247 * enable/disable interrupts
248 */
249 p = ioremap(pci_resource_start(dev, 0), 0x80);
250 if (p == NULL)
251 return -ENOMEM;
252 writel(irq_config, p + 0x4c);
253
254 /*
255 * Read the register back to ensure that it took effect.
256 */
257 readl(p + 0x4c);
258 iounmap(p);
259
260 return 0;
261}
262
263static void __devexit pci_plx9050_exit(struct pci_dev *dev)
264{
265 u8 __iomem *p;
266
267 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
268 return;
269
270 /*
271 * disable interrupts
272 */
273 p = ioremap(pci_resource_start(dev, 0), 0x80);
274 if (p != NULL) {
275 writel(0, p + 0x4c);
276
277 /*
278 * Read the register back to ensure that it took effect.
279 */
280 readl(p + 0x4c);
281 iounmap(p);
282 }
283}
284
285/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
286static int
70db3d91 287sbs_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 288 struct uart_port *port, int idx)
289{
290 unsigned int bar, offset = board->first_offset;
291
292 bar = 0;
293
294 if (idx < 4) {
295 /* first four channels map to 0, 0x100, 0x200, 0x300 */
296 offset += idx * board->uart_offset;
297 } else if (idx < 8) {
298 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
299 offset += idx * board->uart_offset + 0xC00;
300 } else /* we have only 8 ports on PMC-OCTALPRO */
301 return 1;
302
70db3d91 303 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 304}
305
306/*
307* This does initialization for PMC OCTALPRO cards:
308* maps the device memory, resets the UARTs (needed, bc
309* if the module is removed and inserted again, the card
310* is in the sleep mode) and enables global interrupt.
311*/
312
313/* global control register offset for SBS PMC-OctalPro */
314#define OCT_REG_CR_OFF 0x500
315
61a116ef 316static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 317{
318 u8 __iomem *p;
319
320 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
321
322 if (p == NULL)
323 return -ENOMEM;
324 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
325 writeb(0x10,p + OCT_REG_CR_OFF);
326 udelay(50);
327 writeb(0x0,p + OCT_REG_CR_OFF);
328
329 /* Set bit-2 (INTENABLE) of Control Register */
330 writeb(0x4, p + OCT_REG_CR_OFF);
331 iounmap(p);
332
333 return 0;
334}
335
336/*
337 * Disables the global interrupt of PMC-OctalPro
338 */
339
340static void __devexit sbs_exit(struct pci_dev *dev)
341{
342 u8 __iomem *p;
343
344 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
345 if (p != NULL) {
346 writeb(0, p + OCT_REG_CR_OFF);
347 }
348 iounmap(p);
349}
350
351/*
352 * SIIG serial cards have an PCI interface chip which also controls
353 * the UART clocking frequency. Each UART can be clocked independently
354 * (except cards equiped with 4 UARTs) and initial clocking settings
355 * are stored in the EEPROM chip. It can cause problems because this
356 * version of serial driver doesn't support differently clocked UART's
357 * on single PCI card. To prevent this, initialization functions set
358 * high frequency clocking for all UART's on given card. It is safe (I
359 * hope) because it doesn't touch EEPROM settings to prevent conflicts
360 * with other OSes (like M$ DOS).
361 *
362 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
363 *
364 * There is two family of SIIG serial cards with different PCI
365 * interface chip and different configuration methods:
366 * - 10x cards have control registers in IO and/or memory space;
367 * - 20x cards have control registers in standard PCI configuration space.
368 *
67d74b87
RK		 369 * Note: all 10x cards have PCI device ids 0x10..
370 * all 20x cards have PCI device ids 0x20..
371 *
fbc0dc0d
AP		 372 * There are also Quartet Serial cards which use Oxford Semiconductor
373 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
374 *
1da177e4
LT		 375 * Note: some SIIG cards are probed by the parport_serial object.
376 */
377
378#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
379#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
380
381static int pci_siig10x_init(struct pci_dev *dev)
382{
383 u16 data;
384 void __iomem *p;
385
386 switch (dev->device & 0xfff8) {
387 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
388 data = 0xffdf;
389 break;
390 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
391 data = 0xf7ff;
392 break;
393 default: /* 1S1P, 4S */
394 data = 0xfffb;
395 break;
396 }
397
398 p = ioremap(pci_resource_start(dev, 0), 0x80);
399 if (p == NULL)
400 return -ENOMEM;
401
402 writew(readw(p + 0x28) & data, p + 0x28);
403 readw(p + 0x28);
404 iounmap(p);
405 return 0;
406}
407
408#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
409#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
410
411static int pci_siig20x_init(struct pci_dev *dev)
412{
413 u8 data;
414
415 /* Change clock frequency for the first UART. */
416 pci_read_config_byte(dev, 0x6f, &data);
417 pci_write_config_byte(dev, 0x6f, data & 0xef);
418
419 /* If this card has 2 UART, we have to do the same with second UART. */
420 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
421 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
422 pci_read_config_byte(dev, 0x73, &data);
423 pci_write_config_byte(dev, 0x73, data & 0xef);
424 }
425 return 0;
426}
427
67d74b87
RK		 428static int pci_siig_init(struct pci_dev *dev)
429{
430 unsigned int type = dev->device & 0xff00;
431
432 if (type == 0x1000)
433 return pci_siig10x_init(dev);
434 else if (type == 0x2000)
435 return pci_siig20x_init(dev);
436
437 moan_device("Unknown SIIG card", dev);
438 return -ENODEV;
439}
440
3ec9c594
AP		 441static int pci_siig_setup(struct serial_private *priv,
442 struct pciserial_board *board,
443 struct uart_port *port, int idx)
444{
445 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
446
447 if (idx > 3) {
448 bar = 4;
449 offset = (idx - 4) * 8;
450 }
451
452 return setup_port(priv, port, bar, offset, 0);
453}
454
1da177e4
LT		 455/*
456 * Timedia has an explosion of boards, and to avoid the PCI table from
457 * growing *huge*, we use this function to collapse some 70 entries
458 * in the PCI table into one, for sanity's and compactness's sake.
459 */
e9422e09 460static const unsigned short timedia_single_port[] = {
1da177e4
LT		 461 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
462};
463
e9422e09 464static const unsigned short timedia_dual_port[] = {
1da177e4
LT		 465 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
466 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
467 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
468 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
469 0xD079, 0
470};
471
e9422e09 472static const unsigned short timedia_quad_port[] = {
1da177e4
LT		 473 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
474 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
475 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
476 0xB157, 0
477};
478
e9422e09 479static const unsigned short timedia_eight_port[] = {
1da177e4
LT		 480 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
481 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
482};
483
cb3592be 484static const struct timedia_struct {
1da177e4 485 int num;
e9422e09 486 const unsigned short *ids;
1da177e4
LT		 487} timedia_data[] = {
488 { 1, timedia_single_port },
489 { 2, timedia_dual_port },
490 { 4, timedia_quad_port },
e9422e09 491 { 8, timedia_eight_port }
1da177e4
LT		 492};
493
61a116ef 494static int pci_timedia_init(struct pci_dev *dev)
1da177e4 495{
e9422e09 496 const unsigned short *ids;
1da177e4
LT		 497 int i, j;
498
e9422e09 499 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 500 ids = timedia_data[i].ids;
501 for (j = 0; ids[j]; j++)
502 if (dev->subsystem_device == ids[j])
503 return timedia_data[i].num;
504 }
505 return 0;
506}
507
508/*
509 * Timedia/SUNIX uses a mixture of BARs and offsets
510 * Ugh, this is ugly as all hell --- TYT
511 */
512static int
70db3d91 513pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 514 struct uart_port *port, int idx)
515{
516 unsigned int bar = 0, offset = board->first_offset;
517
518 switch (idx) {
519 case 0:
520 bar = 0;
521 break;
522 case 1:
523 offset = board->uart_offset;
524 bar = 0;
525 break;
526 case 2:
527 bar = 1;
528 break;
529 case 3:
530 offset = board->uart_offset;
c2cd6d3c 531 /* FALLTHROUGH */
1da177e4
LT		 532 case 4: /* BAR 2 */
533 case 5: /* BAR 3 */
534 case 6: /* BAR 4 */
535 case 7: /* BAR 5 */
536 bar = idx - 2;
537 }
538
70db3d91 539 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 540}
541
542/*
543 * Some Titan cards are also a little weird
544 */
545static int
70db3d91 546titan_400l_800l_setup(struct serial_private *priv,
1c7c1fe5 547 struct pciserial_board *board,
1da177e4
LT		 548 struct uart_port *port, int idx)
549{
550 unsigned int bar, offset = board->first_offset;
551
552 switch (idx) {
553 case 0:
554 bar = 1;
555 break;
556 case 1:
557 bar = 2;
558 break;
559 default:
560 bar = 4;
561 offset = (idx - 2) * board->uart_offset;
562 }
563
70db3d91 564 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 565}
566
61a116ef 567static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 568{
569 msleep(100);
570 return 0;
571}
572
61a116ef 573static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 574{
575 /* subdevice 0x00PS means <P> parallel, <S> serial */
576 unsigned int num_serial = dev->subsystem_device & 0xf;
577
578 if (num_serial == 0)
579 return -ENODEV;
580 return num_serial;
581}
582
84f8c6fc
NV		 583/*
584 * ITE support by Niels de Vos <niels.devos@wincor-nixdorf.com>
585 *
586 * These chips are available with optionally one parallel port and up to
587 * two serial ports. Unfortunately they all have the same product id.
588 *
589 * Basic configuration is done over a region of 32 I/O ports. The base
590 * ioport is called INTA or INTC, depending on docs/other drivers.
591 *
592 * The region of the 32 I/O ports is configured in POSIO0R...
593 */
594
595/* registers */
596#define ITE_887x_MISCR 0x9c
597#define ITE_887x_INTCBAR 0x78
598#define ITE_887x_UARTBAR 0x7c
599#define ITE_887x_PS0BAR 0x10
600#define ITE_887x_POSIO0 0x60
601
602/* I/O space size */
603#define ITE_887x_IOSIZE 32
604/* I/O space size (bits 26-24; 8 bytes = 011b) */
605#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
606/* I/O space size (bits 26-24; 32 bytes = 101b) */
607#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
608/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
609#define ITE_887x_POSIO_SPEED (3 << 29)
610/* enable IO_Space bit */
611#define ITE_887x_POSIO_ENABLE (1 << 31)
612
613static int __devinit pci_ite887x_init(struct pci_dev *dev)
614{
615 /* inta_addr are the configuration addresses of the ITE */
616 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
617 0x200, 0x280, 0 };
618 int ret, i, type;
619 struct resource *iobase = NULL;
620 u32 miscr, uartbar, ioport;
621
622 /* search for the base-ioport */
623 i = 0;
624 while (inta_addr[i] && iobase == NULL) {
625 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
626 "ite887x");
627 if (iobase != NULL) {
628 /* write POSIO0R - speed | size | ioport */
629 pci_write_config_dword(dev, ITE_887x_POSIO0,
630 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
631 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
632 /* write INTCBAR - ioport */
633 pci_write_config_dword(dev, ITE_887x_INTCBAR, inta_addr[i]);
634 ret = inb(inta_addr[i]);
635 if (ret != 0xff) {
636 /* ioport connected */
637 break;
638 }
639 release_region(iobase->start, ITE_887x_IOSIZE);
640 iobase = NULL;
641 }
642 i++;
643 }
644
645 if (!inta_addr[i]) {
646 printk(KERN_ERR "ite887x: could not find iobase\n");
647 return -ENODEV;
648 }
649
650 /* start of undocumented type checking (see parport_pc.c) */
651 type = inb(iobase->start + 0x18) & 0x0f;
652
653 switch (type) {
654 case 0x2: /* ITE8871 (1P) */
655 case 0xa: /* ITE8875 (1P) */
656 ret = 0;
657 break;
658 case 0xe: /* ITE8872 (2S1P) */
659 ret = 2;
660 break;
661 case 0x6: /* ITE8873 (1S) */
662 ret = 1;
663 break;
664 case 0x8: /* ITE8874 (2S) */
665 ret = 2;
666 break;
667 default:
668 moan_device("Unknown ITE887x", dev);
669 ret = -ENODEV;
670 }
671
672 /* configure all serial ports */
673 for (i = 0; i < ret; i++) {
674 /* read the I/O port from the device */
675 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
676 &ioport);
677 ioport &= 0x0000FF00; /* the actual base address */
678 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
679 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
680 ITE_887x_POSIO_IOSIZE_8 | ioport);
681
682 /* write the ioport to the UARTBAR */
683 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
684 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
685 uartbar |= (ioport << (16 * i)); /* set the ioport */
686 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
687
688 /* get current config */
689 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
690 /* disable interrupts (UARTx_Routing[3:0]) */
691 miscr &= ~(0xf << (12 - 4 * i));
692 /* activate the UART (UARTx_En) */
693 miscr |= 1 << (23 - i);
694 /* write new config with activated UART */
695 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
696 }
697
698 if (ret <= 0) {
699 /* the device has no UARTs if we get here */
700 release_region(iobase->start, ITE_887x_IOSIZE);
701 }
702
703 return ret;
704}
705
706static void __devexit pci_ite887x_exit(struct pci_dev *dev)
707{
708 u32 ioport;
709 /* the ioport is bit 0-15 in POSIO0R */
710 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
711 ioport &= 0xffff;
712 release_region(ioport, ITE_887x_IOSIZE);
713}
714
1da177e4 715static int
70db3d91 716pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 717 struct uart_port *port, int idx)
718{
719 unsigned int bar, offset = board->first_offset, maxnr;
720
721 bar = FL_GET_BASE(board->flags);
722 if (board->flags & FL_BASE_BARS)
723 bar += idx;
724 else
725 offset += idx * board->uart_offset;
726
2427ddd8
GKH		 727 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
728 (board->reg_shift + 3);
1da177e4
LT		 729
730 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
731 return 1;
732
70db3d91 733 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 734}
735
736/* This should be in linux/pci_ids.h */
737#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
738#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
739#define PCI_DEVICE_ID_OCTPRO 0x0001
740#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
741#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
742#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
743#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
744
745/*
746 * Master list of serial port init/setup/exit quirks.
747 * This does not describe the general nature of the port.
748 * (ie, baud base, number and location of ports, etc)
749 *
750 * This list is ordered alphabetically by vendor then device.
751 * Specific entries must come before more generic entries.
752 */
753static struct pci_serial_quirk pci_serial_quirks[] = {
754 /*
61a116ef 755 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 756 * It is not clear whether this applies to all products.
757 */
758 {
759 .vendor = PCI_VENDOR_ID_AFAVLAB,
760 .device = PCI_ANY_ID,
761 .subvendor = PCI_ANY_ID,
762 .subdevice = PCI_ANY_ID,
763 .setup = afavlab_setup,
764 },
765 /*
766 * HP Diva
767 */
768 {
769 .vendor = PCI_VENDOR_ID_HP,
770 .device = PCI_DEVICE_ID_HP_DIVA,
771 .subvendor = PCI_ANY_ID,
772 .subdevice = PCI_ANY_ID,
773 .init = pci_hp_diva_init,
774 .setup = pci_hp_diva_setup,
775 },
776 /*
777 * Intel
778 */
779 {
780 .vendor = PCI_VENDOR_ID_INTEL,
781 .device = PCI_DEVICE_ID_INTEL_80960_RP,
782 .subvendor = 0xe4bf,
783 .subdevice = PCI_ANY_ID,
784 .init = pci_inteli960ni_init,
785 .setup = pci_default_setup,
786 },
84f8c6fc
NV		 787 /*
788 * ITE
789 */
790 {
791 .vendor = PCI_VENDOR_ID_ITE,
792 .device = PCI_DEVICE_ID_ITE_8872,
793 .subvendor = PCI_ANY_ID,
794 .subdevice = PCI_ANY_ID,
795 .init = pci_ite887x_init,
796 .setup = pci_default_setup,
797 .exit = __devexit_p(pci_ite887x_exit),
798 },
1da177e4
LT		 799 /*
800 * Panacom
801 */
802 {
803 .vendor = PCI_VENDOR_ID_PANACOM,
804 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
805 .subvendor = PCI_ANY_ID,
806 .subdevice = PCI_ANY_ID,
807 .init = pci_plx9050_init,
808 .setup = pci_default_setup,
809 .exit = __devexit_p(pci_plx9050_exit),
810 },
811 {
812 .vendor = PCI_VENDOR_ID_PANACOM,
813 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
814 .subvendor = PCI_ANY_ID,
815 .subdevice = PCI_ANY_ID,
816 .init = pci_plx9050_init,
817 .setup = pci_default_setup,
818 .exit = __devexit_p(pci_plx9050_exit),
819 },
820 /*
821 * PLX
822 */
48212008
TH		 823 {
824 .vendor = PCI_VENDOR_ID_PLX,
825 .device = PCI_DEVICE_ID_PLX_9030,
826 .subvendor = PCI_SUBVENDOR_ID_PERLE,
827 .subdevice = PCI_ANY_ID,
828 .setup = pci_default_setup,
829 },
add7b58e
BH		 830 {
831 .vendor = PCI_VENDOR_ID_PLX,
832 .device = PCI_DEVICE_ID_PLX_9050,
833 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
834 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
835 .init = pci_plx9050_init,
836 .setup = pci_default_setup,
837 .exit = __devexit_p(pci_plx9050_exit),
838 },
1da177e4
LT		 839 {
840 .vendor = PCI_VENDOR_ID_PLX,
841 .device = PCI_DEVICE_ID_PLX_9050,
842 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
843 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
844 .init = pci_plx9050_init,
845 .setup = pci_default_setup,
846 .exit = __devexit_p(pci_plx9050_exit),
847 },
848 {
849 .vendor = PCI_VENDOR_ID_PLX,
850 .device = PCI_DEVICE_ID_PLX_ROMULUS,
851 .subvendor = PCI_VENDOR_ID_PLX,
852 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
853 .init = pci_plx9050_init,
854 .setup = pci_default_setup,
855 .exit = __devexit_p(pci_plx9050_exit),
856 },
857 /*
858 * SBS Technologies, Inc., PMC-OCTALPRO 232
859 */
860 {
861 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
862 .device = PCI_DEVICE_ID_OCTPRO,
863 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
864 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
865 .init = sbs_init,
866 .setup = sbs_setup,
867 .exit = __devexit_p(sbs_exit),
868 },
869 /*
870 * SBS Technologies, Inc., PMC-OCTALPRO 422
871 */
872 {
873 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
874 .device = PCI_DEVICE_ID_OCTPRO,
875 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
876 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
877 .init = sbs_init,
878 .setup = sbs_setup,
879 .exit = __devexit_p(sbs_exit),
880 },
881 /*
882 * SBS Technologies, Inc., P-Octal 232
883 */
884 {
885 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
886 .device = PCI_DEVICE_ID_OCTPRO,
887 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
888 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
889 .init = sbs_init,
890 .setup = sbs_setup,
891 .exit = __devexit_p(sbs_exit),
892 },
893 /*
894 * SBS Technologies, Inc., P-Octal 422
895 */
896 {
897 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
898 .device = PCI_DEVICE_ID_OCTPRO,
899 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
900 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
901 .init = sbs_init,
902 .setup = sbs_setup,
903 .exit = __devexit_p(sbs_exit),
904 },
1da177e4 905 /*
61a116ef 906 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 907 */
908 {
909 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 910 .device = PCI_ANY_ID,
1da177e4
LT		 911 .subvendor = PCI_ANY_ID,
912 .subdevice = PCI_ANY_ID,
67d74b87 913 .init = pci_siig_init,
3ec9c594 914 .setup = pci_siig_setup,
1da177e4
LT		 915 },
916 /*
917 * Titan cards
918 */
919 {
920 .vendor = PCI_VENDOR_ID_TITAN,
921 .device = PCI_DEVICE_ID_TITAN_400L,
922 .subvendor = PCI_ANY_ID,
923 .subdevice = PCI_ANY_ID,
924 .setup = titan_400l_800l_setup,
925 },
926 {
927 .vendor = PCI_VENDOR_ID_TITAN,
928 .device = PCI_DEVICE_ID_TITAN_800L,
929 .subvendor = PCI_ANY_ID,
930 .subdevice = PCI_ANY_ID,
931 .setup = titan_400l_800l_setup,
932 },
933 /*
934 * Timedia cards
935 */
936 {
937 .vendor = PCI_VENDOR_ID_TIMEDIA,
938 .device = PCI_DEVICE_ID_TIMEDIA_1889,
939 .subvendor = PCI_VENDOR_ID_TIMEDIA,
940 .subdevice = PCI_ANY_ID,
941 .init = pci_timedia_init,
942 .setup = pci_timedia_setup,
943 },
944 {
945 .vendor = PCI_VENDOR_ID_TIMEDIA,
946 .device = PCI_ANY_ID,
947 .subvendor = PCI_ANY_ID,
948 .subdevice = PCI_ANY_ID,
949 .setup = pci_timedia_setup,
950 },
951 /*
952 * Xircom cards
953 */
954 {
955 .vendor = PCI_VENDOR_ID_XIRCOM,
956 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
957 .subvendor = PCI_ANY_ID,
958 .subdevice = PCI_ANY_ID,
959 .init = pci_xircom_init,
960 .setup = pci_default_setup,
961 },
962 /*
61a116ef 963 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 964 */
965 {
966 .vendor = PCI_VENDOR_ID_NETMOS,
967 .device = PCI_ANY_ID,
968 .subvendor = PCI_ANY_ID,
969 .subdevice = PCI_ANY_ID,
970 .init = pci_netmos_init,
971 .setup = pci_default_setup,
972 },
973 /*
974 * Default "match everything" terminator entry
975 */
976 {
977 .vendor = PCI_ANY_ID,
978 .device = PCI_ANY_ID,
979 .subvendor = PCI_ANY_ID,
980 .subdevice = PCI_ANY_ID,
981 .setup = pci_default_setup,
982 }
983};
984
985static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
986{
987 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
988}
989
990static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
991{
992 struct pci_serial_quirk *quirk;
993
994 for (quirk = pci_serial_quirks; ; quirk++)
995 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
996 quirk_id_matches(quirk->device, dev->device) &&
997 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
998 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
999 break;
1000 return quirk;
1001}
1002
dd68e88c
AM		 1003static inline int get_pci_irq(struct pci_dev *dev,
1004 struct pciserial_board *board)
1da177e4
LT		 1005{
1006 if (board->flags & FL_NOIRQ)
1007 return 0;
1008 else
1009 return dev->irq;
1010}
1011
1012/*
1013 * This is the configuration table for all of the PCI serial boards
1014 * which we support. It is directly indexed by the pci_board_num_t enum
1015 * value, which is encoded in the pci_device_id PCI probe table's
1016 * driver_data member.
1017 *
1018 * The makeup of these names are:
26e92861 1019 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 1020 *
26e92861
GH		 1021 * bn = PCI BAR number
1022 * bt = Index using PCI BARs
1023 * n = number of serial ports
1024 * baud = baud rate
1025 * offsetinhex = offset for each sequential port (in hex)
1da177e4 1026 *
26e92861 1027 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 1028 *
1da177e4
LT		 1029 * Please note: in theory if n = 1, _bt infix should make no difference.
1030 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1031 */
1032enum pci_board_num_t {
1033 pbn_default = 0,
1034
1035 pbn_b0_1_115200,
1036 pbn_b0_2_115200,
1037 pbn_b0_4_115200,
1038 pbn_b0_5_115200,
1039
1040 pbn_b0_1_921600,
1041 pbn_b0_2_921600,
1042 pbn_b0_4_921600,
1043
db1de159
DR		 1044 pbn_b0_2_1130000,
1045
fbc0dc0d
AP		 1046 pbn_b0_4_1152000,
1047
26e92861
GH		 1048 pbn_b0_2_1843200,
1049 pbn_b0_4_1843200,
1050
1051 pbn_b0_2_1843200_200,
1052 pbn_b0_4_1843200_200,
1053 pbn_b0_8_1843200_200,
1054
1da177e4
LT		 1055 pbn_b0_bt_1_115200,
1056 pbn_b0_bt_2_115200,
1057 pbn_b0_bt_8_115200,
1058
1059 pbn_b0_bt_1_460800,
1060 pbn_b0_bt_2_460800,
1061 pbn_b0_bt_4_460800,
1062
1063 pbn_b0_bt_1_921600,
1064 pbn_b0_bt_2_921600,
1065 pbn_b0_bt_4_921600,
1066 pbn_b0_bt_8_921600,
1067
1068 pbn_b1_1_115200,
1069 pbn_b1_2_115200,
1070 pbn_b1_4_115200,
1071 pbn_b1_8_115200,
1072
1073 pbn_b1_1_921600,
1074 pbn_b1_2_921600,
1075 pbn_b1_4_921600,
1076 pbn_b1_8_921600,
1077
26e92861
GH		 1078 pbn_b1_2_1250000,
1079
84f8c6fc 1080 pbn_b1_bt_1_115200,
1da177e4
LT		 1081 pbn_b1_bt_2_921600,
1082
1083 pbn_b1_1_1382400,
1084 pbn_b1_2_1382400,
1085 pbn_b1_4_1382400,
1086 pbn_b1_8_1382400,
1087
1088 pbn_b2_1_115200,
737c1756 1089 pbn_b2_2_115200,
a9cccd34 1090 pbn_b2_4_115200,
1da177e4
LT		 1091 pbn_b2_8_115200,
1092
1093 pbn_b2_1_460800,
1094 pbn_b2_4_460800,
1095 pbn_b2_8_460800,
1096 pbn_b2_16_460800,
1097
1098 pbn_b2_1_921600,
1099 pbn_b2_4_921600,
1100 pbn_b2_8_921600,
1101
1102 pbn_b2_bt_1_115200,
1103 pbn_b2_bt_2_115200,
1104 pbn_b2_bt_4_115200,
1105
1106 pbn_b2_bt_2_921600,
1107 pbn_b2_bt_4_921600,
1108
d9004eb4 1109 pbn_b3_2_115200,
1da177e4
LT		 1110 pbn_b3_4_115200,
1111 pbn_b3_8_115200,
1112
1113 /*
1114 * Board-specific versions.
1115 */
1116 pbn_panacom,
1117 pbn_panacom2,
1118 pbn_panacom4,
add7b58e 1119 pbn_exsys_4055,
1da177e4
LT		 1120 pbn_plx_romulus,
1121 pbn_oxsemi,
1122 pbn_intel_i960,
1123 pbn_sgi_ioc3,
1da177e4
LT		 1124 pbn_computone_4,
1125 pbn_computone_6,
1126 pbn_computone_8,
1127 pbn_sbsxrsio,
1128 pbn_exar_XR17C152,
1129 pbn_exar_XR17C154,
1130 pbn_exar_XR17C158,
1131};
1132
1133/*
1134 * uart_offset - the space between channels
1135 * reg_shift - describes how the UART registers are mapped
1136 * to PCI memory by the card.
1137 * For example IER register on SBS, Inc. PMC-OctPro is located at
1138 * offset 0x10 from the UART base, while UART_IER is defined as 1
1139 * in include/linux/serial_reg.h,
1140 * see first lines of serial_in() and serial_out() in 8250.c
1141*/
1142
1c7c1fe5 1143static struct pciserial_board pci_boards[] __devinitdata = {
1da177e4
LT		 1144 [pbn_default] = {
1145 .flags = FL_BASE0,
1146 .num_ports = 1,
1147 .base_baud = 115200,
1148 .uart_offset = 8,
1149 },
1150 [pbn_b0_1_115200] = {
1151 .flags = FL_BASE0,
1152 .num_ports = 1,
1153 .base_baud = 115200,
1154 .uart_offset = 8,
1155 },
1156 [pbn_b0_2_115200] = {
1157 .flags = FL_BASE0,
1158 .num_ports = 2,
1159 .base_baud = 115200,
1160 .uart_offset = 8,
1161 },
1162 [pbn_b0_4_115200] = {
1163 .flags = FL_BASE0,
1164 .num_ports = 4,
1165 .base_baud = 115200,
1166 .uart_offset = 8,
1167 },
1168 [pbn_b0_5_115200] = {
1169 .flags = FL_BASE0,
1170 .num_ports = 5,
1171 .base_baud = 115200,
1172 .uart_offset = 8,
1173 },
1174
1175 [pbn_b0_1_921600] = {
1176 .flags = FL_BASE0,
1177 .num_ports = 1,
1178 .base_baud = 921600,
1179 .uart_offset = 8,
1180 },
1181 [pbn_b0_2_921600] = {
1182 .flags = FL_BASE0,
1183 .num_ports = 2,
1184 .base_baud = 921600,
1185 .uart_offset = 8,
1186 },
1187 [pbn_b0_4_921600] = {
1188 .flags = FL_BASE0,
1189 .num_ports = 4,
1190 .base_baud = 921600,
1191 .uart_offset = 8,
1192 },
db1de159
DR		 1193
1194 [pbn_b0_2_1130000] = {
1195 .flags = FL_BASE0,
1196 .num_ports = 2,
1197 .base_baud = 1130000,
1198 .uart_offset = 8,
1199 },
1200
fbc0dc0d
AP		 1201 [pbn_b0_4_1152000] = {
1202 .flags = FL_BASE0,
1203 .num_ports = 4,
1204 .base_baud = 1152000,
1205 .uart_offset = 8,
1206 },
1da177e4 1207
26e92861
GH		 1208 [pbn_b0_2_1843200] = {
1209 .flags = FL_BASE0,
1210 .num_ports = 2,
1211 .base_baud = 1843200,
1212 .uart_offset = 8,
1213 },
1214 [pbn_b0_4_1843200] = {
1215 .flags = FL_BASE0,
1216 .num_ports = 4,
1217 .base_baud = 1843200,
1218 .uart_offset = 8,
1219 },
1220
1221 [pbn_b0_2_1843200_200] = {
1222 .flags = FL_BASE0,
1223 .num_ports = 2,
1224 .base_baud = 1843200,
1225 .uart_offset = 0x200,
1226 },
1227 [pbn_b0_4_1843200_200] = {
1228 .flags = FL_BASE0,
1229 .num_ports = 4,
1230 .base_baud = 1843200,
1231 .uart_offset = 0x200,
1232 },
1233 [pbn_b0_8_1843200_200] = {
1234 .flags = FL_BASE0,
1235 .num_ports = 8,
1236 .base_baud = 1843200,
1237 .uart_offset = 0x200,
1238 },
1239
1da177e4
LT		 1240 [pbn_b0_bt_1_115200] = {
1241 .flags = FL_BASE0|FL_BASE_BARS,
1242 .num_ports = 1,
1243 .base_baud = 115200,
1244 .uart_offset = 8,
1245 },
1246 [pbn_b0_bt_2_115200] = {
1247 .flags = FL_BASE0|FL_BASE_BARS,
1248 .num_ports = 2,
1249 .base_baud = 115200,
1250 .uart_offset = 8,
1251 },
1252 [pbn_b0_bt_8_115200] = {
1253 .flags = FL_BASE0|FL_BASE_BARS,
1254 .num_ports = 8,
1255 .base_baud = 115200,
1256 .uart_offset = 8,
1257 },
1258
1259 [pbn_b0_bt_1_460800] = {
1260 .flags = FL_BASE0|FL_BASE_BARS,
1261 .num_ports = 1,
1262 .base_baud = 460800,
1263 .uart_offset = 8,
1264 },
1265 [pbn_b0_bt_2_460800] = {
1266 .flags = FL_BASE0|FL_BASE_BARS,
1267 .num_ports = 2,
1268 .base_baud = 460800,
1269 .uart_offset = 8,
1270 },
1271 [pbn_b0_bt_4_460800] = {
1272 .flags = FL_BASE0|FL_BASE_BARS,
1273 .num_ports = 4,
1274 .base_baud = 460800,
1275 .uart_offset = 8,
1276 },
1277
1278 [pbn_b0_bt_1_921600] = {
1279 .flags = FL_BASE0|FL_BASE_BARS,
1280 .num_ports = 1,
1281 .base_baud = 921600,
1282 .uart_offset = 8,
1283 },
1284 [pbn_b0_bt_2_921600] = {
1285 .flags = FL_BASE0|FL_BASE_BARS,
1286 .num_ports = 2,
1287 .base_baud = 921600,
1288 .uart_offset = 8,
1289 },
1290 [pbn_b0_bt_4_921600] = {
1291 .flags = FL_BASE0|FL_BASE_BARS,
1292 .num_ports = 4,
1293 .base_baud = 921600,
1294 .uart_offset = 8,
1295 },
1296 [pbn_b0_bt_8_921600] = {
1297 .flags = FL_BASE0|FL_BASE_BARS,
1298 .num_ports = 8,
1299 .base_baud = 921600,
1300 .uart_offset = 8,
1301 },
1302
1303 [pbn_b1_1_115200] = {
1304 .flags = FL_BASE1,
1305 .num_ports = 1,
1306 .base_baud = 115200,
1307 .uart_offset = 8,
1308 },
1309 [pbn_b1_2_115200] = {
1310 .flags = FL_BASE1,
1311 .num_ports = 2,
1312 .base_baud = 115200,
1313 .uart_offset = 8,
1314 },
1315 [pbn_b1_4_115200] = {
1316 .flags = FL_BASE1,
1317 .num_ports = 4,
1318 .base_baud = 115200,
1319 .uart_offset = 8,
1320 },
1321 [pbn_b1_8_115200] = {
1322 .flags = FL_BASE1,
1323 .num_ports = 8,
1324 .base_baud = 115200,
1325 .uart_offset = 8,
1326 },
1327
1328 [pbn_b1_1_921600] = {
1329 .flags = FL_BASE1,
1330 .num_ports = 1,
1331 .base_baud = 921600,
1332 .uart_offset = 8,
1333 },
1334 [pbn_b1_2_921600] = {
1335 .flags = FL_BASE1,
1336 .num_ports = 2,
1337 .base_baud = 921600,
1338 .uart_offset = 8,
1339 },
1340 [pbn_b1_4_921600] = {
1341 .flags = FL_BASE1,
1342 .num_ports = 4,
1343 .base_baud = 921600,
1344 .uart_offset = 8,
1345 },
1346 [pbn_b1_8_921600] = {
1347 .flags = FL_BASE1,
1348 .num_ports = 8,
1349 .base_baud = 921600,
1350 .uart_offset = 8,
1351 },
26e92861
GH		 1352 [pbn_b1_2_1250000] = {
1353 .flags = FL_BASE1,
1354 .num_ports = 2,
1355 .base_baud = 1250000,
1356 .uart_offset = 8,
1357 },
1da177e4 1358
84f8c6fc
NV		 1359 [pbn_b1_bt_1_115200] = {
1360 .flags = FL_BASE1|FL_BASE_BARS,
1361 .num_ports = 1,
1362 .base_baud = 115200,
1363 .uart_offset = 8,
1364 },
1365
1da177e4
LT		 1366 [pbn_b1_bt_2_921600] = {
1367 .flags = FL_BASE1|FL_BASE_BARS,
1368 .num_ports = 2,
1369 .base_baud = 921600,
1370 .uart_offset = 8,
1371 },
1372
1373 [pbn_b1_1_1382400] = {
1374 .flags = FL_BASE1,
1375 .num_ports = 1,
1376 .base_baud = 1382400,
1377 .uart_offset = 8,
1378 },
1379 [pbn_b1_2_1382400] = {
1380 .flags = FL_BASE1,
1381 .num_ports = 2,
1382 .base_baud = 1382400,
1383 .uart_offset = 8,
1384 },
1385 [pbn_b1_4_1382400] = {
1386 .flags = FL_BASE1,
1387 .num_ports = 4,
1388 .base_baud = 1382400,
1389 .uart_offset = 8,
1390 },
1391 [pbn_b1_8_1382400] = {
1392 .flags = FL_BASE1,
1393 .num_ports = 8,
1394 .base_baud = 1382400,
1395 .uart_offset = 8,
1396 },
1397
1398 [pbn_b2_1_115200] = {
1399 .flags = FL_BASE2,
1400 .num_ports = 1,
1401 .base_baud = 115200,
1402 .uart_offset = 8,
1403 },
737c1756
PH		 1404 [pbn_b2_2_115200] = {
1405 .flags = FL_BASE2,
1406 .num_ports = 2,
1407 .base_baud = 115200,
1408 .uart_offset = 8,
1409 },
a9cccd34
MF		 1410 [pbn_b2_4_115200] = {
1411 .flags = FL_BASE2,
1412 .num_ports = 4,
1413 .base_baud = 115200,
1414 .uart_offset = 8,
1415 },
1da177e4
LT		 1416 [pbn_b2_8_115200] = {
1417 .flags = FL_BASE2,
1418 .num_ports = 8,
1419 .base_baud = 115200,
1420 .uart_offset = 8,
1421 },
1422
1423 [pbn_b2_1_460800] = {
1424 .flags = FL_BASE2,
1425 .num_ports = 1,
1426 .base_baud = 460800,
1427 .uart_offset = 8,
1428 },
1429 [pbn_b2_4_460800] = {
1430 .flags = FL_BASE2,
1431 .num_ports = 4,
1432 .base_baud = 460800,
1433 .uart_offset = 8,
1434 },
1435 [pbn_b2_8_460800] = {
1436 .flags = FL_BASE2,
1437 .num_ports = 8,
1438 .base_baud = 460800,
1439 .uart_offset = 8,
1440 },
1441 [pbn_b2_16_460800] = {
1442 .flags = FL_BASE2,
1443 .num_ports = 16,
1444 .base_baud = 460800,
1445 .uart_offset = 8,
1446 },
1447
1448 [pbn_b2_1_921600] = {
1449 .flags = FL_BASE2,
1450 .num_ports = 1,
1451 .base_baud = 921600,
1452 .uart_offset = 8,
1453 },
1454 [pbn_b2_4_921600] = {
1455 .flags = FL_BASE2,
1456 .num_ports = 4,
1457 .base_baud = 921600,
1458 .uart_offset = 8,
1459 },
1460 [pbn_b2_8_921600] = {
1461 .flags = FL_BASE2,
1462 .num_ports = 8,
1463 .base_baud = 921600,
1464 .uart_offset = 8,
1465 },
1466
1467 [pbn_b2_bt_1_115200] = {
1468 .flags = FL_BASE2|FL_BASE_BARS,
1469 .num_ports = 1,
1470 .base_baud = 115200,
1471 .uart_offset = 8,
1472 },
1473 [pbn_b2_bt_2_115200] = {
1474 .flags = FL_BASE2|FL_BASE_BARS,
1475 .num_ports = 2,
1476 .base_baud = 115200,
1477 .uart_offset = 8,
1478 },
1479 [pbn_b2_bt_4_115200] = {
1480 .flags = FL_BASE2|FL_BASE_BARS,
1481 .num_ports = 4,
1482 .base_baud = 115200,
1483 .uart_offset = 8,
1484 },
1485
1486 [pbn_b2_bt_2_921600] = {
1487 .flags = FL_BASE2|FL_BASE_BARS,
1488 .num_ports = 2,
1489 .base_baud = 921600,
1490 .uart_offset = 8,
1491 },
1492 [pbn_b2_bt_4_921600] = {
1493 .flags = FL_BASE2|FL_BASE_BARS,
1494 .num_ports = 4,
1495 .base_baud = 921600,
1496 .uart_offset = 8,
1497 },
1498
d9004eb4
ABL		 1499 [pbn_b3_2_115200] = {
1500 .flags = FL_BASE3,
1501 .num_ports = 2,
1502 .base_baud = 115200,
1503 .uart_offset = 8,
1504 },
1da177e4
LT		 1505 [pbn_b3_4_115200] = {
1506 .flags = FL_BASE3,
1507 .num_ports = 4,
1508 .base_baud = 115200,
1509 .uart_offset = 8,
1510 },
1511 [pbn_b3_8_115200] = {
1512 .flags = FL_BASE3,
1513 .num_ports = 8,
1514 .base_baud = 115200,
1515 .uart_offset = 8,
1516 },
1517
1518 /*
1519 * Entries following this are board-specific.
1520 */
1521
1522 /*
1523 * Panacom - IOMEM
1524 */
1525 [pbn_panacom] = {
1526 .flags = FL_BASE2,
1527 .num_ports = 2,
1528 .base_baud = 921600,
1529 .uart_offset = 0x400,
1530 .reg_shift = 7,
1531 },
1532 [pbn_panacom2] = {
1533 .flags = FL_BASE2|FL_BASE_BARS,
1534 .num_ports = 2,
1535 .base_baud = 921600,
1536 .uart_offset = 0x400,
1537 .reg_shift = 7,
1538 },
1539 [pbn_panacom4] = {
1540 .flags = FL_BASE2|FL_BASE_BARS,
1541 .num_ports = 4,
1542 .base_baud = 921600,
1543 .uart_offset = 0x400,
1544 .reg_shift = 7,
1545 },
1546
add7b58e
BH		 1547 [pbn_exsys_4055] = {
1548 .flags = FL_BASE2,
1549 .num_ports = 4,
1550 .base_baud = 115200,
1551 .uart_offset = 8,
1552 },
1553
1da177e4
LT		 1554 /* I think this entry is broken - the first_offset looks wrong --rmk */
1555 [pbn_plx_romulus] = {
1556 .flags = FL_BASE2,
1557 .num_ports = 4,
1558 .base_baud = 921600,
1559 .uart_offset = 8 << 2,
1560 .reg_shift = 2,
1561 .first_offset = 0x03,
1562 },
1563
1564 /*
1565 * This board uses the size of PCI Base region 0 to
1566 * signal now many ports are available
1567 */
1568 [pbn_oxsemi] = {
1569 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1570 .num_ports = 32,
1571 .base_baud = 115200,
1572 .uart_offset = 8,
1573 },
1574
1575 /*
1576 * EKF addition for i960 Boards form EKF with serial port.
1577 * Max 256 ports.
1578 */
1579 [pbn_intel_i960] = {
1580 .flags = FL_BASE0,
1581 .num_ports = 32,
1582 .base_baud = 921600,
1583 .uart_offset = 8 << 2,
1584 .reg_shift = 2,
1585 .first_offset = 0x10000,
1586 },
1587 [pbn_sgi_ioc3] = {
1588 .flags = FL_BASE0|FL_NOIRQ,
1589 .num_ports = 1,
1590 .base_baud = 458333,
1591 .uart_offset = 8,
1592 .reg_shift = 0,
1593 .first_offset = 0x20178,
1594 },
1595
1da177e4
LT		 1596 /*
1597 * Computone - uses IOMEM.
1598 */
1599 [pbn_computone_4] = {
1600 .flags = FL_BASE0,
1601 .num_ports = 4,
1602 .base_baud = 921600,
1603 .uart_offset = 0x40,
1604 .reg_shift = 2,
1605 .first_offset = 0x200,
1606 },
1607 [pbn_computone_6] = {
1608 .flags = FL_BASE0,
1609 .num_ports = 6,
1610 .base_baud = 921600,
1611 .uart_offset = 0x40,
1612 .reg_shift = 2,
1613 .first_offset = 0x200,
1614 },
1615 [pbn_computone_8] = {
1616 .flags = FL_BASE0,
1617 .num_ports = 8,
1618 .base_baud = 921600,
1619 .uart_offset = 0x40,
1620 .reg_shift = 2,
1621 .first_offset = 0x200,
1622 },
1623 [pbn_sbsxrsio] = {
1624 .flags = FL_BASE0,
1625 .num_ports = 8,
1626 .base_baud = 460800,
1627 .uart_offset = 256,
1628 .reg_shift = 4,
1629 },
1630 /*
1631 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1632 * Only basic 16550A support.
1633 * XR17C15[24] are not tested, but they should work.
1634 */
1635 [pbn_exar_XR17C152] = {
1636 .flags = FL_BASE0,
1637 .num_ports = 2,
1638 .base_baud = 921600,
1639 .uart_offset = 0x200,
1640 },
1641 [pbn_exar_XR17C154] = {
1642 .flags = FL_BASE0,
1643 .num_ports = 4,
1644 .base_baud = 921600,
1645 .uart_offset = 0x200,
1646 },
1647 [pbn_exar_XR17C158] = {
1648 .flags = FL_BASE0,
1649 .num_ports = 8,
1650 .base_baud = 921600,
1651 .uart_offset = 0x200,
1652 },
1653};
1654
436bbd43
CS		 1655static const struct pci_device_id softmodem_blacklist[] = {
1656 { PCI_VDEVICE ( AL, 0x5457 ), }, /* ALi Corporation M5457 AC'97 Modem */
1657};
1658
1da177e4
LT		 1659/*
1660 * Given a complete unknown PCI device, try to use some heuristics to
1661 * guess what the configuration might be, based on the pitiful PCI
1662 * serial specs. Returns 0 on success, 1 on failure.
1663 */
1664static int __devinit
1c7c1fe5 1665serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 1666{
436bbd43 1667 const struct pci_device_id *blacklist;
1da177e4
LT		 1668 int num_iomem, num_port, first_port = -1, i;
1669
1670 /*
1671 * If it is not a communications device or the programming
1672 * interface is greater than 6, give up.
1673 *
1674 * (Should we try to make guesses for multiport serial devices
1675 * later?)
1676 */
1677 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1678 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1679 (dev->class & 0xff) > 6)
1680 return -ENODEV;
1681
436bbd43
CS		 1682 /*
1683 * Do not access blacklisted devices that are known not to
1684 * feature serial ports.
1685 */
1686 for (blacklist = softmodem_blacklist;
1687 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
1688 blacklist++) {
1689 if (dev->vendor == blacklist->vendor &&
1690 dev->device == blacklist->device)
1691 return -ENODEV;
1692 }
1693
1da177e4
LT		 1694 num_iomem = num_port = 0;
1695 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1696 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1697 num_port++;
1698 if (first_port == -1)
1699 first_port = i;
1700 }
1701 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1702 num_iomem++;
1703 }
1704
1705 /*
1706 * If there is 1 or 0 iomem regions, and exactly one port,
1707 * use it. We guess the number of ports based on the IO
1708 * region size.
1709 */
1710 if (num_iomem <= 1 && num_port == 1) {
1711 board->flags = first_port;
1712 board->num_ports = pci_resource_len(dev, first_port) / 8;
1713 return 0;
1714 }
1715
1716 /*
1717 * Now guess if we've got a board which indexes by BARs.
1718 * Each IO BAR should be 8 bytes, and they should follow
1719 * consecutively.
1720 */
1721 first_port = -1;
1722 num_port = 0;
1723 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1724 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1725 pci_resource_len(dev, i) == 8 &&
1726 (first_port == -1 || (first_port + num_port) == i)) {
1727 num_port++;
1728 if (first_port == -1)
1729 first_port = i;
1730 }
1731 }
1732
1733 if (num_port > 1) {
1734 board->flags = first_port | FL_BASE_BARS;
1735 board->num_ports = num_port;
1736 return 0;
1737 }
1738
1739 return -ENODEV;
1740}
1741
1742static inline int
1c7c1fe5
RK		 1743serial_pci_matches(struct pciserial_board *board,
1744 struct pciserial_board *guessed)
1da177e4
LT		 1745{
1746 return
1747 board->num_ports == guessed->num_ports &&
1748 board->base_baud == guessed->base_baud &&
1749 board->uart_offset == guessed->uart_offset &&
1750 board->reg_shift == guessed->reg_shift &&
1751 board->first_offset == guessed->first_offset;
1752}
1753
241fc436
RK		 1754struct serial_private *
1755pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 1756{
72ce9a83 1757 struct uart_port serial_port;
1da177e4 1758 struct serial_private *priv;
1da177e4
LT		 1759 struct pci_serial_quirk *quirk;
1760 int rc, nr_ports, i;
1761
1da177e4
LT		 1762 nr_ports = board->num_ports;
1763
1764 /*
1765 * Find an init and setup quirks.
1766 */
1767 quirk = find_quirk(dev);
1768
1769 /*
1770 * Run the new-style initialization function.
1771 * The initialization function returns:
1772 * <0 - error
1773 * 0 - use board->num_ports
1774 * >0 - number of ports
1775 */
1776 if (quirk->init) {
1777 rc = quirk->init(dev);
241fc436
RK		 1778 if (rc < 0) {
1779 priv = ERR_PTR(rc);
1780 goto err_out;
1781 }
1da177e4
LT		 1782 if (rc)
1783 nr_ports = rc;
1784 }
1785
8f31bb39 1786 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 1787 sizeof(unsigned int) * nr_ports,
1788 GFP_KERNEL);
1789 if (!priv) {
241fc436
RK		 1790 priv = ERR_PTR(-ENOMEM);
1791 goto err_deinit;
1da177e4
LT		 1792 }
1793
70db3d91 1794 priv->dev = dev;
1da177e4 1795 priv->quirk = quirk;
1da177e4 1796
72ce9a83
RK		 1797 memset(&serial_port, 0, sizeof(struct uart_port));
1798 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1799 serial_port.uartclk = board->base_baud * 16;
1800 serial_port.irq = get_pci_irq(dev, board);
1801 serial_port.dev = &dev->dev;
1802
1da177e4 1803 for (i = 0; i < nr_ports; i++) {
70db3d91 1804 if (quirk->setup(priv, board, &serial_port, i))
1da177e4 1805 break;
72ce9a83 1806
1da177e4
LT		 1807#ifdef SERIAL_DEBUG_PCI
1808 printk("Setup PCI port: port %x, irq %d, type %d\n",
1809 serial_port.iobase, serial_port.irq, serial_port.iotype);
1810#endif
1811
1812 priv->line[i] = serial8250_register_port(&serial_port);
1813 if (priv->line[i] < 0) {
1814 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1815 break;
1816 }
1817 }
1818
1819 priv->nr = i;
1820
241fc436 1821 return priv;
1da177e4 1822
241fc436 1823 err_deinit:
1da177e4
LT		 1824 if (quirk->exit)
1825 quirk->exit(dev);
241fc436
RK		 1826 err_out:
1827 return priv;
1da177e4 1828}
241fc436 1829EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 1830
241fc436 1831void pciserial_remove_ports(struct serial_private *priv)
1da177e4 1832{
056a8763
RK		 1833 struct pci_serial_quirk *quirk;
1834 int i;
1da177e4 1835
056a8763
RK		 1836 for (i = 0; i < priv->nr; i++)
1837 serial8250_unregister_port(priv->line[i]);
1da177e4 1838
056a8763
RK		 1839 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1840 if (priv->remapped_bar[i])
1841 iounmap(priv->remapped_bar[i]);
1842 priv->remapped_bar[i] = NULL;
1843 }
1da177e4 1844
056a8763
RK		 1845 /*
1846 * Find the exit quirks.
1847 */
241fc436 1848 quirk = find_quirk(priv->dev);
056a8763 1849 if (quirk->exit)
241fc436
RK		 1850 quirk->exit(priv->dev);
1851
1852 kfree(priv);
1853}
1854EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1855
1856void pciserial_suspend_ports(struct serial_private *priv)
1857{
1858 int i;
1859
1860 for (i = 0; i < priv->nr; i++)
1861 if (priv->line[i] >= 0)
1862 serial8250_suspend_port(priv->line[i]);
1863}
1864EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1865
1866void pciserial_resume_ports(struct serial_private *priv)
1867{
1868 int i;
1869
1870 /*
1871 * Ensure that the board is correctly configured.
1872 */
1873 if (priv->quirk->init)
1874 priv->quirk->init(priv->dev);
1875
1876 for (i = 0; i < priv->nr; i++)
1877 if (priv->line[i] >= 0)
1878 serial8250_resume_port(priv->line[i]);
1879}
1880EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1881
1882/*
1883 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1884 * to the arrangement of serial ports on a PCI card.
1885 */
1886static int __devinit
1887pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1888{
1889 struct serial_private *priv;
1890 struct pciserial_board *board, tmp;
1891 int rc;
1892
1893 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1894 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1895 ent->driver_data);
1896 return -EINVAL;
1897 }
1898
1899 board = &pci_boards[ent->driver_data];
1900
1901 rc = pci_enable_device(dev);
1902 if (rc)
1903 return rc;
1904
1905 if (ent->driver_data == pbn_default) {
1906 /*
1907 * Use a copy of the pci_board entry for this;
1908 * avoid changing entries in the table.
1909 */
1910 memcpy(&tmp, board, sizeof(struct pciserial_board));
1911 board = &tmp;
1912
1913 /*
1914 * We matched one of our class entries. Try to
1915 * determine the parameters of this board.
1916 */
1917 rc = serial_pci_guess_board(dev, board);
1918 if (rc)
1919 goto disable;
1920 } else {
1921 /*
1922 * We matched an explicit entry. If we are able to
1923 * detect this boards settings with our heuristic,
1924 * then we no longer need this entry.
1925 */
1926 memcpy(&tmp, &pci_boards[pbn_default],
1927 sizeof(struct pciserial_board));
1928 rc = serial_pci_guess_board(dev, &tmp);
1929 if (rc == 0 && serial_pci_matches(board, &tmp))
1930 moan_device("Redundant entry in serial pci_table.",
1931 dev);
1932 }
1933
1934 priv = pciserial_init_ports(dev, board);
1935 if (!IS_ERR(priv)) {
1936 pci_set_drvdata(dev, priv);
1937 return 0;
1938 }
1939
1940 rc = PTR_ERR(priv);
1da177e4 1941
241fc436 1942 disable:
056a8763 1943 pci_disable_device(dev);
241fc436
RK		 1944 return rc;
1945}
1da177e4 1946
241fc436
RK		 1947static void __devexit pciserial_remove_one(struct pci_dev *dev)
1948{
1949 struct serial_private *priv = pci_get_drvdata(dev);
1950
1951 pci_set_drvdata(dev, NULL);
1952
1953 pciserial_remove_ports(priv);
1954
1955 pci_disable_device(dev);
1da177e4
LT		 1956}
1957
1d5e7996 1958#ifdef CONFIG_PM
1da177e4
LT		 1959static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1960{
1961 struct serial_private *priv = pci_get_drvdata(dev);
1962
241fc436
RK		 1963 if (priv)
1964 pciserial_suspend_ports(priv);
1da177e4 1965
1da177e4
LT		 1966 pci_save_state(dev);
1967 pci_set_power_state(dev, pci_choose_state(dev, state));
1968 return 0;
1969}
1970
1971static int pciserial_resume_one(struct pci_dev *dev)
1972{
1973 struct serial_private *priv = pci_get_drvdata(dev);
1974
1975 pci_set_power_state(dev, PCI_D0);
1976 pci_restore_state(dev);
1977
1978 if (priv) {
1da177e4
LT		 1979 /*
1980 * The device may have been disabled. Re-enable it.
1981 */
1982 pci_enable_device(dev);
1983
241fc436 1984 pciserial_resume_ports(priv);
1da177e4
LT		 1985 }
1986 return 0;
1987}
1d5e7996 1988#endif
1da177e4
LT		 1989
1990static struct pci_device_id serial_pci_tbl[] = {
1991 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1992 PCI_SUBVENDOR_ID_CONNECT_TECH,
1993 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1994 pbn_b1_8_1382400 },
1995 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1996 PCI_SUBVENDOR_ID_CONNECT_TECH,
1997 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1998 pbn_b1_4_1382400 },
1999 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2000 PCI_SUBVENDOR_ID_CONNECT_TECH,
2001 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2002 pbn_b1_2_1382400 },
2003 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2004 PCI_SUBVENDOR_ID_CONNECT_TECH,
2005 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2006 pbn_b1_8_1382400 },
2007 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2008 PCI_SUBVENDOR_ID_CONNECT_TECH,
2009 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2010 pbn_b1_4_1382400 },
2011 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2012 PCI_SUBVENDOR_ID_CONNECT_TECH,
2013 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2014 pbn_b1_2_1382400 },
2015 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2016 PCI_SUBVENDOR_ID_CONNECT_TECH,
2017 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2018 pbn_b1_8_921600 },
2019 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2020 PCI_SUBVENDOR_ID_CONNECT_TECH,
2021 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2022 pbn_b1_8_921600 },
2023 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2024 PCI_SUBVENDOR_ID_CONNECT_TECH,
2025 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2026 pbn_b1_4_921600 },
2027 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2028 PCI_SUBVENDOR_ID_CONNECT_TECH,
2029 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2030 pbn_b1_4_921600 },
2031 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2032 PCI_SUBVENDOR_ID_CONNECT_TECH,
2033 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2034 pbn_b1_2_921600 },
2035 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2036 PCI_SUBVENDOR_ID_CONNECT_TECH,
2037 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2038 pbn_b1_8_921600 },
2039 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2040 PCI_SUBVENDOR_ID_CONNECT_TECH,
2041 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2042 pbn_b1_8_921600 },
2043 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2044 PCI_SUBVENDOR_ID_CONNECT_TECH,
2045 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2046 pbn_b1_4_921600 },
26e92861
GH		 2047 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2048 PCI_SUBVENDOR_ID_CONNECT_TECH,
2049 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2050 pbn_b1_2_1250000 },
2051 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2052 PCI_SUBVENDOR_ID_CONNECT_TECH,
2053 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2054 pbn_b0_2_1843200 },
2055 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2056 PCI_SUBVENDOR_ID_CONNECT_TECH,
2057 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2058 pbn_b0_4_1843200 },
85d1494e
YY		 2059 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2060 PCI_VENDOR_ID_AFAVLAB,
2061 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2062 pbn_b0_4_1152000 },
26e92861
GH		 2063 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2064 PCI_SUBVENDOR_ID_CONNECT_TECH,
2065 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2066 pbn_b0_2_1843200_200 },
2067 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2068 PCI_SUBVENDOR_ID_CONNECT_TECH,
2069 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2070 pbn_b0_4_1843200_200 },
2071 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2072 PCI_SUBVENDOR_ID_CONNECT_TECH,
2073 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2074 pbn_b0_8_1843200_200 },
2075 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2076 PCI_SUBVENDOR_ID_CONNECT_TECH,
2077 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2078 pbn_b0_2_1843200_200 },
2079 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2080 PCI_SUBVENDOR_ID_CONNECT_TECH,
2081 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2082 pbn_b0_4_1843200_200 },
2083 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2084 PCI_SUBVENDOR_ID_CONNECT_TECH,
2085 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2086 pbn_b0_8_1843200_200 },
2087 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2088 PCI_SUBVENDOR_ID_CONNECT_TECH,
2089 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2090 pbn_b0_2_1843200_200 },
2091 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2092 PCI_SUBVENDOR_ID_CONNECT_TECH,
2093 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2094 pbn_b0_4_1843200_200 },
2095 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2096 PCI_SUBVENDOR_ID_CONNECT_TECH,
2097 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2098 pbn_b0_8_1843200_200 },
2099 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2100 PCI_SUBVENDOR_ID_CONNECT_TECH,
2101 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2102 pbn_b0_2_1843200_200 },
2103 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2104 PCI_SUBVENDOR_ID_CONNECT_TECH,
2105 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2106 pbn_b0_4_1843200_200 },
2107 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2108 PCI_SUBVENDOR_ID_CONNECT_TECH,
2109 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2110 pbn_b0_8_1843200_200 },
1da177e4
LT		 2111
2112 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2113 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2114 pbn_b2_bt_1_115200 },
2115 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2116 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2117 pbn_b2_bt_2_115200 },
2118 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2119 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2120 pbn_b2_bt_4_115200 },
2121 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2122 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2123 pbn_b2_bt_2_115200 },
2124 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2125 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2126 pbn_b2_bt_4_115200 },
2127 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2128 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2129 pbn_b2_8_115200 },
2130 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2131 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2132 pbn_b2_8_115200 },
2133
2134 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2136 pbn_b2_bt_2_115200 },
2137 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2139 pbn_b2_bt_2_921600 },
2140 /*
2141 * VScom SPCOM800, from sl@s.pl
2142 */
2143 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2145 pbn_b2_8_921600 },
2146 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2148 pbn_b2_4_921600 },
2149 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2150 PCI_SUBVENDOR_ID_KEYSPAN,
2151 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2152 pbn_panacom },
2153 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2154 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2155 pbn_panacom4 },
2156 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2157 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2158 pbn_panacom2 },
a9cccd34
MF		 2159 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2160 PCI_VENDOR_ID_ESDGMBH,
2161 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2162 pbn_b2_4_115200 },
1da177e4
LT		 2163 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2164 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2165 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2166 pbn_b2_4_460800 },
2167 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2168 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2169 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2170 pbn_b2_8_460800 },
2171 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2172 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2173 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2174 pbn_b2_16_460800 },
2175 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2176 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2177 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2178 pbn_b2_16_460800 },
2179 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2180 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2181 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2182 pbn_b2_4_460800 },
2183 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2184 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2185 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2186 pbn_b2_8_460800 },
add7b58e
BH		 2187 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2188 PCI_SUBVENDOR_ID_EXSYS,
2189 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2190 pbn_exsys_4055 },
1da177e4
LT		 2191 /*
2192 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2193 * (Exoray@isys.ca)
2194 */
2195 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2196 0x10b5, 0x106a, 0, 0,
2197 pbn_plx_romulus },
2198 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2199 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2200 pbn_b1_4_115200 },
2201 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2202 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2203 pbn_b1_2_115200 },
2204 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2205 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2206 pbn_b1_8_115200 },
2207 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2208 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2209 pbn_b1_8_115200 },
2210 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2211 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
2212 pbn_b0_4_921600 },
fbc0dc0d
AP		 2213 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2214 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
2215 pbn_b0_4_1152000 },
db1de159
DR		 2216
2217 /*
2218 * The below card is a little controversial since it is the
2219 * subject of a PCI vendor/device ID clash. (See
2220 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2221 * For now just used the hex ID 0x950a.
2222 */
2223 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2224 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2225 pbn_b0_2_1130000 },
1da177e4
LT		 2226 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2227 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2228 pbn_b0_4_115200 },
2229 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2230 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2231 pbn_b0_bt_2_921600 },
2232
2233 /*
2234 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2235 * from skokodyn@yahoo.com
2236 */
2237 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2238 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2239 pbn_sbsxrsio },
2240 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2241 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2242 pbn_sbsxrsio },
2243 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2244 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2245 pbn_sbsxrsio },
2246 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2247 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2248 pbn_sbsxrsio },
2249
2250 /*
2251 * Digitan DS560-558, from jimd@esoft.com
2252 */
2253 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2254 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2255 pbn_b1_1_115200 },
2256
2257 /*
2258 * Titan Electronic cards
2259 * The 400L and 800L have a custom setup quirk.
2260 */
2261 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2262 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2263 pbn_b0_1_921600 },
2264 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2265 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2266 pbn_b0_2_921600 },
2267 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2268 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2269 pbn_b0_4_921600 },
2270 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2271 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2272 pbn_b0_4_921600 },
2273 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2274 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2275 pbn_b1_1_921600 },
2276 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2278 pbn_b1_bt_2_921600 },
2279 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2280 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2281 pbn_b0_bt_4_921600 },
2282 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2283 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2284 pbn_b0_bt_8_921600 },
2285
2286 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2287 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2288 pbn_b2_1_460800 },
2289 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2290 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2291 pbn_b2_1_460800 },
2292 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2293 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2294 pbn_b2_1_460800 },
2295 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2296 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2297 pbn_b2_bt_2_921600 },
2298 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2299 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2300 pbn_b2_bt_2_921600 },
2301 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2302 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2303 pbn_b2_bt_2_921600 },
2304 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2305 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2306 pbn_b2_bt_4_921600 },
2307 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2308 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2309 pbn_b2_bt_4_921600 },
2310 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2311 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2312 pbn_b2_bt_4_921600 },
2313 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2314 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2315 pbn_b0_1_921600 },
2316 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2317 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2318 pbn_b0_1_921600 },
2319 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2320 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2321 pbn_b0_1_921600 },
2322 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2323 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2324 pbn_b0_bt_2_921600 },
2325 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2326 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2327 pbn_b0_bt_2_921600 },
2328 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2329 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2330 pbn_b0_bt_2_921600 },
2331 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2332 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2333 pbn_b0_bt_4_921600 },
2334 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2335 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2336 pbn_b0_bt_4_921600 },
2337 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2338 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2339 pbn_b0_bt_4_921600 },
3ec9c594
AP		 2340 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2341 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2342 pbn_b0_bt_8_921600 },
2343 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2344 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2345 pbn_b0_bt_8_921600 },
2346 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2347 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2348 pbn_b0_bt_8_921600 },
1da177e4
LT		 2349
2350 /*
2351 * Computone devices submitted by Doug McNash dmcnash@computone.com
2352 */
2353 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2354 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2355 0, 0, pbn_computone_4 },
2356 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2357 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2358 0, 0, pbn_computone_8 },
2359 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2360 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2361 0, 0, pbn_computone_6 },
2362
2363 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2364 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2365 pbn_oxsemi },
2366 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2367 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2368 pbn_b0_bt_1_921600 },
2369
2370 /*
2371 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2372 */
2373 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2374 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2375 pbn_b0_bt_8_115200 },
2376 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2377 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2378 pbn_b0_bt_8_115200 },
2379
2380 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2381 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2382 pbn_b0_bt_2_115200 },
2383 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2384 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2385 pbn_b0_bt_2_115200 },
2386 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2387 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2388 pbn_b0_bt_2_115200 },
2389 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2390 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2391 pbn_b0_bt_4_460800 },
2392 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2393 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2394 pbn_b0_bt_4_460800 },
2395 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2396 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2397 pbn_b0_bt_2_460800 },
2398 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2399 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2400 pbn_b0_bt_2_460800 },
2401 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2402 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2403 pbn_b0_bt_2_460800 },
2404 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2405 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2406 pbn_b0_bt_1_115200 },
2407 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2408 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2409 pbn_b0_bt_1_460800 },
2410
1fb8cacc
RK		 2411 /*
2412 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
2413 * Cards are identified by their subsystem vendor IDs, which
2414 * (in hex) match the model number.
2415 *
2416 * Note that JC140x are RS422/485 cards which require ox950
2417 * ACR = 0x10, and as such are not currently fully supported.
2418 */
2419 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2420 0x1204, 0x0004, 0, 0,
2421 pbn_b0_4_921600 },
2422 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2423 0x1208, 0x0004, 0, 0,
2424 pbn_b0_4_921600 },
2425/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2426 0x1402, 0x0002, 0, 0,
2427 pbn_b0_2_921600 }, */
2428/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2429 0x1404, 0x0004, 0, 0,
2430 pbn_b0_4_921600 }, */
2431 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
2432 0x1208, 0x0004, 0, 0,
2433 pbn_b0_4_921600 },
2434
1da177e4
LT		 2435 /*
2436 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2437 */
2438 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2439 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2440 pbn_b1_1_1382400 },
2441
2442 /*
2443 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2444 */
2445 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2446 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2447 pbn_b1_1_1382400 },
2448
2449 /*
2450 * RAStel 2 port modem, gerg@moreton.com.au
2451 */
2452 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2454 pbn_b2_bt_2_115200 },
2455
2456 /*
2457 * EKF addition for i960 Boards form EKF with serial port
2458 */
2459 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2460 0xE4BF, PCI_ANY_ID, 0, 0,
2461 pbn_intel_i960 },
2462
2463 /*
2464 * Xircom Cardbus/Ethernet combos
2465 */
2466 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2467 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2468 pbn_b0_1_115200 },
2469 /*
2470 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2471 */
2472 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2473 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2474 pbn_b0_1_115200 },
2475
2476 /*
2477 * Untested PCI modems, sent in from various folks...
2478 */
2479
2480 /*
2481 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2482 */
2483 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2484 0x1048, 0x1500, 0, 0,
2485 pbn_b1_1_115200 },
2486
2487 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2488 0xFF00, 0, 0, 0,
2489 pbn_sgi_ioc3 },
2490
2491 /*
2492 * HP Diva card
2493 */
2494 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2495 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2496 pbn_b1_1_115200 },
2497 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2498 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2499 pbn_b0_5_115200 },
2500 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2501 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2502 pbn_b2_1_115200 },
2503
d9004eb4
ABL		 2504 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2505 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2506 pbn_b3_2_115200 },
1da177e4
LT		 2507 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2508 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2509 pbn_b3_4_115200 },
2510 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2511 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2512 pbn_b3_8_115200 },
2513
2514 /*
2515 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2516 */
2517 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2518 PCI_ANY_ID, PCI_ANY_ID,
2519 0,
2520 0, pbn_exar_XR17C152 },
2521 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2522 PCI_ANY_ID, PCI_ANY_ID,
2523 0,
2524 0, pbn_exar_XR17C154 },
2525 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2526 PCI_ANY_ID, PCI_ANY_ID,
2527 0,
2528 0, pbn_exar_XR17C158 },
2529
2530 /*
2531 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2532 */
2533 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2534 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2535 pbn_b0_1_115200 },
84f8c6fc
NV		 2536 /*
2537 * ITE
2538 */
2539 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2540 PCI_ANY_ID, PCI_ANY_ID,
2541 0, 0,
2542 pbn_b1_bt_1_115200 },
1da177e4 2543
737c1756
PH		 2544 /*
2545 * IntaShield IS-200
2546 */
2547 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
2548 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
2549 pbn_b2_2_115200 },
2550
48212008
TH		 2551 /*
2552 * Perle PCI-RAS cards
2553 */
2554 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2555 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
2556 0, 0, pbn_b2_4_921600 },
2557 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2558 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
2559 0, 0, pbn_b2_8_921600 },
1da177e4
LT		 2560 /*
2561 * These entries match devices with class COMMUNICATION_SERIAL,
2562 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2563 */
2564 { PCI_ANY_ID, PCI_ANY_ID,
2565 PCI_ANY_ID, PCI_ANY_ID,
2566 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2567 0xffff00, pbn_default },
2568 { PCI_ANY_ID, PCI_ANY_ID,
2569 PCI_ANY_ID, PCI_ANY_ID,
2570 PCI_CLASS_COMMUNICATION_MODEM << 8,
2571 0xffff00, pbn_default },
2572 { PCI_ANY_ID, PCI_ANY_ID,
2573 PCI_ANY_ID, PCI_ANY_ID,
2574 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2575 0xffff00, pbn_default },
2576 { 0, }
2577};
2578
2579static struct pci_driver serial_pci_driver = {
2580 .name = "serial",
2581 .probe = pciserial_init_one,
2582 .remove = __devexit_p(pciserial_remove_one),
1d5e7996 2583#ifdef CONFIG_PM
1da177e4
LT		 2584 .suspend = pciserial_suspend_one,
2585 .resume = pciserial_resume_one,
1d5e7996 2586#endif
1da177e4
LT		 2587 .id_table = serial_pci_tbl,
2588};
2589
2590static int __init serial8250_pci_init(void)
2591{
2592 return pci_register_driver(&serial_pci_driver);
2593}
2594
2595static void __exit serial8250_pci_exit(void)
2596{
2597 pci_unregister_driver(&serial_pci_driver);
2598}
2599
2600module_init(serial8250_pci_init);
2601module_exit(serial8250_pci_exit);
2602
2603MODULE_LICENSE("GPL");
2604MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2605MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
kernel source for telekom puls (alcatel/mediatek)