[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-omap2 / cpuidle34xx.c

/*
 * linux/arch/arm/mach-omap2/cpuidle34xx.c
 *
 * OMAP3 CPU IDLE Routines
 *
 * Copyright (C) 2008 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Karthik Dasu <karthik-dp@ti.com>
 *
 * Copyright (C) 2006 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * Based on pm.c for omap2
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/sched.h>
#include <linux/cpuidle.h>
#include <linux/export.h>
#include <linux/cpu_pm.h>
#include <asm/cpuidle.h>

#include "powerdomain.h"
#include "clockdomain.h"

#include "pm.h"
#include "control.h"
#include "common.h"
#include "soc.h"

/* Mach specific information to be recorded in the C-state driver_data */
struct omap3_idle_statedata {
	u8 mpu_state;
	u8 core_state;
	u8 per_min_state;
	u8 flags;
};

static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;

/*
 * Possible flag bits for struct omap3_idle_statedata.flags:
 *
 * OMAP_CPUIDLE_CX_NO_CLKDM_IDLE: don't allow the MPU clockdomain to go
 *    inactive.  This in turn prevents the MPU DPLL from entering autoidle
 *    mode, so wakeup latency is greatly reduced, at the cost of additional
 *    energy consumption.  This also prevents the CORE clockdomain from
 *    entering idle.
 */
#define OMAP_CPUIDLE_CX_NO_CLKDM_IDLE		BIT(0)

/*
 * Prevent PER OFF if CORE is not in RETention or OFF as this would
 * disable PER wakeups completely.
 */
static struct omap3_idle_statedata omap3_idle_data[] = {
	{
		.mpu_state = PWRDM_POWER_ON,
		.core_state = PWRDM_POWER_ON,
		/* In C1 do not allow PER state lower than CORE state */
		.per_min_state = PWRDM_POWER_ON,
		.flags = OMAP_CPUIDLE_CX_NO_CLKDM_IDLE,
	},
	{
		.mpu_state = PWRDM_POWER_ON,
		.core_state = PWRDM_POWER_ON,
		.per_min_state = PWRDM_POWER_RET,
	},
	{
		.mpu_state = PWRDM_POWER_RET,
		.core_state = PWRDM_POWER_ON,
		.per_min_state = PWRDM_POWER_RET,
	},
	{
		.mpu_state = PWRDM_POWER_OFF,
		.core_state = PWRDM_POWER_ON,
		.per_min_state = PWRDM_POWER_RET,
	},
	{
		.mpu_state = PWRDM_POWER_RET,
		.core_state = PWRDM_POWER_RET,
		.per_min_state = PWRDM_POWER_OFF,
	},
	{
		.mpu_state = PWRDM_POWER_OFF,
		.core_state = PWRDM_POWER_RET,
		.per_min_state = PWRDM_POWER_OFF,
	},
	{
		.mpu_state = PWRDM_POWER_OFF,
		.core_state = PWRDM_POWER_OFF,
		.per_min_state = PWRDM_POWER_OFF,
	},
};

/**
 * omap3_enter_idle - Programs OMAP3 to enter the specified state
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: the index of state to be entered
 */
static int omap3_enter_idle(struct cpuidle_device *dev,
			    struct cpuidle_driver *drv,
			    int index)
{
	struct omap3_idle_statedata *cx = &omap3_idle_data[index];

	if (omap_irq_pending() || need_resched())
		goto return_sleep_time;

	/* Deny idle for C1 */
	if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE) {
		clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]);
	} else {
		pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);
		pwrdm_set_next_pwrst(core_pd, cx->core_state);
	}

	/*
	 * Call idle CPU PM enter notifier chain so that
	 * VFP context is saved.
	 */
	if (cx->mpu_state == PWRDM_POWER_OFF)
		cpu_pm_enter();

	/* Execute ARM wfi */
	omap_sram_idle();

	/*
	 * Call idle CPU PM enter notifier chain to restore
	 * VFP context.
	 */
	if (cx->mpu_state == PWRDM_POWER_OFF &&
	    pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
		cpu_pm_exit();

	/* Re-allow idle for C1 */
	if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE)
		clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);

return_sleep_time:

	return index;
}

/**
 * next_valid_state - Find next valid C-state
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: Index of currently selected c-state
 *
 * If the state corresponding to index is valid, index is returned back
 * to the caller. Else, this function searches for a lower c-state which is
 * still valid (as defined in omap3_power_states[]) and returns its index.
 *
 * A state is valid if the 'valid' field is enabled and
 * if it satisfies the enable_off_mode condition.
 */
static int next_valid_state(struct cpuidle_device *dev,
			    struct cpuidle_driver *drv, int index)
{
	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
	u32 mpu_deepest_state = PWRDM_POWER_RET;
	u32 core_deepest_state = PWRDM_POWER_RET;
	int idx;
	int next_index = 0; /* C1 is the default value */

	if (enable_off_mode) {
		mpu_deepest_state = PWRDM_POWER_OFF;
		/*
		 * Erratum i583: valable for ES rev < Es1.2 on 3630.
		 * CORE OFF mode is not supported in a stable form, restrict
		 * instead the CORE state to RET.
		 */
		if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
			core_deepest_state = PWRDM_POWER_OFF;
	}

	/* Check if current state is valid */
	if ((cx->mpu_state >= mpu_deepest_state) &&
	    (cx->core_state >= core_deepest_state))
		return index;

	/*
	 * Drop to next valid state.
	 * Start search from the next (lower) state.
	 */
	for (idx = index - 1; idx >= 0; idx--) {
		cx = &omap3_idle_data[idx];
		if ((cx->mpu_state >= mpu_deepest_state) &&
		    (cx->core_state >= core_deepest_state)) {
			next_index = idx;
			break;
		}
	}

	return next_index;
}

/**
 * omap3_enter_idle_bm - Checks for any bus activity
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: array index of target state to be programmed
 *
 * This function checks for any pending activity and then programs
 * the device to the specified or a safer state.
 */
static int omap3_enter_idle_bm(struct cpuidle_device *dev,
			       struct cpuidle_driver *drv,
			       int index)
{
	int new_state_idx, ret;
	u8 per_next_state, per_saved_state;
	struct omap3_idle_statedata *cx;

	/*
	 * Use only C1 if CAM is active.
	 * CAM does not have wakeup capability in OMAP3.
	 */
	if (pwrdm_read_pwrst(cam_pd) == PWRDM_POWER_ON)
		new_state_idx = drv->safe_state_index;
	else
		new_state_idx = next_valid_state(dev, drv, index);

	/*
	 * FIXME: we currently manage device-specific idle states
	 *        for PER and CORE in combination with CPU-specific
	 *        idle states.  This is wrong, and device-specific
	 *        idle management needs to be separated out into
	 *        its own code.
	 */

	/* Program PER state */
	cx = &omap3_idle_data[new_state_idx];

	per_next_state = pwrdm_read_next_pwrst(per_pd);
	per_saved_state = per_next_state;
	if (per_next_state < cx->per_min_state) {
		per_next_state = cx->per_min_state;
		pwrdm_set_next_pwrst(per_pd, per_next_state);
	}

	ret = omap3_enter_idle(dev, drv, new_state_idx);

	/* Restore original PER state if it was modified */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_saved_state);

	return ret;
}

static struct cpuidle_driver omap3_idle_driver = {
	.name             = "omap3_idle",
	.owner            = THIS_MODULE,
	.states = {
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 2 + 2,
			.target_residency = 5,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C1",
			.desc		  = "MPU ON + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 10 + 10,
			.target_residency = 30,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C2",
			.desc		  = "MPU ON + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 50 + 50,
			.target_residency = 300,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C3",
			.desc		  = "MPU RET + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 1500 + 1800,
			.target_residency = 4000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C4",
			.desc		  = "MPU OFF + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 2500 + 7500,
			.target_residency = 12000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C5",
			.desc		  = "MPU RET + CORE RET",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 3000 + 8500,
			.target_residency = 15000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C6",
			.desc		  = "MPU OFF + CORE RET",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 10000 + 30000,
			.target_residency = 30000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C7",
			.desc		  = "MPU OFF + CORE OFF",
		},
	},
	.state_count = ARRAY_SIZE(omap3_idle_data),
	.safe_state_index = 0,
};

/*
 * Numbers based on measurements made in October 2009 for PM optimized kernel
 * with CPU freq enabled on device Nokia N900. Assumes OPP2 (main idle OPP,
 * and worst case latencies).
 */
static struct cpuidle_driver omap3430_idle_driver = {
	.name             = "omap3430_idle",
	.owner            = THIS_MODULE,
	.states = {
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 110 + 162,
			.target_residency = 5,
			.name		  = "C1",
			.desc		  = "MPU ON + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 106 + 180,
			.target_residency = 309,
			.name		  = "C2",
			.desc		  = "MPU ON + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 107 + 410,
			.target_residency = 46057,
			.name		  = "C3",
			.desc		  = "MPU RET + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 121 + 3374,
			.target_residency = 46057,
			.name		  = "C4",
			.desc		  = "MPU OFF + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 855 + 1146,
			.target_residency = 46057,
			.name		  = "C5",
			.desc		  = "MPU RET + CORE RET",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 7580 + 4134,
			.target_residency = 484329,
			.name		  = "C6",
			.desc		  = "MPU OFF + CORE RET",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 7505 + 15274,
			.target_residency = 484329,
			.name		  = "C7",
			.desc		  = "MPU OFF + CORE OFF",
		},
	},
	.state_count = ARRAY_SIZE(omap3_idle_data),
	.safe_state_index = 0,
};

/* Public functions */

/**
 * omap3_idle_init - Init routine for OMAP3 idle
 *
 * Registers the OMAP3 specific cpuidle driver to the cpuidle
 * framework with the valid set of states.
 */
int __init omap3_idle_init(void)
{
	mpu_pd = pwrdm_lookup("mpu_pwrdm");
	core_pd = pwrdm_lookup("core_pwrdm");
	per_pd = pwrdm_lookup("per_pwrdm");
	cam_pd = pwrdm_lookup("cam_pwrdm");

	if (!mpu_pd || !core_pd || !per_pd || !cam_pd)
		return -ENODEV;

	if (cpu_is_omap3430())
		return cpuidle_register(&omap3430_idle_driver, NULL);
	else
		return cpuidle_register(&omap3_idle_driver, NULL);
}
Commit	Line	Data
99e6a4d2 RN	1	/*
	2	* linux/arch/arm/mach-omap2/cpuidle34xx.c
	3	*
	4	* OMAP3 CPU IDLE Routines
	5	*
	6	* Copyright (C) 2008 Texas Instruments, Inc.
	7	* Rajendra Nayak <rnayak@ti.com>
	8	*
	9	* Copyright (C) 2007 Texas Instruments, Inc.
	10	* Karthik Dasu <karthik-dp@ti.com>
	11	*
	12	* Copyright (C) 2006 Nokia Corporation
	13	* Tony Lindgren <tony@atomide.com>
	14	*
	15	* Copyright (C) 2005 Texas Instruments, Inc.
	16	* Richard Woodruff <r-woodruff2@ti.com>
	17	*
	18	* Based on pm.c for omap2
	19	*
	20	* This program is free software; you can redistribute it and/or modify
	21	* it under the terms of the GNU General Public License version 2 as
	22	* published by the Free Software Foundation.
	23	*/
	24
cf22854c	25	#include <linux/sched.h>
99e6a4d2	26	#include <linux/cpuidle.h>
5698eb4e	27	#include <linux/export.h>
ff819da4	28	#include <linux/cpu_pm.h>
472a85f7	29	#include <asm/cpuidle.h>
99e6a4d2	30
72e06d08	31	#include "powerdomain.h"
1540f214	32	#include "clockdomain.h"
99e6a4d2	33
c98e2230	34	#include "pm.h"
4814ced5	35	#include "control.h"
ba8bb18a	36	#include "common.h"
26898db6	37	#include "soc.h"
c98e2230	38
badc303a JP	39	/* Mach specific information to be recorded in the C-state driver_data */
badc303a JP	40	struct omap3_idle_statedata {
fd6b42a5 PW	41	u8 mpu_state;
	42	u8 core_state;
	43	u8 per_min_state;
1cd96478	44	u8 flags;
badc303a	45	};
0c2487f6	46
9db316b6 PW	47	static struct powerdomain mpu_pd, core_pd, per_pd, cam_pd;
9db316b6 PW	48
1cd96478 PW	49	/*
	50	* Possible flag bits for struct omap3_idle_statedata.flags:
	51	*
	52	* OMAP_CPUIDLE_CX_NO_CLKDM_IDLE: don't allow the MPU clockdomain to go
	53	* inactive. This in turn prevents the MPU DPLL from entering autoidle
	54	* mode, so wakeup latency is greatly reduced, at the cost of additional
	55	* energy consumption. This also prevents the CORE clockdomain from
	56	* entering idle.
	57	*/
	58	#define OMAP_CPUIDLE_CX_NO_CLKDM_IDLE BIT(0)
	59
fd6b42a5 PW	60	/*
	61	* Prevent PER OFF if CORE is not in RETention or OFF as this would
	62	* disable PER wakeups completely.
	63	*/
97abc496	64	static struct omap3_idle_statedata omap3_idle_data[] = {
88c377dd DL	65	{
	66	.mpu_state = PWRDM_POWER_ON,
	67	.core_state = PWRDM_POWER_ON,
fd6b42a5 PW	68	/* In C1 do not allow PER state lower than CORE state */
fd6b42a5 PW	69	.per_min_state = PWRDM_POWER_ON,
1cd96478	70	.flags = OMAP_CPUIDLE_CX_NO_CLKDM_IDLE,
88c377dd DL	71	},
	72	{
	73	.mpu_state = PWRDM_POWER_ON,
	74	.core_state = PWRDM_POWER_ON,
fd6b42a5	75	.per_min_state = PWRDM_POWER_RET,
88c377dd DL	76	},
	77	{
	78	.mpu_state = PWRDM_POWER_RET,
	79	.core_state = PWRDM_POWER_ON,
fd6b42a5	80	.per_min_state = PWRDM_POWER_RET,
88c377dd DL	81	},
	82	{
	83	.mpu_state = PWRDM_POWER_OFF,
	84	.core_state = PWRDM_POWER_ON,
fd6b42a5	85	.per_min_state = PWRDM_POWER_RET,
88c377dd DL	86	},
	87	{
	88	.mpu_state = PWRDM_POWER_RET,
	89	.core_state = PWRDM_POWER_RET,
fd6b42a5	90	.per_min_state = PWRDM_POWER_OFF,
88c377dd DL	91	},
	92	{
	93	.mpu_state = PWRDM_POWER_OFF,
	94	.core_state = PWRDM_POWER_RET,
fd6b42a5	95	.per_min_state = PWRDM_POWER_OFF,
88c377dd DL	96	},
	97	{
	98	.mpu_state = PWRDM_POWER_OFF,
	99	.core_state = PWRDM_POWER_OFF,
fd6b42a5	100	.per_min_state = PWRDM_POWER_OFF,
88c377dd DL	101	},
88c377dd DL	102	};
badc303a	103
3dcb9f1b DL	104	/**
	105	* omap3_enter_idle - Programs OMAP3 to enter the specified state
	106	* @dev: cpuidle device
	107	* @drv: cpuidle driver
	108	* @index: the index of state to be entered
	109	*/
	110	static int omap3_enter_idle(struct cpuidle_device *dev,
	111	struct cpuidle_driver *drv,
	112	int index)
99e6a4d2	113	{
6622ac55	114	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
99e6a4d2	115
cf22854c	116	if (omap_irq_pending() \|\| need_resched())
20b01669	117	goto return_sleep_time;
99e6a4d2	118
badc303a	119	/* Deny idle for C1 */
1cd96478	120	if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE) {
05011f71	121	clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]);
1cd96478 PW	122	} else {
	123	pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);
	124	pwrdm_set_next_pwrst(core_pd, cx->core_state);
06d8f065 PDS	125	}
06d8f065 PDS	126
ff819da4 SS	127	/*
	128	* Call idle CPU PM enter notifier chain so that
	129	* VFP context is saved.
	130	*/
1cd96478	131	if (cx->mpu_state == PWRDM_POWER_OFF)
ff819da4 SS	132	cpu_pm_enter();
ff819da4 SS	133
99e6a4d2 RN	134	/* Execute ARM wfi */
	135	omap_sram_idle();
	136
ff819da4 SS	137	/*
	138	* Call idle CPU PM enter notifier chain to restore
	139	* VFP context.
	140	*/
1cd96478 PW	141	if (cx->mpu_state == PWRDM_POWER_OFF &&
1cd96478 PW	142	pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
ff819da4 SS	143	cpu_pm_exit();
ff819da4 SS	144
badc303a	145	/* Re-allow idle for C1 */
1cd96478	146	if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE)
05011f71	147	clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);
06d8f065	148
20b01669	149	return_sleep_time:
99e6a4d2	150
e978aa7d	151	return index;
99e6a4d2 RN	152	}
99e6a4d2 RN	153
6af83b38	154	/**
04908918	155	* next_valid_state - Find next valid C-state
6af83b38	156	* @dev: cpuidle device
46bcfad7	157	* @drv: cpuidle driver
e978aa7d	158	* @index: Index of currently selected c-state
6af83b38	159	*
e978aa7d DD	160	* If the state corresponding to index is valid, index is returned back
	161	* to the caller. Else, this function searches for a lower c-state which is
	162	* still valid (as defined in omap3_power_states[]) and returns its index.
04908918 JP	163	*
	164	* A state is valid if the 'valid' field is enabled and
	165	* if it satisfies the enable_off_mode condition.
6af83b38	166	*/
e978aa7d	167	static int next_valid_state(struct cpuidle_device *dev,
e92a4586	168	struct cpuidle_driver *drv, int index)
6af83b38	169	{
6622ac55	170	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
04908918 JP	171	u32 mpu_deepest_state = PWRDM_POWER_RET;
04908918 JP	172	u32 core_deepest_state = PWRDM_POWER_RET;
e92a4586	173	int idx;
063a5d01	174	int next_index = 0; /* C1 is the default value */
04908918 JP	175
	176	if (enable_off_mode) {
	177	mpu_deepest_state = PWRDM_POWER_OFF;
	178	/*
	179	* Erratum i583: valable for ES rev < Es1.2 on 3630.
	180	* CORE OFF mode is not supported in a stable form, restrict
	181	* instead the CORE state to RET.
	182	*/
	183	if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
	184	core_deepest_state = PWRDM_POWER_OFF;
	185	}
6af83b38 SP	186
6af83b38 SP	187	/* Check if current state is valid */
f79b5d8a	188	if ((cx->mpu_state >= mpu_deepest_state) &&
e92a4586	189	(cx->core_state >= core_deepest_state))
e978aa7d	190	return index;
6af83b38	191
e92a4586 DL	192	/*
	193	* Drop to next valid state.
	194	* Start search from the next (lower) state.
	195	*/
	196	for (idx = index - 1; idx >= 0; idx--) {
1cd96478	197	cx = &omap3_idle_data[idx];
e92a4586 DL	198	if ((cx->mpu_state >= mpu_deepest_state) &&
	199	(cx->core_state >= core_deepest_state)) {
	200	next_index = idx;
	201	break;
6af83b38	202	}
6af83b38 SP	203	}
6af83b38 SP	204
e978aa7d	205	return next_index;
6af83b38 SP	206	}
6af83b38 SP	207
99e6a4d2 RN	208	/**
	209	* omap3_enter_idle_bm - Checks for any bus activity
	210	* @dev: cpuidle device
46bcfad7	211	* @drv: cpuidle driver
e978aa7d	212	* @index: array index of target state to be programmed
99e6a4d2	213	*
badc303a JP	214	* This function checks for any pending activity and then programs
badc303a JP	215	* the device to the specified or a safer state.
99e6a4d2 RN	216	*/
99e6a4d2 RN	217	static int omap3_enter_idle_bm(struct cpuidle_device *dev,
13d65c89	218	struct cpuidle_driver *drv,
e978aa7d	219	int index)
99e6a4d2	220	{
fd6b42a5 PW	221	int new_state_idx, ret;
fd6b42a5 PW	222	u8 per_next_state, per_saved_state;
badc303a	223	struct omap3_idle_statedata *cx;
0f724ed9	224
e7410cf7	225	/*
13d65c89	226	* Use only C1 if CAM is active.
e7410cf7 KH	227	* CAM does not have wakeup capability in OMAP3.
e7410cf7 KH	228	*/
13d65c89	229	if (pwrdm_read_pwrst(cam_pd) == PWRDM_POWER_ON)
46bcfad7	230	new_state_idx = drv->safe_state_index;
13d65c89 JP	231	else
13d65c89 JP	232	new_state_idx = next_valid_state(dev, drv, index);
e7410cf7	233
c6cd91de JP	234	/*
	235	* FIXME: we currently manage device-specific idle states
	236	* for PER and CORE in combination with CPU-specific
	237	* idle states. This is wrong, and device-specific
	238	* idle management needs to be separated out into
	239	* its own code.
	240	*/
	241
13d65c89 JP	242	/* Program PER state */
13d65c89 JP	243	cx = &omap3_idle_data[new_state_idx];
0f724ed9	244
fd6b42a5 PW	245	per_next_state = pwrdm_read_next_pwrst(per_pd);
	246	per_saved_state = per_next_state;
	247	if (per_next_state < cx->per_min_state) {
	248	per_next_state = cx->per_min_state;
e7410cf7	249	pwrdm_set_next_pwrst(per_pd, per_next_state);
fd6b42a5	250	}
e7410cf7	251
46bcfad7	252	ret = omap3_enter_idle(dev, drv, new_state_idx);
e7410cf7 KH	253
	254	/* Restore original PER state if it was modified */
	255	if (per_next_state != per_saved_state)
	256	pwrdm_set_next_pwrst(per_pd, per_saved_state);
	257
	258	return ret;
99e6a4d2 RN	259	}
99e6a4d2 RN	260
9db316b6	261	static struct cpuidle_driver omap3_idle_driver = {
0d975589 DL	262	.name = "omap3_idle",
0d975589 DL	263	.owner = THIS_MODULE,
200dd520 DL	264	.states = {
200dd520 DL	265	{
13d65c89	266	.enter = omap3_enter_idle_bm,
200dd520 DL	267	.exit_latency = 2 + 2,
	268	.target_residency = 5,
	269	.flags = CPUIDLE_FLAG_TIME_VALID,
	270	.name = "C1",
	271	.desc = "MPU ON + CORE ON",
	272	},
	273	{
	274	.enter = omap3_enter_idle_bm,
	275	.exit_latency = 10 + 10,
	276	.target_residency = 30,
	277	.flags = CPUIDLE_FLAG_TIME_VALID,
	278	.name = "C2",
	279	.desc = "MPU ON + CORE ON",
	280	},
	281	{
	282	.enter = omap3_enter_idle_bm,
	283	.exit_latency = 50 + 50,
	284	.target_residency = 300,
	285	.flags = CPUIDLE_FLAG_TIME_VALID,
	286	.name = "C3",
	287	.desc = "MPU RET + CORE ON",
	288	},
	289	{
	290	.enter = omap3_enter_idle_bm,
	291	.exit_latency = 1500 + 1800,
	292	.target_residency = 4000,
	293	.flags = CPUIDLE_FLAG_TIME_VALID,
	294	.name = "C4",
	295	.desc = "MPU OFF + CORE ON",
	296	},
	297	{
	298	.enter = omap3_enter_idle_bm,
	299	.exit_latency = 2500 + 7500,
	300	.target_residency = 12000,
	301	.flags = CPUIDLE_FLAG_TIME_VALID,
	302	.name = "C5",
	303	.desc = "MPU RET + CORE RET",
	304	},
	305	{
	306	.enter = omap3_enter_idle_bm,
	307	.exit_latency = 3000 + 8500,
	308	.target_residency = 15000,
	309	.flags = CPUIDLE_FLAG_TIME_VALID,
	310	.name = "C6",
	311	.desc = "MPU OFF + CORE RET",
	312	},
	313	{
	314	.enter = omap3_enter_idle_bm,
	315	.exit_latency = 10000 + 30000,
	316	.target_residency = 30000,
	317	.flags = CPUIDLE_FLAG_TIME_VALID,
	318	.name = "C7",
	319	.desc = "MPU OFF + CORE OFF",
	320	},
	321	},
88c377dd	322	.state_count = ARRAY_SIZE(omap3_idle_data),
200dd520	323	.safe_state_index = 0,
99e6a4d2 RN	324	};
99e6a4d2 RN	325
26898db6 PR	326	/*
	327	* Numbers based on measurements made in October 2009 for PM optimized kernel
	328	* with CPU freq enabled on device Nokia N900. Assumes OPP2 (main idle OPP,
	329	* and worst case latencies).
	330	*/
	331	static struct cpuidle_driver omap3430_idle_driver = {
	332	.name = "omap3430_idle",
	333	.owner = THIS_MODULE,
	334	.states = {
	335	{
	336	.enter = omap3_enter_idle_bm,
	337	.exit_latency = 110 + 162,
	338	.target_residency = 5,
	339	.name = "C1",
	340	.desc = "MPU ON + CORE ON",
	341	},
	342	{
	343	.enter = omap3_enter_idle_bm,
	344	.exit_latency = 106 + 180,
	345	.target_residency = 309,
	346	.name = "C2",
	347	.desc = "MPU ON + CORE ON",
	348	},
	349	{
	350	.enter = omap3_enter_idle_bm,
	351	.exit_latency = 107 + 410,
	352	.target_residency = 46057,
	353	.name = "C3",
	354	.desc = "MPU RET + CORE ON",
	355	},
	356	{
	357	.enter = omap3_enter_idle_bm,
	358	.exit_latency = 121 + 3374,
	359	.target_residency = 46057,
	360	.name = "C4",
	361	.desc = "MPU OFF + CORE ON",
	362	},
	363	{
	364	.enter = omap3_enter_idle_bm,
	365	.exit_latency = 855 + 1146,
	366	.target_residency = 46057,
	367	.name = "C5",
	368	.desc = "MPU RET + CORE RET",
	369	},
	370	{
	371	.enter = omap3_enter_idle_bm,
	372	.exit_latency = 7580 + 4134,
	373	.target_residency = 484329,
	374	.name = "C6",
	375	.desc = "MPU OFF + CORE RET",
	376	},
	377	{
	378	.enter = omap3_enter_idle_bm,
	379	.exit_latency = 7505 + 15274,
	380	.target_residency = 484329,
	381	.name = "C7",
	382	.desc = "MPU OFF + CORE OFF",
	383	},
	384	},
	385	.state_count = ARRAY_SIZE(omap3_idle_data),
	386	.safe_state_index = 0,
	387	};
	388
9db316b6 PW	389	/* Public functions */
9db316b6 PW	390
99e6a4d2 RN	391	/**
	392	* omap3_idle_init - Init routine for OMAP3 idle
	393	*
badc303a	394	* Registers the OMAP3 specific cpuidle driver to the cpuidle
99e6a4d2 RN	395	* framework with the valid set of states.
99e6a4d2 RN	396	*/
0343371e	397	int __init omap3_idle_init(void)
99e6a4d2	398	{
99e6a4d2	399	mpu_pd = pwrdm_lookup("mpu_pwrdm");
20b01669	400	core_pd = pwrdm_lookup("core_pwrdm");
e7410cf7 KH	401	per_pd = pwrdm_lookup("per_pwrdm");
e7410cf7 KH	402	cam_pd = pwrdm_lookup("cam_pwrdm");
99e6a4d2	403
daa37cee DL	404	if (!mpu_pd \|\| !core_pd \|\| !per_pd \|\| !cam_pd)
	405	return -ENODEV;
	406
26898db6 PR	407	if (cpu_is_omap3430())
	408	return cpuidle_register(&omap3430_idle_driver, NULL);
	409	else
	410	return cpuidle_register(&omap3_idle_driver, NULL);
99e6a4d2	411	}