edac: edac_mc_handle_error(): add an error_count parameter
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / edac / i5000_edac.c
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1/*
2 * Intel 5000(P/V/X) class Memory Controllers kernel module
3 *
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * Written by Douglas Thompson Linux Networx (http://lnxi.com)
8 * norsk5@xmission.com
9 *
10 * This module is based on the following document:
11 *
12 * Intel 5000X Chipset Memory Controller Hub (MCH) - Datasheet
13 * http://developer.intel.com/design/chipsets/datashts/313070.htm
14 *
15 */
16
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/pci.h>
20#include <linux/pci_ids.h>
21#include <linux/slab.h>
c0d12172 22#include <linux/edac.h>
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23#include <asm/mmzone.h>
24
20bcb7a8 25#include "edac_core.h"
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26
27/*
28 * Alter this version for the I5000 module when modifications are made
29 */
152ba394 30#define I5000_REVISION " Ver: 2.0.12"
456a2f95 31#define EDAC_MOD_STR "i5000_edac"
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32
33#define i5000_printk(level, fmt, arg...) \
34 edac_printk(level, "i5000", fmt, ##arg)
35
36#define i5000_mc_printk(mci, level, fmt, arg...) \
37 edac_mc_chipset_printk(mci, level, "i5000", fmt, ##arg)
38
39#ifndef PCI_DEVICE_ID_INTEL_FBD_0
40#define PCI_DEVICE_ID_INTEL_FBD_0 0x25F5
41#endif
42#ifndef PCI_DEVICE_ID_INTEL_FBD_1
43#define PCI_DEVICE_ID_INTEL_FBD_1 0x25F6
44#endif
45
46/* Device 16,
47 * Function 0: System Address
48 * Function 1: Memory Branch Map, Control, Errors Register
49 * Function 2: FSB Error Registers
50 *
51 * All 3 functions of Device 16 (0,1,2) share the SAME DID
52 */
53#define PCI_DEVICE_ID_INTEL_I5000_DEV16 0x25F0
54
55/* OFFSETS for Function 0 */
56
57/* OFFSETS for Function 1 */
58#define AMBASE 0x48
59#define MAXCH 0x56
60#define MAXDIMMPERCH 0x57
61#define TOLM 0x6C
62#define REDMEMB 0x7C
63#define RED_ECC_LOCATOR(x) ((x) & 0x3FFFF)
64#define REC_ECC_LOCATOR_EVEN(x) ((x) & 0x001FF)
65#define REC_ECC_LOCATOR_ODD(x) ((x) & 0x3FE00)
66#define MIR0 0x80
67#define MIR1 0x84
68#define MIR2 0x88
69#define AMIR0 0x8C
70#define AMIR1 0x90
71#define AMIR2 0x94
72
73#define FERR_FAT_FBD 0x98
74#define NERR_FAT_FBD 0x9C
75#define EXTRACT_FBDCHAN_INDX(x) (((x)>>28) & 0x3)
76#define FERR_FAT_FBDCHAN 0x30000000
77#define FERR_FAT_M3ERR 0x00000004
78#define FERR_FAT_M2ERR 0x00000002
79#define FERR_FAT_M1ERR 0x00000001
052dfb45 80#define FERR_FAT_MASK (FERR_FAT_M1ERR | \
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81 FERR_FAT_M2ERR | \
82 FERR_FAT_M3ERR)
83
84#define FERR_NF_FBD 0xA0
85
86/* Thermal and SPD or BFD errors */
87#define FERR_NF_M28ERR 0x01000000
88#define FERR_NF_M27ERR 0x00800000
89#define FERR_NF_M26ERR 0x00400000
90#define FERR_NF_M25ERR 0x00200000
91#define FERR_NF_M24ERR 0x00100000
92#define FERR_NF_M23ERR 0x00080000
93#define FERR_NF_M22ERR 0x00040000
94#define FERR_NF_M21ERR 0x00020000
95
96/* Correctable errors */
97#define FERR_NF_M20ERR 0x00010000
98#define FERR_NF_M19ERR 0x00008000
99#define FERR_NF_M18ERR 0x00004000
100#define FERR_NF_M17ERR 0x00002000
101
102/* Non-Retry or redundant Retry errors */
103#define FERR_NF_M16ERR 0x00001000
104#define FERR_NF_M15ERR 0x00000800
105#define FERR_NF_M14ERR 0x00000400
106#define FERR_NF_M13ERR 0x00000200
107
108/* Uncorrectable errors */
109#define FERR_NF_M12ERR 0x00000100
110#define FERR_NF_M11ERR 0x00000080
111#define FERR_NF_M10ERR 0x00000040
112#define FERR_NF_M9ERR 0x00000020
113#define FERR_NF_M8ERR 0x00000010
114#define FERR_NF_M7ERR 0x00000008
115#define FERR_NF_M6ERR 0x00000004
116#define FERR_NF_M5ERR 0x00000002
117#define FERR_NF_M4ERR 0x00000001
118
119#define FERR_NF_UNCORRECTABLE (FERR_NF_M12ERR | \
120 FERR_NF_M11ERR | \
121 FERR_NF_M10ERR | \
c0667407 122 FERR_NF_M9ERR | \
052dfb45 123 FERR_NF_M8ERR | \
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124 FERR_NF_M7ERR | \
125 FERR_NF_M6ERR | \
126 FERR_NF_M5ERR | \
127 FERR_NF_M4ERR)
128#define FERR_NF_CORRECTABLE (FERR_NF_M20ERR | \
129 FERR_NF_M19ERR | \
130 FERR_NF_M18ERR | \
131 FERR_NF_M17ERR)
132#define FERR_NF_DIMM_SPARE (FERR_NF_M27ERR | \
133 FERR_NF_M28ERR)
134#define FERR_NF_THERMAL (FERR_NF_M26ERR | \
052dfb45 135 FERR_NF_M25ERR | \
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136 FERR_NF_M24ERR | \
137 FERR_NF_M23ERR)
138#define FERR_NF_SPD_PROTOCOL (FERR_NF_M22ERR)
139#define FERR_NF_NORTH_CRC (FERR_NF_M21ERR)
140#define FERR_NF_NON_RETRY (FERR_NF_M13ERR | \
141 FERR_NF_M14ERR | \
142 FERR_NF_M15ERR)
143
144#define NERR_NF_FBD 0xA4
145#define FERR_NF_MASK (FERR_NF_UNCORRECTABLE | \
146 FERR_NF_CORRECTABLE | \
147 FERR_NF_DIMM_SPARE | \
148 FERR_NF_THERMAL | \
149 FERR_NF_SPD_PROTOCOL | \
150 FERR_NF_NORTH_CRC | \
151 FERR_NF_NON_RETRY)
152
153#define EMASK_FBD 0xA8
154#define EMASK_FBD_M28ERR 0x08000000
155#define EMASK_FBD_M27ERR 0x04000000
156#define EMASK_FBD_M26ERR 0x02000000
157#define EMASK_FBD_M25ERR 0x01000000
158#define EMASK_FBD_M24ERR 0x00800000
159#define EMASK_FBD_M23ERR 0x00400000
160#define EMASK_FBD_M22ERR 0x00200000
161#define EMASK_FBD_M21ERR 0x00100000
162#define EMASK_FBD_M20ERR 0x00080000
163#define EMASK_FBD_M19ERR 0x00040000
164#define EMASK_FBD_M18ERR 0x00020000
165#define EMASK_FBD_M17ERR 0x00010000
166
167#define EMASK_FBD_M15ERR 0x00004000
168#define EMASK_FBD_M14ERR 0x00002000
169#define EMASK_FBD_M13ERR 0x00001000
170#define EMASK_FBD_M12ERR 0x00000800
171#define EMASK_FBD_M11ERR 0x00000400
172#define EMASK_FBD_M10ERR 0x00000200
173#define EMASK_FBD_M9ERR 0x00000100
174#define EMASK_FBD_M8ERR 0x00000080
175#define EMASK_FBD_M7ERR 0x00000040
176#define EMASK_FBD_M6ERR 0x00000020
177#define EMASK_FBD_M5ERR 0x00000010
178#define EMASK_FBD_M4ERR 0x00000008
179#define EMASK_FBD_M3ERR 0x00000004
180#define EMASK_FBD_M2ERR 0x00000002
181#define EMASK_FBD_M1ERR 0x00000001
182
183#define ENABLE_EMASK_FBD_FATAL_ERRORS (EMASK_FBD_M1ERR | \
184 EMASK_FBD_M2ERR | \
185 EMASK_FBD_M3ERR)
186
187#define ENABLE_EMASK_FBD_UNCORRECTABLE (EMASK_FBD_M4ERR | \
188 EMASK_FBD_M5ERR | \
189 EMASK_FBD_M6ERR | \
190 EMASK_FBD_M7ERR | \
191 EMASK_FBD_M8ERR | \
192 EMASK_FBD_M9ERR | \
193 EMASK_FBD_M10ERR | \
194 EMASK_FBD_M11ERR | \
195 EMASK_FBD_M12ERR)
196#define ENABLE_EMASK_FBD_CORRECTABLE (EMASK_FBD_M17ERR | \
197 EMASK_FBD_M18ERR | \
198 EMASK_FBD_M19ERR | \
199 EMASK_FBD_M20ERR)
200#define ENABLE_EMASK_FBD_DIMM_SPARE (EMASK_FBD_M27ERR | \
201 EMASK_FBD_M28ERR)
202#define ENABLE_EMASK_FBD_THERMALS (EMASK_FBD_M26ERR | \
203 EMASK_FBD_M25ERR | \
204 EMASK_FBD_M24ERR | \
205 EMASK_FBD_M23ERR)
206#define ENABLE_EMASK_FBD_SPD_PROTOCOL (EMASK_FBD_M22ERR)
207#define ENABLE_EMASK_FBD_NORTH_CRC (EMASK_FBD_M21ERR)
208#define ENABLE_EMASK_FBD_NON_RETRY (EMASK_FBD_M15ERR | \
209 EMASK_FBD_M14ERR | \
210 EMASK_FBD_M13ERR)
211
212#define ENABLE_EMASK_ALL (ENABLE_EMASK_FBD_NON_RETRY | \
213 ENABLE_EMASK_FBD_NORTH_CRC | \
214 ENABLE_EMASK_FBD_SPD_PROTOCOL | \
215 ENABLE_EMASK_FBD_THERMALS | \
216 ENABLE_EMASK_FBD_DIMM_SPARE | \
217 ENABLE_EMASK_FBD_FATAL_ERRORS | \
218 ENABLE_EMASK_FBD_CORRECTABLE | \
219 ENABLE_EMASK_FBD_UNCORRECTABLE)
220
221#define ERR0_FBD 0xAC
222#define ERR1_FBD 0xB0
223#define ERR2_FBD 0xB4
224#define MCERR_FBD 0xB8
225#define NRECMEMA 0xBE
226#define NREC_BANK(x) (((x)>>12) & 0x7)
227#define NREC_RDWR(x) (((x)>>11) & 1)
228#define NREC_RANK(x) (((x)>>8) & 0x7)
229#define NRECMEMB 0xC0
230#define NREC_CAS(x) (((x)>>16) & 0xFFFFFF)
231#define NREC_RAS(x) ((x) & 0x7FFF)
232#define NRECFGLOG 0xC4
233#define NREEECFBDA 0xC8
234#define NREEECFBDB 0xCC
235#define NREEECFBDC 0xD0
236#define NREEECFBDD 0xD4
237#define NREEECFBDE 0xD8
238#define REDMEMA 0xDC
239#define RECMEMA 0xE2
240#define REC_BANK(x) (((x)>>12) & 0x7)
241#define REC_RDWR(x) (((x)>>11) & 1)
242#define REC_RANK(x) (((x)>>8) & 0x7)
243#define RECMEMB 0xE4
244#define REC_CAS(x) (((x)>>16) & 0xFFFFFF)
245#define REC_RAS(x) ((x) & 0x7FFF)
246#define RECFGLOG 0xE8
247#define RECFBDA 0xEC
248#define RECFBDB 0xF0
249#define RECFBDC 0xF4
250#define RECFBDD 0xF8
251#define RECFBDE 0xFC
252
253/* OFFSETS for Function 2 */
254
255/*
256 * Device 21,
257 * Function 0: Memory Map Branch 0
258 *
259 * Device 22,
260 * Function 0: Memory Map Branch 1
261 */
262#define PCI_DEVICE_ID_I5000_BRANCH_0 0x25F5
263#define PCI_DEVICE_ID_I5000_BRANCH_1 0x25F6
264
265#define AMB_PRESENT_0 0x64
266#define AMB_PRESENT_1 0x66
267#define MTR0 0x80
268#define MTR1 0x84
269#define MTR2 0x88
270#define MTR3 0x8C
271
272#define NUM_MTRS 4
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273#define CHANNELS_PER_BRANCH 2
274#define MAX_BRANCHES 2
eb60705a 275
7e881856 276/* Defines to extract the various fields from the
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277 * MTRx - Memory Technology Registers
278 */
279#define MTR_DIMMS_PRESENT(mtr) ((mtr) & (0x1 << 8))
280#define MTR_DRAM_WIDTH(mtr) ((((mtr) >> 6) & 0x1) ? 8 : 4)
281#define MTR_DRAM_BANKS(mtr) ((((mtr) >> 5) & 0x1) ? 8 : 4)
282#define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)
283#define MTR_DIMM_RANK(mtr) (((mtr) >> 4) & 0x1)
977c76bd 284#define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1)
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285#define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
286#define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
287#define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
288#define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
289
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290/* enables the report of miscellaneous messages as CE errors - default off */
291static int misc_messages;
292
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293/* Enumeration of supported devices */
294enum i5000_chips {
295 I5000P = 0,
296 I5000V = 1, /* future */
297 I5000X = 2 /* future */
298};
299
300/* Device name and register DID (Device ID) */
301struct i5000_dev_info {
302 const char *ctl_name; /* name for this device */
303 u16 fsb_mapping_errors; /* DID for the branchmap,control */
304};
305
306/* Table of devices attributes supported by this driver */
307static const struct i5000_dev_info i5000_devs[] = {
308 [I5000P] = {
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309 .ctl_name = "I5000",
310 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I5000_DEV16,
311 },
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312};
313
314struct i5000_dimm_info {
315 int megabytes; /* size, 0 means not present */
316 int dual_rank;
317};
318
319#define MAX_CHANNELS 6 /* max possible channels */
320#define MAX_CSROWS (8*2) /* max possible csrows per channel */
321
322/* driver private data structure */
323struct i5000_pvt {
324 struct pci_dev *system_address; /* 16.0 */
325 struct pci_dev *branchmap_werrors; /* 16.1 */
326 struct pci_dev *fsb_error_regs; /* 16.2 */
327 struct pci_dev *branch_0; /* 21.0 */
328 struct pci_dev *branch_1; /* 22.0 */
329
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330 u16 tolm; /* top of low memory */
331 u64 ambase; /* AMB BAR */
332
333 u16 mir0, mir1, mir2;
334
335 u16 b0_mtr[NUM_MTRS]; /* Memory Technlogy Reg */
336 u16 b0_ambpresent0; /* Branch 0, Channel 0 */
337 u16 b0_ambpresent1; /* Brnach 0, Channel 1 */
338
339 u16 b1_mtr[NUM_MTRS]; /* Memory Technlogy Reg */
340 u16 b1_ambpresent0; /* Branch 1, Channel 8 */
341 u16 b1_ambpresent1; /* Branch 1, Channel 1 */
342
6f042b50 343 /* DIMM information matrix, allocating architecture maximums */
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344 struct i5000_dimm_info dimm_info[MAX_CSROWS][MAX_CHANNELS];
345
346 /* Actual values for this controller */
347 int maxch; /* Max channels */
348 int maxdimmperch; /* Max DIMMs per channel */
349};
350
351/* I5000 MCH error information retrieved from Hardware */
352struct i5000_error_info {
353
354 /* These registers are always read from the MC */
355 u32 ferr_fat_fbd; /* First Errors Fatal */
356 u32 nerr_fat_fbd; /* Next Errors Fatal */
357 u32 ferr_nf_fbd; /* First Errors Non-Fatal */
358 u32 nerr_nf_fbd; /* Next Errors Non-Fatal */
359
360 /* These registers are input ONLY if there was a Recoverable Error */
361 u32 redmemb; /* Recoverable Mem Data Error log B */
362 u16 recmema; /* Recoverable Mem Error log A */
363 u32 recmemb; /* Recoverable Mem Error log B */
364
365 /* These registers are input ONLY if there was a
366 * Non-Recoverable Error */
367 u16 nrecmema; /* Non-Recoverable Mem log A */
368 u16 nrecmemb; /* Non-Recoverable Mem log B */
369
370};
371
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372static struct edac_pci_ctl_info *i5000_pci;
373
b2ccaeca 374/*
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375 * i5000_get_error_info Retrieve the hardware error information from
376 * the hardware and cache it in the 'info'
377 * structure
378 */
379static void i5000_get_error_info(struct mem_ctl_info *mci,
b2ccaeca 380 struct i5000_error_info *info)
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381{
382 struct i5000_pvt *pvt;
383 u32 value;
384
b2ccaeca 385 pvt = mci->pvt_info;
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386
387 /* read in the 1st FATAL error register */
388 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
389
390 /* Mask only the bits that the doc says are valid
391 */
392 value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK);
393
394 /* If there is an error, then read in the */
395 /* NEXT FATAL error register and the Memory Error Log Register A */
396 if (value & FERR_FAT_MASK) {
397 info->ferr_fat_fbd = value;
398
399 /* harvest the various error data we need */
400 pci_read_config_dword(pvt->branchmap_werrors,
052dfb45 401 NERR_FAT_FBD, &info->nerr_fat_fbd);
eb60705a 402 pci_read_config_word(pvt->branchmap_werrors,
052dfb45 403 NRECMEMA, &info->nrecmema);
eb60705a 404 pci_read_config_word(pvt->branchmap_werrors,
052dfb45 405 NRECMEMB, &info->nrecmemb);
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406
407 /* Clear the error bits, by writing them back */
408 pci_write_config_dword(pvt->branchmap_werrors,
052dfb45 409 FERR_FAT_FBD, value);
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410 } else {
411 info->ferr_fat_fbd = 0;
412 info->nerr_fat_fbd = 0;
413 info->nrecmema = 0;
414 info->nrecmemb = 0;
415 }
416
417 /* read in the 1st NON-FATAL error register */
418 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
419
420 /* If there is an error, then read in the 1st NON-FATAL error
421 * register as well */
422 if (value & FERR_NF_MASK) {
423 info->ferr_nf_fbd = value;
424
425 /* harvest the various error data we need */
426 pci_read_config_dword(pvt->branchmap_werrors,
052dfb45 427 NERR_NF_FBD, &info->nerr_nf_fbd);
eb60705a 428 pci_read_config_word(pvt->branchmap_werrors,
052dfb45 429 RECMEMA, &info->recmema);
eb60705a 430 pci_read_config_dword(pvt->branchmap_werrors,
052dfb45 431 RECMEMB, &info->recmemb);
eb60705a 432 pci_read_config_dword(pvt->branchmap_werrors,
052dfb45 433 REDMEMB, &info->redmemb);
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434
435 /* Clear the error bits, by writing them back */
436 pci_write_config_dword(pvt->branchmap_werrors,
052dfb45 437 FERR_NF_FBD, value);
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438 } else {
439 info->ferr_nf_fbd = 0;
440 info->nerr_nf_fbd = 0;
441 info->recmema = 0;
442 info->recmemb = 0;
443 info->redmemb = 0;
444 }
445}
446
b2ccaeca 447/*
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448 * i5000_process_fatal_error_info(struct mem_ctl_info *mci,
449 * struct i5000_error_info *info,
450 * int handle_errors);
451 *
452 * handle the Intel FATAL errors, if any
453 */
454static void i5000_process_fatal_error_info(struct mem_ctl_info *mci,
b2ccaeca 455 struct i5000_error_info *info,
052dfb45 456 int handle_errors)
eb60705a 457{
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458 char msg[EDAC_MC_LABEL_LEN + 1 + 160];
459 char *specific = NULL;
eb60705a 460 u32 allErrors;
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461 int channel;
462 int bank;
463 int rank;
464 int rdwr;
465 int ras, cas;
466
467 /* mask off the Error bits that are possible */
468 allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK);
469 if (!allErrors)
470 return; /* if no error, return now */
471
486dfb16 472 channel = EXTRACT_FBDCHAN_INDX(info->ferr_fat_fbd);
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473
474 /* Use the NON-Recoverable macros to extract data */
475 bank = NREC_BANK(info->nrecmema);
476 rank = NREC_RANK(info->nrecmema);
477 rdwr = NREC_RDWR(info->nrecmema);
478 ras = NREC_RAS(info->nrecmemb);
479 cas = NREC_CAS(info->nrecmemb);
480
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481 edac_dbg(0, "\t\tCSROW= %d Channel= %d (DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
482 rank, channel, bank,
483 rdwr ? "Write" : "Read", ras, cas);
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484
485 /* Only 1 bit will be on */
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486 switch (allErrors) {
487 case FERR_FAT_M1ERR:
488 specific = "Alert on non-redundant retry or fast "
489 "reset timeout";
490 break;
491 case FERR_FAT_M2ERR:
492 specific = "Northbound CRC error on non-redundant "
493 "retry";
494 break;
495 case FERR_FAT_M3ERR:
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496 {
497 static int done;
498
499 /*
500 * This error is generated to inform that the intelligent
501 * throttling is disabled and the temperature passed the
502 * specified middle point. Since this is something the BIOS
503 * should take care of, we'll warn only once to avoid
504 * worthlessly flooding the log.
505 */
506 if (done)
507 return;
508 done++;
509
c0667407 510 specific = ">Tmid Thermal event with intelligent "
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511 "throttling disabled";
512 }
c0667407 513 break;
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514 }
515
516 /* Form out message */
517 snprintf(msg, sizeof(msg),
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518 "Bank=%d RAS=%d CAS=%d FATAL Err=0x%x (%s)",
519 bank, ras, cas, allErrors, specific);
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520
521 /* Call the helper to output message */
9eb07a7f 522 edac_mc_handle_error(HW_EVENT_ERR_FATAL, mci, 1, 0, 0, 0,
486dfb16 523 channel >> 1, channel & 1, rank,
702df640 524 rdwr ? "Write error" : "Read error",
03f7eae8 525 msg);
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526}
527
b2ccaeca 528/*
eb60705a 529 * i5000_process_fatal_error_info(struct mem_ctl_info *mci,
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530 * struct i5000_error_info *info,
531 * int handle_errors);
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532 *
533 * handle the Intel NON-FATAL errors, if any
534 */
535static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
b2ccaeca 536 struct i5000_error_info *info,
052dfb45 537 int handle_errors)
eb60705a 538{
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539 char msg[EDAC_MC_LABEL_LEN + 1 + 170];
540 char *specific = NULL;
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541 u32 allErrors;
542 u32 ue_errors;
543 u32 ce_errors;
544 u32 misc_errors;
545 int branch;
546 int channel;
547 int bank;
548 int rank;
549 int rdwr;
550 int ras, cas;
551
552 /* mask off the Error bits that are possible */
553 allErrors = (info->ferr_nf_fbd & FERR_NF_MASK);
554 if (!allErrors)
555 return; /* if no error, return now */
556
557 /* ONLY ONE of the possible error bits will be set, as per the docs */
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558 ue_errors = allErrors & FERR_NF_UNCORRECTABLE;
559 if (ue_errors) {
956b9ba1 560 edac_dbg(0, "\tUncorrected bits= 0x%x\n", ue_errors);
eb60705a
EW
561
562 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
118f3e1a
TV
563
564 /*
565 * According with i5000 datasheet, bit 28 has no significance
566 * for errors M4Err-M12Err and M17Err-M21Err, on FERR_NF_FBD
567 */
568 channel = branch & 2;
569
eb60705a
EW
570 bank = NREC_BANK(info->nrecmema);
571 rank = NREC_RANK(info->nrecmema);
572 rdwr = NREC_RDWR(info->nrecmema);
573 ras = NREC_RAS(info->nrecmemb);
574 cas = NREC_CAS(info->nrecmemb);
575
956b9ba1
JP
576 edac_dbg(0, "\t\tCSROW= %d Channels= %d,%d (Branch= %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
577 rank, channel, channel + 1, branch >> 1, bank,
578 rdwr ? "Write" : "Read", ras, cas);
eb60705a 579
c0667407
AR
580 switch (ue_errors) {
581 case FERR_NF_M12ERR:
582 specific = "Non-Aliased Uncorrectable Patrol Data ECC";
583 break;
584 case FERR_NF_M11ERR:
585 specific = "Non-Aliased Uncorrectable Spare-Copy "
586 "Data ECC";
587 break;
588 case FERR_NF_M10ERR:
589 specific = "Non-Aliased Uncorrectable Mirrored Demand "
590 "Data ECC";
591 break;
592 case FERR_NF_M9ERR:
593 specific = "Non-Aliased Uncorrectable Non-Mirrored "
594 "Demand Data ECC";
595 break;
596 case FERR_NF_M8ERR:
597 specific = "Aliased Uncorrectable Patrol Data ECC";
598 break;
599 case FERR_NF_M7ERR:
600 specific = "Aliased Uncorrectable Spare-Copy Data ECC";
601 break;
602 case FERR_NF_M6ERR:
603 specific = "Aliased Uncorrectable Mirrored Demand "
604 "Data ECC";
605 break;
606 case FERR_NF_M5ERR:
607 specific = "Aliased Uncorrectable Non-Mirrored Demand "
608 "Data ECC";
609 break;
610 case FERR_NF_M4ERR:
611 specific = "Uncorrectable Data ECC on Replay";
612 break;
613 }
614
eb60705a
EW
615 /* Form out message */
616 snprintf(msg, sizeof(msg),
702df640
MCC
617 "Rank=%d Bank=%d RAS=%d CAS=%d, UE Err=0x%x (%s)",
618 rank, bank, ras, cas, ue_errors, specific);
eb60705a
EW
619
620 /* Call the helper to output message */
9eb07a7f 621 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
702df640
MCC
622 channel >> 1, -1, rank,
623 rdwr ? "Write error" : "Read error",
03f7eae8 624 msg);
eb60705a
EW
625 }
626
627 /* Check correctable errors */
628 ce_errors = allErrors & FERR_NF_CORRECTABLE;
629 if (ce_errors) {
956b9ba1 630 edac_dbg(0, "\tCorrected bits= 0x%x\n", ce_errors);
eb60705a
EW
631
632 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
633
634 channel = 0;
635 if (REC_ECC_LOCATOR_ODD(info->redmemb))
636 channel = 1;
637
638 /* Convert channel to be based from zero, instead of
639 * from branch base of 0 */
640 channel += branch;
641
642 bank = REC_BANK(info->recmema);
643 rank = REC_RANK(info->recmema);
644 rdwr = REC_RDWR(info->recmema);
645 ras = REC_RAS(info->recmemb);
646 cas = REC_CAS(info->recmemb);
647
956b9ba1
JP
648 edac_dbg(0, "\t\tCSROW= %d Channel= %d (Branch %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
649 rank, channel, branch >> 1, bank,
650 rdwr ? "Write" : "Read", ras, cas);
eb60705a 651
c0667407
AR
652 switch (ce_errors) {
653 case FERR_NF_M17ERR:
654 specific = "Correctable Non-Mirrored Demand Data ECC";
655 break;
656 case FERR_NF_M18ERR:
657 specific = "Correctable Mirrored Demand Data ECC";
658 break;
659 case FERR_NF_M19ERR:
660 specific = "Correctable Spare-Copy Data ECC";
661 break;
662 case FERR_NF_M20ERR:
663 specific = "Correctable Patrol Data ECC";
664 break;
665 }
666
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667 /* Form out message */
668 snprintf(msg, sizeof(msg),
702df640 669 "Rank=%d Bank=%d RDWR=%s RAS=%d "
c0667407
AR
670 "CAS=%d, CE Err=0x%x (%s))", branch >> 1, bank,
671 rdwr ? "Write" : "Read", ras, cas, ce_errors,
672 specific);
eb60705a
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673
674 /* Call the helper to output message */
9eb07a7f 675 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0,
702df640
MCC
676 channel >> 1, channel % 2, rank,
677 rdwr ? "Write error" : "Read error",
03f7eae8 678 msg);
eb60705a
EW
679 }
680
c0667407
AR
681 if (!misc_messages)
682 return;
eb60705a 683
c0667407
AR
684 misc_errors = allErrors & (FERR_NF_NON_RETRY | FERR_NF_NORTH_CRC |
685 FERR_NF_SPD_PROTOCOL | FERR_NF_DIMM_SPARE);
eb60705a 686 if (misc_errors) {
c0667407
AR
687 switch (misc_errors) {
688 case FERR_NF_M13ERR:
689 specific = "Non-Retry or Redundant Retry FBD Memory "
690 "Alert or Redundant Fast Reset Timeout";
691 break;
692 case FERR_NF_M14ERR:
693 specific = "Non-Retry or Redundant Retry FBD "
694 "Configuration Alert";
695 break;
696 case FERR_NF_M15ERR:
697 specific = "Non-Retry or Redundant Retry FBD "
698 "Northbound CRC error on read data";
699 break;
700 case FERR_NF_M21ERR:
701 specific = "FBD Northbound CRC error on "
702 "FBD Sync Status";
703 break;
704 case FERR_NF_M22ERR:
705 specific = "SPD protocol error";
706 break;
707 case FERR_NF_M27ERR:
708 specific = "DIMM-spare copy started";
709 break;
710 case FERR_NF_M28ERR:
711 specific = "DIMM-spare copy completed";
712 break;
713 }
714 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
eb60705a 715
c0667407
AR
716 /* Form out message */
717 snprintf(msg, sizeof(msg),
702df640 718 "Err=%#x (%s)", misc_errors, specific);
eb60705a 719
c0667407 720 /* Call the helper to output message */
9eb07a7f 721 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0,
702df640 722 branch >> 1, -1, -1,
03f7eae8 723 "Misc error", msg);
eb60705a
EW
724 }
725}
726
b2ccaeca 727/*
eb60705a
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728 * i5000_process_error_info Process the error info that is
729 * in the 'info' structure, previously retrieved from hardware
730 */
731static void i5000_process_error_info(struct mem_ctl_info *mci,
b2ccaeca 732 struct i5000_error_info *info,
052dfb45 733 int handle_errors)
eb60705a
EW
734{
735 /* First handle any fatal errors that occurred */
736 i5000_process_fatal_error_info(mci, info, handle_errors);
737
738 /* now handle any non-fatal errors that occurred */
739 i5000_process_nonfatal_error_info(mci, info, handle_errors);
740}
741
b2ccaeca 742/*
eb60705a
EW
743 * i5000_clear_error Retrieve any error from the hardware
744 * but do NOT process that error.
745 * Used for 'clearing' out of previous errors
746 * Called by the Core module.
747 */
748static void i5000_clear_error(struct mem_ctl_info *mci)
749{
750 struct i5000_error_info info;
751
752 i5000_get_error_info(mci, &info);
753}
754
b2ccaeca 755/*
eb60705a
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756 * i5000_check_error Retrieve and process errors reported by the
757 * hardware. Called by the Core module.
758 */
759static void i5000_check_error(struct mem_ctl_info *mci)
760{
761 struct i5000_error_info info;
956b9ba1 762 edac_dbg(4, "MC%d\n", mci->mc_idx);
eb60705a
EW
763 i5000_get_error_info(mci, &info);
764 i5000_process_error_info(mci, &info, 1);
765}
766
b2ccaeca 767/*
eb60705a
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768 * i5000_get_devices Find and perform 'get' operation on the MCH's
769 * device/functions we want to reference for this driver
770 *
771 * Need to 'get' device 16 func 1 and func 2
772 */
773static int i5000_get_devices(struct mem_ctl_info *mci, int dev_idx)
774{
775 //const struct i5000_dev_info *i5000_dev = &i5000_devs[dev_idx];
776 struct i5000_pvt *pvt;
777 struct pci_dev *pdev;
778
b2ccaeca 779 pvt = mci->pvt_info;
eb60705a
EW
780
781 /* Attempt to 'get' the MCH register we want */
782 pdev = NULL;
783 while (1) {
784 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
052dfb45 785 PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
eb60705a
EW
786
787 /* End of list, leave */
788 if (pdev == NULL) {
789 i5000_printk(KERN_ERR,
052dfb45
DT
790 "'system address,Process Bus' "
791 "device not found:"
792 "vendor 0x%x device 0x%x FUNC 1 "
793 "(broken BIOS?)\n",
794 PCI_VENDOR_ID_INTEL,
795 PCI_DEVICE_ID_INTEL_I5000_DEV16);
eb60705a
EW
796
797 return 1;
798 }
799
800 /* Scan for device 16 func 1 */
801 if (PCI_FUNC(pdev->devfn) == 1)
802 break;
803 }
804
805 pvt->branchmap_werrors = pdev;
806
807 /* Attempt to 'get' the MCH register we want */
808 pdev = NULL;
809 while (1) {
810 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
052dfb45 811 PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
eb60705a
EW
812
813 if (pdev == NULL) {
814 i5000_printk(KERN_ERR,
052dfb45
DT
815 "MC: 'branchmap,control,errors' "
816 "device not found:"
817 "vendor 0x%x device 0x%x Func 2 "
818 "(broken BIOS?)\n",
819 PCI_VENDOR_ID_INTEL,
820 PCI_DEVICE_ID_INTEL_I5000_DEV16);
eb60705a
EW
821
822 pci_dev_put(pvt->branchmap_werrors);
823 return 1;
824 }
825
826 /* Scan for device 16 func 1 */
827 if (PCI_FUNC(pdev->devfn) == 2)
828 break;
829 }
830
831 pvt->fsb_error_regs = pdev;
832
956b9ba1
JP
833 edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s %x:%x\n",
834 pci_name(pvt->system_address),
835 pvt->system_address->vendor, pvt->system_address->device);
836 edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
837 pci_name(pvt->branchmap_werrors),
838 pvt->branchmap_werrors->vendor,
839 pvt->branchmap_werrors->device);
840 edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s %x:%x\n",
841 pci_name(pvt->fsb_error_regs),
842 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
eb60705a
EW
843
844 pdev = NULL;
845 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
052dfb45 846 PCI_DEVICE_ID_I5000_BRANCH_0, pdev);
eb60705a
EW
847
848 if (pdev == NULL) {
849 i5000_printk(KERN_ERR,
052dfb45
DT
850 "MC: 'BRANCH 0' device not found:"
851 "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
852 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_I5000_BRANCH_0);
eb60705a
EW
853
854 pci_dev_put(pvt->branchmap_werrors);
855 pci_dev_put(pvt->fsb_error_regs);
856 return 1;
857 }
858
859 pvt->branch_0 = pdev;
860
861 /* If this device claims to have more than 2 channels then
862 * fetch Branch 1's information
863 */
864 if (pvt->maxch >= CHANNELS_PER_BRANCH) {
865 pdev = NULL;
866 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
052dfb45 867 PCI_DEVICE_ID_I5000_BRANCH_1, pdev);
eb60705a
EW
868
869 if (pdev == NULL) {
870 i5000_printk(KERN_ERR,
052dfb45
DT
871 "MC: 'BRANCH 1' device not found:"
872 "vendor 0x%x device 0x%x Func 0 "
873 "(broken BIOS?)\n",
874 PCI_VENDOR_ID_INTEL,
875 PCI_DEVICE_ID_I5000_BRANCH_1);
eb60705a
EW
876
877 pci_dev_put(pvt->branchmap_werrors);
878 pci_dev_put(pvt->fsb_error_regs);
879 pci_dev_put(pvt->branch_0);
880 return 1;
881 }
882
883 pvt->branch_1 = pdev;
884 }
885
886 return 0;
887}
888
b2ccaeca 889/*
eb60705a
EW
890 * i5000_put_devices 'put' all the devices that we have
891 * reserved via 'get'
892 */
893static void i5000_put_devices(struct mem_ctl_info *mci)
894{
895 struct i5000_pvt *pvt;
896
b2ccaeca 897 pvt = mci->pvt_info;
eb60705a
EW
898
899 pci_dev_put(pvt->branchmap_werrors); /* FUNC 1 */
900 pci_dev_put(pvt->fsb_error_regs); /* FUNC 2 */
901 pci_dev_put(pvt->branch_0); /* DEV 21 */
902
903 /* Only if more than 2 channels do we release the second branch */
b2ccaeca 904 if (pvt->maxch >= CHANNELS_PER_BRANCH)
eb60705a 905 pci_dev_put(pvt->branch_1); /* DEV 22 */
eb60705a
EW
906}
907
b2ccaeca 908/*
eb60705a
EW
909 * determine_amb_resent
910 *
911 * the information is contained in NUM_MTRS different registers
912 * determineing which of the NUM_MTRS requires knowing
913 * which channel is in question
914 *
915 * 2 branches, each with 2 channels
916 * b0_ambpresent0 for channel '0'
917 * b0_ambpresent1 for channel '1'
918 * b1_ambpresent0 for channel '2'
919 * b1_ambpresent1 for channel '3'
920 */
921static int determine_amb_present_reg(struct i5000_pvt *pvt, int channel)
922{
923 int amb_present;
924
925 if (channel < CHANNELS_PER_BRANCH) {
926 if (channel & 0x1)
927 amb_present = pvt->b0_ambpresent1;
928 else
929 amb_present = pvt->b0_ambpresent0;
930 } else {
931 if (channel & 0x1)
932 amb_present = pvt->b1_ambpresent1;
933 else
934 amb_present = pvt->b1_ambpresent0;
935 }
936
937 return amb_present;
938}
939
b2ccaeca 940/*
eb60705a
EW
941 * determine_mtr(pvt, csrow, channel)
942 *
943 * return the proper MTR register as determine by the csrow and channel desired
944 */
64e1fdaf 945static int determine_mtr(struct i5000_pvt *pvt, int slot, int channel)
eb60705a
EW
946{
947 int mtr;
948
949 if (channel < CHANNELS_PER_BRANCH)
64e1fdaf 950 mtr = pvt->b0_mtr[slot];
eb60705a 951 else
64e1fdaf 952 mtr = pvt->b1_mtr[slot];
eb60705a
EW
953
954 return mtr;
955}
956
b2ccaeca 957/*
eb60705a
EW
958 */
959static void decode_mtr(int slot_row, u16 mtr)
960{
961 int ans;
962
963 ans = MTR_DIMMS_PRESENT(mtr);
964
956b9ba1
JP
965 edac_dbg(2, "\tMTR%d=0x%x: DIMMs are %sPresent\n",
966 slot_row, mtr, ans ? "" : "NOT ");
eb60705a
EW
967 if (!ans)
968 return;
969
956b9ba1
JP
970 edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
971 edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
972 edac_dbg(2, "\t\tNUMRANK: %s\n",
973 MTR_DIMM_RANK(mtr) ? "double" : "single");
974 edac_dbg(2, "\t\tNUMROW: %s\n",
975 MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" :
976 MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" :
977 MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" :
978 "reserved");
979 edac_dbg(2, "\t\tNUMCOL: %s\n",
980 MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" :
981 MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" :
982 MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" :
983 "reserved");
eb60705a
EW
984}
985
64e1fdaf 986static void handle_channel(struct i5000_pvt *pvt, int slot, int channel,
052dfb45 987 struct i5000_dimm_info *dinfo)
eb60705a
EW
988{
989 int mtr;
990 int amb_present_reg;
991 int addrBits;
992
64e1fdaf 993 mtr = determine_mtr(pvt, slot, channel);
eb60705a
EW
994 if (MTR_DIMMS_PRESENT(mtr)) {
995 amb_present_reg = determine_amb_present_reg(pvt, channel);
996
64e1fdaf
MCC
997 /* Determine if there is a DIMM present in this DIMM slot */
998 if (amb_present_reg) {
eb60705a
EW
999 dinfo->dual_rank = MTR_DIMM_RANK(mtr);
1000
64e1fdaf
MCC
1001 /* Start with the number of bits for a Bank
1002 * on the DRAM */
1003 addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);
1004 /* Add the number of ROW bits */
1005 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
1006 /* add the number of COLUMN bits */
1007 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
1008
1009 addrBits += 6; /* add 64 bits per DIMM */
1010 addrBits -= 20; /* divide by 2^^20 */
1011 addrBits -= 3; /* 8 bits per bytes */
1012
1013 dinfo->megabytes = 1 << addrBits;
eb60705a
EW
1014 }
1015 }
1016}
1017
b2ccaeca 1018/*
eb60705a
EW
1019 * calculate_dimm_size
1020 *
1021 * also will output a DIMM matrix map, if debug is enabled, for viewing
1022 * how the DIMMs are populated
1023 */
1024static void calculate_dimm_size(struct i5000_pvt *pvt)
1025{
1026 struct i5000_dimm_info *dinfo;
64e1fdaf 1027 int slot, channel, branch;
eb60705a
EW
1028 char *p, *mem_buffer;
1029 int space, n;
eb60705a
EW
1030
1031 /* ================= Generate some debug output ================= */
1032 space = PAGE_SIZE;
1033 mem_buffer = p = kmalloc(space, GFP_KERNEL);
1034 if (p == NULL) {
1035 i5000_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n",
052dfb45 1036 __FILE__, __func__);
eb60705a
EW
1037 return;
1038 }
1039
64e1fdaf 1040 /* Scan all the actual slots
eb60705a 1041 * and calculate the information for each DIMM
64e1fdaf
MCC
1042 * Start with the highest slot first, to display it first
1043 * and work toward the 0th slot
eb60705a 1044 */
64e1fdaf 1045 for (slot = pvt->maxdimmperch - 1; slot >= 0; slot--) {
eb60705a 1046
64e1fdaf 1047 /* on an odd slot, first output a 'boundary' marker,
eb60705a 1048 * then reset the message buffer */
64e1fdaf
MCC
1049 if (slot & 0x1) {
1050 n = snprintf(p, space, "--------------------------"
052dfb45 1051 "--------------------------------");
eb60705a
EW
1052 p += n;
1053 space -= n;
956b9ba1 1054 edac_dbg(2, "%s\n", mem_buffer);
eb60705a
EW
1055 p = mem_buffer;
1056 space = PAGE_SIZE;
1057 }
64e1fdaf 1058 n = snprintf(p, space, "slot %2d ", slot);
eb60705a
EW
1059 p += n;
1060 space -= n;
1061
1062 for (channel = 0; channel < pvt->maxch; channel++) {
64e1fdaf
MCC
1063 dinfo = &pvt->dimm_info[slot][channel];
1064 handle_channel(pvt, slot, channel, dinfo);
1065 if (dinfo->megabytes)
1066 n = snprintf(p, space, "%4d MB %dR| ",
1067 dinfo->megabytes, dinfo->dual_rank + 1);
1068 else
1069 n = snprintf(p, space, "%4d MB | ", 0);
eb60705a
EW
1070 p += n;
1071 space -= n;
1072 }
eb60705a
EW
1073 p += n;
1074 space -= n;
956b9ba1 1075 edac_dbg(2, "%s\n", mem_buffer);
64e1fdaf
MCC
1076 p = mem_buffer;
1077 space = PAGE_SIZE;
eb60705a
EW
1078 }
1079
1080 /* Output the last bottom 'boundary' marker */
64e1fdaf
MCC
1081 n = snprintf(p, space, "--------------------------"
1082 "--------------------------------");
eb60705a
EW
1083 p += n;
1084 space -= n;
956b9ba1 1085 edac_dbg(2, "%s\n", mem_buffer);
64e1fdaf
MCC
1086 p = mem_buffer;
1087 space = PAGE_SIZE;
eb60705a
EW
1088
1089 /* now output the 'channel' labels */
64e1fdaf 1090 n = snprintf(p, space, " ");
eb60705a
EW
1091 p += n;
1092 space -= n;
1093 for (channel = 0; channel < pvt->maxch; channel++) {
1094 n = snprintf(p, space, "channel %d | ", channel);
1095 p += n;
1096 space -= n;
1097 }
956b9ba1 1098 edac_dbg(2, "%s\n", mem_buffer);
64e1fdaf
MCC
1099 p = mem_buffer;
1100 space = PAGE_SIZE;
1101
1102 n = snprintf(p, space, " ");
eb60705a 1103 p += n;
64e1fdaf
MCC
1104 for (branch = 0; branch < MAX_BRANCHES; branch++) {
1105 n = snprintf(p, space, " branch %d | ", branch);
1106 p += n;
1107 space -= n;
1108 }
eb60705a
EW
1109
1110 /* output the last message and free buffer */
956b9ba1 1111 edac_dbg(2, "%s\n", mem_buffer);
eb60705a
EW
1112 kfree(mem_buffer);
1113}
1114
b2ccaeca 1115/*
eb60705a
EW
1116 * i5000_get_mc_regs read in the necessary registers and
1117 * cache locally
1118 *
1119 * Fills in the private data members
1120 */
1121static void i5000_get_mc_regs(struct mem_ctl_info *mci)
1122{
1123 struct i5000_pvt *pvt;
1124 u32 actual_tolm;
1125 u16 limit;
1126 int slot_row;
1127 int maxch;
1128 int maxdimmperch;
1129 int way0, way1;
1130
b2ccaeca 1131 pvt = mci->pvt_info;
eb60705a
EW
1132
1133 pci_read_config_dword(pvt->system_address, AMBASE,
052dfb45 1134 (u32 *) & pvt->ambase);
eb60705a 1135 pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
052dfb45 1136 ((u32 *) & pvt->ambase) + sizeof(u32));
eb60705a
EW
1137
1138 maxdimmperch = pvt->maxdimmperch;
1139 maxch = pvt->maxch;
1140
956b9ba1
JP
1141 edac_dbg(2, "AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n",
1142 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
eb60705a
EW
1143
1144 /* Get the Branch Map regs */
1145 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
1146 pvt->tolm >>= 12;
956b9ba1
JP
1147 edac_dbg(2, "TOLM (number of 256M regions) =%u (0x%x)\n",
1148 pvt->tolm, pvt->tolm);
eb60705a
EW
1149
1150 actual_tolm = pvt->tolm << 28;
956b9ba1
JP
1151 edac_dbg(2, "Actual TOLM byte addr=%u (0x%x)\n",
1152 actual_tolm, actual_tolm);
eb60705a
EW
1153
1154 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
1155 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
1156 pci_read_config_word(pvt->branchmap_werrors, MIR2, &pvt->mir2);
1157
1158 /* Get the MIR[0-2] regs */
1159 limit = (pvt->mir0 >> 4) & 0x0FFF;
1160 way0 = pvt->mir0 & 0x1;
1161 way1 = pvt->mir0 & 0x2;
956b9ba1
JP
1162 edac_dbg(2, "MIR0: limit= 0x%x WAY1= %u WAY0= %x\n",
1163 limit, way1, way0);
eb60705a
EW
1164 limit = (pvt->mir1 >> 4) & 0x0FFF;
1165 way0 = pvt->mir1 & 0x1;
1166 way1 = pvt->mir1 & 0x2;
956b9ba1
JP
1167 edac_dbg(2, "MIR1: limit= 0x%x WAY1= %u WAY0= %x\n",
1168 limit, way1, way0);
eb60705a
EW
1169 limit = (pvt->mir2 >> 4) & 0x0FFF;
1170 way0 = pvt->mir2 & 0x1;
1171 way1 = pvt->mir2 & 0x2;
956b9ba1
JP
1172 edac_dbg(2, "MIR2: limit= 0x%x WAY1= %u WAY0= %x\n",
1173 limit, way1, way0);
eb60705a
EW
1174
1175 /* Get the MTR[0-3] regs */
1176 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1177 int where = MTR0 + (slot_row * sizeof(u32));
1178
1179 pci_read_config_word(pvt->branch_0, where,
052dfb45 1180 &pvt->b0_mtr[slot_row]);
eb60705a 1181
956b9ba1
JP
1182 edac_dbg(2, "MTR%d where=0x%x B0 value=0x%x\n",
1183 slot_row, where, pvt->b0_mtr[slot_row]);
eb60705a
EW
1184
1185 if (pvt->maxch >= CHANNELS_PER_BRANCH) {
1186 pci_read_config_word(pvt->branch_1, where,
052dfb45 1187 &pvt->b1_mtr[slot_row]);
956b9ba1
JP
1188 edac_dbg(2, "MTR%d where=0x%x B1 value=0x%x\n",
1189 slot_row, where, pvt->b1_mtr[slot_row]);
eb60705a
EW
1190 } else {
1191 pvt->b1_mtr[slot_row] = 0;
1192 }
1193 }
1194
1195 /* Read and dump branch 0's MTRs */
956b9ba1
JP
1196 edac_dbg(2, "Memory Technology Registers:\n");
1197 edac_dbg(2, " Branch 0:\n");
eb60705a
EW
1198 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1199 decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
1200 }
1201 pci_read_config_word(pvt->branch_0, AMB_PRESENT_0,
052dfb45 1202 &pvt->b0_ambpresent0);
956b9ba1 1203 edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
eb60705a 1204 pci_read_config_word(pvt->branch_0, AMB_PRESENT_1,
052dfb45 1205 &pvt->b0_ambpresent1);
956b9ba1 1206 edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
eb60705a
EW
1207
1208 /* Only if we have 2 branchs (4 channels) */
1209 if (pvt->maxch < CHANNELS_PER_BRANCH) {
1210 pvt->b1_ambpresent0 = 0;
1211 pvt->b1_ambpresent1 = 0;
1212 } else {
1213 /* Read and dump branch 1's MTRs */
956b9ba1 1214 edac_dbg(2, " Branch 1:\n");
eb60705a
EW
1215 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1216 decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
1217 }
1218 pci_read_config_word(pvt->branch_1, AMB_PRESENT_0,
052dfb45 1219 &pvt->b1_ambpresent0);
956b9ba1
JP
1220 edac_dbg(2, "\t\tAMB-Branch 1-present0 0x%x:\n",
1221 pvt->b1_ambpresent0);
eb60705a 1222 pci_read_config_word(pvt->branch_1, AMB_PRESENT_1,
052dfb45 1223 &pvt->b1_ambpresent1);
956b9ba1
JP
1224 edac_dbg(2, "\t\tAMB-Branch 1-present1 0x%x:\n",
1225 pvt->b1_ambpresent1);
eb60705a
EW
1226 }
1227
1228 /* Go and determine the size of each DIMM and place in an
1229 * orderly matrix */
1230 calculate_dimm_size(pvt);
1231}
1232
b2ccaeca 1233/*
eb60705a
EW
1234 * i5000_init_csrows Initialize the 'csrows' table within
1235 * the mci control structure with the
1236 * addressing of memory.
1237 *
1238 * return:
1239 * 0 success
1240 * 1 no actual memory found on this MC
1241 */
1242static int i5000_init_csrows(struct mem_ctl_info *mci)
1243{
1244 struct i5000_pvt *pvt;
a895bf8b 1245 struct dimm_info *dimm;
eb60705a
EW
1246 int empty, channel_count;
1247 int max_csrows;
64e1fdaf 1248 int mtr;
eb60705a
EW
1249 int csrow_megs;
1250 int channel;
64e1fdaf 1251 int slot;
eb60705a 1252
b2ccaeca 1253 pvt = mci->pvt_info;
eb60705a
EW
1254
1255 channel_count = pvt->maxch;
1256 max_csrows = pvt->maxdimmperch * 2;
1257
1258 empty = 1; /* Assume NO memory */
1259
702df640 1260 /*
64e1fdaf
MCC
1261 * FIXME: The memory layout used to map slot/channel into the
1262 * real memory architecture is weird: branch+slot are "csrows"
1263 * and channel is channel. That required an extra array (dimm_info)
1264 * to map the dimms. A good cleanup would be to remove this array,
1265 * and do a loop here with branch, channel, slot
702df640 1266 */
64e1fdaf
MCC
1267 for (slot = 0; slot < max_csrows; slot++) {
1268 for (channel = 0; channel < pvt->maxch; channel++) {
eb60705a 1269
64e1fdaf 1270 mtr = determine_mtr(pvt, slot, channel);
eb60705a 1271
64e1fdaf
MCC
1272 if (!MTR_DIMMS_PRESENT(mtr))
1273 continue;
eb60705a 1274
64e1fdaf
MCC
1275 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
1276 channel / MAX_BRANCHES,
1277 channel % MAX_BRANCHES, slot);
eb60705a 1278
64e1fdaf 1279 csrow_megs = pvt->dimm_info[slot][channel].megabytes;
a895bf8b 1280 dimm->grain = 8;
eb60705a 1281
084a4fcc 1282 /* Assume DDR2 for now */
a895bf8b 1283 dimm->mtype = MEM_FB_DDR2;
eb60705a 1284
084a4fcc
MCC
1285 /* ask what device type on this row */
1286 if (MTR_DRAM_WIDTH(mtr))
a895bf8b 1287 dimm->dtype = DEV_X8;
084a4fcc 1288 else
a895bf8b 1289 dimm->dtype = DEV_X4;
eb60705a 1290
a895bf8b 1291 dimm->edac_mode = EDAC_S8ECD8ED;
64e1fdaf 1292 dimm->nr_pages = csrow_megs << 8;
084a4fcc 1293 }
eb60705a
EW
1294
1295 empty = 0;
1296 }
1297
1298 return empty;
1299}
1300
b2ccaeca 1301/*
eb60705a
EW
1302 * i5000_enable_error_reporting
1303 * Turn on the memory reporting features of the hardware
1304 */
1305static void i5000_enable_error_reporting(struct mem_ctl_info *mci)
1306{
1307 struct i5000_pvt *pvt;
1308 u32 fbd_error_mask;
1309
b2ccaeca 1310 pvt = mci->pvt_info;
eb60705a
EW
1311
1312 /* Read the FBD Error Mask Register */
1313 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
052dfb45 1314 &fbd_error_mask);
eb60705a
EW
1315
1316 /* Enable with a '0' */
1317 fbd_error_mask &= ~(ENABLE_EMASK_ALL);
1318
1319 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
052dfb45 1320 fbd_error_mask);
eb60705a
EW
1321}
1322
b2ccaeca 1323/*
702df640 1324 * i5000_get_dimm_and_channel_counts(pdev, &nr_csrows, &num_channels)
eb60705a
EW
1325 *
1326 * ask the device how many channels are present and how many CSROWS
1327 * as well
1328 */
1329static void i5000_get_dimm_and_channel_counts(struct pci_dev *pdev,
052dfb45
DT
1330 int *num_dimms_per_channel,
1331 int *num_channels)
eb60705a
EW
1332{
1333 u8 value;
1334
1335 /* Need to retrieve just how many channels and dimms per channel are
1336 * supported on this memory controller
1337 */
1338 pci_read_config_byte(pdev, MAXDIMMPERCH, &value);
64e1fdaf 1339 *num_dimms_per_channel = (int)value;
eb60705a
EW
1340
1341 pci_read_config_byte(pdev, MAXCH, &value);
1342 *num_channels = (int)value;
1343}
1344
b2ccaeca 1345/*
eb60705a
EW
1346 * i5000_probe1 Probe for ONE instance of device to see if it is
1347 * present.
1348 * return:
1349 * 0 for FOUND a device
1350 * < 0 for error code
1351 */
1352static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
1353{
1354 struct mem_ctl_info *mci;
702df640 1355 struct edac_mc_layer layers[3];
eb60705a
EW
1356 struct i5000_pvt *pvt;
1357 int num_channels;
1358 int num_dimms_per_channel;
eb60705a 1359
956b9ba1
JP
1360 edac_dbg(0, "MC: pdev bus %u dev=0x%x fn=0x%x\n",
1361 pdev->bus->number,
1362 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
eb60705a
EW
1363
1364 /* We only are looking for func 0 of the set */
1365 if (PCI_FUNC(pdev->devfn) != 0)
1366 return -ENODEV;
1367
1368 /* Ask the devices for the number of CSROWS and CHANNELS so
1369 * that we can calculate the memory resources, etc
1370 *
1371 * The Chipset will report what it can handle which will be greater
1372 * or equal to what the motherboard manufacturer will implement.
1373 *
1374 * As we don't have a motherboard identification routine to determine
1375 * actual number of slots/dimms per channel, we thus utilize the
1376 * resource as specified by the chipset. Thus, we might have
1377 * have more DIMMs per channel than actually on the mobo, but this
25985edc 1378 * allows the driver to support up to the chipset max, without
eb60705a
EW
1379 * some fancy mobo determination.
1380 */
1381 i5000_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel,
052dfb45 1382 &num_channels);
eb60705a 1383
956b9ba1
JP
1384 edac_dbg(0, "MC: Number of Branches=2 Channels= %d DIMMS= %d\n",
1385 num_channels, num_dimms_per_channel);
eb60705a
EW
1386
1387 /* allocate a new MC control structure */
64e1fdaf 1388
702df640 1389 layers[0].type = EDAC_MC_LAYER_BRANCH;
64e1fdaf
MCC
1390 layers[0].size = MAX_BRANCHES;
1391 layers[0].is_virt_csrow = false;
702df640 1392 layers[1].type = EDAC_MC_LAYER_CHANNEL;
64e1fdaf 1393 layers[1].size = num_channels / MAX_BRANCHES;
702df640
MCC
1394 layers[1].is_virt_csrow = false;
1395 layers[2].type = EDAC_MC_LAYER_SLOT;
1396 layers[2].size = num_dimms_per_channel;
1397 layers[2].is_virt_csrow = true;
ca0907b9 1398 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
eb60705a
EW
1399 if (mci == NULL)
1400 return -ENOMEM;
1401
956b9ba1 1402 edac_dbg(0, "MC: mci = %p\n", mci);
eb60705a 1403
fd687502 1404 mci->pdev = &pdev->dev; /* record ptr to the generic device */
eb60705a 1405
b2ccaeca 1406 pvt = mci->pvt_info;
eb60705a
EW
1407 pvt->system_address = pdev; /* Record this device in our private */
1408 pvt->maxch = num_channels;
1409 pvt->maxdimmperch = num_dimms_per_channel;
1410
1411 /* 'get' the pci devices we want to reserve for our use */
1412 if (i5000_get_devices(mci, dev_idx))
1413 goto fail0;
1414
1415 /* Time to get serious */
1416 i5000_get_mc_regs(mci); /* retrieve the hardware registers */
1417
1418 mci->mc_idx = 0;
1419 mci->mtype_cap = MEM_FLAG_FB_DDR2;
1420 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1421 mci->edac_cap = EDAC_FLAG_NONE;
1422 mci->mod_name = "i5000_edac.c";
1423 mci->mod_ver = I5000_REVISION;
1424 mci->ctl_name = i5000_devs[dev_idx].ctl_name;
c4192705 1425 mci->dev_name = pci_name(pdev);
eb60705a
EW
1426 mci->ctl_page_to_phys = NULL;
1427
1428 /* Set the function pointer to an actual operation function */
1429 mci->edac_check = i5000_check_error;
1430
1431 /* initialize the MC control structure 'csrows' table
1432 * with the mapping and control information */
1433 if (i5000_init_csrows(mci)) {
956b9ba1 1434 edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i5000_init_csrows() returned nonzero value\n");
eb60705a
EW
1435 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
1436 } else {
956b9ba1 1437 edac_dbg(1, "MC: Enable error reporting now\n");
eb60705a
EW
1438 i5000_enable_error_reporting(mci);
1439 }
1440
1441 /* add this new MC control structure to EDAC's list of MCs */
b8f6f975 1442 if (edac_mc_add_mc(mci)) {
956b9ba1 1443 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
eb60705a
EW
1444 /* FIXME: perhaps some code should go here that disables error
1445 * reporting if we just enabled it
1446 */
1447 goto fail1;
1448 }
1449
1450 i5000_clear_error(mci);
1451
456a2f95
DJ
1452 /* allocating generic PCI control info */
1453 i5000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1454 if (!i5000_pci) {
1455 printk(KERN_WARNING
1456 "%s(): Unable to create PCI control\n",
1457 __func__);
1458 printk(KERN_WARNING
1459 "%s(): PCI error report via EDAC not setup\n",
1460 __func__);
1461 }
1462
eb60705a
EW
1463 return 0;
1464
1465 /* Error exit unwinding stack */
052dfb45 1466fail1:
eb60705a
EW
1467
1468 i5000_put_devices(mci);
1469
052dfb45 1470fail0:
eb60705a
EW
1471 edac_mc_free(mci);
1472 return -ENODEV;
1473}
1474
b2ccaeca 1475/*
eb60705a
EW
1476 * i5000_init_one constructor for one instance of device
1477 *
1478 * returns:
1479 * negative on error
1480 * count (>= 0)
1481 */
1482static int __devinit i5000_init_one(struct pci_dev *pdev,
052dfb45 1483 const struct pci_device_id *id)
eb60705a
EW
1484{
1485 int rc;
1486
956b9ba1 1487 edac_dbg(0, "MC:\n");
eb60705a
EW
1488
1489 /* wake up device */
1490 rc = pci_enable_device(pdev);
44aa80f0 1491 if (rc)
eb60705a
EW
1492 return rc;
1493
1494 /* now probe and enable the device */
1495 return i5000_probe1(pdev, id->driver_data);
1496}
1497
b2ccaeca 1498/*
eb60705a
EW
1499 * i5000_remove_one destructor for one instance of device
1500 *
1501 */
1502static void __devexit i5000_remove_one(struct pci_dev *pdev)
1503{
1504 struct mem_ctl_info *mci;
1505
956b9ba1 1506 edac_dbg(0, "\n");
eb60705a 1507
456a2f95
DJ
1508 if (i5000_pci)
1509 edac_pci_release_generic_ctl(i5000_pci);
1510
eb60705a
EW
1511 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
1512 return;
1513
1514 /* retrieve references to resources, and free those resources */
1515 i5000_put_devices(mci);
eb60705a
EW
1516 edac_mc_free(mci);
1517}
1518
b2ccaeca 1519/*
eb60705a
EW
1520 * pci_device_id table for which devices we are looking for
1521 *
1522 * The "E500P" device is the first device supported.
1523 */
36c46f31 1524static DEFINE_PCI_DEVICE_TABLE(i5000_pci_tbl) = {
eb60705a
EW
1525 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000_DEV16),
1526 .driver_data = I5000P},
1527
1528 {0,} /* 0 terminated list. */
1529};
1530
1531MODULE_DEVICE_TABLE(pci, i5000_pci_tbl);
1532
b2ccaeca 1533/*
eb60705a
EW
1534 * i5000_driver pci_driver structure for this module
1535 *
1536 */
1537static struct pci_driver i5000_driver = {
57510c2f 1538 .name = KBUILD_BASENAME,
eb60705a
EW
1539 .probe = i5000_init_one,
1540 .remove = __devexit_p(i5000_remove_one),
1541 .id_table = i5000_pci_tbl,
1542};
1543
b2ccaeca 1544/*
eb60705a
EW
1545 * i5000_init Module entry function
1546 * Try to initialize this module for its devices
1547 */
1548static int __init i5000_init(void)
1549{
1550 int pci_rc;
1551
956b9ba1 1552 edac_dbg(2, "MC:\n");
eb60705a 1553
c3c52bce
HM
1554 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1555 opstate_init();
1556
eb60705a
EW
1557 pci_rc = pci_register_driver(&i5000_driver);
1558
1559 return (pci_rc < 0) ? pci_rc : 0;
1560}
1561
b2ccaeca 1562/*
eb60705a
EW
1563 * i5000_exit() Module exit function
1564 * Unregister the driver
1565 */
1566static void __exit i5000_exit(void)
1567{
956b9ba1 1568 edac_dbg(2, "MC:\n");
eb60705a
EW
1569 pci_unregister_driver(&i5000_driver);
1570}
1571
1572module_init(i5000_init);
1573module_exit(i5000_exit);
1574
1575MODULE_LICENSE("GPL");
1576MODULE_AUTHOR
1577 ("Linux Networx (http://lnxi.com) Doug Thompson <norsk5@xmission.com>");
1578MODULE_DESCRIPTION("MC Driver for Intel I5000 memory controllers - "
052dfb45 1579 I5000_REVISION);
c3c52bce 1580
c0d12172
DJ
1581module_param(edac_op_state, int, 0444);
1582MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
c0667407
AR
1583module_param(misc_messages, int, 0444);
1584MODULE_PARM_DESC(misc_messages, "Log miscellaneous non fatal messages");
1585