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drivers/edac: fix leaf sysfs attribute
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / edac / i5000_edac.c
CommitLineData
eb60705a
EW		 1/*
2 * Intel 5000(P/V/X) class Memory Controllers kernel module
3 *
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * Written by Douglas Thompson Linux Networx (http://lnxi.com)
8 * norsk5@xmission.com
9 *
10 * This module is based on the following document:
11 *
12 * Intel 5000X Chipset Memory Controller Hub (MCH) - Datasheet
13 * http://developer.intel.com/design/chipsets/datashts/313070.htm
14 *
15 */
16
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/pci.h>
20#include <linux/pci_ids.h>
21#include <linux/slab.h>
c0d12172 22#include <linux/edac.h>
eb60705a
EW		 23#include <asm/mmzone.h>
24
20bcb7a8 25#include "edac_core.h"
eb60705a
EW		 26
27/*
28 * Alter this version for the I5000 module when modifications are made
29 */
20bcb7a8 30#define I5000_REVISION " Ver: 2.0.12 " __DATE__
456a2f95 31#define EDAC_MOD_STR "i5000_edac"
eb60705a
EW		 32
33#define i5000_printk(level, fmt, arg...) \
34 edac_printk(level, "i5000", fmt, ##arg)
35
36#define i5000_mc_printk(mci, level, fmt, arg...) \
37 edac_mc_chipset_printk(mci, level, "i5000", fmt, ##arg)
38
39#ifndef PCI_DEVICE_ID_INTEL_FBD_0
40#define PCI_DEVICE_ID_INTEL_FBD_0 0x25F5
41#endif
42#ifndef PCI_DEVICE_ID_INTEL_FBD_1
43#define PCI_DEVICE_ID_INTEL_FBD_1 0x25F6
44#endif
45
46/* Device 16,
47 * Function 0: System Address
48 * Function 1: Memory Branch Map, Control, Errors Register
49 * Function 2: FSB Error Registers
50 *
51 * All 3 functions of Device 16 (0,1,2) share the SAME DID
52 */
53#define PCI_DEVICE_ID_INTEL_I5000_DEV16 0x25F0
54
55/* OFFSETS for Function 0 */
56
57/* OFFSETS for Function 1 */
58#define AMBASE 0x48
59#define MAXCH 0x56
60#define MAXDIMMPERCH 0x57
61#define TOLM 0x6C
62#define REDMEMB 0x7C
63#define RED_ECC_LOCATOR(x) ((x) & 0x3FFFF)
64#define REC_ECC_LOCATOR_EVEN(x) ((x) & 0x001FF)
65#define REC_ECC_LOCATOR_ODD(x) ((x) & 0x3FE00)
66#define MIR0 0x80
67#define MIR1 0x84
68#define MIR2 0x88
69#define AMIR0 0x8C
70#define AMIR1 0x90
71#define AMIR2 0x94
72
73#define FERR_FAT_FBD 0x98
74#define NERR_FAT_FBD 0x9C
75#define EXTRACT_FBDCHAN_INDX(x) (((x)>>28) & 0x3)
76#define FERR_FAT_FBDCHAN 0x30000000
77#define FERR_FAT_M3ERR 0x00000004
78#define FERR_FAT_M2ERR 0x00000002
79#define FERR_FAT_M1ERR 0x00000001
052dfb45 80#define FERR_FAT_MASK (FERR_FAT_M1ERR | \
eb60705a
EW		 81 FERR_FAT_M2ERR | \
82 FERR_FAT_M3ERR)
83
84#define FERR_NF_FBD 0xA0
85
86/* Thermal and SPD or BFD errors */
87#define FERR_NF_M28ERR 0x01000000
88#define FERR_NF_M27ERR 0x00800000
89#define FERR_NF_M26ERR 0x00400000
90#define FERR_NF_M25ERR 0x00200000
91#define FERR_NF_M24ERR 0x00100000
92#define FERR_NF_M23ERR 0x00080000
93#define FERR_NF_M22ERR 0x00040000
94#define FERR_NF_M21ERR 0x00020000
95
96/* Correctable errors */
97#define FERR_NF_M20ERR 0x00010000
98#define FERR_NF_M19ERR 0x00008000
99#define FERR_NF_M18ERR 0x00004000
100#define FERR_NF_M17ERR 0x00002000
101
102/* Non-Retry or redundant Retry errors */
103#define FERR_NF_M16ERR 0x00001000
104#define FERR_NF_M15ERR 0x00000800
105#define FERR_NF_M14ERR 0x00000400
106#define FERR_NF_M13ERR 0x00000200
107
108/* Uncorrectable errors */
109#define FERR_NF_M12ERR 0x00000100
110#define FERR_NF_M11ERR 0x00000080
111#define FERR_NF_M10ERR 0x00000040
112#define FERR_NF_M9ERR 0x00000020
113#define FERR_NF_M8ERR 0x00000010
114#define FERR_NF_M7ERR 0x00000008
115#define FERR_NF_M6ERR 0x00000004
116#define FERR_NF_M5ERR 0x00000002
117#define FERR_NF_M4ERR 0x00000001
118
119#define FERR_NF_UNCORRECTABLE (FERR_NF_M12ERR | \
120 FERR_NF_M11ERR | \
121 FERR_NF_M10ERR | \
052dfb45 122 FERR_NF_M8ERR | \
eb60705a
EW		 123 FERR_NF_M7ERR | \
124 FERR_NF_M6ERR | \
125 FERR_NF_M5ERR | \
126 FERR_NF_M4ERR)
127#define FERR_NF_CORRECTABLE (FERR_NF_M20ERR | \
128 FERR_NF_M19ERR | \
129 FERR_NF_M18ERR | \
130 FERR_NF_M17ERR)
131#define FERR_NF_DIMM_SPARE (FERR_NF_M27ERR | \
132 FERR_NF_M28ERR)
133#define FERR_NF_THERMAL (FERR_NF_M26ERR | \
052dfb45 134 FERR_NF_M25ERR | \
eb60705a
EW		 135 FERR_NF_M24ERR | \
136 FERR_NF_M23ERR)
137#define FERR_NF_SPD_PROTOCOL (FERR_NF_M22ERR)
138#define FERR_NF_NORTH_CRC (FERR_NF_M21ERR)
139#define FERR_NF_NON_RETRY (FERR_NF_M13ERR | \
140 FERR_NF_M14ERR | \
141 FERR_NF_M15ERR)
142
143#define NERR_NF_FBD 0xA4
144#define FERR_NF_MASK (FERR_NF_UNCORRECTABLE | \
145 FERR_NF_CORRECTABLE | \
146 FERR_NF_DIMM_SPARE | \
147 FERR_NF_THERMAL | \
148 FERR_NF_SPD_PROTOCOL | \
149 FERR_NF_NORTH_CRC | \
150 FERR_NF_NON_RETRY)
151
152#define EMASK_FBD 0xA8
153#define EMASK_FBD_M28ERR 0x08000000
154#define EMASK_FBD_M27ERR 0x04000000
155#define EMASK_FBD_M26ERR 0x02000000
156#define EMASK_FBD_M25ERR 0x01000000
157#define EMASK_FBD_M24ERR 0x00800000
158#define EMASK_FBD_M23ERR 0x00400000
159#define EMASK_FBD_M22ERR 0x00200000
160#define EMASK_FBD_M21ERR 0x00100000
161#define EMASK_FBD_M20ERR 0x00080000
162#define EMASK_FBD_M19ERR 0x00040000
163#define EMASK_FBD_M18ERR 0x00020000
164#define EMASK_FBD_M17ERR 0x00010000
165
166#define EMASK_FBD_M15ERR 0x00004000
167#define EMASK_FBD_M14ERR 0x00002000
168#define EMASK_FBD_M13ERR 0x00001000
169#define EMASK_FBD_M12ERR 0x00000800
170#define EMASK_FBD_M11ERR 0x00000400
171#define EMASK_FBD_M10ERR 0x00000200
172#define EMASK_FBD_M9ERR 0x00000100
173#define EMASK_FBD_M8ERR 0x00000080
174#define EMASK_FBD_M7ERR 0x00000040
175#define EMASK_FBD_M6ERR 0x00000020
176#define EMASK_FBD_M5ERR 0x00000010
177#define EMASK_FBD_M4ERR 0x00000008
178#define EMASK_FBD_M3ERR 0x00000004
179#define EMASK_FBD_M2ERR 0x00000002
180#define EMASK_FBD_M1ERR 0x00000001
181
182#define ENABLE_EMASK_FBD_FATAL_ERRORS (EMASK_FBD_M1ERR | \
183 EMASK_FBD_M2ERR | \
184 EMASK_FBD_M3ERR)
185
186#define ENABLE_EMASK_FBD_UNCORRECTABLE (EMASK_FBD_M4ERR | \
187 EMASK_FBD_M5ERR | \
188 EMASK_FBD_M6ERR | \
189 EMASK_FBD_M7ERR | \
190 EMASK_FBD_M8ERR | \
191 EMASK_FBD_M9ERR | \
192 EMASK_FBD_M10ERR | \
193 EMASK_FBD_M11ERR | \
194 EMASK_FBD_M12ERR)
195#define ENABLE_EMASK_FBD_CORRECTABLE (EMASK_FBD_M17ERR | \
196 EMASK_FBD_M18ERR | \
197 EMASK_FBD_M19ERR | \
198 EMASK_FBD_M20ERR)
199#define ENABLE_EMASK_FBD_DIMM_SPARE (EMASK_FBD_M27ERR | \
200 EMASK_FBD_M28ERR)
201#define ENABLE_EMASK_FBD_THERMALS (EMASK_FBD_M26ERR | \
202 EMASK_FBD_M25ERR | \
203 EMASK_FBD_M24ERR | \
204 EMASK_FBD_M23ERR)
205#define ENABLE_EMASK_FBD_SPD_PROTOCOL (EMASK_FBD_M22ERR)
206#define ENABLE_EMASK_FBD_NORTH_CRC (EMASK_FBD_M21ERR)
207#define ENABLE_EMASK_FBD_NON_RETRY (EMASK_FBD_M15ERR | \
208 EMASK_FBD_M14ERR | \
209 EMASK_FBD_M13ERR)
210
211#define ENABLE_EMASK_ALL (ENABLE_EMASK_FBD_NON_RETRY | \
212 ENABLE_EMASK_FBD_NORTH_CRC | \
213 ENABLE_EMASK_FBD_SPD_PROTOCOL | \
214 ENABLE_EMASK_FBD_THERMALS | \
215 ENABLE_EMASK_FBD_DIMM_SPARE | \
216 ENABLE_EMASK_FBD_FATAL_ERRORS | \
217 ENABLE_EMASK_FBD_CORRECTABLE | \
218 ENABLE_EMASK_FBD_UNCORRECTABLE)
219
220#define ERR0_FBD 0xAC
221#define ERR1_FBD 0xB0
222#define ERR2_FBD 0xB4
223#define MCERR_FBD 0xB8
224#define NRECMEMA 0xBE
225#define NREC_BANK(x) (((x)>>12) & 0x7)
226#define NREC_RDWR(x) (((x)>>11) & 1)
227#define NREC_RANK(x) (((x)>>8) & 0x7)
228#define NRECMEMB 0xC0
229#define NREC_CAS(x) (((x)>>16) & 0xFFFFFF)
230#define NREC_RAS(x) ((x) & 0x7FFF)
231#define NRECFGLOG 0xC4
232#define NREEECFBDA 0xC8
233#define NREEECFBDB 0xCC
234#define NREEECFBDC 0xD0
235#define NREEECFBDD 0xD4
236#define NREEECFBDE 0xD8
237#define REDMEMA 0xDC
238#define RECMEMA 0xE2
239#define REC_BANK(x) (((x)>>12) & 0x7)
240#define REC_RDWR(x) (((x)>>11) & 1)
241#define REC_RANK(x) (((x)>>8) & 0x7)
242#define RECMEMB 0xE4
243#define REC_CAS(x) (((x)>>16) & 0xFFFFFF)
244#define REC_RAS(x) ((x) & 0x7FFF)
245#define RECFGLOG 0xE8
246#define RECFBDA 0xEC
247#define RECFBDB 0xF0
248#define RECFBDC 0xF4
249#define RECFBDD 0xF8
250#define RECFBDE 0xFC
251
252/* OFFSETS for Function 2 */
253
254/*
255 * Device 21,
256 * Function 0: Memory Map Branch 0
257 *
258 * Device 22,
259 * Function 0: Memory Map Branch 1
260 */
261#define PCI_DEVICE_ID_I5000_BRANCH_0 0x25F5
262#define PCI_DEVICE_ID_I5000_BRANCH_1 0x25F6
263
264#define AMB_PRESENT_0 0x64
265#define AMB_PRESENT_1 0x66
266#define MTR0 0x80
267#define MTR1 0x84
268#define MTR2 0x88
269#define MTR3 0x8C
270
271#define NUM_MTRS 4
272#define CHANNELS_PER_BRANCH (2)
273
274/* Defines to extract the vaious fields from the
275 * MTRx - Memory Technology Registers
276 */
277#define MTR_DIMMS_PRESENT(mtr) ((mtr) & (0x1 << 8))
278#define MTR_DRAM_WIDTH(mtr) ((((mtr) >> 6) & 0x1) ? 8 : 4)
279#define MTR_DRAM_BANKS(mtr) ((((mtr) >> 5) & 0x1) ? 8 : 4)
280#define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)
281#define MTR_DIMM_RANK(mtr) (((mtr) >> 4) & 0x1)
977c76bd 282#define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1)
eb60705a
EW		 283#define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
284#define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
285#define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
286#define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
287
288#ifdef CONFIG_EDAC_DEBUG
289static char *numrow_toString[] = {
290 "8,192 - 13 rows",
291 "16,384 - 14 rows",
292 "32,768 - 15 rows",
293 "reserved"
294};
295
296static char *numcol_toString[] = {
297 "1,024 - 10 columns",
298 "2,048 - 11 columns",
299 "4,096 - 12 columns",
300 "reserved"
301};
302#endif
303
304/* Enumeration of supported devices */
305enum i5000_chips {
306 I5000P = 0,
307 I5000V = 1, /* future */
308 I5000X = 2 /* future */
309};
310
311/* Device name and register DID (Device ID) */
312struct i5000_dev_info {
313 const char *ctl_name; /* name for this device */
314 u16 fsb_mapping_errors; /* DID for the branchmap,control */
315};
316
317/* Table of devices attributes supported by this driver */
318static const struct i5000_dev_info i5000_devs[] = {
319 [I5000P] = {
052dfb45
DT		 320 .ctl_name = "I5000",
321 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I5000_DEV16,
322 },
eb60705a
EW		 323};
324
325struct i5000_dimm_info {
326 int megabytes; /* size, 0 means not present */
327 int dual_rank;
328};
329
330#define MAX_CHANNELS 6 /* max possible channels */
331#define MAX_CSROWS (8*2) /* max possible csrows per channel */
332
333/* driver private data structure */
334struct i5000_pvt {
335 struct pci_dev *system_address; /* 16.0 */
336 struct pci_dev *branchmap_werrors; /* 16.1 */
337 struct pci_dev *fsb_error_regs; /* 16.2 */
338 struct pci_dev *branch_0; /* 21.0 */
339 struct pci_dev *branch_1; /* 22.0 */
340
341 int node_id; /* ID of this node */
342
343 u16 tolm; /* top of low memory */
344 u64 ambase; /* AMB BAR */
345
346 u16 mir0, mir1, mir2;
347
348 u16 b0_mtr[NUM_MTRS]; /* Memory Technlogy Reg */
349 u16 b0_ambpresent0; /* Branch 0, Channel 0 */
350 u16 b0_ambpresent1; /* Brnach 0, Channel 1 */
351
352 u16 b1_mtr[NUM_MTRS]; /* Memory Technlogy Reg */
353 u16 b1_ambpresent0; /* Branch 1, Channel 8 */
354 u16 b1_ambpresent1; /* Branch 1, Channel 1 */
355
356 /* DIMM infomation matrix, allocating architecture maximums */
357 struct i5000_dimm_info dimm_info[MAX_CSROWS][MAX_CHANNELS];
358
359 /* Actual values for this controller */
360 int maxch; /* Max channels */
361 int maxdimmperch; /* Max DIMMs per channel */
362};
363
364/* I5000 MCH error information retrieved from Hardware */
365struct i5000_error_info {
366
367 /* These registers are always read from the MC */
368 u32 ferr_fat_fbd; /* First Errors Fatal */
369 u32 nerr_fat_fbd; /* Next Errors Fatal */
370 u32 ferr_nf_fbd; /* First Errors Non-Fatal */
371 u32 nerr_nf_fbd; /* Next Errors Non-Fatal */
372
373 /* These registers are input ONLY if there was a Recoverable Error */
374 u32 redmemb; /* Recoverable Mem Data Error log B */
375 u16 recmema; /* Recoverable Mem Error log A */
376 u32 recmemb; /* Recoverable Mem Error log B */
377
378 /* These registers are input ONLY if there was a
379 * Non-Recoverable Error */
380 u16 nrecmema; /* Non-Recoverable Mem log A */
381 u16 nrecmemb; /* Non-Recoverable Mem log B */
382
383};
384
456a2f95
DJ		 385static struct edac_pci_ctl_info *i5000_pci;
386
b2ccaeca 387/*
eb60705a
EW		 388 * i5000_get_error_info Retrieve the hardware error information from
389 * the hardware and cache it in the 'info'
390 * structure
391 */
392static void i5000_get_error_info(struct mem_ctl_info *mci,
b2ccaeca 393 struct i5000_error_info *info)
eb60705a
EW		 394{
395 struct i5000_pvt *pvt;
396 u32 value;
397
b2ccaeca 398 pvt = mci->pvt_info;
eb60705a
EW		 399
400 /* read in the 1st FATAL error register */
401 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
402
403 /* Mask only the bits that the doc says are valid
404 */
405 value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK);
406
407 /* If there is an error, then read in the */
408 /* NEXT FATAL error register and the Memory Error Log Register A */
409 if (value & FERR_FAT_MASK) {
410 info->ferr_fat_fbd = value;
411
412 /* harvest the various error data we need */
413 pci_read_config_dword(pvt->branchmap_werrors,
052dfb45 414 NERR_FAT_FBD, &info->nerr_fat_fbd);
eb60705a 415 pci_read_config_word(pvt->branchmap_werrors,
052dfb45 416 NRECMEMA, &info->nrecmema);
eb60705a 417 pci_read_config_word(pvt->branchmap_werrors,
052dfb45 418 NRECMEMB, &info->nrecmemb);
eb60705a
EW		 419
420 /* Clear the error bits, by writing them back */
421 pci_write_config_dword(pvt->branchmap_werrors,
052dfb45 422 FERR_FAT_FBD, value);
eb60705a
EW		 423 } else {
424 info->ferr_fat_fbd = 0;
425 info->nerr_fat_fbd = 0;
426 info->nrecmema = 0;
427 info->nrecmemb = 0;
428 }
429
430 /* read in the 1st NON-FATAL error register */
431 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
432
433 /* If there is an error, then read in the 1st NON-FATAL error
434 * register as well */
435 if (value & FERR_NF_MASK) {
436 info->ferr_nf_fbd = value;
437
438 /* harvest the various error data we need */
439 pci_read_config_dword(pvt->branchmap_werrors,
052dfb45 440 NERR_NF_FBD, &info->nerr_nf_fbd);
eb60705a 441 pci_read_config_word(pvt->branchmap_werrors,
052dfb45 442 RECMEMA, &info->recmema);
eb60705a 443 pci_read_config_dword(pvt->branchmap_werrors,
052dfb45 444 RECMEMB, &info->recmemb);
eb60705a 445 pci_read_config_dword(pvt->branchmap_werrors,
052dfb45 446 REDMEMB, &info->redmemb);
eb60705a
EW		 447
448 /* Clear the error bits, by writing them back */
449 pci_write_config_dword(pvt->branchmap_werrors,
052dfb45 450 FERR_NF_FBD, value);
eb60705a
EW		 451 } else {
452 info->ferr_nf_fbd = 0;
453 info->nerr_nf_fbd = 0;
454 info->recmema = 0;
455 info->recmemb = 0;
456 info->redmemb = 0;
457 }
458}
459
b2ccaeca 460/*
eb60705a
EW		 461 * i5000_process_fatal_error_info(struct mem_ctl_info *mci,
462 * struct i5000_error_info *info,
463 * int handle_errors);
464 *
465 * handle the Intel FATAL errors, if any
466 */
467static void i5000_process_fatal_error_info(struct mem_ctl_info *mci,
b2ccaeca 468 struct i5000_error_info *info,
052dfb45 469 int handle_errors)
eb60705a
EW		 470{
471 char msg[EDAC_MC_LABEL_LEN + 1 + 90];
472 u32 allErrors;
473 int branch;
474 int channel;
475 int bank;
476 int rank;
477 int rdwr;
478 int ras, cas;
479
480 /* mask off the Error bits that are possible */
481 allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK);
482 if (!allErrors)
483 return; /* if no error, return now */
484
485 /* ONLY ONE of the possible error bits will be set, as per the docs */
486 i5000_mc_printk(mci, KERN_ERR,
487 "FATAL ERRORS Found!!! 1st FATAL Err Reg= 0x%x\n",
488 allErrors);
489
490 branch = EXTRACT_FBDCHAN_INDX(info->ferr_fat_fbd);
491 channel = branch;
492
493 /* Use the NON-Recoverable macros to extract data */
494 bank = NREC_BANK(info->nrecmema);
495 rank = NREC_RANK(info->nrecmema);
496 rdwr = NREC_RDWR(info->nrecmema);
497 ras = NREC_RAS(info->nrecmemb);
498 cas = NREC_CAS(info->nrecmemb);
499
500 debugf0("\t\tCSROW= %d Channels= %d,%d (Branch= %d "
501 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
502 rank, channel, channel + 1, branch >> 1, bank,
503 rdwr ? "Write" : "Read", ras, cas);
504
505 /* Only 1 bit will be on */
506 if (allErrors & FERR_FAT_M1ERR) {
507 i5000_mc_printk(mci, KERN_ERR,
508 "Alert on non-redundant retry or fast "
509 "reset timeout\n");
510
511 } else if (allErrors & FERR_FAT_M2ERR) {
512 i5000_mc_printk(mci, KERN_ERR,
513 "Northbound CRC error on non-redundant "
514 "retry\n");
515
516 } else if (allErrors & FERR_FAT_M3ERR) {
517 i5000_mc_printk(mci, KERN_ERR,
518 ">Tmid Thermal event with intelligent "
519 "throttling disabled\n");
520 }
521
522 /* Form out message */
523 snprintf(msg, sizeof(msg),
524 "(Branch=%d DRAM-Bank=%d RDWR=%s RAS=%d CAS=%d "
525 "FATAL Err=0x%x)",
526 branch >> 1, bank, rdwr ? "Write" : "Read", ras, cas,
527 allErrors);
528
529 /* Call the helper to output message */
530 edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg);
531}
532
b2ccaeca 533/*
eb60705a 534 * i5000_process_fatal_error_info(struct mem_ctl_info *mci,
052dfb45
DT		 535 * struct i5000_error_info *info,
536 * int handle_errors);
eb60705a
EW		 537 *
538 * handle the Intel NON-FATAL errors, if any
539 */
540static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
b2ccaeca 541 struct i5000_error_info *info,
052dfb45 542 int handle_errors)
eb60705a
EW		 543{
544 char msg[EDAC_MC_LABEL_LEN + 1 + 90];
545 u32 allErrors;
546 u32 ue_errors;
547 u32 ce_errors;
548 u32 misc_errors;
549 int branch;
550 int channel;
551 int bank;
552 int rank;
553 int rdwr;
554 int ras, cas;
555
556 /* mask off the Error bits that are possible */
557 allErrors = (info->ferr_nf_fbd & FERR_NF_MASK);
558 if (!allErrors)
559 return; /* if no error, return now */
560
561 /* ONLY ONE of the possible error bits will be set, as per the docs */
562 i5000_mc_printk(mci, KERN_WARNING,
563 "NON-FATAL ERRORS Found!!! 1st NON-FATAL Err "
564 "Reg= 0x%x\n", allErrors);
565
566 ue_errors = allErrors & FERR_NF_UNCORRECTABLE;
567 if (ue_errors) {
568 debugf0("\tUncorrected bits= 0x%x\n", ue_errors);
569
570 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
571 channel = branch;
572 bank = NREC_BANK(info->nrecmema);
573 rank = NREC_RANK(info->nrecmema);
574 rdwr = NREC_RDWR(info->nrecmema);
575 ras = NREC_RAS(info->nrecmemb);
576 cas = NREC_CAS(info->nrecmemb);
577
578 debugf0
052dfb45
DT		 579 ("\t\tCSROW= %d Channels= %d,%d (Branch= %d "
580 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
581 rank, channel, channel + 1, branch >> 1, bank,
582 rdwr ? "Write" : "Read", ras, cas);
eb60705a
EW		 583
584 /* Form out message */
585 snprintf(msg, sizeof(msg),
586 "(Branch=%d DRAM-Bank=%d RDWR=%s RAS=%d "
587 "CAS=%d, UE Err=0x%x)",
588 branch >> 1, bank, rdwr ? "Write" : "Read", ras, cas,
589 ue_errors);
590
591 /* Call the helper to output message */
592 edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg);
593 }
594
595 /* Check correctable errors */
596 ce_errors = allErrors & FERR_NF_CORRECTABLE;
597 if (ce_errors) {
598 debugf0("\tCorrected bits= 0x%x\n", ce_errors);
599
600 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
601
602 channel = 0;
603 if (REC_ECC_LOCATOR_ODD(info->redmemb))
604 channel = 1;
605
606 /* Convert channel to be based from zero, instead of
607 * from branch base of 0 */
608 channel += branch;
609
610 bank = REC_BANK(info->recmema);
611 rank = REC_RANK(info->recmema);
612 rdwr = REC_RDWR(info->recmema);
613 ras = REC_RAS(info->recmemb);
614 cas = REC_CAS(info->recmemb);
615
616 debugf0("\t\tCSROW= %d Channel= %d (Branch %d "
617 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
618 rank, channel, branch >> 1, bank,
619 rdwr ? "Write" : "Read", ras, cas);
620
621 /* Form out message */
622 snprintf(msg, sizeof(msg),
623 "(Branch=%d DRAM-Bank=%d RDWR=%s RAS=%d "
624 "CAS=%d, CE Err=0x%x)", branch >> 1, bank,
625 rdwr ? "Write" : "Read", ras, cas, ce_errors);
626
627 /* Call the helper to output message */
628 edac_mc_handle_fbd_ce(mci, rank, channel, msg);
629 }
630
631 /* See if any of the thermal errors have fired */
632 misc_errors = allErrors & FERR_NF_THERMAL;
633 if (misc_errors) {
634 i5000_printk(KERN_WARNING, "\tTHERMAL Error, bits= 0x%x\n",
052dfb45 635 misc_errors);
eb60705a
EW		 636 }
637
638 /* See if any of the thermal errors have fired */
639 misc_errors = allErrors & FERR_NF_NON_RETRY;
640 if (misc_errors) {
641 i5000_printk(KERN_WARNING, "\tNON-Retry Errors, bits= 0x%x\n",
052dfb45 642 misc_errors);
eb60705a
EW		 643 }
644
645 /* See if any of the thermal errors have fired */
646 misc_errors = allErrors & FERR_NF_NORTH_CRC;
647 if (misc_errors) {
648 i5000_printk(KERN_WARNING,
052dfb45
DT		 649 "\tNORTHBOUND CRC Error, bits= 0x%x\n",
650 misc_errors);
eb60705a
EW		 651 }
652
653 /* See if any of the thermal errors have fired */
654 misc_errors = allErrors & FERR_NF_SPD_PROTOCOL;
655 if (misc_errors) {
656 i5000_printk(KERN_WARNING,
052dfb45
DT		 657 "\tSPD Protocol Error, bits= 0x%x\n",
658 misc_errors);
eb60705a
EW		 659 }
660
661 /* See if any of the thermal errors have fired */
662 misc_errors = allErrors & FERR_NF_DIMM_SPARE;
663 if (misc_errors) {
664 i5000_printk(KERN_WARNING, "\tDIMM-Spare Error, bits= 0x%x\n",
052dfb45 665 misc_errors);
eb60705a
EW		 666 }
667}
668
b2ccaeca 669/*
eb60705a
EW		 670 * i5000_process_error_info Process the error info that is
671 * in the 'info' structure, previously retrieved from hardware
672 */
673static void i5000_process_error_info(struct mem_ctl_info *mci,
b2ccaeca 674 struct i5000_error_info *info,
052dfb45 675 int handle_errors)
eb60705a
EW		 676{
677 /* First handle any fatal errors that occurred */
678 i5000_process_fatal_error_info(mci, info, handle_errors);
679
680 /* now handle any non-fatal errors that occurred */
681 i5000_process_nonfatal_error_info(mci, info, handle_errors);
682}
683
b2ccaeca 684/*
eb60705a
EW		 685 * i5000_clear_error Retrieve any error from the hardware
686 * but do NOT process that error.
687 * Used for 'clearing' out of previous errors
688 * Called by the Core module.
689 */
690static void i5000_clear_error(struct mem_ctl_info *mci)
691{
692 struct i5000_error_info info;
693
694 i5000_get_error_info(mci, &info);
695}
696
b2ccaeca 697/*
eb60705a
EW		 698 * i5000_check_error Retrieve and process errors reported by the
699 * hardware. Called by the Core module.
700 */
701static void i5000_check_error(struct mem_ctl_info *mci)
702{
703 struct i5000_error_info info;
704 debugf4("MC%d: " __FILE__ ": %s()\n", mci->mc_idx, __func__);
705 i5000_get_error_info(mci, &info);
706 i5000_process_error_info(mci, &info, 1);
707}
708
b2ccaeca 709/*
eb60705a
EW		 710 * i5000_get_devices Find and perform 'get' operation on the MCH's
711 * device/functions we want to reference for this driver
712 *
713 * Need to 'get' device 16 func 1 and func 2
714 */
715static int i5000_get_devices(struct mem_ctl_info *mci, int dev_idx)
716{
717 //const struct i5000_dev_info *i5000_dev = &i5000_devs[dev_idx];
718 struct i5000_pvt *pvt;
719 struct pci_dev *pdev;
720
b2ccaeca 721 pvt = mci->pvt_info;
eb60705a
EW		 722
723 /* Attempt to 'get' the MCH register we want */
724 pdev = NULL;
725 while (1) {
726 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
052dfb45 727 PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
eb60705a
EW		 728
729 /* End of list, leave */
730 if (pdev == NULL) {
731 i5000_printk(KERN_ERR,
052dfb45
DT		 732 "'system address,Process Bus' "
733 "device not found:"
734 "vendor 0x%x device 0x%x FUNC 1 "
735 "(broken BIOS?)\n",
736 PCI_VENDOR_ID_INTEL,
737 PCI_DEVICE_ID_INTEL_I5000_DEV16);
eb60705a
EW		 738
739 return 1;
740 }
741
742 /* Scan for device 16 func 1 */
743 if (PCI_FUNC(pdev->devfn) == 1)
744 break;
745 }
746
747 pvt->branchmap_werrors = pdev;
748
749 /* Attempt to 'get' the MCH register we want */
750 pdev = NULL;
751 while (1) {
752 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
052dfb45 753 PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
eb60705a
EW		 754
755 if (pdev == NULL) {
756 i5000_printk(KERN_ERR,
052dfb45
DT		 757 "MC: 'branchmap,control,errors' "
758 "device not found:"
759 "vendor 0x%x device 0x%x Func 2 "
760 "(broken BIOS?)\n",
761 PCI_VENDOR_ID_INTEL,
762 PCI_DEVICE_ID_INTEL_I5000_DEV16);
eb60705a
EW		 763
764 pci_dev_put(pvt->branchmap_werrors);
765 return 1;
766 }
767
768 /* Scan for device 16 func 1 */
769 if (PCI_FUNC(pdev->devfn) == 2)
770 break;
771 }
772
773 pvt->fsb_error_regs = pdev;
774
775 debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x\n",
776 pci_name(pvt->system_address),
777 pvt->system_address->vendor, pvt->system_address->device);
778 debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
779 pci_name(pvt->branchmap_werrors),
780 pvt->branchmap_werrors->vendor, pvt->branchmap_werrors->device);
781 debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x\n",
782 pci_name(pvt->fsb_error_regs),
783 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
784
785 pdev = NULL;
786 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
052dfb45 787 PCI_DEVICE_ID_I5000_BRANCH_0, pdev);
eb60705a
EW		 788
789 if (pdev == NULL) {
790 i5000_printk(KERN_ERR,
052dfb45
DT		 791 "MC: 'BRANCH 0' device not found:"
792 "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
793 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_I5000_BRANCH_0);
eb60705a
EW		 794
795 pci_dev_put(pvt->branchmap_werrors);
796 pci_dev_put(pvt->fsb_error_regs);
797 return 1;
798 }
799
800 pvt->branch_0 = pdev;
801
802 /* If this device claims to have more than 2 channels then
803 * fetch Branch 1's information
804 */
805 if (pvt->maxch >= CHANNELS_PER_BRANCH) {
806 pdev = NULL;
807 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
052dfb45 808 PCI_DEVICE_ID_I5000_BRANCH_1, pdev);
eb60705a
EW		 809
810 if (pdev == NULL) {
811 i5000_printk(KERN_ERR,
052dfb45
DT		 812 "MC: 'BRANCH 1' device not found:"
813 "vendor 0x%x device 0x%x Func 0 "
814 "(broken BIOS?)\n",
815 PCI_VENDOR_ID_INTEL,
816 PCI_DEVICE_ID_I5000_BRANCH_1);
eb60705a
EW		 817
818 pci_dev_put(pvt->branchmap_werrors);
819 pci_dev_put(pvt->fsb_error_regs);
820 pci_dev_put(pvt->branch_0);
821 return 1;
822 }
823
824 pvt->branch_1 = pdev;
825 }
826
827 return 0;
828}
829
b2ccaeca 830/*
eb60705a
EW		 831 * i5000_put_devices 'put' all the devices that we have
832 * reserved via 'get'
833 */
834static void i5000_put_devices(struct mem_ctl_info *mci)
835{
836 struct i5000_pvt *pvt;
837
b2ccaeca 838 pvt = mci->pvt_info;
eb60705a
EW		 839
840 pci_dev_put(pvt->branchmap_werrors); /* FUNC 1 */
841 pci_dev_put(pvt->fsb_error_regs); /* FUNC 2 */
842 pci_dev_put(pvt->branch_0); /* DEV 21 */
843
844 /* Only if more than 2 channels do we release the second branch */
b2ccaeca 845 if (pvt->maxch >= CHANNELS_PER_BRANCH)
eb60705a 846 pci_dev_put(pvt->branch_1); /* DEV 22 */
eb60705a
EW		 847}
848
b2ccaeca 849/*
eb60705a
EW		 850 * determine_amb_resent
851 *
852 * the information is contained in NUM_MTRS different registers
853 * determineing which of the NUM_MTRS requires knowing
854 * which channel is in question
855 *
856 * 2 branches, each with 2 channels
857 * b0_ambpresent0 for channel '0'
858 * b0_ambpresent1 for channel '1'
859 * b1_ambpresent0 for channel '2'
860 * b1_ambpresent1 for channel '3'
861 */
862static int determine_amb_present_reg(struct i5000_pvt *pvt, int channel)
863{
864 int amb_present;
865
866 if (channel < CHANNELS_PER_BRANCH) {
867 if (channel & 0x1)
868 amb_present = pvt->b0_ambpresent1;
869 else
870 amb_present = pvt->b0_ambpresent0;
871 } else {
872 if (channel & 0x1)
873 amb_present = pvt->b1_ambpresent1;
874 else
875 amb_present = pvt->b1_ambpresent0;
876 }
877
878 return amb_present;
879}
880
b2ccaeca 881/*
eb60705a
EW		 882 * determine_mtr(pvt, csrow, channel)
883 *
884 * return the proper MTR register as determine by the csrow and channel desired
885 */
886static int determine_mtr(struct i5000_pvt *pvt, int csrow, int channel)
887{
888 int mtr;
889
890 if (channel < CHANNELS_PER_BRANCH)
891 mtr = pvt->b0_mtr[csrow >> 1];
892 else
893 mtr = pvt->b1_mtr[csrow >> 1];
894
895 return mtr;
896}
897
b2ccaeca 898/*
eb60705a
EW		 899 */
900static void decode_mtr(int slot_row, u16 mtr)
901{
902 int ans;
903
904 ans = MTR_DIMMS_PRESENT(mtr);
905
906 debugf2("\tMTR%d=0x%x: DIMMs are %s\n", slot_row, mtr,
907 ans ? "Present" : "NOT Present");
908 if (!ans)
909 return;
910
911 debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
912 debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
913 debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANK(mtr) ? "double" : "single");
914 debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]);
915 debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
916}
917
918static void handle_channel(struct i5000_pvt *pvt, int csrow, int channel,
052dfb45 919 struct i5000_dimm_info *dinfo)
eb60705a
EW		 920{
921 int mtr;
922 int amb_present_reg;
923 int addrBits;
924
925 mtr = determine_mtr(pvt, csrow, channel);
926 if (MTR_DIMMS_PRESENT(mtr)) {
927 amb_present_reg = determine_amb_present_reg(pvt, channel);
928
929 /* Determine if there is a DIMM present in this DIMM slot */
930 if (amb_present_reg & (1 << (csrow >> 1))) {
931 dinfo->dual_rank = MTR_DIMM_RANK(mtr);
932
933 if (!((dinfo->dual_rank == 0) &&
052dfb45 934 ((csrow & 0x1) == 0x1))) {
eb60705a
EW		 935 /* Start with the number of bits for a Bank
936 * on the DRAM */
937 addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);
938 /* Add thenumber of ROW bits */
939 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
940 /* add the number of COLUMN bits */
941 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
942
943 addrBits += 6; /* add 64 bits per DIMM */
944 addrBits -= 20; /* divide by 2^^20 */
945 addrBits -= 3; /* 8 bits per bytes */
946
947 dinfo->megabytes = 1 << addrBits;
948 }
949 }
950 }
951}
952
b2ccaeca 953/*
eb60705a
EW		 954 * calculate_dimm_size
955 *
956 * also will output a DIMM matrix map, if debug is enabled, for viewing
957 * how the DIMMs are populated
958 */
959static void calculate_dimm_size(struct i5000_pvt *pvt)
960{
961 struct i5000_dimm_info *dinfo;
962 int csrow, max_csrows;
963 char *p, *mem_buffer;
964 int space, n;
965 int channel;
966
967 /* ================= Generate some debug output ================= */
968 space = PAGE_SIZE;
969 mem_buffer = p = kmalloc(space, GFP_KERNEL);
970 if (p == NULL) {
971 i5000_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n",
052dfb45 972 __FILE__, __func__);
eb60705a
EW		 973 return;
974 }
975
976 n = snprintf(p, space, "\n");
977 p += n;
978 space -= n;
979
980 /* Scan all the actual CSROWS (which is # of DIMMS * 2)
981 * and calculate the information for each DIMM
982 * Start with the highest csrow first, to display it first
983 * and work toward the 0th csrow
984 */
985 max_csrows = pvt->maxdimmperch * 2;
986 for (csrow = max_csrows - 1; csrow >= 0; csrow--) {
987
988 /* on an odd csrow, first output a 'boundary' marker,
989 * then reset the message buffer */
990 if (csrow & 0x1) {
991 n = snprintf(p, space, "---------------------------"
052dfb45 992 "--------------------------------");
eb60705a
EW		 993 p += n;
994 space -= n;
995 debugf2("%s\n", mem_buffer);
996 p = mem_buffer;
997 space = PAGE_SIZE;
998 }
999 n = snprintf(p, space, "csrow %2d ", csrow);
1000 p += n;
1001 space -= n;
1002
1003 for (channel = 0; channel < pvt->maxch; channel++) {
1004 dinfo = &pvt->dimm_info[csrow][channel];
1005 handle_channel(pvt, csrow, channel, dinfo);
1006 n = snprintf(p, space, "%4d MB | ", dinfo->megabytes);
1007 p += n;
1008 space -= n;
1009 }
1010 n = snprintf(p, space, "\n");
1011 p += n;
1012 space -= n;
1013 }
1014
1015 /* Output the last bottom 'boundary' marker */
1016 n = snprintf(p, space, "---------------------------"
052dfb45 1017 "--------------------------------\n");
eb60705a
EW		 1018 p += n;
1019 space -= n;
1020
1021 /* now output the 'channel' labels */
1022 n = snprintf(p, space, " ");
1023 p += n;
1024 space -= n;
1025 for (channel = 0; channel < pvt->maxch; channel++) {
1026 n = snprintf(p, space, "channel %d | ", channel);
1027 p += n;
1028 space -= n;
1029 }
1030 n = snprintf(p, space, "\n");
1031 p += n;
1032 space -= n;
1033
1034 /* output the last message and free buffer */
1035 debugf2("%s\n", mem_buffer);
1036 kfree(mem_buffer);
1037}
1038
b2ccaeca 1039/*
eb60705a
EW		 1040 * i5000_get_mc_regs read in the necessary registers and
1041 * cache locally
1042 *
1043 * Fills in the private data members
1044 */
1045static void i5000_get_mc_regs(struct mem_ctl_info *mci)
1046{
1047 struct i5000_pvt *pvt;
1048 u32 actual_tolm;
1049 u16 limit;
1050 int slot_row;
1051 int maxch;
1052 int maxdimmperch;
1053 int way0, way1;
1054
b2ccaeca 1055 pvt = mci->pvt_info;
eb60705a
EW		 1056
1057 pci_read_config_dword(pvt->system_address, AMBASE,
052dfb45 1058 (u32 *) & pvt->ambase);
eb60705a 1059 pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
052dfb45 1060 ((u32 *) & pvt->ambase) + sizeof(u32));
eb60705a
EW		 1061
1062 maxdimmperch = pvt->maxdimmperch;
1063 maxch = pvt->maxch;
1064
1065 debugf2("AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n",
1066 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
1067
1068 /* Get the Branch Map regs */
1069 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
1070 pvt->tolm >>= 12;
1071 debugf2("\nTOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm,
1072 pvt->tolm);
1073
1074 actual_tolm = pvt->tolm << 28;
1075 debugf2("Actual TOLM byte addr=%u (0x%x)\n", actual_tolm, actual_tolm);
1076
1077 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
1078 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
1079 pci_read_config_word(pvt->branchmap_werrors, MIR2, &pvt->mir2);
1080
1081 /* Get the MIR[0-2] regs */
1082 limit = (pvt->mir0 >> 4) & 0x0FFF;
1083 way0 = pvt->mir0 & 0x1;
1084 way1 = pvt->mir0 & 0x2;
1085 debugf2("MIR0: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0);
1086 limit = (pvt->mir1 >> 4) & 0x0FFF;
1087 way0 = pvt->mir1 & 0x1;
1088 way1 = pvt->mir1 & 0x2;
1089 debugf2("MIR1: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0);
1090 limit = (pvt->mir2 >> 4) & 0x0FFF;
1091 way0 = pvt->mir2 & 0x1;
1092 way1 = pvt->mir2 & 0x2;
1093 debugf2("MIR2: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0);
1094
1095 /* Get the MTR[0-3] regs */
1096 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1097 int where = MTR0 + (slot_row * sizeof(u32));
1098
1099 pci_read_config_word(pvt->branch_0, where,
052dfb45 1100 &pvt->b0_mtr[slot_row]);
eb60705a
EW		 1101
1102 debugf2("MTR%d where=0x%x B0 value=0x%x\n", slot_row, where,
1103 pvt->b0_mtr[slot_row]);
1104
1105 if (pvt->maxch >= CHANNELS_PER_BRANCH) {
1106 pci_read_config_word(pvt->branch_1, where,
052dfb45 1107 &pvt->b1_mtr[slot_row]);
eb60705a
EW		 1108 debugf2("MTR%d where=0x%x B1 value=0x%x\n", slot_row,
1109 where, pvt->b0_mtr[slot_row]);
1110 } else {
1111 pvt->b1_mtr[slot_row] = 0;
1112 }
1113 }
1114
1115 /* Read and dump branch 0's MTRs */
1116 debugf2("\nMemory Technology Registers:\n");
1117 debugf2(" Branch 0:\n");
1118 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1119 decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
1120 }
1121 pci_read_config_word(pvt->branch_0, AMB_PRESENT_0,
052dfb45 1122 &pvt->b0_ambpresent0);
eb60705a
EW		 1123 debugf2("\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
1124 pci_read_config_word(pvt->branch_0, AMB_PRESENT_1,
052dfb45 1125 &pvt->b0_ambpresent1);
eb60705a
EW		 1126 debugf2("\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
1127
1128 /* Only if we have 2 branchs (4 channels) */
1129 if (pvt->maxch < CHANNELS_PER_BRANCH) {
1130 pvt->b1_ambpresent0 = 0;
1131 pvt->b1_ambpresent1 = 0;
1132 } else {
1133 /* Read and dump branch 1's MTRs */
1134 debugf2(" Branch 1:\n");
1135 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1136 decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
1137 }
1138 pci_read_config_word(pvt->branch_1, AMB_PRESENT_0,
052dfb45 1139 &pvt->b1_ambpresent0);
eb60705a
EW		 1140 debugf2("\t\tAMB-Branch 1-present0 0x%x:\n",
1141 pvt->b1_ambpresent0);
1142 pci_read_config_word(pvt->branch_1, AMB_PRESENT_1,
052dfb45 1143 &pvt->b1_ambpresent1);
eb60705a
EW		 1144 debugf2("\t\tAMB-Branch 1-present1 0x%x:\n",
1145 pvt->b1_ambpresent1);
1146 }
1147
1148 /* Go and determine the size of each DIMM and place in an
1149 * orderly matrix */
1150 calculate_dimm_size(pvt);
1151}
1152
b2ccaeca 1153/*
eb60705a
EW		 1154 * i5000_init_csrows Initialize the 'csrows' table within
1155 * the mci control structure with the
1156 * addressing of memory.
1157 *
1158 * return:
1159 * 0 success
1160 * 1 no actual memory found on this MC
1161 */
1162static int i5000_init_csrows(struct mem_ctl_info *mci)
1163{
1164 struct i5000_pvt *pvt;
1165 struct csrow_info *p_csrow;
1166 int empty, channel_count;
1167 int max_csrows;
1168 int mtr;
1169 int csrow_megs;
1170 int channel;
1171 int csrow;
1172
b2ccaeca 1173 pvt = mci->pvt_info;
eb60705a
EW		 1174
1175 channel_count = pvt->maxch;
1176 max_csrows = pvt->maxdimmperch * 2;
1177
1178 empty = 1; /* Assume NO memory */
1179
1180 for (csrow = 0; csrow < max_csrows; csrow++) {
1181 p_csrow = &mci->csrows[csrow];
1182
1183 p_csrow->csrow_idx = csrow;
1184
1185 /* use branch 0 for the basis */
1186 mtr = pvt->b0_mtr[csrow >> 1];
1187
1188 /* if no DIMMS on this row, continue */
1189 if (!MTR_DIMMS_PRESENT(mtr))
1190 continue;
1191
1192 /* FAKE OUT VALUES, FIXME */
1193 p_csrow->first_page = 0 + csrow * 20;
1194 p_csrow->last_page = 9 + csrow * 20;
1195 p_csrow->page_mask = 0xFFF;
1196
1197 p_csrow->grain = 8;
1198
1199 csrow_megs = 0;
1200 for (channel = 0; channel < pvt->maxch; channel++) {
1201 csrow_megs += pvt->dimm_info[csrow][channel].megabytes;
1202 }
1203
1204 p_csrow->nr_pages = csrow_megs << 8;
1205
1206 /* Assume DDR2 for now */
1207 p_csrow->mtype = MEM_FB_DDR2;
1208
1209 /* ask what device type on this row */
1210 if (MTR_DRAM_WIDTH(mtr))
1211 p_csrow->dtype = DEV_X8;
1212 else
1213 p_csrow->dtype = DEV_X4;
1214
1215 p_csrow->edac_mode = EDAC_S8ECD8ED;
1216
1217 empty = 0;
1218 }
1219
1220 return empty;
1221}
1222
b2ccaeca 1223/*
eb60705a
EW		 1224 * i5000_enable_error_reporting
1225 * Turn on the memory reporting features of the hardware
1226 */
1227static void i5000_enable_error_reporting(struct mem_ctl_info *mci)
1228{
1229 struct i5000_pvt *pvt;
1230 u32 fbd_error_mask;
1231
b2ccaeca 1232 pvt = mci->pvt_info;
eb60705a
EW		 1233
1234 /* Read the FBD Error Mask Register */
1235 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
052dfb45 1236 &fbd_error_mask);
eb60705a
EW		 1237
1238 /* Enable with a '0' */
1239 fbd_error_mask &= ~(ENABLE_EMASK_ALL);
1240
1241 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
052dfb45 1242 fbd_error_mask);
eb60705a
EW		 1243}
1244
b2ccaeca 1245/*
eb60705a
EW		 1246 * i5000_get_dimm_and_channel_counts(pdev, &num_csrows, &num_channels)
1247 *
1248 * ask the device how many channels are present and how many CSROWS
1249 * as well
1250 */
1251static void i5000_get_dimm_and_channel_counts(struct pci_dev *pdev,
052dfb45
DT		 1252 int *num_dimms_per_channel,
1253 int *num_channels)
eb60705a
EW		 1254{
1255 u8 value;
1256
1257 /* Need to retrieve just how many channels and dimms per channel are
1258 * supported on this memory controller
1259 */
1260 pci_read_config_byte(pdev, MAXDIMMPERCH, &value);
1261 *num_dimms_per_channel = (int)value *2;
1262
1263 pci_read_config_byte(pdev, MAXCH, &value);
1264 *num_channels = (int)value;
1265}
1266
b2ccaeca 1267/*
eb60705a
EW		 1268 * i5000_probe1 Probe for ONE instance of device to see if it is
1269 * present.
1270 * return:
1271 * 0 for FOUND a device
1272 * < 0 for error code
1273 */
1274static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
1275{
1276 struct mem_ctl_info *mci;
1277 struct i5000_pvt *pvt;
1278 int num_channels;
1279 int num_dimms_per_channel;
1280 int num_csrows;
1281
1282 debugf0("MC: " __FILE__ ": %s(), pdev bus %u dev=0x%x fn=0x%x\n",
1283 __func__,
1284 pdev->bus->number,
1285 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1286
1287 /* We only are looking for func 0 of the set */
1288 if (PCI_FUNC(pdev->devfn) != 0)
1289 return -ENODEV;
1290
c0d12172 1291 /* make sure error reporting method is sane */
f4aff426
DT		 1292 switch (edac_op_state) {
1293 case EDAC_OPSTATE_POLL:
1294 case EDAC_OPSTATE_NMI:
1295 break;
1296 default:
1297 edac_op_state = EDAC_OPSTATE_POLL;
1298 break;
c0d12172
DJ		 1299 }
1300
eb60705a
EW		 1301 /* Ask the devices for the number of CSROWS and CHANNELS so
1302 * that we can calculate the memory resources, etc
1303 *
1304 * The Chipset will report what it can handle which will be greater
1305 * or equal to what the motherboard manufacturer will implement.
1306 *
1307 * As we don't have a motherboard identification routine to determine
1308 * actual number of slots/dimms per channel, we thus utilize the
1309 * resource as specified by the chipset. Thus, we might have
1310 * have more DIMMs per channel than actually on the mobo, but this
1311 * allows the driver to support upto the chipset max, without
1312 * some fancy mobo determination.
1313 */
1314 i5000_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel,
052dfb45 1315 &num_channels);
eb60705a
EW		 1316 num_csrows = num_dimms_per_channel * 2;
1317
1318 debugf0("MC: %s(): Number of - Channels= %d DIMMS= %d CSROWS= %d\n",
1319 __func__, num_channels, num_dimms_per_channel, num_csrows);
1320
1321 /* allocate a new MC control structure */
1322 mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels);
1323
1324 if (mci == NULL)
1325 return -ENOMEM;
1326
1327 debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
1328
1329 mci->dev = &pdev->dev; /* record ptr to the generic device */
1330
b2ccaeca 1331 pvt = mci->pvt_info;
eb60705a
EW		 1332 pvt->system_address = pdev; /* Record this device in our private */
1333 pvt->maxch = num_channels;
1334 pvt->maxdimmperch = num_dimms_per_channel;
1335
1336 /* 'get' the pci devices we want to reserve for our use */
1337 if (i5000_get_devices(mci, dev_idx))
1338 goto fail0;
1339
1340 /* Time to get serious */
1341 i5000_get_mc_regs(mci); /* retrieve the hardware registers */
1342
1343 mci->mc_idx = 0;
1344 mci->mtype_cap = MEM_FLAG_FB_DDR2;
1345 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1346 mci->edac_cap = EDAC_FLAG_NONE;
1347 mci->mod_name = "i5000_edac.c";
1348 mci->mod_ver = I5000_REVISION;
1349 mci->ctl_name = i5000_devs[dev_idx].ctl_name;
c4192705 1350 mci->dev_name = pci_name(pdev);
eb60705a
EW		 1351 mci->ctl_page_to_phys = NULL;
1352
1353 /* Set the function pointer to an actual operation function */
1354 mci->edac_check = i5000_check_error;
1355
1356 /* initialize the MC control structure 'csrows' table
1357 * with the mapping and control information */
1358 if (i5000_init_csrows(mci)) {
1359 debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n"
1360 " because i5000_init_csrows() returned nonzero "
1361 "value\n");
1362 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
1363 } else {
1364 debugf1("MC: Enable error reporting now\n");
1365 i5000_enable_error_reporting(mci);
1366 }
1367
1368 /* add this new MC control structure to EDAC's list of MCs */
1369 if (edac_mc_add_mc(mci, pvt->node_id)) {
1370 debugf0("MC: " __FILE__
1371 ": %s(): failed edac_mc_add_mc()\n", __func__);
1372 /* FIXME: perhaps some code should go here that disables error
1373 * reporting if we just enabled it
1374 */
1375 goto fail1;
1376 }
1377
1378 i5000_clear_error(mci);
1379
456a2f95
DJ		 1380 /* allocating generic PCI control info */
1381 i5000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1382 if (!i5000_pci) {
1383 printk(KERN_WARNING
1384 "%s(): Unable to create PCI control\n",
1385 __func__);
1386 printk(KERN_WARNING
1387 "%s(): PCI error report via EDAC not setup\n",
1388 __func__);
1389 }
1390
eb60705a
EW		 1391 return 0;
1392
1393 /* Error exit unwinding stack */
052dfb45 1394fail1:
eb60705a
EW		 1395
1396 i5000_put_devices(mci);
1397
052dfb45 1398fail0:
eb60705a
EW		 1399 edac_mc_free(mci);
1400 return -ENODEV;
1401}
1402
b2ccaeca 1403/*
eb60705a
EW		 1404 * i5000_init_one constructor for one instance of device
1405 *
1406 * returns:
1407 * negative on error
1408 * count (>= 0)
1409 */
1410static int __devinit i5000_init_one(struct pci_dev *pdev,
052dfb45 1411 const struct pci_device_id *id)
eb60705a
EW		 1412{
1413 int rc;
1414
1415 debugf0("MC: " __FILE__ ": %s()\n", __func__);
1416
1417 /* wake up device */
1418 rc = pci_enable_device(pdev);
1419 if (rc == -EIO)
1420 return rc;
1421
1422 /* now probe and enable the device */
1423 return i5000_probe1(pdev, id->driver_data);
1424}
1425
b2ccaeca 1426/*
eb60705a
EW		 1427 * i5000_remove_one destructor for one instance of device
1428 *
1429 */
1430static void __devexit i5000_remove_one(struct pci_dev *pdev)
1431{
1432 struct mem_ctl_info *mci;
1433
1434 debugf0(__FILE__ ": %s()\n", __func__);
1435
456a2f95
DJ		 1436 if (i5000_pci)
1437 edac_pci_release_generic_ctl(i5000_pci);
1438
eb60705a
EW		 1439 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
1440 return;
1441
1442 /* retrieve references to resources, and free those resources */
1443 i5000_put_devices(mci);
1444
1445 edac_mc_free(mci);
1446}
1447
b2ccaeca 1448/*
eb60705a
EW		 1449 * pci_device_id table for which devices we are looking for
1450 *
1451 * The "E500P" device is the first device supported.
1452 */
1453static const struct pci_device_id i5000_pci_tbl[] __devinitdata = {
1454 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000_DEV16),
1455 .driver_data = I5000P},
1456
1457 {0,} /* 0 terminated list. */
1458};
1459
1460MODULE_DEVICE_TABLE(pci, i5000_pci_tbl);
1461
b2ccaeca 1462/*
eb60705a
EW		 1463 * i5000_driver pci_driver structure for this module
1464 *
1465 */
1466static struct pci_driver i5000_driver = {
1467 .name = __stringify(KBUILD_BASENAME),
1468 .probe = i5000_init_one,
1469 .remove = __devexit_p(i5000_remove_one),
1470 .id_table = i5000_pci_tbl,
1471};
1472
b2ccaeca 1473/*
eb60705a
EW		 1474 * i5000_init Module entry function
1475 * Try to initialize this module for its devices
1476 */
1477static int __init i5000_init(void)
1478{
1479 int pci_rc;
1480
1481 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1482
1483 pci_rc = pci_register_driver(&i5000_driver);
1484
1485 return (pci_rc < 0) ? pci_rc : 0;
1486}
1487
b2ccaeca 1488/*
eb60705a
EW		 1489 * i5000_exit() Module exit function
1490 * Unregister the driver
1491 */
1492static void __exit i5000_exit(void)
1493{
1494 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1495 pci_unregister_driver(&i5000_driver);
1496}
1497
1498module_init(i5000_init);
1499module_exit(i5000_exit);
1500
1501MODULE_LICENSE("GPL");
1502MODULE_AUTHOR
1503 ("Linux Networx (http://lnxi.com) Doug Thompson <norsk5@xmission.com>");
1504MODULE_DESCRIPTION("MC Driver for Intel I5000 memory controllers - "
052dfb45 1505 I5000_REVISION);
c0d12172
DJ		 1506module_param(edac_op_state, int, 0444);
1507MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
kernel source for telekom puls (alcatel/mediatek)