Merge branch 'fixes' into next/cleanup

Merging in fixes since there's a conflict in the omap4 clock tables caused by
it.

* fixes: (245 commits)
  ARM: highbank: fix cache flush ordering for cpu hotplug
  ARM: OMAP4: hwmod data: make 'ocp2scp_usb_phy_phy_48m" as the main clock
  arm: mvebu: Fix the irq map function in SMP mode
  Fix GE0/GE1 init on ix2-200 as GE0 has no PHY
  ARM: S3C24XX: Fix interrupt pending register offset of the EINT controller
  ARM: S3C24XX: Correct NR_IRQS definition for s3c2440
  ARM i.MX6: Fix ldb_di clock selection
  ARM: imx: provide twd clock lookup from device tree
  ARM: imx35 Bugfix admux clock
  ARM: clk-imx35: Bugfix iomux clock
  + Linux 3.9-rc6

Signed-off-by: Olof Johansson <olof@lixom.net>
Conflicts:
	arch/arm/mach-omap2/cclock44xx_data.c

diff --cc arch/arm/Kconfig
Simple merge

diff --cc arch/arm/mach-imx/common.h
index d4b2f369751b65ba0b39f3688395f6d97d535442,5bf4a97ab2413c3a7234a092a74350423cba359b..9fea2522d7a3921f60f43fa0aae71ee2c3225c3d
--- 1/arch/arm/mach-imx/common.h
--- 2/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@@ -110,7 -110,10 +110,9 @@@ void tzic_handle_irq(struct pt_regs *)
  
  extern void imx_enable_cpu(int cpu, bool enable);
  extern void imx_set_cpu_jump(int cpu, void *jump_addr);
+ extern u32 imx_get_cpu_arg(int cpu);
+ extern void imx_set_cpu_arg(int cpu, u32 arg);
  extern void v7_cpu_resume(void);
 -extern u32 *pl310_get_save_ptr(void);
  #ifdef CONFIG_SMP
  extern void v7_secondary_startup(void);
  extern void imx_scu_map_io(void);

diff --cc arch/arm/mach-omap2/cclock44xx_data.c
index b1e77ef968fae267d3b26c0b5aa53cf638708862,0c6834ae1fc43a8ab20409dccd1bb24d7eeb20fd..88e37a474334df7589fc866bbf37fbd645258b00
--- 1/arch/arm/mach-omap2/cclock44xx_data.c
--- 2/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@@ -1413,265 -1424,255 +1424,266 @@@ DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq
               0x0, NULL);
  
  /*
 - * clkdev
 + * clocks specific to omap4460
   */
 +static struct omap_clk omap446x_clks[] = {
 +      CLK(NULL,       "div_ts_ck",                    &div_ts_ck),
 +      CLK(NULL,       "bandgap_ts_fclk",              &bandgap_ts_fclk),
 +};
 +
 +/*
 + * clocks specific to omap4430
 + */
 +static struct omap_clk omap443x_clks[] = {
 +      CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk),
 +};
  
 +/*
 + * clocks common to omap44xx
 + */
  static struct omap_clk omap44xx_clks[] = {
 -      CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck,       CK_443X),
 -      CLK(NULL,       "pad_clks_src_ck",              &pad_clks_src_ck,       CK_443X),
 -      CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck,   CK_443X),
 -      CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck,      CK_443X),
 -      CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck, CK_443X),
 -      CLK(NULL,       "slimbus_src_clk",              &slimbus_src_clk,       CK_443X),
 -      CLK(NULL,       "slimbus_clk",                  &slimbus_clk,   CK_443X),
 -      CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck,    CK_443X),
 -      CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck,      CK_443X),
 -      CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck,      CK_443X),
 -      CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck,      CK_443X),
 -      CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck,      CK_443X),
 -      CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck,      CK_443X),
 -      CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
 -      CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
 -      CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
 -      CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck,      CK_443X),
 -      CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
 -      CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
 -      CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
 -      CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
 -      CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
 -      CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
 -      CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
 -      CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck,        CK_443X),
 -      CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
 -      CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
 -      CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
 -      CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
 -      CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck,      CK_443X),
 -      CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
 -      CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
 -      CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck,       CK_443X),
 -      CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck,     CK_443X),
 -      CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
 -      CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
 -      CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
 -      CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck,     CK_443X),
 -      CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
 -      CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
 -      CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
 -      CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck,     CK_443X),
 -      CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
 -      CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
 -      CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck,     CK_443X),
 -      CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck,     CK_443X),
 -      CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
 -      CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
 -      CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck,        CK_443X),
 -      CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck,      CK_443X),
 -      CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck,      CK_443X),
 -      CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
 -      CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
 -      CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
 -      CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
 -      CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
 -      CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
 -      CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck,        CK_443X),
 -      CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
 -      CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck,      CK_443X),
 -      CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck,      CK_443X),
 -      CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
 -      CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
 -      CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
 -      CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
 -      CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
 -      CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
 -      CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck,        CK_443X),
 -      CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck,     CK_443X),
 -      CLK(NULL,       "func_12m_fclk",                &func_12m_fclk, CK_443X),
 -      CLK(NULL,       "func_24m_clk",                 &func_24m_clk,  CK_443X),
 -      CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk,        CK_443X),
 -      CLK(NULL,       "func_48m_fclk",                &func_48m_fclk, CK_443X),
 -      CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
 -      CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
 -      CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
 -      CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
 -      CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
 -      CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
 -      CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
 -      CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
 -      CLK("smp_twd",  NULL,                           &mpu_periphclk, CK_443X),
 -      CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
 -      CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
 -      CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
 -      CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
 -      CLK(NULL,       "aes1_fck",                     &aes1_fck,      CK_443X),
 -      CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
 -      CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
 -      CLK(NULL,       "div_ts_ck",                    &div_ts_ck,     CK_446X),
 -      CLK(NULL,       "bandgap_ts_fclk",              &bandgap_ts_fclk,       CK_446X),
 -      CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
 -      CLK(NULL,       "func_dmic_abe_gfclk",                  &func_dmic_abe_gfclk,   CK_443X),
 -      CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk,   CK_443X),
 -      CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
 -      CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
 -      CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
 -      CLK(NULL,       "dss_fck",                      &dss_fck,       CK_443X),
 -      CLK("omapdss_dss",      "ick",                  &dss_fck,       CK_443X),
 -      CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
 -      CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk,   CK_443X),
 -      CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk,   CK_443X),
 -      CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk,   CK_443X),
 -      CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk,   CK_443X),
 -      CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk,   CK_443X),
 -      CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk,   CK_443X),
 -      CLK(NULL,       "sgx_clk_mux",                  &sgx_clk_mux,   CK_443X),
 -      CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
 -      CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
 -      CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
 -      CLK(NULL,       "func_mcasp_abe_gfclk",                 &func_mcasp_abe_gfclk,  CK_443X),
 -      CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
 -      CLK(NULL,       "func_mcbsp1_gfclk",                    &func_mcbsp1_gfclk,     CK_443X),
 -      CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck,    CK_443X),
 -      CLK(NULL,       "func_mcbsp2_gfclk",                    &func_mcbsp2_gfclk,     CK_443X),
 -      CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck,    CK_443X),
 -      CLK(NULL,       "func_mcbsp3_gfclk",                    &func_mcbsp3_gfclk,     CK_443X),
 -      CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
 -      CLK(NULL,       "per_mcbsp4_gfclk",                     &per_mcbsp4_gfclk,      CK_443X),
 -      CLK(NULL,       "hsmmc1_fclk",                  &hsmmc1_fclk,   CK_443X),
 -      CLK(NULL,       "hsmmc2_fclk",                  &hsmmc2_fclk,   CK_443X),
 -      CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
 -      CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
 -      CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1,       CK_443X),
 -      CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0,       CK_443X),
 -      CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2,       CK_443X),
 -      CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk,  CK_443X),
 -      CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1,       CK_443X),
 -      CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0,       CK_443X),
 -      CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk,  CK_443X),
 -      CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
 -      CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
 -      CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
 -      CLK(NULL,       "dmt1_clk_mux",                 &dmt1_clk_mux,  CK_443X),
 -      CLK(NULL,       "cm2_dm10_mux",                 &cm2_dm10_mux,  CK_443X),
 -      CLK(NULL,       "cm2_dm11_mux",                 &cm2_dm11_mux,  CK_443X),
 -      CLK(NULL,       "cm2_dm2_mux",                  &cm2_dm2_mux,   CK_443X),
 -      CLK(NULL,       "cm2_dm3_mux",                  &cm2_dm3_mux,   CK_443X),
 -      CLK(NULL,       "cm2_dm4_mux",                  &cm2_dm4_mux,   CK_443X),
 -      CLK(NULL,       "timer5_sync_mux",              &timer5_sync_mux,       CK_443X),
 -      CLK(NULL,       "timer6_sync_mux",                      &timer6_sync_mux,       CK_443X),
 -      CLK(NULL,       "timer7_sync_mux",                      &timer7_sync_mux,       CK_443X),
 -      CLK(NULL,       "timer8_sync_mux",                      &timer8_sync_mux,       CK_443X),
 -      CLK(NULL,       "cm2_dm9_mux",                  &cm2_dm9_mux,   CK_443X),
 -      CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
 -      CLK("usbhs_omap",       "fs_fck",               &usb_host_fs_fck,       CK_443X),
 -      CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
 -      CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
 -      CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
 -      CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk,       CK_443X),
 -      CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk,       CK_443X),
 -      CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk,   CK_443X),
 -      CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk,    CK_443X),
 -      CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
 -      CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
 -      CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
 -      CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
 -      CLK("usbhs_omap",       "hs_fck",               &usb_host_hs_fck,       CK_443X),
 -      CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
 -      CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
 -      CLK(NULL,       "usb_otg_hs_ick",               &usb_otg_hs_ick,        CK_443X),
 -      CLK("musb-omap2430",    "ick",                  &usb_otg_hs_ick,        CK_443X),
 -      CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
 -      CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
 -      CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
 -      CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
 -      CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
 -      CLK("usbhs_omap",       "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
 -      CLK("usbhs_tll",        "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
 -      CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
 -      CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
 -      CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
 -      CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
 -      CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
 -      CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
 -      CLK(NULL,       "auxclk0_src_ck",               &auxclk0_src_ck,        CK_443X),
 -      CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
 -      CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
 -      CLK(NULL,       "auxclk1_src_ck",               &auxclk1_src_ck,        CK_443X),
 -      CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
 -      CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
 -      CLK(NULL,       "auxclk2_src_ck",               &auxclk2_src_ck,        CK_443X),
 -      CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
 -      CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
 -      CLK(NULL,       "auxclk3_src_ck",               &auxclk3_src_ck,        CK_443X),
 -      CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
 -      CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
 -      CLK(NULL,       "auxclk4_src_ck",               &auxclk4_src_ck,        CK_443X),
 -      CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
 -      CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
 -      CLK(NULL,       "auxclk5_src_ck",               &auxclk5_src_ck,        CK_443X),
 -      CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
 -      CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
 -      CLK("omap-gpmc",        "fck",                  &dummy_ck,      CK_443X),
 -      CLK("omap_i2c.1",       "ick",                  &dummy_ck,      CK_443X),
 -      CLK("omap_i2c.2",       "ick",                  &dummy_ck,      CK_443X),
 -      CLK("omap_i2c.3",       "ick",                  &dummy_ck,      CK_443X),
 -      CLK("omap_i2c.4",       "ick",                  &dummy_ck,      CK_443X),
 -      CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
 -      CLK("omap_hsmmc.0",     "ick",                  &dummy_ck,      CK_443X),
 -      CLK("omap_hsmmc.1",     "ick",                  &dummy_ck,      CK_443X),
 -      CLK("omap_hsmmc.2",     "ick",                  &dummy_ck,      CK_443X),
 -      CLK("omap_hsmmc.3",     "ick",                  &dummy_ck,      CK_443X),
 -      CLK("omap_hsmmc.4",     "ick",                  &dummy_ck,      CK_443X),
 -      CLK("omap-mcbsp.1",     "ick",                  &dummy_ck,      CK_443X),
 -      CLK("omap-mcbsp.2",     "ick",                  &dummy_ck,      CK_443X),
 -      CLK("omap-mcbsp.3",     "ick",                  &dummy_ck,      CK_443X),
 -      CLK("omap-mcbsp.4",     "ick",                  &dummy_ck,      CK_443X),
 -      CLK("omap2_mcspi.1",    "ick",                  &dummy_ck,      CK_443X),
 -      CLK("omap2_mcspi.2",    "ick",                  &dummy_ck,      CK_443X),
 -      CLK("omap2_mcspi.3",    "ick",                  &dummy_ck,      CK_443X),
 -      CLK("omap2_mcspi.4",    "ick",                  &dummy_ck,      CK_443X),
 -      CLK(NULL,       "uart1_ick",                    &dummy_ck,      CK_443X),
 -      CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
 -      CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
 -      CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
 -      CLK("usbhs_omap",       "usbhost_ick",          &dummy_ck,              CK_443X),
 -      CLK("usbhs_omap",       "usbtll_fck",           &dummy_ck,      CK_443X),
 -      CLK("usbhs_tll",        "usbtll_fck",           &dummy_ck,      CK_443X),
 -      CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
 -      CLK(NULL,       "timer_32k_ck", &sys_32k_ck,    CK_443X),
 +      CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck),
 +      CLK(NULL,       "pad_clks_src_ck",              &pad_clks_src_ck),
 +      CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck),
 +      CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck),
 +      CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck),
 +      CLK(NULL,       "slimbus_src_clk",              &slimbus_src_clk),
 +      CLK(NULL,       "slimbus_clk",                  &slimbus_clk),
 +      CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck),
 +      CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck),
 +      CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck),
 +      CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck),
 +      CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck),
 +      CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck),
 +      CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck),
 +      CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck),
 +      CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck),
 +      CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck),
 +      CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck),
 +      CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck),
 +      CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck),
 +      CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck),
 +      CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck),
 +      CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck),
 +      CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck),
 +      CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck),
 +      CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck),
 +      CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk),
 +      CLK(NULL,       "abe_clk",                      &abe_clk),
 +      CLK(NULL,       "aess_fclk",                    &aess_fclk),
 +      CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck),
 +      CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck),
 +      CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck),
 +      CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck),
 +      CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck),
 +      CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck),
 +      CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck),
 +      CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck),
 +      CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck),
 +      CLK(NULL,       "div_core_ck",                  &div_core_ck),
 +      CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk),
 +      CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk),
 +      CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck),
 +      CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck),
 +      CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck),
 +      CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck),
 +      CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck),
 +      CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck),
 +      CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck),
 +      CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck),
 +      CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck),
 +      CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck),
 +      CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck),
 +      CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck),
 +      CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck),
 +      CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck),
 +      CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck),
 +      CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck),
 +      CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck),
 +      CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck),
 +      CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck),
 +      CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck),
 +      CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck),
 +      CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck),
 +      CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck),
 +      CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck),
 +      CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck),
 +      CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck),
 +      CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck),
 +      CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck),
 +      CLK(NULL,       "func_12m_fclk",                &func_12m_fclk),
 +      CLK(NULL,       "func_24m_clk",                 &func_24m_clk),
 +      CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk),
 +      CLK(NULL,       "func_48m_fclk",                &func_48m_fclk),
 +      CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk),
 +      CLK(NULL,       "func_64m_fclk",                &func_64m_fclk),
 +      CLK(NULL,       "func_96m_fclk",                &func_96m_fclk),
 +      CLK(NULL,       "init_60m_fclk",                &init_60m_fclk),
 +      CLK(NULL,       "l3_div_ck",                    &l3_div_ck),
 +      CLK(NULL,       "l4_div_ck",                    &l4_div_ck),
 +      CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck),
 +      CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck),
 +      CLK("smp_twd",  NULL,                           &mpu_periphclk),
 +      CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk),
 +      CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk),
 +      CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk),
 +      CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck),
 +      CLK(NULL,       "aes1_fck",                     &aes1_fck),
 +      CLK(NULL,       "aes2_fck",                     &aes2_fck),
 +      CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck),
 +      CLK(NULL,       "func_dmic_abe_gfclk",          &func_dmic_abe_gfclk),
 +      CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk),
 +      CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk),
 +      CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk),
 +      CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk),
 +      CLK(NULL,       "dss_fck",                      &dss_fck),
 +      CLK("omapdss_dss",      "ick",                  &dss_fck),
 +      CLK(NULL,       "fdif_fck",                     &fdif_fck),
 +      CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk),
 +      CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk),
 +      CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk),
 +      CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk),
 +      CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk),
 +      CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk),
 +      CLK(NULL,       "sgx_clk_mux",                  &sgx_clk_mux),
 +      CLK(NULL,       "hsi_fck",                      &hsi_fck),
 +      CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk),
 +      CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck),
 +      CLK(NULL,       "func_mcasp_abe_gfclk",         &func_mcasp_abe_gfclk),
 +      CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck),
 +      CLK(NULL,       "func_mcbsp1_gfclk",            &func_mcbsp1_gfclk),
 +      CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck),
 +      CLK(NULL,       "func_mcbsp2_gfclk",            &func_mcbsp2_gfclk),
 +      CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck),
 +      CLK(NULL,       "func_mcbsp3_gfclk",            &func_mcbsp3_gfclk),
 +      CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck),
 +      CLK(NULL,       "per_mcbsp4_gfclk",             &per_mcbsp4_gfclk),
 +      CLK(NULL,       "hsmmc1_fclk",                  &hsmmc1_fclk),
 +      CLK(NULL,       "hsmmc2_fclk",                  &hsmmc2_fclk),
++      CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m),
 +      CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck),
 +      CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1),
 +      CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0),
 +      CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2),
 +      CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk),
 +      CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1),
 +      CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0),
 +      CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk),
 +      CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck),
 +      CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck),
 +      CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck),
 +      CLK(NULL,       "dmt1_clk_mux",                 &dmt1_clk_mux),
 +      CLK(NULL,       "cm2_dm10_mux",                 &cm2_dm10_mux),
 +      CLK(NULL,       "cm2_dm11_mux",                 &cm2_dm11_mux),
 +      CLK(NULL,       "cm2_dm2_mux",                  &cm2_dm2_mux),
 +      CLK(NULL,       "cm2_dm3_mux",                  &cm2_dm3_mux),
 +      CLK(NULL,       "cm2_dm4_mux",                  &cm2_dm4_mux),
 +      CLK(NULL,       "timer5_sync_mux",              &timer5_sync_mux),
 +      CLK(NULL,       "timer6_sync_mux",              &timer6_sync_mux),
 +      CLK(NULL,       "timer7_sync_mux",              &timer7_sync_mux),
 +      CLK(NULL,       "timer8_sync_mux",              &timer8_sync_mux),
 +      CLK(NULL,       "cm2_dm9_mux",                  &cm2_dm9_mux),
 +      CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck),
 +      CLK("usbhs_omap",       "fs_fck",               &usb_host_fs_fck),
 +      CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk),
 +      CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk),
 +      CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk),
 +      CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk),
 +      CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk),
 +      CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk),
 +      CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk),
 +      CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk),
 +      CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk),
 +      CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk),
 +      CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck),
 +      CLK("usbhs_omap",       "hs_fck",               &usb_host_hs_fck),
 +      CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk),
 +      CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk),
 +      CLK(NULL,       "usb_otg_hs_ick",               &usb_otg_hs_ick),
 +      CLK("musb-omap2430",    "ick",                  &usb_otg_hs_ick),
 +      CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k),
 +      CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk),
 +      CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk),
 +      CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk),
 +      CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick),
 +      CLK("usbhs_omap",       "usbtll_ick",           &usb_tll_hs_ick),
 +      CLK("usbhs_tll",        "usbtll_ick",           &usb_tll_hs_ick),
 +      CLK(NULL,       "usim_ck",                      &usim_ck),
 +      CLK(NULL,       "usim_fclk",                    &usim_fclk),
 +      CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck),
 +      CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck),
 +      CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck),
 +      CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck),
 +      CLK(NULL,       "auxclk0_src_ck",               &auxclk0_src_ck),
 +      CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck),
 +      CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck),
 +      CLK(NULL,       "auxclk1_src_ck",               &auxclk1_src_ck),
 +      CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck),
 +      CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck),
 +      CLK(NULL,       "auxclk2_src_ck",               &auxclk2_src_ck),
 +      CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck),
 +      CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck),
 +      CLK(NULL,       "auxclk3_src_ck",               &auxclk3_src_ck),
 +      CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck),
 +      CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck),
 +      CLK(NULL,       "auxclk4_src_ck",               &auxclk4_src_ck),
 +      CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck),
 +      CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck),
 +      CLK(NULL,       "auxclk5_src_ck",               &auxclk5_src_ck),
 +      CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck),
 +      CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck),
 +      CLK("omap-gpmc",        "fck",                  &dummy_ck),
 +      CLK("omap_i2c.1",       "ick",                  &dummy_ck),
 +      CLK("omap_i2c.2",       "ick",                  &dummy_ck),
 +      CLK("omap_i2c.3",       "ick",                  &dummy_ck),
 +      CLK("omap_i2c.4",       "ick",                  &dummy_ck),
 +      CLK(NULL,       "mailboxes_ick",                &dummy_ck),
 +      CLK("omap_hsmmc.0",     "ick",                  &dummy_ck),
 +      CLK("omap_hsmmc.1",     "ick",                  &dummy_ck),
 +      CLK("omap_hsmmc.2",     "ick",                  &dummy_ck),
 +      CLK("omap_hsmmc.3",     "ick",                  &dummy_ck),
 +      CLK("omap_hsmmc.4",     "ick",                  &dummy_ck),
 +      CLK("omap-mcbsp.1",     "ick",                  &dummy_ck),
 +      CLK("omap-mcbsp.2",     "ick",                  &dummy_ck),
 +      CLK("omap-mcbsp.3",     "ick",                  &dummy_ck),
 +      CLK("omap-mcbsp.4",     "ick",                  &dummy_ck),
 +      CLK("omap2_mcspi.1",    "ick",                  &dummy_ck),
 +      CLK("omap2_mcspi.2",    "ick",                  &dummy_ck),
 +      CLK("omap2_mcspi.3",    "ick",                  &dummy_ck),
 +      CLK("omap2_mcspi.4",    "ick",                  &dummy_ck),
 +      CLK(NULL,       "uart1_ick",                    &dummy_ck),
 +      CLK(NULL,       "uart2_ick",                    &dummy_ck),
 +      CLK(NULL,       "uart3_ick",                    &dummy_ck),
 +      CLK(NULL,       "uart4_ick",                    &dummy_ck),
 +      CLK("usbhs_omap",       "usbhost_ick",          &dummy_ck),
 +      CLK("usbhs_omap",       "usbtll_fck",           &dummy_ck),
 +      CLK("usbhs_tll",        "usbtll_fck",           &dummy_ck),
 +      CLK("omap_wdt", "ick",                          &dummy_ck),
 +      CLK(NULL,       "timer_32k_ck", &sys_32k_ck),
        /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
 -      CLK("omap_timer.1",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
 -      CLK("omap_timer.2",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
 -      CLK("omap_timer.3",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
 -      CLK("omap_timer.4",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
 -      CLK("omap_timer.9",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
 -      CLK("omap_timer.10",    "timer_sys_ck", &sys_clkin_ck,  CK_443X),
 -      CLK("omap_timer.11",    "timer_sys_ck", &sys_clkin_ck,  CK_443X),
 -      CLK("omap_timer.5",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
 -      CLK("omap_timer.6",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
 -      CLK("omap_timer.7",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
 -      CLK("omap_timer.8",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
 -      CLK("4a318000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
 -      CLK("48032000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
 -      CLK("48034000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
 -      CLK("48036000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
 -      CLK("4803e000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
 -      CLK("48086000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
 -      CLK("48088000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
 -      CLK("40138000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
 -      CLK("4013a000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
 -      CLK("4013c000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
 -      CLK("4013e000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
 -      CLK(NULL,       "cpufreq_ck",   &dpll_mpu_ck,   CK_443X),
 +      CLK("omap_timer.1",     "timer_sys_ck", &sys_clkin_ck),
 +      CLK("omap_timer.2",     "timer_sys_ck", &sys_clkin_ck),
 +      CLK("omap_timer.3",     "timer_sys_ck", &sys_clkin_ck),
 +      CLK("omap_timer.4",     "timer_sys_ck", &sys_clkin_ck),
 +      CLK("omap_timer.9",     "timer_sys_ck", &sys_clkin_ck),
 +      CLK("omap_timer.10",    "timer_sys_ck", &sys_clkin_ck),
 +      CLK("omap_timer.11",    "timer_sys_ck", &sys_clkin_ck),
 +      CLK("omap_timer.5",     "timer_sys_ck", &syc_clk_div_ck),
 +      CLK("omap_timer.6",     "timer_sys_ck", &syc_clk_div_ck),
 +      CLK("omap_timer.7",     "timer_sys_ck", &syc_clk_div_ck),
 +      CLK("omap_timer.8",     "timer_sys_ck", &syc_clk_div_ck),
 +      CLK("4a318000.timer",   "timer_sys_ck", &sys_clkin_ck),
 +      CLK("48032000.timer",   "timer_sys_ck", &sys_clkin_ck),
 +      CLK("48034000.timer",   "timer_sys_ck", &sys_clkin_ck),
 +      CLK("48036000.timer",   "timer_sys_ck", &sys_clkin_ck),
 +      CLK("4803e000.timer",   "timer_sys_ck", &sys_clkin_ck),
 +      CLK("48086000.timer",   "timer_sys_ck", &sys_clkin_ck),
 +      CLK("48088000.timer",   "timer_sys_ck", &sys_clkin_ck),
 +      CLK("40138000.timer",   "timer_sys_ck", &syc_clk_div_ck),
 +      CLK("4013a000.timer",   "timer_sys_ck", &syc_clk_div_ck),
 +      CLK("4013c000.timer",   "timer_sys_ck", &syc_clk_div_ck),
 +      CLK("4013e000.timer",   "timer_sys_ck", &syc_clk_div_ck),
 +      CLK(NULL,       "cpufreq_ck",   &dpll_mpu_ck),
  };
  
  int __init omap4xxx_clk_init(void)

diff --cc arch/arm/mach-omap2/timer.c
Simple merge

diff --cc arch/arm/mach-s3c24xx/irq.c
Simple merge

diff --cc drivers/clk/tegra/clk-tegra20.c
Simple merge