perf/x86/intel: Fix PEBS data source interpretation on Nehalem/Westmere
authorAndi Kleen <ak@linux.intel.com>
Tue, 1 Mar 2016 22:25:24 +0000 (14:25 -0800)
committerWilly Tarreau <w@1wt.eu>
Tue, 7 Jun 2016 08:42:48 +0000 (10:42 +0200)
commit750fc132a8fe380d651ccc5d11992d9ffa4c03e7
tree6de2e6ceb81481b6a545c33276184be6347b7aaa
parent0579a12791e483fcaaad76748fb163ec855102a4
perf/x86/intel: Fix PEBS data source interpretation on Nehalem/Westmere

commit e17dc65328057c00db7e1bfea249c8771a78b30b upstream.

Jiri reported some time ago that some entries in the PEBS data source table
in perf do not agree with the SDM. We investigated and the bits
changed for Sandy Bridge, but the SDM was not updated.

perf already implements the bits correctly for Sandy Bridge
and later. This patch patches it up for Nehalem and Westmere.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: jolsa@kernel.org
Link: http://lkml.kernel.org/r/1456871124-15985-1-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Willy Tarreau <w@1wt.eu>
arch/x86/kernel/cpu/perf_event.h
arch/x86/kernel/cpu/perf_event_intel.c
arch/x86/kernel/cpu/perf_event_intel_ds.c