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(parent: fbab1c8) | patch
ARM: entry: rejig register allocation in exception entry handlers
authorRussell King <rmk+kernel@arm.linux.org.uk>
Sat, 25 Jun 2011 14:44:20 +0000 (15:44 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Thu, 30 Jun 2011 10:04:59 +0000 (11:04 +0100)
commitb059bdc39321696fe8f344acb7117d57fbd7b475
tree3a5001287ea0e16339e5cc633f1248470377f967tree | snapshot (tar.gz zip)
parentfbab1c809467efe001194ab8bb17f0f451a17f97commit | diff
ARM: entry: rejig register allocation in exception entry handlers

This allows us to avoid moving registers twice to work around the
clobbered registers when we add calls to trace_hardirqs_{on,off}.

Ensure that all SVC handlers return with SPSR in r5 for consistency.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/kernel/entry-armv.S diff | blob | blame | history
kernel source for telekom puls (alcatel/mediatek)