Merge tag 'v3.10.86' into update

[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / host / xhci.h

diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 11f12f1d5b29db245bf05fa08ee2fdc0e7916ba0..6d5839213405f87bacfe36d75a6e67da5bb68339 100644 (file)
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1,3 +1,4 @@
+
 /*
  * xHCI host controller driver
  *
@@ -32,6 +33,7 @@
 #include       "xhci-ext-caps.h"
 #include "pci-quirks.h"
 
+
 /* xHCI PCI Configuration Registers */
 #define XHCI_SBRN_OFFSET       (0x60)
 
@@ -279,6 +281,7 @@ struct xhci_op_regs {
 #define XDEV_U0                (0x0 << 5)
 #define XDEV_U2                (0x2 << 5)
 #define XDEV_U3                (0x3 << 5)
+#define XDEV_INACTIVE  (0x6 << 5)
 #define XDEV_RESUME    (0xf << 5)
 /* true: port has power (see HCC_PPC) */
 #define PORT_POWER     (1 << 9)
@@ -678,6 +681,14 @@ struct xhci_ep_ctx {
 /* deq bitmasks */
 #define EP_CTX_CYCLE_MASK              (1 << 0)
 
+#ifdef CONFIG_MTK_XHCI
+/* mtk scheduler bitmasks */
+#define BPKTS(p)       ((p) & 0x3f)
+#define BCSCOUNT(p)    (((p) & 0x7) << 8)
+#define BBM(p)         ((p) << 11)
+#define BOFFSET(p)     ((p) & 0x3fff)
+#define BREPEAT(p)     (((p) & 0x7fff) << 16)
+#endif
 
 /**
  * struct xhci_input_control_context
@@ -1236,7 +1247,7 @@ union xhci_trb {
  * since the command ring is 64-byte aligned.
  * It must also be greater than 16.
  */
-#define TRBS_PER_SEGMENT       64
+#define TRBS_PER_SEGMENT       256
 /* Allow two commands + a link TRB, along with any reserved command TRBs */
 #define MAX_RSVD_CMD_TRBS      (TRBS_PER_SEGMENT - 3)
 #define TRB_SEGMENT_SIZE       (TRBS_PER_SEGMENT*16)
@@ -1259,6 +1270,8 @@ struct xhci_td {
        struct xhci_segment     *start_seg;
        union xhci_trb          *first_trb;
        union xhci_trb          *last_trb;
+       /* actual_length of the URB has already been set */
+       bool                    urb_length_set;
 };
 
 /* xHCI command default timeout value */
@@ -1409,6 +1422,12 @@ struct xhci_hcd {
        /* Our HCD's current interrupter register set */
        struct  xhci_intr_reg __iomem *ir_set;
 
+       #ifdef CONFIG_MTK_XHCI
+       unsigned long base_regs;
+       unsigned long sif_regs;
+       unsigned long sif2_regs;
+       #endif
+
        /* Cached register copies of read-only HC data */
        __u32           hcs_params1;
        __u32           hcs_params2;
@@ -1495,7 +1514,9 @@ struct xhci_hcd {
 #define        XHCI_LINK_TRB_QUIRK     (1 << 0)
 #define XHCI_RESET_EP_QUIRK    (1 << 1)
 #define XHCI_NEC_HOST          (1 << 2)
+#ifndef CONFIG_MTK_XHCI
 #define XHCI_AMD_PLL_FIX       (1 << 3)
+#endif
 #define XHCI_SPURIOUS_SUCCESS  (1 << 4)
 /*
  * Certain Intel host controllers have a limit to the number of endpoint
@@ -1510,7 +1531,9 @@ struct xhci_hcd {
 #define XHCI_BROKEN_MSI                (1 << 6)
 #define XHCI_RESET_ON_RESUME   (1 << 7)
 #define        XHCI_SW_BW_CHECKING     (1 << 8)
+#ifndef CONFIG_MTK_XHCI
 #define XHCI_AMD_0x96_HOST     (1 << 9)
+#endif
 #define XHCI_TRUST_TX_LENGTH   (1 << 10)
 #define XHCI_LPM_SUPPORT       (1 << 11)
 #define XHCI_INTEL_HOST                (1 << 12)
@@ -1572,12 +1595,12 @@ static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
 /* TODO: copied from ehci.h - can be refactored? */
 /* xHCI spec says all registers are little endian */
 static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
-               __le32 __iomem *regs)
+               void __iomem *regs)
 {
        return readl(regs);
 }
 static inline void xhci_writel(struct xhci_hcd *xhci,
-               const unsigned int val, __le32 __iomem *regs)
+               const unsigned int val, void __iomem *regs)
 {
        writel(val, regs);
 }