* carry over the chain bit of the previous TRB
* (which may mean the chain bit is cleared).
*/
+ #ifdef CONFIG_MTK_XHCI
+ if (!xhci_link_trb_quirk(xhci)) {
+ #else
if (!(ring->type == TYPE_ISOC &&
(xhci->quirks & XHCI_AMD_0x96_HOST))
&& !xhci_link_trb_quirk(xhci)) {
+ #endif
next->link.control &=
cpu_to_le32(~TRB_CHAIN);
next->link.control |=
static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
unsigned int num_trbs)
{
+#ifndef CONFIG_MTK_XHCI
int num_trbs_in_deq_seg;
+#endif
if (ring->num_trbs_free < num_trbs)
return 0;
+#ifndef CONFIG_MTK_XHCI
if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
return 0;
}
+#endif
return 1;
}
if (urb_priv->td_cnt == urb_priv->length) {
if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
+ #ifndef CONFIG_MTK_XHCI
if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
if (xhci->quirks & XHCI_AMD_PLL_FIX)
usb_amd_quirk_pll_enable();
}
+ #endif
}
usb_hcd_unlink_urb_from_ep(hcd, urb);
ret = 1;
if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
+ #ifndef CONFIG_MTK_XHCI
if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
== 0) {
if (xhci->quirks & XHCI_AMD_PLL_FIX)
usb_amd_quirk_pll_enable();
}
+ #endif
}
}
}
* successful event after a short transfer.
* Ignore it.
*/
- if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
+ if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
ep_ring->last_td_was_short) {
ep_ring->last_td_was_short = false;
ret = 0;
/* If we're not dealing with 0.95 hardware or isoc rings
* on AMD 0.96 host, clear the chain bit.
*/
+ #ifndef CONFIG_MTK_XHCI
if (!xhci_link_trb_quirk(xhci) &&
!(ring->type == TYPE_ISOC &&
(xhci->quirks & XHCI_AMD_0x96_HOST)))
next->link.control &= cpu_to_le32(~TRB_CHAIN);
else
next->link.control |= cpu_to_le32(TRB_CHAIN);
-
+ #else
+ next->link.control &= cpu_to_le32(~TRB_CHAIN);
+ #endif
wmb();
next->link.control ^= cpu_to_le32(TRB_CYCLE);
* right shifted by 10.
* It must fit in bits 21:17, so it can't be bigger than 31.
*/
+#ifdef CONFIG_MTK_XHCI
+static u32 xhci_td_remainder(unsigned int td_transfer_size, unsigned int td_running_total
+ , unsigned int maxp, unsigned trb_buffer_length)
+{
+ u32 max = 31;
+ int remainder, td_packet_count, packet_transferred;
+
+ //0 for the last TRB
+ //FIXME: need to workaround if there is ZLP in this TD
+ if (td_running_total + trb_buffer_length == td_transfer_size)
+ return 0;
+
+ //FIXME: need to take care of high-bandwidth (MAX_ESIT)
+ packet_transferred = (td_running_total /*+ trb_buffer_length*/) / maxp;
+ td_packet_count = DIV_ROUND_UP(td_transfer_size, maxp);
+ remainder = td_packet_count - packet_transferred;
+
+ if (remainder > max)
+ return max << 17;
+ else
+ return remainder << 17;
+}
+#else
static u32 xhci_td_remainder(unsigned int remainder)
{
u32 max = (1 << (21 - 17 + 1)) - 1;
else
return (remainder >> 10) << 17;
}
+#endif
+
+#ifndef CONFIG_MTK_XHCI
/*
* For xHCI 1.0 host controllers, TD size is the number of max packet sized
* packets remaining in the TD (*not* including this TRB).
return 31 << 17;
return (total_packet_count - packets_transferred) << 17;
}
+#endif
static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
struct urb *urb, int slot_id, unsigned int ep_index)
(unsigned int) addr + trb_buff_len);
}
+ /* Set the TRB length, TD size, and interrupter fields. */
+ #ifdef CONFIG_MTK_XHCI
+ if(num_trbs >1){
+ remainder = xhci_td_remainder(urb->transfer_buffer_length,
+ running_total, urb->ep->desc.wMaxPacketSize, trb_buff_len);
+ }
+ #else
/* Set the TRB length, TD size, and interrupter fields. */
if (xhci->hci_version < 0x100) {
remainder = xhci_td_remainder(
trb_buff_len, total_packet_count, urb,
num_trbs - 1);
}
+ #endif
+
length_field = TRB_LEN(trb_buff_len) |
remainder |
TRB_INTR_TARGET(0);
bool more_trbs_coming;
int start_cycle;
u32 field, length_field;
-
+#ifdef CONFIG_MTK_XHCI
+ int max_packet = USB_SPEED_HIGH;
+#endif
int running_total, trb_buff_len, ret;
unsigned int total_packet_count;
u64 addr;
}
/* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
+#ifdef CONFIG_MTK_XHCI
+ switch(urb->dev->speed){
+ case USB_SPEED_SUPER:
+ max_packet = urb->ep->desc.wMaxPacketSize;
+ break;
+ case USB_SPEED_HIGH:
+ case USB_SPEED_FULL:
+ case USB_SPEED_LOW:
+ default:
+ max_packet = urb->ep->desc.wMaxPacketSize & 0x7ff;
+ break;
+ }
+ if((urb->transfer_flags & URB_ZERO_PACKET)
+ && ((urb->transfer_buffer_length % max_packet) == 0)){
+ num_trbs++;
+ }
+#endif
+
ret = prepare_transfer(xhci, xhci->devs[slot_id],
ep_index, urb->stream_id,
num_trbs, urb, 0, mem_flags);
/* Only set interrupt on short packet for IN endpoints */
if (usb_urb_dir_in(urb))
field |= TRB_ISP;
-
+ #ifdef CONFIG_MTK_XHCI
+ remainder = xhci_td_remainder(urb->transfer_buffer_length, running_total, max_packet, trb_buff_len);
+ #else
/* Set the TRB length, TD size, and interrupter fields. */
if (xhci->hci_version < 0x100) {
remainder = xhci_td_remainder(
trb_buff_len, total_packet_count, urb,
num_trbs - 1);
}
+ #endif
length_field = TRB_LEN(trb_buff_len) |
remainder |
TRB_INTR_TARGET(0);
field |= 0x1;
/* xHCI 1.0 6.4.1.2.1: Transfer Type field */
+#ifdef CONFIG_MTK_XHCI
+ if(1){
+#else
if (xhci->hci_version == 0x100) {
+#endif
if (urb->transfer_buffer_length > 0) {
if (setup->bRequestType & USB_DIR_IN)
field |= TRB_TX_TYPE(TRB_DATA_IN);
field = TRB_TYPE(TRB_DATA);
length_field = TRB_LEN(urb->transfer_buffer_length) |
+ #ifdef CONFIG_MTK_XHCI
+ //CC: MTK style, no scatter-gather for control transfer
+ 0 |
+ #else
xhci_td_remainder(urb->transfer_buffer_length) |
+ #endif
TRB_INTR_TARGET(0);
if (urb->transfer_buffer_length > 0) {
if (setup->bRequestType & USB_DIR_IN)
u64 start_addr, addr;
int i, j;
bool more_trbs_coming;
+#ifdef CONFIG_MTK_XHCI
+ int max_packet = USB_SPEED_HIGH;
+#endif
ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
start_trb = &ep_ring->enqueue->generic;
start_cycle = ep_ring->cycle_state;
+#ifdef CONFIG_MTK_XHCI
+ switch(urb->dev->speed){
+ case USB_SPEED_SUPER:
+ max_packet = urb->ep->desc.wMaxPacketSize;
+ break;
+ case USB_SPEED_HIGH:
+ case USB_SPEED_FULL:
+ case USB_SPEED_LOW:
+ default:
+ max_packet = urb->ep->desc.wMaxPacketSize & 0x7ff;
+ break;
+ }
+#endif
urb_priv = urb->hcpriv;
/* Queue the first TRB, even if it's zero-length */
for (i = 0; i < num_tds; i++) {
trb_buff_len = td_remain_len;
/* Set the TRB length, TD size, & interrupter fields. */
+ #ifdef CONFIG_MTK_XHCI
+ remainder = xhci_td_remainder(urb->transfer_buffer_length, running_total, max_packet, trb_buff_len);
+ #else
if (xhci->hci_version < 0x100) {
remainder = xhci_td_remainder(
td_len - running_total);
total_packet_count, urb,
(trbs_per_td - j - 1));
}
+ #endif
length_field = TRB_LEN(trb_buff_len) |
remainder |
TRB_INTR_TARGET(0);
goto cleanup;
}
}
-
+ #ifndef CONFIG_MTK_XHCI
if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
if (xhci->quirks & XHCI_AMD_PLL_FIX)
usb_amd_quirk_pll_disable();
}
+ #endif
xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blobdiff