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import OT_8063_20170412 mali driver
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / misc / mediatek / gpu / mt8127 / mali / mali / regs / mali_gp_regs.h
diff --git a/drivers/misc/mediatek/gpu/mt8127/mali/mali/regs/mali_gp_regs.h b/drivers/misc/mediatek/gpu/mt8127/mali/mali/regs/mali_gp_regs.h
index e865e13bbb8c9e586ee3b837b4d98bcc0040159d..779f7b84d33ea40fdd819437d7ee3491a9d9b0d1 100644 (file)
--- a/drivers/misc/mediatek/gpu/mt8127/mali/mali/regs/mali_gp_regs.h
+++ b/drivers/misc/mediatek/gpu/mt8127/mali/mali/regs/mali_gp_regs.h
@@ -1,7 +1,7 @@
 /*
  * This confidential and proprietary software may be used only as
  * authorised by a licensing agreement from ARM Limited
- * (C) COPYRIGHT 2007-2010, 2012-2013 ARM Limited
+ * (C) COPYRIGHT 2007-2010, 2012-2015 ARM Limited
  * ALL RIGHTS RESERVED
  * The entire notice above must be reproduced on all authorised
  * copies and copies may only be made to the extent permitted
@@ -31,13 +31,13 @@ typedef enum {
        MALIGP2_REG_ADDR_MGMT_INT_CLEAR                 = 0x28,
        MALIGP2_REG_ADDR_MGMT_INT_MASK                  = 0x2C,
        MALIGP2_REG_ADDR_MGMT_INT_STAT                  = 0x30,
-       MALIGP2_REG_ADDR_MGMT_WRITE_BOUND_LOW           = 0x34,
        MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_ENABLE         = 0x3C,
        MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_ENABLE         = 0x40,
        MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_SRC            = 0x44,
        MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_SRC            = 0x48,
        MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_VALUE          = 0x4C,
        MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_VALUE          = 0x50,
+       MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_LIMIT          = 0x54,
        MALIGP2_REG_ADDR_MGMT_STATUS                    = 0x68,
        MALIGP2_REG_ADDR_MGMT_VERSION                   = 0x6C,
        MALIGP2_REG_ADDR_MGMT_VSCL_START_ADDR_READ      = 0x80,
@@ -53,13 +53,13 @@ typedef enum {
  *  @see MALIGP2_CTRL_REG_CMD
  */
 typedef enum {
-       MALIGP2_REG_VAL_CMD_START_VS                    = (1<< 0),
-       MALIGP2_REG_VAL_CMD_START_PLBU                  = (1<< 1),
-       MALIGP2_REG_VAL_CMD_UPDATE_PLBU_ALLOC   = (1<< 4),
-       MALIGP2_REG_VAL_CMD_RESET                               = (1<< 5),
-       MALIGP2_REG_VAL_CMD_FORCE_HANG                  = (1<< 6),
-       MALIGP2_REG_VAL_CMD_STOP_BUS                    = (1<< 9),
-       MALI400GP_REG_VAL_CMD_SOFT_RESET                = (1<<10), /* only valid for Mali-300 and later */
+       MALIGP2_REG_VAL_CMD_START_VS                    = (1 << 0),
+       MALIGP2_REG_VAL_CMD_START_PLBU                  = (1 << 1),
+       MALIGP2_REG_VAL_CMD_UPDATE_PLBU_ALLOC   = (1 << 4),
+       MALIGP2_REG_VAL_CMD_RESET                               = (1 << 5),
+       MALIGP2_REG_VAL_CMD_FORCE_HANG                  = (1 << 6),
+       MALIGP2_REG_VAL_CMD_STOP_BUS                    = (1 << 9),
+       MALI400GP_REG_VAL_CMD_SOFT_RESET                = (1 << 10), /* only valid for Mali-300 and later */
 } mgp_contr_reg_val_cmd;
 
 
@@ -92,41 +92,41 @@ typedef enum {
 /* Mask defining all IRQs in Mali GP */
 #define MALIGP2_REG_VAL_IRQ_MASK_ALL \
        (\
-               MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST      | \
-               MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST    | \
-               MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM     | \
-               MALIGP2_REG_VAL_IRQ_VS_SEM_IRQ          | \
-               MALIGP2_REG_VAL_IRQ_PLBU_SEM_IRQ        | \
-               MALIGP2_REG_VAL_IRQ_HANG                | \
-               MALIGP2_REG_VAL_IRQ_FORCE_HANG          | \
-               MALIGP2_REG_VAL_IRQ_PERF_CNT_0_LIMIT    | \
-               MALIGP2_REG_VAL_IRQ_PERF_CNT_1_LIMIT    | \
-               MALIGP2_REG_VAL_IRQ_WRITE_BOUND_ERR     | \
-               MALIGP2_REG_VAL_IRQ_SYNC_ERROR          | \
-               MALIGP2_REG_VAL_IRQ_AXI_BUS_ERROR       | \
-               MALI400GP_REG_VAL_IRQ_AXI_BUS_STOPPED     | \
-               MALI400GP_REG_VAL_IRQ_VS_INVALID_CMD      | \
-               MALI400GP_REG_VAL_IRQ_PLB_INVALID_CMD     | \
-               MALI400GP_REG_VAL_IRQ_RESET_COMPLETED     | \
-               MALI400GP_REG_VAL_IRQ_SEMAPHORE_UNDERFLOW | \
-               MALI400GP_REG_VAL_IRQ_SEMAPHORE_OVERFLOW  | \
-               MALI400GP_REG_VAL_IRQ_PTR_ARRAY_OUT_OF_BOUNDS)
+        MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST      | \
+        MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST    | \
+        MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM     | \
+        MALIGP2_REG_VAL_IRQ_VS_SEM_IRQ          | \
+        MALIGP2_REG_VAL_IRQ_PLBU_SEM_IRQ        | \
+        MALIGP2_REG_VAL_IRQ_HANG                | \
+        MALIGP2_REG_VAL_IRQ_FORCE_HANG          | \
+        MALIGP2_REG_VAL_IRQ_PERF_CNT_0_LIMIT    | \
+        MALIGP2_REG_VAL_IRQ_PERF_CNT_1_LIMIT    | \
+        MALIGP2_REG_VAL_IRQ_WRITE_BOUND_ERR     | \
+        MALIGP2_REG_VAL_IRQ_SYNC_ERROR          | \
+        MALIGP2_REG_VAL_IRQ_AXI_BUS_ERROR       | \
+        MALI400GP_REG_VAL_IRQ_AXI_BUS_STOPPED     | \
+        MALI400GP_REG_VAL_IRQ_VS_INVALID_CMD      | \
+        MALI400GP_REG_VAL_IRQ_PLB_INVALID_CMD     | \
+        MALI400GP_REG_VAL_IRQ_RESET_COMPLETED     | \
+        MALI400GP_REG_VAL_IRQ_SEMAPHORE_UNDERFLOW | \
+        MALI400GP_REG_VAL_IRQ_SEMAPHORE_OVERFLOW  | \
+        MALI400GP_REG_VAL_IRQ_PTR_ARRAY_OUT_OF_BOUNDS)
 
 /* Mask defining the IRQs in Mali GP which we use */
 #define MALIGP2_REG_VAL_IRQ_MASK_USED \
        (\
-               MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST      | \
-               MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST    | \
-               MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM     | \
-               MALIGP2_REG_VAL_IRQ_FORCE_HANG          | \
-               MALIGP2_REG_VAL_IRQ_WRITE_BOUND_ERR     | \
-               MALIGP2_REG_VAL_IRQ_SYNC_ERROR          | \
-               MALIGP2_REG_VAL_IRQ_AXI_BUS_ERROR       | \
-               MALI400GP_REG_VAL_IRQ_VS_INVALID_CMD      | \
-               MALI400GP_REG_VAL_IRQ_PLB_INVALID_CMD     | \
-               MALI400GP_REG_VAL_IRQ_SEMAPHORE_UNDERFLOW | \
-               MALI400GP_REG_VAL_IRQ_SEMAPHORE_OVERFLOW  | \
-               MALI400GP_REG_VAL_IRQ_PTR_ARRAY_OUT_OF_BOUNDS)
+        MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST      | \
+        MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST    | \
+        MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM     | \
+        MALIGP2_REG_VAL_IRQ_FORCE_HANG          | \
+        MALIGP2_REG_VAL_IRQ_WRITE_BOUND_ERR     | \
+        MALIGP2_REG_VAL_IRQ_SYNC_ERROR          | \
+        MALIGP2_REG_VAL_IRQ_AXI_BUS_ERROR       | \
+        MALI400GP_REG_VAL_IRQ_VS_INVALID_CMD      | \
+        MALI400GP_REG_VAL_IRQ_PLB_INVALID_CMD     | \
+        MALI400GP_REG_VAL_IRQ_SEMAPHORE_UNDERFLOW | \
+        MALI400GP_REG_VAL_IRQ_SEMAPHORE_OVERFLOW  | \
+        MALI400GP_REG_VAL_IRQ_PTR_ARRAY_OUT_OF_BOUNDS)
 
 /* Mask defining non IRQs on MaliGP2*/
 #define MALIGP2_REG_VAL_IRQ_MASK_NONE 0
@@ -146,13 +146,13 @@ typedef enum {
 /** }@ defgroup MALIGP2_STATUS*/
 
 #define MALIGP2_REG_VAL_STATUS_MASK_ACTIVE (\
-       MALIGP2_REG_VAL_STATUS_VS_ACTIVE|\
-       MALIGP2_REG_VAL_STATUS_PLBU_ACTIVE)
+               MALIGP2_REG_VAL_STATUS_VS_ACTIVE|\
+               MALIGP2_REG_VAL_STATUS_PLBU_ACTIVE)
 
 
 #define MALIGP2_REG_VAL_STATUS_MASK_ERROR (\
-       MALIGP2_REG_VAL_STATUS_BUS_ERROR |\
-       MALIGP2_REG_VAL_STATUS_WRITE_BOUND_ERR )
+               MALIGP2_REG_VAL_STATUS_BUS_ERROR |\
+               MALIGP2_REG_VAL_STATUS_WRITE_BOUND_ERR )
 
 /* This should be in the top 16 bit of the version register of gp.*/
 #define MALI200_GP_PRODUCT_ID 0xA07
kernel source for telekom puls (alcatel/mediatek)