Merge tag 'kvm-3.10-1' of git://git.kernel.org/pub/scm/virt/kvm/kvm

[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / include / asm / reg.h

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index c9c67fc888c93d229b23a617d0fd9c2aa7a71e79..a6136515c7f2952d82843eb47586901b3747f22f 100644 (file)
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -267,7 +267,17 @@
 #define SPRN_HSRR1     0x13B   /* Hypervisor Save/Restore 1 */
 #define SPRN_FSCR      0x099   /* Facility Status & Control Register */
 #define   FSCR_TAR     (1 << (63-55)) /* Enable Target Address Register */
+#define   FSCR_EBB     (1 << (63-56)) /* Enable Event Based Branching */
 #define   FSCR_DSCR    (1 << (63-61)) /* Enable Data Stream Control Register */
+#define SPRN_HFSCR     0xbe    /* HV=1 Facility Status & Control Register */
+#define   HFSCR_TAR    (1 << (63-55)) /* Enable Target Address Register */
+#define   HFSCR_EBB    (1 << (63-56)) /* Enable Event Based Branching */
+#define   HFSCR_TM     (1 << (63-58)) /* Enable Transactional Memory */
+#define   HFSCR_PM     (1 << (63-60)) /* Enable prob/priv access to PMU SPRs */
+#define   HFSCR_BHRB   (1 << (63-59)) /* Enable Branch History Rolling Buffer*/
+#define   HFSCR_DSCR   (1 << (63-61)) /* Enable Data Stream Control Register */
+#define   HFSCR_VECVSX (1 << (63-62)) /* Enable VMX/VSX  */
+#define   HFSCR_FP     (1 << (63-63)) /* Enable Floating Point */
 #define SPRN_TAR       0x32f   /* Target Address Register */
 #define SPRN_LPCR      0x13E   /* LPAR Control Register */
 #define   LPCR_VPM0    (1ul << (63-0))
@@ -290,6 +300,7 @@
 #define     LPCR_PECE1 0x00002000      /* decrementer can cause exit */
 #define     LPCR_PECE2 0x00001000      /* machine check etc can cause exit */
 #define   LPCR_MER     0x00000800      /* Mediated External Exception */
+#define   LPCR_MER_SH  11
 #define   LPCR_LPES    0x0000000c
 #define   LPCR_LPES0   0x00000008      /* LPAR Env selector 0 */
 #define   LPCR_LPES1   0x00000004      /* LPAR Env selector 1 */
@@ -631,6 +642,7 @@
 #define   MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */
 #define   MMCR0_FCHV   0x00000001UL /* freeze conditions in hypervisor mode */
 #define SPRN_MMCR1     798
+#define SPRN_MMCR2     769
 #define SPRN_MMCRA     0x312
 #define   MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */
 #define   MMCRA_SDAR_DCACHE_MISS 0x40000000UL
@@ -649,6 +661,13 @@
 #define   POWER7P_MMCRA_SIAR_VALID 0x10000000  /* P7+ SIAR contents valid */
 #define   POWER7P_MMCRA_SDAR_VALID 0x08000000  /* P7+ SDAR contents valid */
 
+#define SPRN_MMCRH     316     /* Hypervisor monitor mode control register */
+#define SPRN_MMCRS     894     /* Supervisor monitor mode control register */
+#define SPRN_MMCRC     851     /* Core monitor mode control register */
+#define SPRN_EBBHR     804     /* Event based branch handler register */
+#define SPRN_EBBRR     805     /* Event based branch return register */
+#define SPRN_BESCR     806     /* Branch event status and control register */
+
 #define SPRN_PMC1      787
 #define SPRN_PMC2      788
 #define SPRN_PMC3      789
@@ -659,6 +678,11 @@
 #define SPRN_PMC8      794
 #define SPRN_SIAR      780
 #define SPRN_SDAR      781
+#define SPRN_SIER      784
+#define   SIER_SIPR            0x2000000       /* Sampled MSR_PR */
+#define   SIER_SIHV            0x1000000       /* Sampled MSR_HV */
+#define   SIER_SIAR_VALID      0x0400000       /* SIAR contents valid */
+#define   SIER_SDAR_VALID      0x0200000       /* SDAR contents valid */
 
 #define SPRN_PA6T_MMCR0 795
 #define   PA6T_MMCR0_EN0       0x0000000000000001UL