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Merge tag 'v3.10.56' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git]
/
arch
/
arm64
/
kernel
/
sys_compat.c
diff --git
a/arch/arm64/kernel/sys_compat.c
b/arch/arm64/kernel/sys_compat.c
index 26e9c4eeaba82a20f539991c754d5e40cb161e3a..dc47e53e9e28c15da99e62976a9ca29f71da8bc4 100644
(file)
--- a/
arch/arm64/kernel/sys_compat.c
+++ b/
arch/arm64/kernel/sys_compat.c
@@
-26,7
+26,7
@@
#include <linux/uaccess.h>
#include <asm/cacheflush.h>
#include <linux/uaccess.h>
#include <asm/cacheflush.h>
-#include <asm/unistd
32
.h>
+#include <asm/unistd.h>
static inline void
do_compat_cache_op(unsigned long start, unsigned long end, int flags)
static inline void
do_compat_cache_op(unsigned long start, unsigned long end, int flags)
@@
-79,6
+79,12
@@
long compat_arm_syscall(struct pt_regs *regs)
case __ARM_NR_compat_set_tls:
current->thread.tp_value = regs->regs[0];
case __ARM_NR_compat_set_tls:
current->thread.tp_value = regs->regs[0];
+
+ /*
+ * Protect against register corruption from context switch.
+ * See comment in tls_thread_flush.
+ */
+ barrier();
asm ("msr tpidrro_el0, %0" : : "r" (regs->regs[0]));
return 0;
asm ("msr tpidrro_el0, %0" : : "r" (regs->regs[0]));
return 0;