Merge tag 'v3.10.56' into update

[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm64 / kernel / sys_compat.c

diff --git a/arch/arm64/kernel/sys_compat.c b/arch/arm64/kernel/sys_compat.c
index f7b05edf8ce36c925196b59dcf4c03ac12259b73..dc47e53e9e28c15da99e62976a9ca29f71da8bc4 100644 (file)
--- a/arch/arm64/kernel/sys_compat.c
+++ b/arch/arm64/kernel/sys_compat.c
@@ -26,22 +26,7 @@
 #include <linux/uaccess.h>
 
 #include <asm/cacheflush.h>
-#include <asm/unistd32.h>
-
-asmlinkage int compat_sys_sched_rr_get_interval(compat_pid_t pid,
-                                               struct compat_timespec __user *interval)
-{
-       struct timespec t;
-       int ret;
-       mm_segment_t old_fs = get_fs();
-
-       set_fs(KERNEL_DS);
-       ret = sys_sched_rr_get_interval(pid, (struct timespec __user *)&t);
-       set_fs(old_fs);
-       if (put_compat_timespec(&t, interval))
-               return -EFAULT;
-       return ret;
-}
+#include <asm/unistd.h>
 
 static inline void
 do_compat_cache_op(unsigned long start, unsigned long end, int flags)
@@ -94,6 +79,12 @@ long compat_arm_syscall(struct pt_regs *regs)
 
        case __ARM_NR_compat_set_tls:
                current->thread.tp_value = regs->regs[0];
+
+               /*
+                * Protect against register corruption from context switch.
+                * See comment in tls_thread_flush.
+                */
+               barrier();
                asm ("msr tpidrro_el0, %0" : : "r" (regs->regs[0]));
                return 0;