import PULS_20160108

[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm64 / kernel / asm-offsets.c

diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c
index a2a4d810bea3ee70cee2a14b93faec49ba81d7c5..09e4f45f86e9421d38cb7d23332153e3f1aefd06 100644 (file)
--- a/arch/arm64/kernel/asm-offsets.c
+++ b/arch/arm64/kernel/asm-offsets.c
@@ -24,6 +24,8 @@
 #include <asm/thread_info.h>
 #include <asm/memory.h>
 #include <asm/cputable.h>
+#include <asm/smp_plat.h>
+#include <asm/suspend.h>
 #include <asm/vdso_datapage.h>
 #include <linux/kbuild.h>
 
@@ -37,6 +39,8 @@ int main(void)
   DEFINE(TI_TASK,              offsetof(struct thread_info, task));
   DEFINE(TI_EXEC_DOMAIN,       offsetof(struct thread_info, exec_domain));
   DEFINE(TI_CPU,               offsetof(struct thread_info, cpu));
+  DEFINE(TI_CPU_EXCP,          offsetof(struct thread_info, cpu_excp));
+  DEFINE(TI_REGS_ON_EXCP,      offsetof(struct thread_info, regs_on_excp));
   BLANK();
   DEFINE(THREAD_CPU_CONTEXT,   offsetof(struct task_struct, thread.cpu_context));
   BLANK();
@@ -48,6 +52,9 @@ int main(void)
   DEFINE(S_X5,                 offsetof(struct pt_regs, regs[5]));
   DEFINE(S_X6,                 offsetof(struct pt_regs, regs[6]));
   DEFINE(S_X7,                 offsetof(struct pt_regs, regs[7]));
+  DEFINE(S_X15,                        offsetof(struct pt_regs, regs[15]));
+  DEFINE(S_X16,                        offsetof(struct pt_regs, regs[16]));
+  DEFINE(S_X29,                        offsetof(struct pt_regs, regs[29]));
   DEFINE(S_LR,                 offsetof(struct pt_regs, regs[30]));
   DEFINE(S_SP,                 offsetof(struct pt_regs, sp));
 #ifdef CONFIG_COMPAT
@@ -104,5 +111,47 @@ int main(void)
   BLANK();
   DEFINE(TZ_MINWEST,           offsetof(struct timezone, tz_minuteswest));
   DEFINE(TZ_DSTTIME,           offsetof(struct timezone, tz_dsttime));
+  BLANK();
+#ifdef CONFIG_KVM_ARM_HOST
+  DEFINE(VCPU_CONTEXT,         offsetof(struct kvm_vcpu, arch.ctxt));
+  DEFINE(CPU_GP_REGS,          offsetof(struct kvm_cpu_context, gp_regs));
+  DEFINE(CPU_USER_PT_REGS,     offsetof(struct kvm_regs, regs));
+  DEFINE(CPU_FP_REGS,          offsetof(struct kvm_regs, fp_regs));
+  DEFINE(CPU_SP_EL1,           offsetof(struct kvm_regs, sp_el1));
+  DEFINE(CPU_ELR_EL1,          offsetof(struct kvm_regs, elr_el1));
+  DEFINE(CPU_SPSR,             offsetof(struct kvm_regs, spsr));
+  DEFINE(CPU_SYSREGS,          offsetof(struct kvm_cpu_context, sys_regs));
+  DEFINE(VCPU_ESR_EL2,         offsetof(struct kvm_vcpu, arch.fault.esr_el2));
+  DEFINE(VCPU_FAR_EL2,         offsetof(struct kvm_vcpu, arch.fault.far_el2));
+  DEFINE(VCPU_HPFAR_EL2,       offsetof(struct kvm_vcpu, arch.fault.hpfar_el2));
+  DEFINE(VCPU_HCR_EL2,         offsetof(struct kvm_vcpu, arch.hcr_el2));
+  DEFINE(VCPU_IRQ_LINES,       offsetof(struct kvm_vcpu, arch.irq_lines));
+  DEFINE(VCPU_HOST_CONTEXT,    offsetof(struct kvm_vcpu, arch.host_cpu_context));
+  DEFINE(VCPU_TIMER_CNTV_CTL,  offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_ctl));
+  DEFINE(VCPU_TIMER_CNTV_CVAL, offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_cval));
+  DEFINE(KVM_TIMER_CNTVOFF,    offsetof(struct kvm, arch.timer.cntvoff));
+  DEFINE(KVM_TIMER_ENABLED,    offsetof(struct kvm, arch.timer.enabled));
+  DEFINE(VCPU_KVM,             offsetof(struct kvm_vcpu, kvm));
+  DEFINE(VCPU_VGIC_CPU,                offsetof(struct kvm_vcpu, arch.vgic_cpu));
+  DEFINE(VGIC_CPU_HCR,         offsetof(struct vgic_cpu, vgic_hcr));
+  DEFINE(VGIC_CPU_VMCR,                offsetof(struct vgic_cpu, vgic_vmcr));
+  DEFINE(VGIC_CPU_MISR,                offsetof(struct vgic_cpu, vgic_misr));
+  DEFINE(VGIC_CPU_EISR,                offsetof(struct vgic_cpu, vgic_eisr));
+  DEFINE(VGIC_CPU_ELRSR,       offsetof(struct vgic_cpu, vgic_elrsr));
+  DEFINE(VGIC_CPU_APR,         offsetof(struct vgic_cpu, vgic_apr));
+  DEFINE(VGIC_CPU_LR,          offsetof(struct vgic_cpu, vgic_lr));
+  DEFINE(VGIC_CPU_NR_LR,       offsetof(struct vgic_cpu, nr_lr));
+  DEFINE(KVM_VTTBR,            offsetof(struct kvm, arch.vttbr));
+  DEFINE(KVM_VGIC_VCTRL,       offsetof(struct kvm, arch.vgic.vctrl_base));
+#endif
+#ifdef CONFIG_ARM64_CPU_SUSPEND
+  DEFINE(CPU_SUSPEND_SZ,       sizeof(struct cpu_suspend_ctx));
+  DEFINE(CPU_CTX_SP,           offsetof(struct cpu_suspend_ctx, sp));
+  DEFINE(MPIDR_HASH_MASK,      offsetof(struct mpidr_hash, mask));
+  DEFINE(MPIDR_HASH_SHIFTS,    offsetof(struct mpidr_hash, shift_aff));
+  DEFINE(SLEEP_SAVE_SP_SZ,     sizeof(struct sleep_save_sp));
+  DEFINE(SLEEP_SAVE_SP_PHYS,   offsetof(struct sleep_save_sp, save_ptr_stash_phys));
+  DEFINE(SLEEP_SAVE_SP_VIRT,   offsetof(struct sleep_save_sp, save_ptr_stash));
+#endif
   return 0;
 }