import PULS_20160108

[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm64 / include / asm / ptrace.h

diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h
index 4ce845f8ee1c4160ebfa14cc9144c2f665c3b713..2861aed5a67b62e52cf87a2a7b546b51e915d7eb 100644 (file)
--- a/arch/arm64/include/asm/ptrace.h
+++ b/arch/arm64/include/asm/ptrace.h
@@ -42,6 +42,16 @@
 #define COMPAT_PSR_MODE_UND    0x0000001b
 #define COMPAT_PSR_MODE_SYS    0x0000001f
 #define COMPAT_PSR_T_BIT       0x00000020
+#define COMPAT_PSR_F_BIT       0x00000040
+#define COMPAT_PSR_I_BIT       0x00000080
+#define COMPAT_PSR_A_BIT       0x00000100
+#define COMPAT_PSR_E_BIT       0x00000200
+#define COMPAT_PSR_J_BIT       0x01000000
+#define COMPAT_PSR_Q_BIT       0x08000000
+#define COMPAT_PSR_V_BIT       0x10000000
+#define COMPAT_PSR_C_BIT       0x20000000
+#define COMPAT_PSR_Z_BIT       0x40000000
+#define COMPAT_PSR_N_BIT       0x80000000
 #define COMPAT_PSR_IT_MASK     0x0600fc00      /* If-Then execution state mask */
 /*
  * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
@@ -50,6 +60,15 @@
 #define COMPAT_PT_TEXT_ADDR            0x10000
 #define COMPAT_PT_DATA_ADDR            0x10004
 #define COMPAT_PT_TEXT_END_ADDR                0x10008
+
+/*
+ * used to skip a system call when tracer changes its number to -1
+ * with ptrace(PTRACE_SET_SYSCALL)
+ */
+#define RET_SKIP_SYSCALL       -1
+#define RET_SKIP_SYSCALL_TRACE -2
+#define IS_SKIP_SYSCALL(no)    ((int)(no & 0xffffffff) == -1)
+
 #ifndef __ASSEMBLY__
 
 /* sizeof(struct user) for AArch32 */
@@ -121,7 +140,12 @@ struct pt_regs {
        (!((regs)->pstate & PSR_F_BIT))
 
 #define user_stack_pointer(regs) \
-       ((regs)->sp)
+       (!compat_user_mode(regs) ? (regs)->sp : (regs)->compat_sp)
+
+static inline unsigned long regs_return_value(struct pt_regs *regs)
+{
+       return regs->regs[0];
+}
 
 /*
  * Are the current registers suitable for user mode? (used to maintain
@@ -153,7 +177,7 @@ static inline int valid_user_regs(struct user_pt_regs *regs)
        return 0;
 }
 
-#define instruction_pointer(regs)      (regs)->pc
+#define instruction_pointer(regs)      ((unsigned long)(regs)->pc)
 
 #ifdef CONFIG_SMP
 extern unsigned long profile_pc(struct pt_regs *regs);
@@ -161,7 +185,13 @@ extern unsigned long profile_pc(struct pt_regs *regs);
 #define profile_pc(regs) instruction_pointer(regs)
 #endif
 
-extern int aarch32_break_trap(struct pt_regs *regs);
+/*
+ * True if instr is a 32-bit thumb instruction. This works if instr
+ * is the first or only half-word of a thumb instruction. It also works
+ * when instr holds all 32-bits of a wide thumb instruction if stored
+ * in the form (first_half<<16)|(second_half)
+ */
+#define is_wide_instruction(instr)     ((unsigned)(instr) >= 0xe800)
 
 #endif /* __ASSEMBLY__ */
 #endif