select ARCH_SUPPORTS_ATOMIC_RMW
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
+ select ARM_HAS_SG_CHAIN
select ARCH_WANT_FRAME_POINTERS
select ARM_AMBA
select ARM_ARCH_TIMER
- select ARM_GIC
+ select AUDIT_ARCH_COMPAT_GENERIC
select CLONE_BACKWARDS
select COMMON_CLK
+ select ARM_GIC
select GENERIC_CLOCKEVENTS
+ select GENERIC_CLOCKEVENTS_BROADCAST if SMP
+ select GENERIC_CPU_AUTOPROBE
select GENERIC_IOMAP
select GENERIC_IRQ_PROBE
select GENERIC_IRQ_SHOW
select GENERIC_SMP_IDLE_THREAD
select GENERIC_TIME_VSYSCALL
select HARDIRQS_SW_RESEND
+ select HAVE_ARCH_JUMP_LABEL
+ select HAVE_ARCH_AUDITSYSCALL
+ select HAVE_ARCH_SECCOMP_FILTER
+ select HAVE_ARCH_KGDB
select HAVE_ARCH_TRACEHOOK
+ select HAVE_C_RECORDMCOUNT
select HAVE_DEBUG_BUGVERBOSE
select HAVE_DEBUG_KMEMLEAK
select HAVE_DMA_API_DEBUG
select HAVE_DMA_ATTRS
+ select HAVE_DYNAMIC_FTRACE
+ select HAVE_FTRACE_MCOUNT_RECORD
+ select HAVE_FUNCTION_TRACER
+ select HAVE_FUNCTION_GRAPH_TRACER
select HAVE_GENERIC_DMA_COHERENT
select HAVE_GENERIC_HARDIRQS
select HAVE_HW_BREAKPOINT if PERF_EVENTS
select HAVE_MEMBLOCK
select HAVE_PERF_EVENTS
+ select HAVE_SYSCALL_TRACEPOINTS
select IRQ_DOMAIN
select MODULES_USE_ELF_RELA
select NO_BOOTMEM
select OF
select OF_EARLY_FLATTREE
+ select OF_RESERVED_MEM
select PERF_USE_VMALLOC
select POWER_RESET
select POWER_SUPPLY
help
ARM 64-bit (AArch64) Linux support.
+config ARM_HAS_SG_CHAIN
+ def_bool y
+
config 64BIT
def_bool y
config RWSEM_GENERIC_SPINLOCK
def_bool y
+config ARCH_HAS_CPUFREQ
+ bool
+ help
+ Internal node to signify that the ARCH has CPUFREQ support
+ and that the relevant menu configurations are displayed for
+ it.
+
config GENERIC_HWEIGHT
def_bool y
config GENERIC_CALIBRATE_DELAY
def_bool y
-config ZONE_DMA32
+config ZONE_DMA
def_bool y
config ARCH_DMA_ADDR_T_64BIT
config IOMMU_HELPER
def_bool SWIOTLB
+config ARM_ERRATA_824069
+ bool "ARM errata: Cache line might not be marked as clean after a CleanShared snoop"
+ depends on SMP
+ help
+ This option enables the workaround for erratum 824069
+ affecting Cortex-A53 MPCore with two or more processors (r0p0..r0p2).
+ If a Cortex-A53 processor is executing a store or PLDW instruction at the same time
+ as a processor in another cluster is executing a cache maintenance operation
+ to the same address, then this erratum might cause a clean cache line to be
+ incorrectly marked as dirty. This workaround replaces all cache clean opeartion
+ to clean & invalidate.
+
+config KERNEL_MODE_NEON
+ def_bool y
+
source "init/Kconfig"
source "kernel/Kconfig.freezer"
This enables support for the ARMv8 software model (Versatile
Express).
+config ARCH_MT6735
+ bool "MediaTek MT6735"
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
+ select ARCH_HAS_CPUFREQ
+ select ARM_AMBA
+ select CPU_V7
+ select HAVE_SMP
+ select NEED_MACH_MEMORY_H
+ select IRQ_DOMAIN
+ select IRQ_DOMAIN_DEBUG
+ select GENERIC_SCHED_CLOCK
+ select MTK_SYSTRACKER
+ select ARMV7_COMPAT
+ select ARMV7_COMPAT_CPUINFO
+ help
+ This enable support for MediaTek MT6735
+
+config ARCH_MT6735M
+ bool "MediaTek MT6735M"
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
+ select ARCH_HAS_CPUFREQ
+ select ARM_AMBA
+ select CPU_V7
+ select HAVE_SMP
+ select NEED_MACH_MEMORY_H
+ select IRQ_DOMAIN
+ select IRQ_DOMAIN_DEBUG
+ select GENERIC_SCHED_CLOCK
+ select MTK_SYSTRACKER
+ select ARMV7_COMPAT
+ select ARMV7_COMPAT_CPUINFO
+ help
+ This enable support for MediaTek MT6735M
+
+config ARCH_MT6753
+ bool "MediaTek MT6735M"
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
+ select ARCH_HAS_CPUFREQ
+ select ARM_AMBA
+ select CPU_V7
+ select HAVE_SMP
+ select NEED_MACH_MEMORY_H
+ select IRQ_DOMAIN
+ select IRQ_DOMAIN_DEBUG
+ select GENERIC_SCHED_CLOCK
+ select MTK_SYSTRACKER
+ select ARMV7_COMPAT
+ select ARMV7_COMPAT_CPUINFO
+ help
+ This enable support for MediaTek MT6753
+
+config ARCH_MT6752
+ bool "MediaTek MT6752"
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
+ select ARCH_HAS_CPUFREQ
+ select ARM_AMBA
+ select CPU_V7
+ select HAVE_SMP
+ select NEED_MACH_MEMORY_H
+ select IRQ_DOMAIN
+ select IRQ_DOMAIN_DEBUG
+ select GENERIC_SCHED_CLOCK
+ select MTK_SYSTRACKER
+ select MTK_L2C_SHARE
+ select ARCH_REQUIRE_GPIOLIB
+ select MTK_ETM
+ select MTK_EIC
+ select ARMV7_COMPAT
+ select ARMV7_COMPAT_CPUINFO
+ help
+ This enable support for MediaTek MT6752
+
+config ARCH_MT6795
+ bool "MediaTek MT6795"
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
+ select ARCH_HAS_CPUFREQ
+ select ARM_AMBA
+ select CPU_V7
+ select HAVE_SMP
+ select NEED_MACH_MEMORY_H
+ select FIQ_GLUE
+ select IRQ_DOMAIN
+ select IRQ_DOMAIN_DEBUG
+ select GENERIC_SCHED_CLOCK
+ select ARCH_REQUIRE_GPIOLIB
+ select MTK_CIRQ
+ select MTK_CPU_STRESS
+ select MTK_SYSTRACKER
+ select MTK_LASTPC
+ select ARMV7_COMPAT
+ select ARMV7_COMPAT_CPUINFO
+ help
+ This enable support for MediaTek MT6795
endmenu
+source "drivers/misc/mediatek/mach/Kconfig"
+
menu "Bus support"
config ARM_AMBA
If you don't know what to do here, say N.
+config ARM_CPU_TOPOLOGY
+ bool "Support CPU topology definition"
+ depends on SMP
+ default y
+ help
+ Support CPU topology definition, based on configuration
+ provided by the firmware.
+
+config SCHED_MC
+ bool "Multi-core scheduler support"
+ depends on ARM_CPU_TOPOLOGY
+ help
+ Multi-core scheduler support improves the CPU scheduler's decision
+ making when dealing with multi-core CPU chips at a cost of slightly
+ increased overhead in some places. If unsure say N here.
+
+config SCHED_SMT
+ bool "SMT scheduler support"
+ depends on ARM_CPU_TOPOLOGY
+ help
+ Improves the CPU scheduler's decision making when dealing with
+ MultiThreading at a cost of slightly increased overhead in some
+ places. If unsure say N here.
+
+config DISABLE_CPU_SCHED_DOMAIN_BALANCE
+ bool "(EXPERIMENTAL) Disable CPU level scheduler load-balancing"
+ help
+ Disables scheduler load-balancing at CPU sched domain level.
+
+config SCHED_HMP
+ bool "(EXPERIMENTAL) Heterogenous multiprocessor scheduling"
+ depends on DISABLE_CPU_SCHED_DOMAIN_BALANCE && SCHED_MC && FAIR_GROUP_SCHED && !SCHED_AUTOGROUP
+ help
+ Experimental scheduler optimizations for heterogeneous platforms.
+ Attempts to introspectively select task affinity to optimize power
+ and performance. Basic support for multiple (>2) cpu types is in place,
+ but it has only been tested with two types of cpus.
+ There is currently no support for migration of task groups, hence
+ !SCHED_AUTOGROUP. Furthermore, normal load-balancing must be disabled
+ between cpus of different type (DISABLE_CPU_SCHED_DOMAIN_BALANCE).
+
+config SCHED_HMP_PRIO_FILTER
+ bool "(EXPERIMENTAL) Filter HMP migrations by task priority"
+ depends on SCHED_HMP
+ help
+ Enables task priority based HMP migration filter. Any task with
+ a NICE value above the threshold will always be on low-power cpus
+ with less compute capacity.
+
+config SCHED_HMP_PRIO_FILTER_VAL
+ int "NICE priority threshold"
+ default 5
+ depends on SCHED_HMP_PRIO_FILTER
+
+config HMP_FAST_CPU_MASK
+ string "HMP scheduler fast CPU mask"
+ depends on SCHED_HMP
+ help
+ Leave empty to use device tree information.
+ Specify the cpuids of the fast CPUs in the system as a list string,
+ e.g. cpuid 0+1 should be specified as 0-1.
+
+config HMP_SLOW_CPU_MASK
+ string "HMP scheduler slow CPU mask"
+ depends on SCHED_HMP
+ help
+ Leave empty to use device tree information.
+ Specify the cpuids of the slow CPUs in the system as a list string,
+ e.g. cpuid 0+1 should be specified as 0-1.
+
+config HMP_VARIABLE_SCALE
+ bool "Allows changing the load tracking scale through sysfs"
+ depends on SCHED_HMP
+ help
+ When turned on, this option exports the thresholds and load average
+ period value for the load tracking patches through sysfs.
+ The values can be modified to change the rate of load accumulation
+ and the thresholds used for HMP migration.
+ The load_avg_period_ms is the time in ms to reach a load average of
+ 0.5 for an idle task of 0 load average ratio that start a busy loop.
+ The up_threshold and down_threshold is the value to go to a faster
+ CPU or to go back to a slower cpu.
+ The {up,down}_threshold are devided by 1024 before being compared
+ to the load average.
+ For examples, with load_avg_period_ms = 128 and up_threshold = 512,
+ a running task with a load of 0 will be migrated to a bigger CPU after
+ 128ms, because after 128ms its load_avg_ratio is 0.5 and the real
+ up_threshold is 0.5.
+ This patch has the same behavior as changing the Y of the load
+ average computation to
+ (1002/1024)^(LOAD_AVG_PERIOD/load_avg_period_ms)
+ but it remove intermadiate overflows in computation.
+
+config MET_SCHED_HMP
+ bool "(EXPERIMENTAL) MET SCHED HMP Info"
+ depends on SCHED_HMP_ENHANCEMENT
+ depends on HMP_TRACER
+ help
+ MET SCHED HMP Info
+
+config HMP_FREQUENCY_INVARIANT_SCALE
+ bool "(EXPERIMENTAL) Frequency-Invariant Tracked Load for HMP"
+ depends on HMP_VARIABLE_SCALE && CPU_FREQ
+ depends on !ARCH_SCALE_INVARIANT_CPU_CAPACITY
+ help
+ Scales the current load contribution in line with the frequency
+ of the CPU that the task was executed on.
+ In this version, we use a simple linear scale derived from the
+ maximum frequency reported by CPUFreq.
+ Restricting tracked load to be scaled by the CPU's frequency
+ represents the consumption of possible compute capacity
+ (rather than consumption of actual instantaneous capacity as
+ normal) and allows the HMP migration's simple threshold
+ migration strategy to interact more predictably with CPUFreq's
+ asynchronous compute capacity changes.
+
+config SCHED_HMP_ENHANCEMENT
+ bool "(EXPERIMENTAL) HMP Ennhancement"
+ depends on SCHED_HMP
+ help
+ HMP Ennhancement
+
+config HMP_TRACER
+ bool "(EXPERIMENTAL) Profile HMP scheduler"
+ depends on SCHED_HMP_ENHANCEMENT
+ help
+ Profile HMP scheduler
+
+config HMP_DYNAMIC_THRESHOLD
+ bool "(EXPERIMENTAL) Dynamically adjust task migration threshold"
+ depends on SCHED_HMP_ENHANCEMENT
+ help
+ Dynamically adjust task migration threshold according to current system load
+
+config HMP_GLOBAL_BALANCE
+ bool "(EXPERIMENTAL) Enhance HMP global load balance"
+ depends on SCHED_HMP_ENHANCEMENT
+ help
+ Enhance HMP global load balance
+
+config HMP_TASK_ASSIGNMENT
+ bool "(EXPERIMENTAL) Enhance HMP task assignment"
+ depends on SCHED_HMP_ENHANCEMENT
+ help
+ Enhance HMP task assignment
+
+config HMP_DISCARD_CFS_SELECTION_RESULT
+ bool "(EXPERIMENTAL) Discard CFS runqueue selection result"
+ depends on SCHED_HMP_ENHANCEMENT && HMP_TASK_ASSIGNMENT
+ help
+ Discard CFS runqueue selection result even if only one cluster exists
+
+config HMP_PACK_SMALL_TASK
+ bool "(EXPERIMENTAL) Packing Small Tasks"
+ depends on SCHED_HMP_ENHANCEMENT
+ help
+ This option enables Packing Small Tasks
+
+config HMP_PACK_BUDDY_INFO
+ bool "(EXPERIMENTAL) Packing Small Tasks Buddy Information Log"
+ depends on SCHED_HMP_ENHANCEMENT && HMP_PACK_SMALL_TASK
+ help
+ This option enables Packing Small Tasks Buddy Information Log
+
+config HMP_LAZY_BALANCE
+ bool "(EXPERIMENTAL) Lazy Balance"
+ depends on SCHED_HMP_ENHANCEMENT && HMP_PACK_SMALL_TASK
+ help
+ This option enables Lazy Balance
+
+config HMP_POWER_AWARE_CONTROLLER
+ bool "(EXPERIMENTAL) Power-aware Scheduler for b.L MP Controller"
+ depends on SCHED_HMP_ENHANCEMENT && HMP_PACK_SMALL_TASK && HMP_LAZY_BALANCE
+ help
+ Power-aware scheduler for b.L MP controller and status interface
+
+config HEVTASK_INTERFACE
+ bool "task status interface"
+ help
+ The option provide an interface to show task status
+
+config ARCH_SCALE_INVARIANT_CPU_CAPACITY
+ bool "(EXPERIMENTAL) Scale-Invariant CPU Compute Capacity Recording"
+ depends on CPU_FREQ
+ help
+ Provides a new measure of maximum and instantaneous CPU compute
+ capacity, derived from a table of relative compute performance
+ for each core type present in the system. The table is an
+ estimate and specific core performance may be different for
+ any particular workload. The measure includes the relative
+ performance and a linear scale of current to maximum frequency
+ such that at maximum frequency (as expressed in the DTB) the
+ reported compute capacity will be equal to the estimated
+ performance from the table. Values range between 0 and 1023 where
+ 1023 is the highest capacity available in the system.
+
config NR_CPUS
int "Maximum number of CPUs (2-32)"
range 2 32
depends on SMP
default "4"
+config SWP_EMULATE
+ bool "Emulate SWP/SWPB instructions"
+ help
+ ARMv6 architecture deprecates use of the SWP/SWPB instructions. ARMv8
+ oblosetes the use of SWP/SWPB instructions. ARMv7 multiprocessing
+ extensions introduce the ability to disable these instructions,
+ triggering an undefined instruction exception when executed. Say Y
+ here to enable software emulation of these instructions for userspace
+ (not kernel) using LDREX/STREX. Also creates /proc/cpu/swp_emulation
+ for statistics.
+
+ In some older versions of glibc [<=2.8] SWP is used during futex
+ trylock() operations with the assumption that the code will not
+ be preempted. This invalid assumption may be more likely to fail
+ with SWP emulation enabled, leading to deadlock of the user
+ application.
+
+ NOTE: when accessing uncached shared regions, LDREX/STREX rely
+ on an external transaction monitoring block called a global
+ monitor to maintain update atomicity. If your system does not
+ implement a global monitor, this option can cause programs that
+ perform SWP operations to uncached memory to deadlock.
+
+ If unsure, say Y.
+
+config HOTPLUG_CPU
+ bool "Support for hot-pluggable CPUs"
+ depends on SMP
+ help
+ Say Y here to experiment with turning CPUs off and on. CPUs
+ can be controlled through /sys/devices/system/cpu.
+
source kernel/Kconfig.preempt
config HZ
Enable hardware performance counter support for perf events. If
disabled, perf events will use software events only.
+config ARMV7_COMPAT
+ bool "Kernel support for ARMv7 applications"
+ depends on COMPAT
+ select SWP_EMULATE
+ help
+ This option enables features that allow that ran on an ARMv7 or older
+ processor to continue functioning.
+
+ If you want to execute ARMv7 applications, say Y
+
+config ARMV7_COMPAT_CPUINFO
+ bool "Report backwards compatible cpu features in /proc/cpuinfo"
+ depends on ARMV7_COMPAT
+ default y
+ help
+ This option makes /proc/cpuinfo list CPU features that an ARMv7 or
+ earlier kernel would report, but are not optional on an ARMv8 or later
+ processor.
+
+ If you want to execute ARMv7 applications, say Y
+
source "mm/Kconfig"
+config SECCOMP
+ bool "Enable seccomp to safely compute untrusted bytecode"
+ ---help---
+ This kernel feature is useful for number crunching applications
+ that may need to compute untrusted bytecode during their
+ execution. By using pipes or other transports made available to
+ the process as file descriptors supporting the read/write
+ syscalls, it's possible to isolate those applications in
+ their own address space using seccomp. Once seccomp is
+ enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
+ and the task is only allowed to execute a few safe syscalls
+ defined by each seccomp mode.
+
+
endmenu
menu "Boot options"
entering them here. As a minimum, you should specify the the
root device (e.g. root=/dev/nfs).
+choice
+ prompt "Kernel command line type" if CMDLINE != ""
+ default CMDLINE_FROM_BOOTLOADER
+
+config CMDLINE_FROM_BOOTLOADER
+ bool "Use bootloader kernel arguments if available"
+ help
+ Uses the command-line options passed by the boot loader. If
+ the boot loader doesn't provide any, the default kernel command
+ string provided in CMDLINE will be used.
+
+config CMDLINE_EXTEND
+ bool "Extend bootloader kernel arguments"
+ help
+ The command-line arguments provided by the boot loader will be
+ appended to the default kernel command string.
+
config CMDLINE_FORCE
bool "Always use the default kernel command string"
help
loader passes other arguments to the kernel.
This is useful if you cannot or don't want to change the
command-line options your boot loader passes to the kernel.
+endchoice
+
+config BUILD_ARM64_APPENDED_DTB_IMAGE
+ bool "Build a concatenated Image.gz/dtb by default"
+ depends on OF
+ help
+ Enabling this option will cause a concatenated Image.gz and list of
+ DTBs to be built by default (instead of a standalone Image.gz.)
+ The image will built in arch/arm64/boot/Image.gz-dtb
+
+config BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES
+ string "Default dtb names"
+ depends on BUILD_ARM64_APPENDED_DTB_IMAGE
+ help
+ Space separated list of names of dtbs to append when
+ building a concatenated Image.gz-dtb.
+
+endmenu
+
+menu "CPU Power Management"
+
+if ARCH_HAS_CPUFREQ
+source "drivers/cpufreq/Kconfig"
+endif
endmenu
endmenu
+menu "Power management options"
+
+source "kernel/power/Kconfig"
+
+config ARCH_SUSPEND_POSSIBLE
+ depends on !ARCH_S5PC100
+ depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
+ CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK || ARM64
+ def_bool y
+
+config ARM64_CPU_SUSPEND
+ def_bool PM_SLEEP
+
+config ARCH_HIBERNATION_POSSIBLE
+ bool
+ depends on MMU
+ default y if ARCH_SUSPEND_POSSIBLE
+
+endmenu
+
source "net/Kconfig"
source "drivers/Kconfig"
source "security/Kconfig"
source "crypto/Kconfig"
+if CRYPTO
+source "arch/arm64/crypto/Kconfig"
+endif
source "lib/Kconfig"
+
projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blobdiff