import PULS_20160108

[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mm / tlb-v7.S

diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index ea94765acf9a3650f5cb850f6990893f3ccb459b..39a008bfc3ffe0ac429c6b1a1a5e9c8ed54d7cb2 100644 (file)
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -48,8 +48,14 @@ ENTRY(v7wbi_flush_user_tlb_range)
 1:
 #ifdef CONFIG_ARM_ERRATA_720789
        ALT_SMP(mcr     p15, 0, r0, c8, c3, 3)  @ TLB invalidate U MVA all ASID (shareable)
+#ifdef CONFIG_ARM_ERRATA_831171
+       ALT_SMP(mcr     p15, 0, r0, c8, c3, 3)  @ TLB invalidate U MVA all ASID (shareable)
+#endif
 #else
        ALT_SMP(mcr     p15, 0, r0, c8, c3, 1)  @ TLB invalidate U MVA (shareable)
+#ifdef CONFIG_ARM_ERRATA_831171
+       ALT_SMP(mcr     p15, 0, r0, c8, c3, 1)  @ TLB invalidate U MVA (shareable)
+#endif
 #endif
        ALT_UP(mcr      p15, 0, r0, c8, c7, 1)  @ TLB invalidate U MVA
 
@@ -77,8 +83,14 @@ ENTRY(v7wbi_flush_kern_tlb_range)
 1:
 #ifdef CONFIG_ARM_ERRATA_720789
        ALT_SMP(mcr     p15, 0, r0, c8, c3, 3)  @ TLB invalidate U MVA all ASID (shareable)
+#ifdef CONFIG_ARM_ERRATA_831171
+       ALT_SMP(mcr     p15, 0, r0, c8, c3, 3)  @ TLB invalidate U MVA all ASID (shareable)
+#endif
 #else
        ALT_SMP(mcr     p15, 0, r0, c8, c3, 1)  @ TLB invalidate U MVA (shareable)
+#ifdef CONFIG_ARM_ERRATA_831171
+       ALT_SMP(mcr     p15, 0, r0, c8, c3, 1)  @ TLB invalidate U MVA (shareable)
+#endif
 #endif
        ALT_UP(mcr      p15, 0, r0, c8, c7, 1)  @ TLB invalidate U MVA
        add     r0, r0, #PAGE_SZ